diff --git a/sys/dev/bnxt/bnxt_en/bnxt.h b/sys/dev/bnxt/bnxt_en/bnxt.h --- a/sys/dev/bnxt/bnxt_en/bnxt.h +++ b/sys/dev/bnxt/bnxt_en/bnxt.h @@ -771,7 +771,7 @@ #define BNXT_CTX_CQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW #define BNXT_CTX_QTKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC #define BNXT_CTX_QRKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC -#define BNXT_CTX_MAX (BNXT_CTX_QRKC + 1) +#define BNXT_CTX_MAX (BNXT_CTX_TIM + 1) struct bnxt_ctx_mem_info { u8 tqm_fp_rings_count; diff --git a/sys/dev/bnxt/bnxt_en/hsi_struct_def.h b/sys/dev/bnxt/bnxt_en/hsi_struct_def.h --- a/sys/dev/bnxt/bnxt_en/hsi_struct_def.h +++ b/sys/dev/bnxt/bnxt_en/hsi_struct_def.h @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright (c) 2016 Broadcom, All Rights Reserved. + * Copyright (c) 2024 Broadcom, All Rights Reserved. * The term Broadcom refers to Broadcom Limited and/or its subsidiaries * * Redistribution and use in source and binary forms, with or without @@ -31,7 +31,7 @@ __FBSDID("$FreeBSD$"); /* - * Copyright(c) 2001-2023, Broadcom. All rights reserved. The + * Copyright(c) 2001-2024, Broadcom. All rights reserved. The * term Broadcom refers to Broadcom Inc. and/or its subsidiaries. * Proprietary and Confidential Information. * @@ -45,6 +45,10 @@ #ifndef _HSI_STRUCT_DEF_H_ #define _HSI_STRUCT_DEF_H_ +#if defined(HAVE_STDINT_H) +#include +#endif + /* This is the HWRM command header. */ /* hwrm_cmd_hdr (size:128b/16B) */ @@ -76,7 +80,7 @@ * physical address (HPA) or a guest physical address (GPA) and must * point to a physically contiguous block of memory. */ - uint64_t resp_addr; + uint64_t resp_addr; } hwrm_cmd_hdr_t, *phwrm_cmd_hdr_t; /* This is the HWRM response header. */ @@ -111,6 +115,10 @@ #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4) /* RoCE slow path command to modify CC Gen1 support. */ #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5) +/* RoCE slow path command to query CC Gen2 support. */ +#define TLV_TYPE_QUERY_ROCE_CC_GEN2 UINT32_C(0x6) +/* RoCE slow path command to modify CC Gen2 support. */ +#define TLV_TYPE_MODIFY_ROCE_CC_GEN2 UINT32_C(0x7) /* Engine CKV - The Alias key EC curve and ECC public key information. */ #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001) /* Engine CKV - Initialization vector. */ @@ -193,14 +201,14 @@ typedef struct input { /* - * This value indicates what type of request this is. The format + * This value indicates what type of request this is. The format * for the rest of the command is determined by this field. */ uint16_t req_type; /* * This value indicates the what completion ring the request will - * be optionally completed on. If the value is -1, then no - * CR completion will be generated. Any other value must be a + * be optionally completed on. If the value is -1, then no + * CR completion will be generated. Any other value must be a * valid CR ring_id value for this function. */ uint16_t cmpl_ring; @@ -216,7 +224,7 @@ uint16_t target_id; /* * This is the host address where the response will be written - * when the request is complete. This area must be 16B aligned + * when the request is complete. This area must be 16B aligned * and must be cleared to zero before the request is made. */ uint64_t resp_addr; @@ -238,7 +246,7 @@ /* This field provides original sequence number of the command. */ uint16_t seq_id; /* - * This field is the length of the response in bytes. The + * This field is the length of the response in bytes. The * last byte of the response is a valid flag that will read * as '1' when the command has been completely written to * memory. @@ -374,6 +382,14 @@ ((x) == 0x85 ? "HWRM_QUEUE_VLANPRI2PRI_CFG": \ ((x) == 0x86 ? "HWRM_QUEUE_GLOBAL_CFG": \ ((x) == 0x87 ? "HWRM_QUEUE_GLOBAL_QCFG": \ + ((x) == 0x88 ? "HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG": \ + ((x) == 0x89 ? "HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG": \ + ((x) == 0x8a ? "HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG": \ + ((x) == 0x8b ? "HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG": \ + ((x) == 0x8c ? "HWRM_QUEUE_QCAPS": \ + ((x) == 0x8d ? "HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG": \ + ((x) == 0x8e ? "HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG": \ + ((x) == 0x8f ? "HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG": \ ((x) == 0x90 ? "HWRM_CFA_L2_FILTER_ALLOC": \ ((x) == 0x91 ? "HWRM_CFA_L2_FILTER_FREE": \ ((x) == 0x92 ? "HWRM_CFA_L2_FILTER_CFG": \ @@ -392,6 +408,7 @@ ((x) == 0xa0 ? "HWRM_TUNNEL_DST_PORT_QUERY": \ ((x) == 0xa1 ? "HWRM_TUNNEL_DST_PORT_ALLOC": \ ((x) == 0xa2 ? "HWRM_TUNNEL_DST_PORT_FREE": \ + ((x) == 0xa3 ? "HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG": \ ((x) == 0xaf ? "HWRM_STAT_CTX_ENG_QUERY": \ ((x) == 0xb0 ? "HWRM_STAT_CTX_ALLOC": \ ((x) == 0xb1 ? "HWRM_STAT_CTX_FREE": \ @@ -439,6 +456,7 @@ ((x) == 0xdb ? "HWRM_PORT_EP_TX_CFG": \ ((x) == 0xdc ? "HWRM_PORT_CFG": \ ((x) == 0xdd ? "HWRM_PORT_QCFG": \ + ((x) == 0xdf ? "HWRM_PORT_MAC_QCAPS": \ ((x) == 0xe0 ? "HWRM_TEMP_MONITOR_QUERY": \ ((x) == 0xe1 ? "HWRM_REG_POWER_QUERY": \ ((x) == 0xe2 ? "HWRM_CORE_FREQUENCY_QUERY": \ @@ -456,7 +474,7 @@ ((x) == 0xfa ? "HWRM_CFA_METER_INSTANCE_CFG": \ ((x) == 0xfd ? "HWRM_CFA_VFR_ALLOC": \ ((x) == 0xfe ? "HWRM_CFA_VFR_FREE": \ - "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ + "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ (((x) < 0x180) ? \ ((x) == 0x100 ? "HWRM_CFA_VF_PAIR_ALLOC": \ ((x) == 0x101 ? "HWRM_CFA_VF_PAIR_FREE": \ @@ -500,6 +518,7 @@ ((x) == 0x127 ? "HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR": \ ((x) == 0x128 ? "HWRM_CFA_TLS_FILTER_ALLOC": \ ((x) == 0x129 ? "HWRM_CFA_TLS_FILTER_FREE": \ + ((x) == 0x12a ? "HWRM_CFA_RELEASE_AFM_FUNC": \ ((x) == 0x12e ? "HWRM_ENGINE_CKV_STATUS": \ ((x) == 0x12f ? "HWRM_ENGINE_CKV_CKEK_ADD": \ ((x) == 0x130 ? "HWRM_ENGINE_CKV_CKEK_DELETE": \ @@ -539,7 +558,7 @@ ((x) == 0x163 ? "HWRM_ENGINE_NQ_FREE": \ ((x) == 0x164 ? "HWRM_ENGINE_ON_DIE_RQE_CREDITS": \ ((x) == 0x165 ? "HWRM_ENGINE_FUNC_QCFG": \ - "Unknown decode" ))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ + "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ (((x) < 0x200) ? \ ((x) == 0x190 ? "HWRM_FUNC_RESOURCE_QCAPS": \ ((x) == 0x191 ? "HWRM_FUNC_VF_RESOURCE_CFG": \ @@ -570,7 +589,14 @@ ((x) == 0x1aa ? "HWRM_FUNC_DBR_RECOVERY_COMPLETED": \ ((x) == 0x1ab ? "HWRM_FUNC_SYNCE_CFG": \ ((x) == 0x1ac ? "HWRM_FUNC_SYNCE_QCFG": \ - "Unknown decode" ))))))))))))))))))))))))))))) : \ + ((x) == 0x1ad ? "HWRM_FUNC_KEY_CTX_FREE": \ + ((x) == 0x1ae ? "HWRM_FUNC_LAG_MODE_CFG": \ + ((x) == 0x1af ? "HWRM_FUNC_LAG_MODE_QCFG": \ + ((x) == 0x1b0 ? "HWRM_FUNC_LAG_CREATE": \ + ((x) == 0x1b1 ? "HWRM_FUNC_LAG_UPDATE": \ + ((x) == 0x1b2 ? "HWRM_FUNC_LAG_FREE": \ + ((x) == 0x1b3 ? "HWRM_FUNC_LAG_QCFG": \ + "Unknown decode" )))))))))))))))))))))))))))))))))))) : \ (((x) < 0x280) ? \ ((x) == 0x200 ? "HWRM_SELFTEST_QLIST": \ ((x) == 0x201 ? "HWRM_SELFTEST_EXEC": \ @@ -586,9 +612,9 @@ ((x) == 0x20b ? "HWRM_MFG_FRU_EEPROM_READ": \ ((x) == 0x20c ? "HWRM_MFG_SOC_IMAGE": \ ((x) == 0x20d ? "HWRM_MFG_SOC_QSTATUS": \ - ((x) == 0x20e ? "HWRM_MFG_PARAM_SEEPROM_SYNC": \ - ((x) == 0x20f ? "HWRM_MFG_PARAM_SEEPROM_READ": \ - ((x) == 0x210 ? "HWRM_MFG_PARAM_SEEPROM_HEALTH": \ + ((x) == 0x20e ? "HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE": \ + ((x) == 0x20f ? "HWRM_MFG_PARAM_CRITICAL_DATA_READ": \ + ((x) == 0x210 ? "HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH": \ ((x) == 0x211 ? "HWRM_MFG_PRVSN_EXPORT_CSR": \ ((x) == 0x212 ? "HWRM_MFG_PRVSN_IMPORT_CERT": \ ((x) == 0x213 ? "HWRM_MFG_PRVSN_GET_STATE": \ @@ -597,12 +623,22 @@ ((x) == 0x216 ? "HWRM_MFG_SELFTEST_QLIST": \ ((x) == 0x217 ? "HWRM_MFG_SELFTEST_EXEC": \ ((x) == 0x218 ? "HWRM_STAT_GENERIC_QSTATS": \ - "Unknown decode" ))))))))))))))))))))))))) : \ + ((x) == 0x219 ? "HWRM_MFG_PRVSN_EXPORT_CERT": \ + ((x) == 0x21a ? "HWRM_STAT_DB_ERROR_QSTATS": \ + ((x) == 0x258 ? "HWRM_UDCC_QCAPS": \ + ((x) == 0x259 ? "HWRM_UDCC_CFG": \ + ((x) == 0x25a ? "HWRM_UDCC_QCFG": \ + ((x) == 0x25b ? "HWRM_UDCC_SESSION_CFG": \ + ((x) == 0x25c ? "HWRM_UDCC_SESSION_QCFG": \ + ((x) == 0x25d ? "HWRM_UDCC_SESSION_QUERY": \ + ((x) == 0x25e ? "HWRM_UDCC_COMP_CFG": \ + ((x) == 0x25f ? "HWRM_UDCC_COMP_QCFG": \ + ((x) == 0x260 ? "HWRM_UDCC_COMP_QUERY": \ + "Unknown decode" )))))))))))))))))))))))))))))))))))) : \ (((x) < 0x300) ? \ ((x) == 0x2bc ? "HWRM_TF": \ ((x) == 0x2bd ? "HWRM_TF_VERSION_GET": \ ((x) == 0x2c6 ? "HWRM_TF_SESSION_OPEN": \ - ((x) == 0x2c7 ? "HWRM_TF_SESSION_ATTACH": \ ((x) == 0x2c8 ? "HWRM_TF_SESSION_REGISTER": \ ((x) == 0x2c9 ? "HWRM_TF_SESSION_UNREGISTER": \ ((x) == 0x2ca ? "HWRM_TF_SESSION_CLOSE": \ @@ -617,14 +653,6 @@ ((x) == 0x2da ? "HWRM_TF_TBL_TYPE_GET": \ ((x) == 0x2db ? "HWRM_TF_TBL_TYPE_SET": \ ((x) == 0x2dc ? "HWRM_TF_TBL_TYPE_BULK_GET": \ - ((x) == 0x2e2 ? "HWRM_TF_CTXT_MEM_ALLOC": \ - ((x) == 0x2e3 ? "HWRM_TF_CTXT_MEM_FREE": \ - ((x) == 0x2e4 ? "HWRM_TF_CTXT_MEM_RGTR": \ - ((x) == 0x2e5 ? "HWRM_TF_CTXT_MEM_UNRGTR": \ - ((x) == 0x2e6 ? "HWRM_TF_EXT_EM_QCAPS": \ - ((x) == 0x2e7 ? "HWRM_TF_EXT_EM_OP": \ - ((x) == 0x2e8 ? "HWRM_TF_EXT_EM_CFG": \ - ((x) == 0x2e9 ? "HWRM_TF_EXT_EM_QCFG": \ ((x) == 0x2ea ? "HWRM_TF_EM_INSERT": \ ((x) == 0x2eb ? "HWRM_TF_EM_DELETE": \ ((x) == 0x2ec ? "HWRM_TF_EM_HASH_INSERT": \ @@ -637,7 +665,13 @@ ((x) == 0x2fd ? "HWRM_TF_GLOBAL_CFG_GET": \ ((x) == 0x2fe ? "HWRM_TF_IF_TBL_SET": \ ((x) == 0x2ff ? "HWRM_TF_IF_TBL_GET": \ - "Unknown decode" )))))))))))))))))))))))))))))))))))))) : \ + "Unknown decode" ))))))))))))))))))))))))))))) : \ + (((x) < 0x380) ? \ + ((x) == 0x300 ? "HWRM_TF_RESC_USAGE_SET": \ + ((x) == 0x301 ? "HWRM_TF_RESC_USAGE_QUERY": \ + ((x) == 0x302 ? "HWRM_TF_TBL_TYPE_ALLOC": \ + ((x) == 0x303 ? "HWRM_TF_TBL_TYPE_FREE": \ + "Unknown decode" )))) : \ (((x) < 0x400) ? \ ((x) == 0x380 ? "HWRM_TFC_TBL_SCOPE_QCAPS": \ ((x) == 0x381 ? "HWRM_TFC_TBL_SCOPE_ID_ALLOC": \ @@ -663,11 +697,19 @@ ((x) == 0x395 ? "HWRM_TFC_TCAM_ALLOC": \ ((x) == 0x396 ? "HWRM_TFC_TCAM_ALLOC_SET": \ ((x) == 0x397 ? "HWRM_TFC_TCAM_FREE": \ - "Unknown decode" )))))))))))))))))))))))) : \ + ((x) == 0x398 ? "HWRM_TFC_IF_TBL_SET": \ + ((x) == 0x399 ? "HWRM_TFC_IF_TBL_GET": \ + ((x) == 0x39a ? "HWRM_TFC_TBL_SCOPE_CONFIG_GET": \ + ((x) == 0x39b ? "HWRM_TFC_RESC_USAGE_QUERY": \ + ((x) == 0x39c ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS": \ + ((x) == 0x39d ? "HWRM_QUEUE_PFCWD_TIMEOUT_CFG": \ + ((x) == 0x39e ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCFG": \ + "Unknown decode" ))))))))))))))))))))))))))))))) : \ (((x) < 0x480) ? \ ((x) == 0x400 ? "HWRM_SV": \ "Unknown decode" ) : \ (((x) < 0xff80) ? \ + ((x) == 0xff0f ? "HWRM_DBG_LOG_BUFFER_FLUSH": \ ((x) == 0xff10 ? "HWRM_DBG_READ_DIRECT": \ ((x) == 0xff11 ? "HWRM_DBG_READ_INDIRECT": \ ((x) == 0xff12 ? "HWRM_DBG_WRITE_DIRECT": \ @@ -696,8 +738,10 @@ ((x) == 0xff29 ? "HWRM_DBG_USEQ_RUN": \ ((x) == 0xff2a ? "HWRM_DBG_USEQ_DELIVERY_REQ": \ ((x) == 0xff2b ? "HWRM_DBG_USEQ_RESP_HDR": \ - "Unknown decode" )))))))))))))))))))))))))))) : \ + "Unknown decode" ))))))))))))))))))))))))))))) : \ (((x) <= 0xffff) ? \ + ((x) == 0xffea ? "HWRM_NVM_GET_VPD_FIELD_INFO": \ + ((x) == 0xffeb ? "HWRM_NVM_SET_VPD_FIELD_INFO": \ ((x) == 0xffec ? "HWRM_NVM_DEFRAG": \ ((x) == 0xffed ? "HWRM_NVM_REQ_ARBITRATION": \ ((x) == 0xffee ? "HWRM_NVM_FACTORY_DEFAULTS": \ @@ -718,8 +762,8 @@ ((x) == 0xfffd ? "HWRM_NVM_READ": \ ((x) == 0xfffe ? "HWRM_NVM_WRITE": \ ((x) == 0xffff ? "HWRM_NVM_RAW_WRITE_BLK": \ - "Unknown decode" )))))))))))))))))))) : \ - "Unknown decode" )))))))))) + "Unknown decode" )))))))))))))))))))))) : \ + "Unknown decode" ))))))))))) /* @@ -800,7 +844,7 @@ #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34) #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35) #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36) - #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37) + #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37) #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38) #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39) #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a) @@ -848,6 +892,14 @@ #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85) #define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86) #define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG UINT32_C(0x88) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG UINT32_C(0x89) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG UINT32_C(0x8a) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG UINT32_C(0x8b) + #define HWRM_QUEUE_QCAPS UINT32_C(0x8c) + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG UINT32_C(0x8d) + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG UINT32_C(0x8e) + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG UINT32_C(0x8f) #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90) #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91) #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92) @@ -871,6 +923,7 @@ #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0) #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1) #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2) + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG UINT32_C(0xa3) #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf) #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0) #define HWRM_STAT_CTX_FREE UINT32_C(0xb1) @@ -926,6 +979,8 @@ #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb) #define HWRM_PORT_CFG UINT32_C(0xdc) #define HWRM_PORT_QCFG UINT32_C(0xdd) + /* Queries MAC capabilities for the specified port */ + #define HWRM_PORT_MAC_QCAPS UINT32_C(0xdf) #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) @@ -1029,7 +1084,12 @@ #define HWRM_CFA_TLS_FILTER_ALLOC UINT32_C(0x128) /* Experimental */ #define HWRM_CFA_TLS_FILTER_FREE UINT32_C(0x129) - /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */ + /* Release an AFM function for TF control */ + #define HWRM_CFA_RELEASE_AFM_FUNC UINT32_C(0x12a) + /* + * Engine CKV - Get the current allocation status of keys provisioned in + * the key vault. + */ #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e) /* Engine CKV - Add a new CKEK used to encrypt keys. */ #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f) @@ -1089,7 +1149,10 @@ #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156) /* Engine - Query the statistics accumulator for an Engine. */ #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157) - /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */ + /* + * Engine - Query statistics counters for continuous errors from all CDDIP + * Engines. + */ #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158) /* Engine - Allocate an Engine RQ. */ #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e) @@ -1171,6 +1234,20 @@ #define HWRM_FUNC_SYNCE_CFG UINT32_C(0x1ab) /* Queries SyncE configurations. */ #define HWRM_FUNC_SYNCE_QCFG UINT32_C(0x1ac) + /* The command is used to deallocate KTLS or QUIC key contexts. */ + #define HWRM_FUNC_KEY_CTX_FREE UINT32_C(0x1ad) + /* The command is used to configure link aggr group mode. */ + #define HWRM_FUNC_LAG_MODE_CFG UINT32_C(0x1ae) + /* The command is used to query link aggr group mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG UINT32_C(0x1af) + /* The command is used to create a link aggr group. */ + #define HWRM_FUNC_LAG_CREATE UINT32_C(0x1b0) + /* The command is used to update a link aggr group. */ + #define HWRM_FUNC_LAG_UPDATE UINT32_C(0x1b1) + /* The command is used to free a link aggr group. */ + #define HWRM_FUNC_LAG_FREE UINT32_C(0x1b2) + /* The command is used to query a link aggr group. */ + #define HWRM_FUNC_LAG_QCFG UINT32_C(0x1b3) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -1202,12 +1279,12 @@ #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c) /* Retrieves the SoC status and image provisioning information */ #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d) - /* Tells the fw to program the seeprom memory */ - #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e) - /* Tells the fw to read the seeprom memory */ - #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f) - /* Tells the fw to get the health of seeprom data */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210) + /* Tells the fw to finalize the critical data (store and lock it) */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE UINT32_C(0x20e) + /* Tells the fw to read the critical data */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_READ UINT32_C(0x20f) + /* Tells the fw to get the health of critical data */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH UINT32_C(0x210) /* * The command is used for certificate provisioning to export a * Certificate Signing Request (CSR) from the device. @@ -1242,6 +1319,37 @@ #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217) /* Queries the generic stats */ #define HWRM_STAT_GENERIC_QSTATS UINT32_C(0x218) + /* + * The command is used for certificate provisioning to export a + * certificate chain from the device. + */ + #define HWRM_MFG_PRVSN_EXPORT_CERT UINT32_C(0x219) + /* Query the statistics for doorbell drops due to various error conditions. */ + #define HWRM_STAT_DB_ERROR_QSTATS UINT32_C(0x21a) + /* + * This command returns the capabilities related to User Defined + * Congestion Control on a function. + */ + #define HWRM_UDCC_QCAPS UINT32_C(0x258) + /* This command configures User Defined Congestion Control on a function. */ + #define HWRM_UDCC_CFG UINT32_C(0x259) + /* + * This command queries the configuration of User Defined Congestion + * Control on a function. + */ + #define HWRM_UDCC_QCFG UINT32_C(0x25a) + /* This command configures an existing UDCC session. */ + #define HWRM_UDCC_SESSION_CFG UINT32_C(0x25b) + /* This command queries the configuration of a UDCC session. */ + #define HWRM_UDCC_SESSION_QCFG UINT32_C(0x25c) + /* This command queries the UDCC session. */ + #define HWRM_UDCC_SESSION_QUERY UINT32_C(0x25d) + /* This command configures the computation unit. */ + #define HWRM_UDCC_COMP_CFG UINT32_C(0x25e) + /* This command queries the configuration of the computation unit. */ + #define HWRM_UDCC_COMP_QCFG UINT32_C(0x25f) + /* This command queries the status and statistics of the computation unit. */ + #define HWRM_UDCC_COMP_QUERY UINT32_C(0x260) /* Experimental */ #define HWRM_TF UINT32_C(0x2bc) /* Experimental */ @@ -1249,8 +1357,6 @@ /* Experimental */ #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6) /* Experimental */ - #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7) - /* Experimental */ #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8) /* Experimental */ #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9) @@ -1279,22 +1385,6 @@ /* Experimental */ #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc) /* Experimental */ - #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2) - /* Experimental */ - #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3) - /* Experimental */ - #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4) - /* Experimental */ - #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5) - /* Experimental */ - #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6) - /* Experimental */ - #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7) - /* Experimental */ - #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8) - /* Experimental */ - #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9) - /* Experimental */ #define HWRM_TF_EM_INSERT UINT32_C(0x2ea) /* Experimental */ #define HWRM_TF_EM_DELETE UINT32_C(0x2eb) @@ -1318,6 +1408,14 @@ #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe) /* Experimental */ #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff) + /* Experimental */ + #define HWRM_TF_RESC_USAGE_SET UINT32_C(0x300) + /* Experimental */ + #define HWRM_TF_RESC_USAGE_QUERY UINT32_C(0x301) + /* Truflow command to allocate a table */ + #define HWRM_TF_TBL_TYPE_ALLOC UINT32_C(0x302) + /* Truflow command to free a table */ + #define HWRM_TF_TBL_TYPE_FREE UINT32_C(0x303) /* TruFlow command to check firmware table scope capabilities. */ #define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380) /* TruFlow command to allocate a table scope ID and create the pools. */ @@ -1330,9 +1428,9 @@ #define HWRM_TFC_TBL_SCOPE_FID_ADD UINT32_C(0x384) /* TruFlow command to remove a FID from a table scope. */ #define HWRM_TFC_TBL_SCOPE_FID_REM UINT32_C(0x385) - /* TruFlow command to allocate a table scope pool. */ + /* DEPRECATED */ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC UINT32_C(0x386) - /* TruFlow command to free a table scope pool. */ + /* DEPRECATED */ #define HWRM_TFC_TBL_SCOPE_POOL_FREE UINT32_C(0x387) /* Experimental */ #define HWRM_TFC_SESSION_ID_ALLOC UINT32_C(0x388) @@ -1366,8 +1464,30 @@ #define HWRM_TFC_TCAM_ALLOC_SET UINT32_C(0x396) /* TruFlow command to free a TCAM entry. */ #define HWRM_TFC_TCAM_FREE UINT32_C(0x397) + /* Truflow command to set an interface table entry */ + #define HWRM_TFC_IF_TBL_SET UINT32_C(0x398) + /* Truflow command to get an interface table entry */ + #define HWRM_TFC_IF_TBL_GET UINT32_C(0x399) + /* TruFlow command to get configured info about a table scope. */ + #define HWRM_TFC_TBL_SCOPE_CONFIG_GET UINT32_C(0x39a) + /* TruFlow command to query the resource usage state. */ + #define HWRM_TFC_RESC_USAGE_QUERY UINT32_C(0x39b) + /* + * This command is used to query the pfc watchdog max configurable + * timeout value. + */ + #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS UINT32_C(0x39c) + /* This command is used to set the PFC watchdog timeout value. */ + #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG UINT32_C(0x39d) + /* + * This command is used to query the current configured pfc watchdog + * timeout value. + */ + #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG UINT32_C(0x39e) /* Experimental */ #define HWRM_SV UINT32_C(0x400) + /* Flush any trace buffer data that has not been sent to the host. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH UINT32_C(0xff0f) /* Experimental */ #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10) /* Experimental */ @@ -1423,6 +1543,8 @@ #define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a) /* Experimental */ #define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b) + #define HWRM_NVM_GET_VPD_FIELD_INFO UINT32_C(0xffea) + #define HWRM_NVM_SET_VPD_FIELD_INFO UINT32_C(0xffeb) #define HWRM_NVM_DEFRAG UINT32_C(0xffec) #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed) /* Experimental */ @@ -1518,14 +1640,14 @@ #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc) /* * This error code is only reported by firmware when the registered - * driver instances requested to offloaded a flow but was unable to because - * the requested key's hash collides with the installed keys. + * driver instances requested to offloaded a flow but was unable to + * because the requested key's hash collides with the installed keys. */ #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd) /* * This error code is only reported by firmware when the registered - * driver instances requested to offloaded a flow but was unable to because - * the same key has already been installed. + * driver instances requested to offloaded a flow but was unable to + * because the same key has already been installed. */ #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe) /* @@ -1534,8 +1656,8 @@ */ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf) /* - * Firmware is unable to service the request at the present time. Caller - * may try again later. + * Firmware is unable to service the request at the present time. + * Caller may try again later. */ #define HWRM_ERR_CODE_BUSY UINT32_C(0x10) /* @@ -1550,6 +1672,11 @@ * async completion ring or associated forwarding buffers configured. */ #define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12) + /* + * This error code is reported by Firmware when the specific entity + * requested by the host is not present or does not exist. + */ + #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT UINT32_C(0x13) /* * This value indicates that the HWRM response is in TLV format and * should be interpreted as one or more TLVs starting with the @@ -1587,7 +1714,8 @@ ((x) == 0x10 ? "BUSY": \ ((x) == 0x11 ? "RESOURCE_LOCKED": \ ((x) == 0x12 ? "PF_UNAVAILABLE": \ - "Unknown decode" ))))))))))))))))))) : \ + ((x) == 0x13 ? "ENTITY_NOT_PRESENT": \ + "Unknown decode" )))))))))))))))))))) : \ (((x) < 0x8080) ? \ ((x) == 0x8000 ? "TLV_ENCAPSULATED_RESPONSE": \ "Unknown decode" ) : \ @@ -1614,7 +1742,7 @@ /* This field provides original sequence number of the command. */ uint16_t seq_id; /* - * This field is the length of the response in bytes. The + * This field is the length of the response in bytes. The * last byte of the response is a valid flag that will read * as '1' when the command has been completely written to * memory. @@ -1631,9 +1759,9 @@ uint8_t cmd_err; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -1644,7 +1772,12 @@ * applicable (All F's). Need to cast it the size of the field if needed. */ #define HWRM_NA_SIGNATURE ((uint32_t)(-1)) -/* hwrm_func_buf_rgtr */ +/* + * This is reflecting the size of the PF mailbox and not the maximum + * command size for any of the HWRM command structures. To determine + * the maximum size of an HWRM command supported by the firmware, see + * the max_ext_req_len field in the response of the HWRM_VER_GET command. + */ #define HWRM_MAX_REQ_LEN 128 /* hwrm_cfa_flow_info */ #define HWRM_MAX_RESP_LEN 704 @@ -1668,10 +1801,10 @@ #define HWRM_TARGET_ID_TOOLS 0xFFFD #define HWRM_VERSION_MAJOR 1 #define HWRM_VERSION_MINOR 10 -#define HWRM_VERSION_UPDATE 2 +#define HWRM_VERSION_UPDATE 3 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 136 -#define HWRM_VERSION_STR "1.10.2.136" +#define HWRM_VERSION_RSVD 42 +#define HWRM_VERSION_STR "1.10.3.42" /**************** * hwrm_ver_get * @@ -1887,47 +2020,52 @@ /* * If set to 1, then the KONG host mailbox channel is supported. * If set to 0, then the KONG host mailbox channel is not supported. - * By default, this flag should be 0 for older version of core firmware. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED UINT32_C(0x10) /* - * If set to 1, then the 64bit flow handle is supported in addition to the - * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not - * supported. By default, this flag should be 0 for older version of core firmware. + * If set to 1, then the 64bit flow handle is supported in addition + * to the legacy 16bit flow handle. If set to 0, then the 64bit flow + * handle is not supported. By default, this flag should be 0 for + * older version of core firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED UINT32_C(0x20) /* - * If set to 1, then filter type can be provided in filter_alloc or filter_cfg - * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic. - * If set to 0, then filter types not supported. - * By default, this flag should be 0 for older version of core firmware. + * If set to 1, then filter type can be provided in filter_alloc or + * filter_cfg filter types like L2 for l2 traffic and ROCE for roce & + * l2 traffic. If set to 0, then filter types not supported. By + * default, this flag should be 0 for older version of core firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED UINT32_C(0x40) /* - * If set to 1, firmware is capable to support virtio vSwitch offload model. - * If set to 0, firmware can't supported virtio vSwitch offload model. - * By default, this flag should be 0 for older version of core firmware. + * If set to 1, firmware is capable to support virtio vSwitch offload + * model. If set to 0, firmware can't supported virtio vSwitch + * offload model. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED UINT32_C(0x80) /* * If set to 1, firmware is capable to support trusted VF. * If set to 0, firmware is not capable to support trusted VF. - * By default, this flag should be 0 for older version of core firmware. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED UINT32_C(0x100) /* * If set to 1, firmware is capable to support flow aging. * If set to 0, firmware is not capable to support flow aging. - * By default, this flag should be 0 for older version of core firmware. - * (deprecated) + * By default, this flag should be 0 for older version of core + * firmware. (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED UINT32_C(0x200) /* - * If set to 1, firmware is capable to support advanced flow counters like, - * Meter drop counters and EEM counters. - * If set to 0, firmware is not capable to support advanced flow counters. - * By default, this flag should be 0 for older version of core firmware. - * (deprecated) + * If set to 1, firmware is capable to support advanced flow counters + * like, Meter drop counters and EEM counters. + * If set to 0, firmware is not capable to support advanced flow + * counters. By default, this flag should be 0 for older version of + * core firmware. (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED UINT32_C(0x400) /* @@ -1935,28 +2073,30 @@ * Extended Exact Match(EEM) feature. * If set to 0, firmware is not capable to support the use of the * CFA EEM feature. - * By default, this flag should be 0 for older version of core firmware. - * (deprecated) + * By default, this flag should be 0 for older version of core + * firmware. (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED UINT32_C(0x800) /* - * If set to 1, the firmware is able to support advance CFA flow management - * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS. - * If set to 0, then the firmware doesn’t support the advance CFA flow management - * features. - * By default, this flag should be 0 for older version of core firmware. + * If set to 1, the firmware is able to support advance CFA flow + * management features reported in the HWRM_CFA_FLOW_MGNT_QCAPS. + * If set to 0, then the firmware doesn't support the advance CFA + * flow management features. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED UINT32_C(0x1000) /* * Deprecated and replaced with cfa_truflow_supported. * If set to 1, the firmware is able to support TFLIB features. - * If set to 0, then the firmware doesn’t support TFLIB features. - * By default, this flag should be 0 for older version of core firmware. + * If set to 0, then the firmware doesn't support TFLIB features. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED UINT32_C(0x2000) /* * If set to 1, the firmware is able to support TruFlow features. - * If set to 0, then the firmware doesn’t support TruFlow features. + * If set to 0, then the firmware doesn't support TruFlow features. * By default, this flag should be 0 for older version of * core firmware. */ @@ -1966,6 +2106,13 @@ * If set to 0, then firmware doesn't support secure boot. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE UINT32_C(0x8000) + /* + * If set to 1, then firmware is able to support the secure solution + * feature. + * If set to 0, then firmware does not support the secure solution + * feature. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_SOC_CAPABLE UINT32_C(0x10000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -2018,7 +2165,10 @@ uint8_t chip_metal; /* This field returns the bond id of the chip. */ uint8_t chip_bond_id; - /* This value indicates the type of platform used for chip implementation. */ + /* + * This value indicates the type of platform used for chip + * implementation. + */ uint8_t chip_platform_type; /* ASIC */ #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0) @@ -2071,8 +2221,8 @@ * host drivers that it has not completed resource initialization * required for data path operations. Host drivers should not send * any HWRM command that requires data path resources. Firmware will - * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry - * those commands once both the flags are cleared. + * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can + * retry those commands once both the flags are cleared. * If this flag and dev_not_rdy flag are set to 0, device is ready * to accept all HWRM commands. */ @@ -2232,9 +2382,9 @@ uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -2801,11 +2951,11 @@ * Typically, presync BDs are used for packet retransmissions. Source * port sends all the packets in order over the network to destination * port and packets get dropped in the network. The destination port - * will request retranmission of dropped packets and source port driver - * will send presync BD to setup the transmitter appropriately. It will - * provide the start and end TCP sequence number of the data to be - * transmitted. HW keeps two sets of context variable, one for in order - * traffic and one for retransmission traffic. HW is designed to + * will request retransmission of dropped packets and source port + * driver will send presync BD to setup the transmitter appropriately. + * It will provide the start and end TCP sequence number of the data to + * be transmitted. HW keeps two sets of context variable, one for in + * order traffic and one for retransmission traffic. HW is designed to * transmit everything posted in the presync BD and return to in order * mode after that. No inorder context variables are updated in the * process. There is a special case where packets can be dropped @@ -2955,22 +3105,22 @@ * exchanged as part of sessions setup between the two end * points for QUIC operations. */ - uint64_t quic_iv_lo; + uint8_t quic_iv_lo[8]; /* * Most-significant 32 bits (of 96) of additional IV that is * exchanged as part of sessions setup between the two end * points for QUIC operations. */ - uint32_t quic_iv_hi; + uint8_t quic_iv_hi[4]; uint32_t unused_1; /* * Key used for encrypting or decrypting records. The Key is exchanged * as part of sessions setup between the two end points through this * mid-path BD. */ - uint32_t session_key[8]; + uint8_t session_key[32]; /* Header protection key. */ - uint32_t hp_key[8]; + uint8_t hp_key[32]; /* Packet number associated with the QUIC connection. */ uint64_t pkt_number; } ce_bds_quic_add_data_msg_t, *pce_bds_quic_add_data_msg_t; @@ -3149,7 +3299,8 @@ * * This value must be valid on all BDs of a packet. */ - uint64_t addr; + uint32_t addr_lo; + uint32_t addr_hi; } tx_bd_short_t, *ptx_bd_short_t; /* tx_bd_long (size:128b/16B) */ @@ -3359,7 +3510,7 @@ * 0xffff. * * If set to one when LSO is '1', then the IPID will be treated - * as a 15b number and will be wrapped if it exceeds a value 0f + * as a 15b number and will be wrapped if it exceeds a value of * 0x7fff. */ #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40) @@ -3418,7 +3569,7 @@ * will be the following behavior for all cases independent of * settings of inner LSO and checksum offload BD flags. * If outer UDP checksum is 0, then do not update it. - * If outer UDP checksum is non zero, then the hardware should + * If outer UDP checksum is non zero, then the hardware should * compute and update it. */ #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000) @@ -3554,7 +3705,7 @@ * - Wh+/SR - this option is not supported. * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta * is set in the Lookup Table. - * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if * en_bd_meta is set in the Lookup Table. */ #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER (UINT32_C(0x2) << 28) @@ -3650,7 +3801,8 @@ * This field must be valid on the first BD of a packet. */ uint32_t opaque; - uint64_t unused1; + uint32_t unused1_lo; + uint32_t unused1_hi; /* * All bits in this field must be valid on the first BD of a packet. * Their value on other BDs of the packet is ignored. @@ -3859,7 +4011,7 @@ * - Wh+/SR - this option is not supported. * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta * is set in the Lookup Table. - * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if * en_bd_meta is set in the Lookup Table. */ #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER (UINT32_C(0x2) << 28) @@ -3927,7 +4079,8 @@ * Tx mid-path command. */ uint32_t opaque; - uint64_t unused1; + uint32_t unused1_lo; + uint32_t unused1_hi; } tx_bd_mp_cmd_t, *ptx_bd_mp_cmd_t; /* tx_bd_presync_cmd (size:128b/16B) */ @@ -3987,6 +4140,96 @@ uint32_t unused_1; } tx_bd_presync_cmd_t, *ptx_bd_presync_cmd_t; +/* + * This structure is used to send additional information for transmitting + * packets using timed transmit scheduling. It must only to be applied as + * the second BD of a BD chain that represents a packet. Any subsequent + * BDs will follow the timed transmit BD. + */ +/* tx_bd_timedtx (size:128b/16B) */ + +typedef struct tx_bd_timedtx { + uint16_t flags_type; + /* This value identifies the type of buffer descriptor. */ + #define TX_BD_TIMEDTX_TYPE_MASK UINT32_C(0x3f) + #define TX_BD_TIMEDTX_TYPE_SFT 0 + /* + * Indicates a timed transmit BD. This is a 16b BD that is inserted + * into a packet BD chain immediately after the first BD. It is used + * to control the flow in a timed transmit operation. + */ + #define TX_BD_TIMEDTX_TYPE_TX_BD_TIMEDTX UINT32_C(0xa) + #define TX_BD_TIMEDTX_TYPE_LAST TX_BD_TIMEDTX_TYPE_TX_BD_TIMEDTX + /* Unless otherwise stated, sub-fields of this field are always valid. */ + #define TX_BD_TIMEDTX_FLAGS_MASK UINT32_C(0xffc0) + #define TX_BD_TIMEDTX_FLAGS_SFT 6 + /* + * This value identifies the kind of buffer timed transmit mode that + * is to be enabled for the packet. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_MASK UINT32_C(0x1c0) + #define TX_BD_TIMEDTX_FLAGS_KIND_SFT 6 + /* + * This timed transmit mode indicates that the packet will be + * scheduled and send immediately (or as soon as possible), once + * it is scheduled in the transmitter. + * Note: This mode is similar to regular (non-timed transmit) + * operation. Its main purpose is to cancel pace mode timed + * transmit. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_ASAP (UINT32_C(0x0) << 6) + /* + * This timed transmit mode is used to schedule transmission of + * the packet no earlier than the time given in the tx_time + * field of the BD. + * Note: In case subsequent packets don't include a timed transmit + * BD, they will be scheduled subsequently for transmission + * without any timed transmit constraint. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_SO_TXTIME (UINT32_C(0x1) << 6) + /* + * This timed transmit mode is used to enable rate control for the + * flow (QP) at a rate as defined by the rate field of this BD. + * Note: In case subsequent, adjacent packets on the same flow + * don't include a timed transmit BD, they will continue to be + * paced by the transmitter at the same rate as given in this BD. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_PACE (UINT32_C(0x2) << 6) + #define TX_BD_TIMEDTX_FLAGS_KIND_LAST TX_BD_TIMEDTX_FLAGS_KIND_PACE + /* + * This field exists in all Tx BDs. It doesn't apply to this particular + * BD type since the BD never represents an SGL or inline data; i.e. it + * is only a command. This field must be zero. + */ + /* + * Note that if this field is not zero, a fatal length error will be + * generated as it will be included in the aggregate of SGE lengths for + * the packet. + */ + uint16_t len; + /* + * This field represents the rate of the flow (QP) in terms of KB/s. + * This applies to pace mode timed transmit. + */ + uint32_t rate; + /* + * Applying this rate to a QP will result in this and all subsequent + * packets of the flow being paced at the given rate, until such time + * that the timed transmit mode is either changed or the rate is + * updated in a future packet on the flow. + * This field is applicable only if flags.kind is pace. + */ + #define TX_BD_TIMEDTX_RATE_VAL_MASK UINT32_C(0x1ffffff) + #define TX_BD_TIMEDTX_RATE_VAL_SFT 0 + /* + * This field represents the nano-second time to transmit the + * corresponding packet using SO_TXTIME mode of timed transmit. + * This field is applicable only if flags.kind is so_txtime. + */ + uint32_t tx_time_lo; + uint32_t tx_time_hi; +} tx_bd_timedtx_t, *ptx_bd_timedtx_t; + /* rx_prod_pkt_bd (size:128b/16B) */ typedef struct rx_prod_pkt_bd { @@ -4101,7 +4344,8 @@ * While this is a Byte resolution value, it is often advantageous * to ensure that the buffers provide start on a host cache line. */ - uint64_t addr; + uint32_t addr_lo; + uint32_t addr_hi; } rx_prod_bfr_bd_t, *prx_prod_bfr_bd_t; /* rx_prod_agg_bd (size:128b/16B) */ @@ -4153,7 +4397,8 @@ * While this is a Byte resolution value, it is often advantageous * to ensure that the buffers provide start on a host cache line. */ - uint64_t addr; + uint32_t addr_lo; + uint32_t addr_hi; } rx_prod_agg_bd_t, *prx_prod_agg_bd_t; /* cfa_cmpls_cmp_data_msg (size:128b/16B) */ @@ -6349,7 +6594,19 @@ * is not applicable. */ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 (UINT32_C(0xb) << 7) - #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_LAST RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 + /* The RSS hash was computed over tunnel context and tunnel ID field. */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_12 (UINT32_C(0xc) << 7) + /* + * The RSS hash was computed over tunnel source IP address, tunnel + * destination IP address, and tunnel ID field. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_13 (UINT32_C(0xd) << 7) + /* + * The RSS hash was computed over tunnel source IP address, tunnel + * destination IP address, tunnel context, and tunnel ID field. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14 (UINT32_C(0xe) << 7) + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_LAST RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14 uint16_t metadata1_payload_offset; /* * If truncation placement is not used, this value indicates the offset @@ -6619,16 +6876,12 @@ */ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5) << 9) /* - * Indicates that the IP checksum failed its check in the tunnel - * header. - */ - #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR (UINT32_C(0x6) << 9) - /* - * Indicates that the L4 checksum failed its check in the tunnel + * Indicates that the physical packet is shorter than that claimed + * by the tunnel header length. Valid for GTPv1-U packets. * header. */ - #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR (UINT32_C(0x7) << 9) - #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (UINT32_C(0x6) << 9) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR /* * This indicates that there was an error in the inner * portion of the packet when this @@ -6683,17 +6936,7 @@ * for TCP. */ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12) - /* - * Indicates that the IP checksum failed its check in the - * inner header. - */ - #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR (UINT32_C(0x9) << 12) - /* - * Indicates that the L4 checksum failed its check in the - * inner header. - */ - #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR (UINT32_C(0xa) << 12) - #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN /* * This is data from the CFA block as indicated by the meta_format * field. @@ -7623,7 +7866,7 @@ #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) /* * This indicates that the complete 1's complement checksum was - * calculated for the packet in the affregation. + * calculated for the packet in the aggregation. */ #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200) /* @@ -8602,7 +8845,7 @@ /* This value indicates what format the metadata field is. */ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata informtaion. Value is zero. */ + /* No metadata information. Value is zero. */ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4) /* * The metadata field contains the VLAN tag and TPID value. @@ -8619,7 +8862,7 @@ * - VXLAN = VNI[23:0] -> VXLAN Network ID * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 + * - GRE = KEY[31:0] -> key field with bit mask. Zero if K = 0 * - IPV4 = 0 (not populated) * - IPV6 = Flow Label[19:0] * - PPPoE = sessionID[15:0] @@ -9511,7 +9754,7 @@ */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD UINT32_C(0x46) /* - * An event from firmware indicating that the RSS capabilites have + * An event from firmware indicating that the RSS capabilities have * changed. */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE UINT32_C(0x47) @@ -9529,8 +9772,27 @@ * doorbell copy region. */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR UINT32_C(0x49) + /* + * An event from firmware indicating that the XID partition was not + * allocated/freed by the FW successfully for the request that is + * encapsulated in the HWRM_EXEC_FWD_RESP by the PF driver for VF. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR UINT32_C(0x4a) + /* + * A UDCC session has been modified in the FW. The session_id can be + * used by the driver to retrieve information related to the UDCC + * session. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE UINT32_C(0x4b) + /* + * Used to notify the host that the firmware has DMA-ed additional + * debug data to the host buffer. This is effectively a producer index + * update. The host driver can utilize this information to determine + * how much of its host buffer has been populated by the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER UINT32_C(0x4c) /* Maximum Registrable event id. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID UINT32_C(0x4a) + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID UINT32_C(0x4d) /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental @@ -9604,8 +9866,11 @@ ((x) == 0x47 ? "RSS_CHANGE": \ ((x) == 0x48 ? "DOORBELL_PACING_NQ_UPDATE": \ ((x) == 0x49 ? "HW_DOORBELL_RECOVERY_READ_ERROR": \ - ((x) == 0x4a ? "MAX_RGTR_EVENT_ID": \ - "Unknown decode" ))))))))))))))))))))))))))))))))))))))))))) : \ + ((x) == 0x4a ? "CTX_ERROR": \ + ((x) == 0x4b ? "UDCC_SESSION_CHANGE": \ + ((x) == 0x4c ? "DBG_BUF_PRODUCER": \ + ((x) == 0x4d ? "MAX_RGTR_EVENT_ID": \ + "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))) : \ (((x) < 0x100) ? \ ((x) == 0xfe ? "FW_TRACE_MSG": \ ((x) == 0xff ? "HWRM_ERROR": \ @@ -10136,7 +10401,7 @@ * 16-lsb timestamp (100-msec resolution) * The Maximum Firmware Reset bail out value in the order of 100 * milliseconds. The driver instances will use this value to reinitiate - * the registration process again if the core firmware didn’t set the + * the registration process again if the core firmware didn't set the * state bit. */ uint16_t timestamp_hi; @@ -10748,6 +11013,13 @@ * If set to 0, then this bit should be ignored. */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE UINT32_C(0x10) + /* + * If this bit is set to 1, then the control of VF was relinquished + * back to the firmware flow manager following the function takeover + * by TruFlow. + * If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE UINT32_C(0x20) } hwrm_async_event_cmpl_vf_cfg_change_t, *phwrm_async_event_cmpl_vf_cfg_change_t; /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ @@ -11241,8 +11513,8 @@ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT 8 /* * Additional information about internal hardware state related to - * idle/quiesce state. QUIESCE may succeed per quiesce_status - * regardless of idle_state_flags. If QUIESCE fails, the host may + * idle/quiesce state. QUIESCE may succeed per quiesce_status + * regardless of idle_state_flags. If QUIESCE fails, the host may * inspect idle_state_flags to determine whether a retry is warranted. */ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK UINT32_C(0xff0000) @@ -11854,6 +12126,197 @@ #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_CQ_ERR UINT32_C(0x8) } hwrm_async_event_cmpl_hw_doorbell_recovery_read_error_t, *phwrm_async_event_cmpl_hw_doorbell_recovery_read_error_t; +/* hwrm_async_event_cmpl_ctx_error (size:128b/16B) */ + +typedef struct hwrm_async_event_cmpl_ctx_error { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform the PF driver + * that firmware fails to allocate/free the contexts requested. This + * message is only valid in the XID partition scheme. Given the start + * xid and the number of contexts in error, the PF driver will figure + * out the corresponding XID partition(s) in error. + */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_CTX_ERROR UINT32_C(0x4a) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_CTX_ERROR + /* Event specific data */ + uint32_t event_data2; + /* Context operation code */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE UINT32_C(0x1) + /* Context alloc failure */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_ALLOC UINT32_C(0x0) + /* Context free failure */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_FREE UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_LAST HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_FREE + /* Number of contexts in error */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_NUM_CTXS_MASK UINT32_C(0xfffe) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_NUM_CTXS_SFT 1 + /* Function ID which the XID partitions are associated with */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_FID_MASK UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_FID_SFT 16 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Starting XID that has error */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_MASK UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_SFT 0 +} hwrm_async_event_cmpl_ctx_error_t, *phwrm_async_event_cmpl_ctx_error_t; + +/* hwrm_async_event_udcc_session_change (size:128b/16B) */ + +typedef struct hwrm_async_event_udcc_session_change { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_LAST HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform the PF driver + * that firmware has modified a UDCC session. + */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_UDCC_SESSION_CHANGE UINT32_C(0x4b) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_LAST HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_UDCC_SESSION_CHANGE + /* Event specific data */ + uint32_t event_data2; + /* UDCC Session id operation code */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_MASK UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_SFT 0 + /* session_id has been created */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_CREATED UINT32_C(0x0) + /* session_id has been freed */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_FREED UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_LAST HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_FREED + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* UDCC session id which was modified */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_SFT 0 +} hwrm_async_event_udcc_session_change_t, *phwrm_async_event_udcc_session_change_t; + +/* hwrm_async_event_cmpl_dbg_buf_producer (size:128b/16B) */ + +typedef struct hwrm_async_event_cmpl_dbg_buf_producer { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * Used to notify the host that the firmware has DMA-ed additional + * debug data to the host buffer. This is effectively a producer index + * update. The host driver can utilize this information to determine + * how much of its host buffer has been populated by the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER UINT32_C(0x4c) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER + /* Event specific data */ + uint32_t event_data2; + /* + * Specifies the current host buffer offset. Data up to this offset + * has been populated by the firmware. For example, if the firmware + * has DMA-ed 8192 bytes to the host buffer, then this field has a + * value of 8192. This field rolls over to zero once the firmware + * writes the last page of the host buffer + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_MASK UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_SFT 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Type of trace buffer that has been updated. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT 0 + /* SRT trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE UINT32_C(0x0) + /* SRT2 trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE UINT32_C(0x1) + /* CRT trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE UINT32_C(0x2) + /* CRT2 trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE UINT32_C(0x3) + /* RIGP0 trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE UINT32_C(0x4) + /* L2 HWRM trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE UINT32_C(0x5) + /* RoCE HWRM trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE +} hwrm_async_event_cmpl_dbg_buf_producer_t, *phwrm_async_event_cmpl_dbg_buf_producer_t; + /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ typedef struct hwrm_async_event_cmpl_fw_trace_msg { @@ -12036,10 +12499,10 @@ /* Event specific data */ uint32_t event_data1; /* Indicates the type of error being reported. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 /* Reserved */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED UINT32_C(0x0) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED UINT32_C(0x0) /* * The NIC was subjected to an extended pause storm which caused it * to disable flow control in order to avoid stalling the Tx path. @@ -12052,7 +12515,7 @@ * it. The pin number on which this signal was received is stored * in event_data2 as pin_id. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL UINT32_C(0x2) /* * There was a low level error with an NVM write or erase. * See nvm_err_type for more details. @@ -12063,12 +12526,12 @@ * threshold is crossed, it indicates one or more doorbells for * the function were dropped by hardware. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD UINT32_C(0x4) /* * Indicates the NIC's temperature has crossed one of the thermal * thresholds. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD UINT32_C(0x5) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD UINT32_C(0x5) /* * Speed change not supported with dual rate transceivers * on this board. @@ -12085,7 +12548,8 @@ ((x) == 0x3 ? "NVM": \ ((x) == 0x4 ? "DOORBELL_DROP_THRESHOLD": \ ((x) == 0x5 ? "THERMAL_THRESHOLD": \ - "Unknown decode" )))))) : \ + ((x) == 0x6 ? "DUAL_DATA_RATE_NOT_SUPPORTED": \ + "Unknown decode" ))))))) : \ "Unknown decode" ) @@ -12364,7 +12828,7 @@ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT /* Event specific data. */ uint32_t event_data2; - /* Current temperature. In Celsius */ + /* Current temperature. In Celsius */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK UINT32_C(0xff) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT 0 /* @@ -12430,6 +12894,60 @@ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING } hwrm_async_event_cmpl_error_report_thermal_t, *phwrm_async_event_cmpl_error_report_thermal_t; +/* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */ + +typedef struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT 0 + /* + * Speed change not supported with dual rate transceivers + * on this board. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED UINT32_C(0x6) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED +} hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported_t, *phwrm_async_event_cmpl_error_report_dual_data_rate_not_supported_t; + /* metadata_base_msg (size:64b/8B) */ typedef struct metadata_base_msg { @@ -12884,7 +13402,7 @@ uint32_t key_idx; /* * BD Index of next BD that will be used to transmit data - * on the TX ring mapped to this door bell. NIC may + * on the TX ring mapped to this door bell. NIC may * read and process all BDs up to, but not including this * index. */ @@ -12892,7 +13410,7 @@ #define TX_DOORBELL_IDX_SFT 0 /* * This value indicates the type of door bell operation - * that is begin requested. This value is '0' for TX + * that is begin requested. This value is '0' for TX * door bell operations. */ #define TX_DOORBELL_KEY_MASK UINT32_C(0xf0000000) @@ -12908,7 +13426,7 @@ uint32_t key_idx; /* * BD Index of next BD that will be used for an empty receive - * buffer on the RX ring mapped to this door bell. NIC may + * buffer on the RX ring mapped to this door bell. NIC may * read and process all BDs up to, but not including this * index. */ @@ -12916,7 +13434,7 @@ #define RX_DOORBELL_IDX_SFT 0 /* * This value indicates the type of door bell operation - * that is begin requested. This value is '1' for RX + * that is begin requested. This value is '1' for RX * door bell operations. */ #define RX_DOORBELL_KEY_MASK UINT32_C(0xf0000000) @@ -12940,20 +13458,20 @@ #define CMPL_DOORBELL_IDX_SFT 0 /* * This indicates if the BDIDX value is valid for this - * update when it is '1'. When it is '0', the BDIDX + * update when it is '1'. When it is '0', the BDIDX * value should be ignored. */ #define CMPL_DOORBELL_IDX_VALID UINT32_C(0x4000000) /* * This bit indicates the new interrupt mask state for the - * interrupt associated with the BDIDX. A '1', means the - * interrupt is to be masked. A '0' indicates the interrupt + * interrupt associated with the BDIDX. A '1', means the + * interrupt is to be masked. A '0' indicates the interrupt * is to be unmasked. */ #define CMPL_DOORBELL_MASK UINT32_C(0x8000000) /* * This value indicates the type of door bell operation - * that is begin requested. This value is '2' for CMP + * that is begin requested. This value is '2' for CMP * door bell operations. */ #define CMPL_DOORBELL_KEY_MASK UINT32_C(0xf0000000) @@ -12980,7 +13498,7 @@ #define STATUS_DOORBELL_IDX_SFT 0 /* * This value indicates the type of door bell operation - * that is begin requested. This value is '3' for Status + * that is begin requested. This value is '3' for Status * door bell operations. */ #define STATUS_DOORBELL_KEY_MASK UINT32_C(0xf0000000) @@ -13007,14 +13525,14 @@ * A value of 1 is invalid since backup must start with a * long 32B BE. * A value of 2 indicates just the first 32B BE. - * A value of 3 indicates 32B+16B BD. etc. + * A value of 3 indicates 32B+16B BD. etc. * A value of 0 indicates 16x16B BD spaces are consumed. */ #define PUSH32_DOORBELL_SZ_MASK UINT32_C(0xf000000) #define PUSH32_DOORBELL_SZ_SFT 24 /* * This value indicates the type of door bell operation - * that is begin requested. This value is 4 for push + * that is begin requested. This value is 4 for push * door bell operations. */ #define PUSH32_DOORBELL_KEY_MASK UINT32_C(0xf0000000) @@ -13041,7 +13559,7 @@ #define PUSH32_DOORBELL_FLAGS_SFT 6 /* * If set to 1, the packet ends with the data in the buffer - * pointed to by this descriptor. This flag must be + * pointed to by this descriptor. This flag must be * valid on every BD. * * This bit must be set on all push doorbells. @@ -13142,9 +13660,9 @@ * * This bit must be valid on the first BD of a packet. * - * Packet must be 64B or longer when this flag is set. It is not + * Packet must be 64B or longer when this flag is set. It is not * useful to use this bit with any form of TX offload such as - * CSO or LSO. The intent is that the packet from the host already + * CSO or LSO. The intent is that the packet from the host already * has a valid Ethernet CRC on the packet. */ #define PUSH32_DOORBELL_LFLAGS_NOCRC UINT32_C(0x4) @@ -13161,21 +13679,21 @@ * of the packet associated with this descriptor. * * For outer UDP checksum, global outer UDP checksum TE_NIC register - * needs to be enabled. If the global outer UDP checksum TE_NIC register - * bit is set, outer UDP checksum will be calculated for the following - * cases: - * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner - * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for - * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP - * checksum will not be calculated. - * 2. Packets with lso flag set which implies inner TCP checksum calculation - * as part of LSO operation. + * needs to be enabled. If the global outer UDP checksum TE_NIC + * register bit is set, outer UDP checksum will be calculated for the + * following cases: + * 1. Packets with tcp_udp_chksum flag set to offload checksum for + * inner packet AND the inner packet is TCP/UDP. If the inner packet is + * ICMP for example (non-TCP/UDP), even if the tcp_udp_chksum is set, + * the outer UDP checksum will not be calculated. + * 2. Packets with lso flag set which implies inner TCP checksum + * calculation as part of LSO operation. */ #define PUSH32_DOORBELL_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) /* * If set to 1, the device will treat this packet with LSO(Large * Send Offload) processing for both normal or encapsulated - * packets, which is a form of TCP segmentation. When this bit + * packets, which is a form of TCP segmentation. When this bit * is 1, the hdr_size and mss fields must be valid. The driver * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum * flags since the controller will replace the appropriate @@ -13190,7 +13708,7 @@ * 0xffff. * * If set to one when LSO is '1', then the IPID will be treated - * as a 15b number and will be wrapped if it exceeds a value 0f + * as a 15b number and will be wrapped if it exceeds a value of * 0x7fff. */ #define PUSH32_DOORBELL_LFLAGS_IPID_FMT UINT32_C(0x40) @@ -13208,12 +13726,12 @@ #define PUSH32_DOORBELL_LFLAGS_T_IPID UINT32_C(0x80) /* * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * packet. Packet must be a valid RoCE format packet. */ #define PUSH32_DOORBELL_LFLAGS_ROCE_CRC UINT32_C(0x100) /* * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * packet. Packet must be a valid FCoE format packet. */ #define PUSH32_DOORBELL_LFLAGS_FCOE_CRC UINT32_C(0x200) uint16_t hdr_size; @@ -13296,7 +13814,7 @@ #define PUSH32_DOORBELL_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) #define PUSH32_DOORBELL_CFA_META_KEY_LAST PUSH32_DOORBELL_CFA_META_KEY_VLAN_TAG /* - * This is the data for the push packet. If the packet + * This is the data for the push packet. If the packet * data does not fit in the first pass, data writing * can continue at offset 4 of the doorbell for up to 4 additional * passes for a total data size of 512B maximum. @@ -13350,8 +13868,8 @@ * The ID of the VF that this PF is trying to reset. * Only the parent PF shall be allowed to reset a child VF. * - * A parent PF driver shall use this field only when a specific child VF - * is requested to be reset. + * A parent PF driver shall use this field only when a specific child + * VF is requested to be reset. */ uint16_t vf_id; /* This value indicates the level of a function reset. */ @@ -13397,9 +13915,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13469,16 +13987,16 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * FID value. This value is used to identify operations on the PCI + * FID value. This value is used to identify operations on the PCI * bus as belonging to a particular PCI function. */ uint16_t fid; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13551,9 +14069,9 @@ uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13627,9 +14145,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13640,7 +14158,7 @@ ********************/ -/* hwrm_func_vf_cfg_input (size:512b/64B) */ +/* hwrm_func_vf_cfg_input (size:576b/72B) */ typedef struct hwrm_func_vf_cfg_input { /* The HWRM command request type. */ @@ -13676,12 +14194,12 @@ * This bit must be '1' for the mtu field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU UINT32_C(0x1) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU UINT32_C(0x1) /* * This bit must be '1' for the guest_vlan field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN UINT32_C(0x2) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN UINT32_C(0x2) /* * This bit must be '1' for the async_event_cr field to be * configured. @@ -13691,7 +14209,7 @@ * This bit must be '1' for the dflt_mac_addr field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x8) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x8) /* * This bit must be '1' for the num_rsscos_ctxs field to be * configured. @@ -13706,17 +14224,17 @@ * This bit must be '1' for the num_tx_rings field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS UINT32_C(0x40) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS UINT32_C(0x40) /* * This bit must be '1' for the num_rx_rings field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS UINT32_C(0x80) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS UINT32_C(0x80) /* * This bit must be '1' for the num_l2_ctxs field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS UINT32_C(0x100) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS UINT32_C(0x100) /* * This bit must be '1' for the num_vnics field to be * configured. @@ -13726,22 +14244,32 @@ * This bit must be '1' for the num_stat_ctxs field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS UINT32_C(0x400) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS UINT32_C(0x400) /* * This bit must be '1' for the num_hw_ring_grps field to be * configured. */ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS UINT32_C(0x800) /* - * This bit must be '1' for the num_tx_key_ctxs field to be - * configured. + * This bit must be '1' for the num_ktls_tx_key_ctxs field to + * be configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS UINT32_C(0x1000) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_TX_KEY_CTXS UINT32_C(0x1000) /* - * This bit must be '1' for the num_rx_key_ctxs field to be - * configured. + * This bit must be '1' for the num_ktls_rx_key_ctxs field to + * be configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_RX_KEY_CTXS UINT32_C(0x2000) + /* + * This bit must be '1' for the num_quic_tx_key_ctxs field to + * be configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_TX_KEY_CTXS UINT32_C(0x4000) + /* + * This bit must be '1' for the num_quic_rx_key_ctxs field to + * be configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS UINT32_C(0x2000) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_RX_KEY_CTXS UINT32_C(0x8000) /* * The maximum transmission unit requested on the function. * The HWRM should make sure that the mtu of @@ -13804,10 +14332,10 @@ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST UINT32_C(0x2) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of CMPL rings) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST UINT32_C(0x4) /* @@ -13820,10 +14348,10 @@ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST UINT32_C(0x8) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of ring groups) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST UINT32_C(0x10) /* @@ -13881,11 +14409,17 @@ uint16_t num_stat_ctxs; /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; - /* Number of Tx Key Contexts requested. */ - uint32_t num_tx_key_ctxs; - /* Number of Rx Key Contexts requested. */ - uint32_t num_rx_key_ctxs; - uint8_t unused[4]; + /* Number of KTLS Tx Key Contexts requested. */ + uint32_t num_ktls_tx_key_ctxs; + /* Number of KTLS Rx Key Contexts requested. */ + uint32_t num_ktls_rx_key_ctxs; + /* The number of MSI-X vectors requested for the VF. */ + uint16_t num_msix; + uint8_t unused[2]; + /* Number of QUIC Tx Key Contexts requested. */ + uint32_t num_quic_tx_key_ctxs; + /* Number of QUIC Rx Key Contexts requested. */ + uint32_t num_quic_rx_key_ctxs; } hwrm_func_vf_cfg_input_t, *phwrm_func_vf_cfg_input_t; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -13902,9 +14436,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13957,7 +14491,7 @@ uint8_t unused_0[6]; } hwrm_func_qcaps_input_t, *phwrm_func_qcaps_input_t; -/* hwrm_func_qcaps_output (size:768b/96B) */ +/* hwrm_func_qcaps_output (size:1088b/136B) */ typedef struct hwrm_func_qcaps_output { /* The specific error status for the command. */ @@ -13969,7 +14503,7 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * FID value. This value is used to identify operations on the PCI + * FID value. This value is used to identify operations on the PCI * bus as belonging to a particular PCI function. */ uint16_t fid; @@ -14100,7 +14634,8 @@ /* * If the query is for a VF, then this flag shall be ignored, * If this query is for a PF and this flag is set to 1, - * then the PF has the administrative privilege to configure another PF + * then the PF has the administrative privilege to configure another + * PF. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED UINT32_C(0x40000) /* @@ -14512,7 +15047,7 @@ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED UINT32_C(0x2) /* * When this bit is '1', it indicates that KDNet mode is - * supported on the port for this function. This bit is + * supported on the port for this function. This bit is * never set for a VF. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KDNET_SUPPORTED UINT32_C(0x4) @@ -14567,12 +15102,114 @@ /* * When this bit is '1', it indicates that the hardware based * link aggregation group (L2 and RoCE) feature is supported. + * This LAG feature is only supported on the THOR2 or newer NIC + * with multiple ports. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HW_LAG_SUPPORTED UINT32_C(0x400) - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED UINT32_C(0x800) - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_STEERING_TAG_SUPPORTED UINT32_C(0x1000) - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED UINT32_C(0x2000) - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED UINT32_C(0x4000) + /* + * When this bit is '1', it indicates all contexts can be stored + * on chip instead of using host based backing store memory. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED UINT32_C(0x800) + /* + * When this bit is '1', it indicates that the HW supports + * using a steering tag in the memory transactions targeting + * L2 or RoCE ring resources. + * Steering Tags are system-specific values that must follow the + * encoding requirements of the hardware platform. On devices that + * support steering to multiple address domains, a value of 0 in + * bit 0 of the steering tag specifies the address is associated + * with the SOC address space, and a value of 1 indicates the + * address is associated with the host address space. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_STEERING_TAG_SUPPORTED UINT32_C(0x1000) + /* + * When this bit is '1', it indicates that driver can enable + * support for an enhanced VF scale. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED UINT32_C(0x2000) + /* + * When this bit is '1', it indicates that FW is capable of + * supporting partition based XID management for KTLS/QUIC + * Tx/Rx Key Context types. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED UINT32_C(0x4000) + /* + * This bit is only valid on the condition that both + * 'ktls_supported' and 'quic_supported' flags are set. When this + * bit is valid, it conveys information below: + * 1. If it is set to '1', it indicates that the firmware allows the + * driver to run KTLS and QUIC concurrently; + * 2. If it is cleared to '0', it indicates that the driver has to + * make sure all crypto connections on all functions are of the + * same type, i.e., either KTLS or QUIC. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED UINT32_C(0x8000) + /* + * When this bit is '1', it indicates that the device supports + * setting a cross TC cap on a scheduler queue. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED UINT32_C(0x10000) + /* + * When this bit is '1', it indicates that the device supports + * setting a per TC cap on a scheduler queue. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED UINT32_C(0x20000) + /* + * When this bit is '1', it indicates that the device supports + * setting a per TC reservation on a scheduler queues. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED UINT32_C(0x40000) + /* + * When this bit is '1', it indicates that firmware supports query + * for statistics related to invalid doorbell errors and drops. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED UINT32_C(0x80000) + /* + * When this bit is '1', it indicates that the device supports + * VF RoCE resource management. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED UINT32_C(0x100000) + /* + * When this bit is '1', it indicates that the device supports + * UDCC management. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDCC_SUPPORTED UINT32_C(0x200000) + /* + * When this bit is '1', it indicates that the device supports Timed + * Transmit TxTime scheduling; this is applicable to L2 flows only. + * It is expected that host software assigns each packet a transmit + * time and posts packets for transmit in time order. NIC hardware + * transmits the packet at time assigned by software. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED UINT32_C(0x400000) + /* + * This bit indicates the method used for the advertisement of the + * max resource limit for the PF and its VFs. + * When this bit is '1', it indicates that the maximum resource + * limits for both RoCE and L2 are software defined. These limits + * are queried using the HWRM backing store qcaps v1 + * and v2(max_num_entries). For RoCE, the resource limits are + * derived from nvm options. For L2, the resources will continue + * to use FW enforced SW limits based on chip config and per PF + * function NVM resource parameters. + * If this bit is '0', the FW will use to legacy behavior. + * For RoCE, the maximum resource values supported by the chip will + * be returned. For L2, the maximum resource values returned will + * be the FW enforced SW limits based on chip config and per PF + * function NVM resource parameters. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED UINT32_C(0x800000) + /* + * When this bit is '1', it indicates that the device supports + * migrating ingress NIC flows to Truflow. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED UINT32_C(0x1000000) + /* + * When this bit is '1', it indicates that the Firmware supports + * query and clear of the port loopback statistics. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_LPBK_STATS_SUPPORTED UINT32_C(0x2000000) uint16_t tunnel_disable_flag; /* * When this bit is '1', it indicates that the VXLAN parsing @@ -14614,10 +15251,79 @@ * is disabled in hardware */ #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE UINT32_C(0x80) - uint8_t unused_1; + uint16_t xid_partition_cap; + /* + * When this bit is '1', it indicates that FW is capable of + * supporting partition based XID management for Tx crypto + * key contexts. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_TX_CK UINT32_C(0x1) + /* + * When this bit is '1', it indicates that FW is capable of + * supporting partition based XID management for Rx crypto + * key contexts. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_RX_CK UINT32_C(0x2) + /* + * This value uniquely identifies the hardware NIC used by the + * function. The value returned will be the same for all functions. + * A value of 00-00-00-00-00-00-00-00 indicates no device serial number + * is currently configured. This is the same value that is returned by + * PCIe Capability Device Serial Number. + */ + uint8_t device_serial_number[8]; + /* + * This field is only valid in the XID partition mode. It indicates + * the number contexts per partition. + */ + uint16_t ctxs_per_partition; + uint8_t unused_2[2]; + /* + * The maximum number of address vectors that may be allocated across + * all VFs for the function. This is valid only on the PF with VF RoCE + * (SR-IOV) enabled. Returns zero if this command is called on a PF + * with VF RoCE (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_av; + /* + * The maximum number of completion queues that may be allocated across + * all VFs for the function. This is valid only on the PF with VF RoCE + * (SR-IOV) enabled. Returns zero if this command is called on a PF + * with VF RoCE (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_cq; + /* + * The maximum number of memory regions plus memory windows that may be + * allocated across all VFs for the function. This is valid only on the + * PF with VF RoCE (SR-IOV) enabled. Returns zero if this command is + * called on a PF with VF RoCE (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_mrw; + /* + * The maximum number of queue pairs that may be allocated across + * all VFs for the function. This is valid only on the PF with VF RoCE + * (SR-IOV) enabled. Returns zero if this command is called on a PF + * with VF RoCE (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_qp; + /* + * The maximum number of shared receive queues that may be allocated + * across all VFs for the function. This is valid only on the PF with + * VF RoCE (SR-IOV) enabled. Returns zero if this command is called on + * a PF with VF RoCE (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_srq; + /* + * The maximum number of GIDs that may be allocated across all VFs for + * the function. This is valid only on the PF with VF RoCE (SR-IOV) + * enabled. Returns zero if this command is called on a PF with VF RoCE + * (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_gid; + uint8_t unused_3[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -14673,7 +15379,7 @@ uint8_t unused_0[6]; } hwrm_func_qcfg_input_t, *phwrm_func_qcfg_input_t; -/* hwrm_func_qcfg_output (size:1024b/128B) */ +/* hwrm_func_qcfg_output (size:1280b/160B) */ typedef struct hwrm_func_qcfg_output { /* The specific error status for the command. */ @@ -14685,7 +15391,7 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * FID value. This value is used to identify operations on the PCI + * FID value. This value is used to identify operations on the PCI * bus as belonging to a particular PCI function. */ uint16_t fid; @@ -14752,14 +15458,14 @@ * If the function that is being queried is a PF, then the HWRM shall * set this field to 0 and the HWRM client shall ignore this field. * If the function that is being queried is a VF, then the HWRM shall - * set this field to 1 if the queried VF is trusted, otherwise the HWRM - * shall set this field to 0. + * set this field to 1 if the queried VF is trusted, otherwise the + * HWRM shall set this field to 0. */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF UINT32_C(0x40) /* - * If set to 1, then secure mode is enabled for this function or device. - * If set to 0, then secure mode is disabled (or normal mode) for this - * function or device. + * If set to 1, then secure mode is enabled for this function or + * device. If set to 0, then secure mode is disabled (or normal mode) + * for this function or device. */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED UINT32_C(0x80) /* @@ -14813,6 +15519,12 @@ * If set to 0, RoCE is disabled on all child VFs. */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV UINT32_C(0x4000) + /* + * When set to 1, indicates the field roce_vnic_id in the structure + * is valid. If this bit is 0, the driver should not use the + * 'roce_vnic_id' field. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ROCE_VNIC_ID_VALID UINT32_C(0x8000) /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no @@ -14894,10 +15606,10 @@ #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN UINT32_C(0xff) #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN /* - * This field will indicate number of physical functions on this port_partition. - * HWRM shall return unavail (i.e. value of 0) for this field - * when this command is used to query VF's configuration or - * from older firmware that doesn't support this field. + * This field will indicate number of physical functions on this + * port_partition. HWRM shall return unavail (i.e. value of 0) for this + * field when this command is used to query VF's configuration or from + * older firmware that doesn't support this field. */ uint8_t port_pf_cnt; /* number of PFs is not available */ @@ -15005,7 +15717,10 @@ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (UINT32_C(0x0) << 2) /* Admin link state is in forced up mode. */ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (UINT32_C(0x1) << 2) - /* Admin link state is in auto mode - follows the physical link state. */ + /* + * Admin link state is in auto mode - follows the physical link + * state. + */ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO (UINT32_C(0x2) << 2) #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO /* Reserved for future. */ @@ -15047,7 +15762,7 @@ */ uint16_t alloc_msix; /* - * The number of registered VF’s associated with the PF. This field + * The number of registered VF's associated with the PF. This field * should be ignored when the request received on the VF interface. * This field will be updated on the PF interface to initiate * the unregister request on PF in the HOT Reset Process. @@ -15055,14 +15770,22 @@ uint16_t registered_vfs; /* * The size of the doorbell BAR in KBytes reserved for L2 including - * any area that is shared between L2 and RoCE. The L2 driver - * should only map the L2 portion of the doorbell BAR. Any rounding + * any area that is shared between L2 and RoCE. The L2 driver + * should only map the L2 portion of the doorbell BAR. Any rounding * of the BAR size to the native CPU page size should be performed - * by the driver. If the value is zero, no special partitioning + * by the driver. If the value is zero, no special partitioning * of the doorbell BAR between L2 and RoCE is required. */ uint16_t l2_doorbell_bar_size_kb; - uint8_t unused_1; + /* + * A bitmask indicating the active endpoints. Each bit represents a + * specific endpoint, with bit 0 indicating EP 0 and bit 3 indicating + * EP 3. For example: + * - a single root system would return 0x1 + * - a 2x8 system (where EPs 0 and 2 are active) would return 0x5 + * - a 4x4 system (where EPs 0-3 are active) would return 0xF + */ + uint8_t active_endpoints; /* * For backward compatibility this field must be set to 1. * Older drivers might look for this field to be 1 before @@ -15070,21 +15793,22 @@ */ uint8_t always_1; /* - * This GRC address location is used by the Host driver interfaces to poll - * the adapter ready state to re-initiate the registration process again - * after receiving the RESET Notify event. + * This GRC address location is used by the Host driver interfaces to + * poll the adapter ready state to re-initiate the registration process + * again after receiving the RESET Notify event. */ uint32_t reset_addr_poll; /* - * This field specifies legacy L2 doorbell size in KBytes. Drivers should use - * this value to find out the doorbell page offset from the BAR. + * This field specifies legacy L2 doorbell size in KBytes. Drivers + * should use this value to find out the doorbell page offset from the + * BAR. */ uint16_t legacy_l2_db_size_kb; uint16_t svif_info; /* - * This field specifies the source virtual interface of the function being - * queried. Drivers can use this to program svif field in the L2 context - * table + * This field specifies the source virtual interface of the function + * being queried. Drivers can use this to program svif field in the + * L2 context table */ #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff) #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0 @@ -15146,7 +15870,11 @@ /* DB page size is 4MB. */ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa) #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_LAST HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB - uint8_t unused_2[2]; + /* + * RoCE VNIC ID for the function. If the function does not have a valid + * RoCE vnic id, then the roce_vnic_id_valid bit in flags is set to 0. + */ + uint16_t roce_vnic_id; /* * Minimum guaranteed bandwidth for the network partition made up * of the caller physical function and all its child virtual @@ -15216,7 +15944,7 @@ uint8_t unused_3[2]; uint8_t unused_4[2]; /* - * KDNet mode for the port for this function. If a VF, KDNet + * KDNet mode for the port for this function. If a VF, KDNet * mode is always disabled. */ uint8_t port_kdnet_mode; @@ -15231,22 +15959,92 @@ */ uint8_t kdnet_pcie_function; /* - * Function ID of the KDNET function on this port. If the + * Function ID of the KDNET function on this port. If the * KDNET partition does not exist and the FW supports this * feature, 0xffff will be returned. */ uint16_t port_kdnet_fid; uint8_t unused_5[2]; - /* Number of Tx Key Contexts allocated. */ - uint32_t alloc_tx_key_ctxs; - /* Number of Rx Key Contexts allocated. */ - uint32_t alloc_rx_key_ctxs; - uint8_t unused_6[7]; + /* Number of KTLS Tx Key Contexts allocated. */ + uint32_t num_ktls_tx_key_ctxs; + /* Number of KTLS Rx Key Contexts allocated. */ + uint32_t num_ktls_rx_key_ctxs; + /* + * The LAG idx of this function. The lag_id is per port and the + * valid lag_id is from 0 to 7, if there is no valid lag_id, + * 0xff will be returned. + * This HW lag id is used for Truflow programming only. + */ + uint8_t lag_id; + /* Partition interface for this function. */ + uint8_t parif; + /* + * The LAG ID of a hardware link aggregation group (LAG) whose + * member ports include the port of this function. The LAG was + * previously created using HWRM_FUNC_LAG_CREATE. If the port of this + * function is not a member of any LAG, the fw_lag_id will be 0xff. + */ + uint8_t fw_lag_id; + uint8_t unused_6; + /* Number of QUIC Tx Key Contexts allocated. */ + uint32_t num_quic_tx_key_ctxs; + /* Number of QUIC Rx Key Contexts allocated. */ + uint32_t num_quic_rx_key_ctxs; + /* + * Number of AVs per VF. Only valid for PF. This field is ignored + * when the flag, l2_vf_resource_mgmt, is not set in RoCE + * initialize_fw. + */ + uint32_t roce_max_av_per_vf; + /* + * Number of CQs per VF. Only valid for PF. This field is ignored when + * the flag, l2_vf_resource_mgmt, is not set in RoCE initialize_fw. + */ + uint32_t roce_max_cq_per_vf; + /* + * Number of MR/MWs per VF. Only valid for PF. This field is ignored + * when the flag, l2_vf_resource_mgmt, is not set in RoCE + * initialize_fw. + */ + uint32_t roce_max_mrw_per_vf; + /* + * Number of QPs per VF. Only valid for PF. This field is ignored when + * the flag, l2_vf_resource_mgmt, is not set in RoCE initialize_fw. + */ + uint32_t roce_max_qp_per_vf; + /* + * Number of SRQs per VF. Only valid for PF. This field is ignored + * when the flag, l2_vf_resource_mgmt, is not set in RoCE + * initialize_fw. + */ + uint32_t roce_max_srq_per_vf; + /* + * Number of GIDs per VF. Only valid for PF. This field is ignored + * when the flag, l2_vf_resource_mgmt, is not set in RoCE + * initialize_fw. + */ + uint32_t roce_max_gid_per_vf; + /* + * Bitmap of context types that have XID partition enabled. + * Only valid for PF. + */ + uint16_t xid_partition_cfg; + /* + * When this bit is '1', it indicates that driver enables XID + * partition on Tx crypto key contexts. + */ + #define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_TX_CK UINT32_C(0x1) + /* + * When this bit is '1', it indicates that driver enables XID + * partition on Rx crypto key contexts. + */ + #define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_RX_CK UINT32_C(0x2) + uint8_t unused_7; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -15257,7 +16055,7 @@ *****************/ -/* hwrm_func_cfg_input (size:1024b/128B) */ +/* hwrm_func_cfg_input (size:1280b/160B) */ typedef struct hwrm_func_cfg_input { /* The HWRM command request type. */ @@ -15350,9 +16148,10 @@ #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST UINT32_C(0x800) /* * This bit only applies to the VF. If this bit is set, the statistic - * context counters will not be cleared when the statistic context is freed - * or a function reset is called on VF. This bit will be cleared when the PF - * is unloaded or a function reset is called on the PF. + * context counters will not be cleared when the statistic context is + * freed or a function reset is called on VF. This bit will be + * cleared when the PF is unloaded or a function reset is called on + * the PF. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC UINT32_C(0x1000) /* @@ -15373,10 +16172,10 @@ #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST UINT32_C(0x4000) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of CMPL rings) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST UINT32_C(0x8000) /* @@ -15389,10 +16188,10 @@ #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST UINT32_C(0x10000) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of ring groups) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST UINT32_C(0x20000) /* @@ -15497,14 +16296,6 @@ * on this request if the TX_METADATA is enabled for this function. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE UINT32_C(0x40000000) - /* - * If this bit is set to 1, the driver is requesting FW to see if - * all the assets requested in this command (i.e. number of KTLS/ - * QUIC key contexts) are available. The firmware will return an - * error if the requested assets are not available. The firmware - * will NOT reserve the assets if they are available. - */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_KEY_CTX_ASSETS_TEST UINT32_C(0x80000000) uint32_t enables; /* * This bit must be '1' for the admin_mtu field to be @@ -15658,15 +16449,15 @@ */ #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU UINT32_C(0x20000000) /* - * This bit must be '1' for the number of Tx Key Contexts - * field to be configured. + * This bit must be '1' for the num_ktls_tx_key_ctxs field to be + * configured. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS UINT32_C(0x40000000) + #define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_TX_KEY_CTXS UINT32_C(0x40000000) /* - * This bit must be '1' for the number of Rx Key Contexts - * field to be configured. + * This bit must be '1' for the num_ktls_rx_key_ctxs field to be + * configured. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS UINT32_C(0x80000000) + #define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_RX_KEY_CTXS UINT32_C(0x80000000) /* * This field can be used by the admin PF to configure * mtu of foster PFs. @@ -15858,7 +16649,7 @@ * to configure the EVB mode, it sets the evb_mode_cfg_not_supported * flag in HWRM_FUNC_QCAPS command response for the function. * The HWRM takes into account the switching of EVB mode from one to - * another and reconfigure hardware resources as reqiured. The + * another and reconfigure hardware resources as required. The * switching from VEB to VEPA mode requires the disabling of the * loopback traffic. Additionally, source knockouts are handled * differently in VEB and VEPA modes. @@ -15891,7 +16682,10 @@ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (UINT32_C(0x0) << 2) /* Admin state is forced up. */ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (UINT32_C(0x1) << 2) - /* Admin state is in auto mode - is to follow the physical link state. */ + /* + * Admin state is in auto mode - is to follow the physical link + * state. + */ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO (UINT32_C(0x2) << 2) #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO /* Reserved for future. */ @@ -15908,61 +16702,61 @@ /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the TX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the TX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the RX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the RX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the TX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE UINT32_C(0x10) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the TX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE UINT32_C(0x20) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the RX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE UINT32_C(0x40) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the RX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE UINT32_C(0x80) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the primate processor block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE UINT32_C(0x100) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the primate processor block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE UINT32_C(0x200) /* @@ -16050,7 +16844,23 @@ * ring that is assigned to a function has a valid mtu. */ uint16_t host_mtu; - uint8_t unused_0[4]; + uint32_t flags2; + /* + * If this bit is set to 1, the driver is requesting the firmware + * to see if the assets (i.e., the number of KTLS key contexts) + * requested in this command are available. The firmware will return + * an error if the requested assets are not available. The firmware + * will NOT reserve the assets if they are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST UINT32_C(0x1) + /* + * If this bit is set to 1, the driver is requesting the firmware + * to see if the assets (i.e., the number of QUIC key contexts) + * requested in this command are available. The firmware will return + * an error if the requested assets are not available. The firmware + * will NOT reserve the assets if they are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST UINT32_C(0x2) uint32_t enables2; /* * This bit must be '1' for the kdnet_mode field to be @@ -16062,10 +16872,55 @@ * configured. Legacy controller core FW may silently ignore * the db_page_size programming request through this command. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2) + #define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2) + /* + * This bit must be '1' for the num_quic_tx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_TX_KEY_CTXS UINT32_C(0x4) + /* + * This bit must be '1' for the num_quic_rx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_RX_KEY_CTXS UINT32_C(0x8) + /* + * This bit must be '1' for the roce_max_av_per_vf field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_AV_PER_VF UINT32_C(0x10) + /* + * This bit must be '1' for the roce_max_cq_per_vf field to be + * configured. Only valid for PF. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_CQ_PER_VF UINT32_C(0x20) + /* + * This bit must be '1' for the roce_max_mrw_per_vf field to be + * configured. Only valid for PF. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_MRW_PER_VF UINT32_C(0x40) /* - * KDNet mode for the port for this function. If NPAR is - * also configured on this port, it takes precedence. KDNet + * This bit must be '1' for the roce_max_qp_per_vf field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_QP_PER_VF UINT32_C(0x80) + /* + * This bit must be '1' for the roce_max_srq_per_vf field to be + * configured. Only valid for PF. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_SRQ_PER_VF UINT32_C(0x100) + /* + * This bit must be '1' for the roce_max_gid_per_vf field to be + * configured. Only valid for PF. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_GID_PER_VF UINT32_C(0x200) + /* + * This bit must be '1' for the xid_partition_cfg field to be + * configured. Only valid for PF. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_XID_PARTITION_CFG UINT32_C(0x400) + /* + * KDNet mode for the port for this function. If NPAR is + * also configured on this port, it takes precedence. KDNet * mode is ignored for a VF. */ uint8_t port_kdnet_mode; @@ -16108,11 +16963,42 @@ #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa) #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_LAST HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB uint8_t unused_1[2]; - /* Number of Tx Key Contexts requested. */ - uint32_t num_tx_key_ctxs; - /* Number of Rx Key Contexts requested. */ - uint32_t num_rx_key_ctxs; - uint8_t unused_2[4]; + /* Number of KTLS Tx Key Contexts requested. */ + uint32_t num_ktls_tx_key_ctxs; + /* Number of KTLS Rx Key Contexts requested. */ + uint32_t num_ktls_rx_key_ctxs; + /* Number of QUIC Tx Key Contexts requested. */ + uint32_t num_quic_tx_key_ctxs; + /* Number of QUIC Rx Key Contexts requested. */ + uint32_t num_quic_rx_key_ctxs; + /* Number of AVs per VF. Only valid for PF. */ + uint32_t roce_max_av_per_vf; + /* Number of CQs per VF. Only valid for PF. */ + uint32_t roce_max_cq_per_vf; + /* Number of MR/MWs per VF. Only valid for PF. */ + uint32_t roce_max_mrw_per_vf; + /* Number of QPs per VF. Only valid for PF. */ + uint32_t roce_max_qp_per_vf; + /* Number of SRQs per VF. Only valid for PF. */ + uint32_t roce_max_srq_per_vf; + /* Number of GIDs per VF. Only valid for PF. */ + uint32_t roce_max_gid_per_vf; + /* + * Bitmap of context types that have XID partition enabled. + * Only valid for PF. + */ + uint16_t xid_partition_cfg; + /* + * When this bit is '1', it indicates that driver enables XID + * partition on Tx crypto key contexts. + */ + #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_TX_CK UINT32_C(0x1) + /* + * When this bit is '1', it indicates that driver enables XID + * partition on Rx crypto key contexts. + */ + #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_RX_CK UINT32_C(0x2) + uint16_t unused_2; } hwrm_func_cfg_input_t, *phwrm_func_cfg_input_t; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -16129,9 +17015,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16245,7 +17131,7 @@ uint64_t tx_bcast_pkts; /* * Number of transmitted packets that were discarded due to - * internal NIC resource problems. For transmit, this + * internal NIC resource problems. For transmit, this * can only happen if TMP is configured to allow dropping * in HOL blocking conditions, which is not a normal * configuration. @@ -16272,7 +17158,7 @@ uint64_t rx_bcast_pkts; /* * Number of received packets that were discarded on the function - * due to resource limitations. This can happen for 3 reasons. + * due to resource limitations. This can happen for 3 reasons. * # The BD used for the packet has a bad format. * # There were no BDs available in the ring for the packet. * # There were no BDs available on-chip for the packet. @@ -16303,7 +17189,7 @@ * cleared. Firmware starts the sequence from zero. It increments * the sequence number every time the statistics of the function * are cleared, which can be triggered by a clear statistics request - * or by freeing all statistics contexts of the function. If an user + * or by freeing all statistics contexts of the function. If a user * is interested in knowing if the statistics have been cleared * since the last query, it can keep track of this sequence number * between queries. @@ -16312,9 +17198,9 @@ uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16453,9 +17339,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16520,9 +17406,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16586,9 +17472,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16660,14 +17546,15 @@ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4) /* * When this bit is '1', the function is indicating support of - * 64bit flow handle. The firmware that only supports 64bit flow + * 64bit flow handle. The firmware that only supports 64bit flow * handle should check this bit before allowing processing of - * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware - * with 64bit flow handle support can only be compatible with drivers - * that support 64bit flow handle. The legacy drivers that don't support - * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when - * running with new firmware that only supports 64bit flow handle. The new - * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED + * HWRM_CFA_FLOW_XXX commands from the requesting function as + * firmware with 64bit flow handle support can only be compatible + * with drivers that support 64bit flow handle. The legacy drivers + * that don't support 64bit flow handle won't be able to use + * HWRM_CFA_FLOW_XXX commands when running with new firmware that + * only supports 64bit flow handle. The new firmware support 64bit + * flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED * status to the legacy driver when encounters these commands. */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE UINT32_C(0x8) @@ -16695,11 +17582,12 @@ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT UINT32_C(0x20) /* * When this bit is 1, the function is indicating the support of the - * Master capability. The Firmware will use this capability to select the - * Master function. The master function will be used to initiate - * designated functionality like error recovery etc… If none of the - * registered PF’s or trusted VF’s indicate this support, then - * firmware will select the 1st registered PF as Master capable instance. + * Master capability. The Firmware will use this capability to select + * the Master function. The master function will be used to initiate + * designated functionality like error recovery etc. If none of the + * registered PF's or trusted VF's indicate this support, then + * firmware will select the 1st registered PF as Master capable + * instance. */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT UINT32_C(0x40) /* @@ -16735,6 +17623,14 @@ * corresponding queue configuration on the RX side */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT UINT32_C(0x400) + /* + * When this bit is 1, the function's driver is indicating to the + * firmware that the Ingress NIC flows will be programmed by the + * TruFlow application and the firmware flow manager should reject + * flow-create commands that programs ingress lookup flows for this + * function. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_TF_INGRESS_NIC_FLOW_MODE UINT32_C(0x800) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -16761,7 +17657,10 @@ * configured. */ #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD UINT32_C(0x10) - /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ + /* + * This value indicates the type of OS. The values are based on + * CIM_OperatingSystem.mof file as published by the DMTF. + */ uint16_t os_type; /* Unknown */ #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) @@ -16859,9 +17758,9 @@ uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16926,9 +17825,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17062,9 +17961,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17134,9 +18033,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17186,7 +18085,17 @@ * function. */ uint16_t fid; - uint8_t unused_0[2]; + /* + * This field is used to indicate the driver type. + * L2 or RoCE + */ + uint8_t driver_type; + /* L2 driver version */ + #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_L2 UINT32_C(0x0) + /* RoCE driver version */ + #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_ROCE UINT32_C(0x1) + #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_LAST HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_ROCE + uint8_t unused_0; } hwrm_func_drv_qver_input_t, *phwrm_func_drv_qver_input_t; /* hwrm_func_drv_qver_output (size:256b/32B) */ @@ -17200,7 +18109,10 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ + /* + * This value indicates the type of OS. The values are based on + * CIM_OperatingSystem.mof file as published by the DMTF. + */ uint16_t os_type; /* Unknown */ #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) @@ -17243,9 +18155,9 @@ uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17296,7 +18208,7 @@ uint8_t unused_0[6]; } hwrm_func_resource_qcaps_input_t, *phwrm_func_resource_qcaps_input_t; -/* hwrm_func_resource_qcaps_output (size:576b/72B) */ +/* hwrm_func_resource_qcaps_output (size:704b/88B) */ typedef struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ @@ -17307,13 +18219,22 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */ + /* + * Maximum guaranteed number of VFs supported by PF. Not applicable for + * VFs. + */ uint16_t max_vfs; - /* Maximum guaranteed number of MSI-X vectors supported by function */ + /* Maximum guaranteed number of MSI-X vectors supported by function. */ uint16_t max_msix; - /* Hint of strategy to be used by PF driver to reserve resources for its VF */ + /* + * Hint of strategy to be used by PF driver to reserve resources for + * its VF. + */ uint16_t vf_reservation_strategy; - /* The PF driver should evenly divide its remaining resources among all VFs. */ + /* + * The PF driver should evenly divide its remaining resources among + * all VFs. + */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL UINT32_C(0x0) /* The PF driver should only reserve minimal resources for each VF. */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL UINT32_C(0x1) @@ -17323,7 +18244,7 @@ */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC UINT32_C(0x2) #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC - /* Minimum guaranteed number of RSS/COS contexts */ + /* Minimum guaranteed number of RSS/COS contexts. */ uint16_t min_rsscos_ctx; /* Maximum non-guaranteed number of RSS/COS contexts */ uint16_t max_rsscos_ctx; @@ -17356,32 +18277,42 @@ /* Maximum non-guaranteed number of ring groups */ uint16_t max_hw_ring_grps; /* - * Maximum number of inputs into the transmit scheduler for this function. - * The number of TX rings assigned to the function cannot exceed this value. + * Maximum number of inputs into the transmit scheduler for this + * function. The number of TX rings assigned to the function cannot + * exceed this value. */ uint16_t max_tx_scheduler_inputs; uint16_t flags; /* * When this bit is '1', it indicates that VF_RESOURCE_CFG supports - * feature to reserve all minimum resources when minimum >= 1, otherwise - * returns an error. + * feature to reserve all minimum resources when minimum >= 1, + * otherwise returns an error. */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED UINT32_C(0x1) - uint8_t unused_0[2]; - /* Minimum guaranteed number of Tx Key Contexts */ - uint32_t min_tx_key_ctxs; - /* Maximum non-guaranteed number of Tx Key Contexts */ - uint32_t max_tx_key_ctxs; - /* Minimum guaranteed number of Rx Key Contexts */ - uint32_t min_rx_key_ctxs; - /* Maximum non-guaranteed number of Rx Key Contexts */ - uint32_t max_rx_key_ctxs; - uint8_t unused_1[3]; + /* Minimum guaranteed number of MSI-X vectors supported by function */ + uint16_t min_msix; + /* Minimum guaranteed number of KTLS Tx Key Contexts */ + uint32_t min_ktls_tx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Tx Key Contexts */ + uint32_t max_ktls_tx_key_ctxs; + /* Minimum guaranteed number of KTLS Rx Key Contexts */ + uint32_t min_ktls_rx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Rx Key Contexts */ + uint32_t max_ktls_rx_key_ctxs; + /* Minimum guaranteed number of QUIC Tx Key Contexts */ + uint32_t min_quic_tx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Tx Key Contexts */ + uint32_t max_quic_tx_key_ctxs; + /* Minimum guaranteed number of QUIC Rx Key Contexts */ + uint32_t min_quic_rx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Rx Key Contexts */ + uint32_t max_quic_rx_key_ctxs; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17392,7 +18323,7 @@ *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:576b/72B) */ +/* hwrm_func_vf_resource_cfg_input (size:704b/88B) */ typedef struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ @@ -17466,18 +18397,27 @@ * error, keep all existing reservations before the call. */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED UINT32_C(0x1) - uint8_t unused_0[2]; - /* Minimum guaranteed number of Tx Key Contexts */ - uint32_t min_tx_key_ctxs; - /* Maximum non-guaranteed number of Tx Key Contexts */ - uint32_t max_tx_key_ctxs; - /* Minimum guaranteed number of Rx Key Contexts */ - uint32_t min_rx_key_ctxs; - /* Maximum non-guaranteed number of Rx Key Contexts */ - uint32_t max_rx_key_ctxs; + /* Minimum guaranteed number of MSI-X vectors for the function */ + uint16_t min_msix; + /* Minimum guaranteed number of KTLS Tx Key Contexts */ + uint32_t min_ktls_tx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Tx Key Contexts */ + uint32_t max_ktls_tx_key_ctxs; + /* Minimum guaranteed number of KTLS Rx Key Contexts */ + uint32_t min_ktls_rx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Rx Key Contexts */ + uint32_t max_ktls_rx_key_ctxs; + /* Minimum guaranteed number of QUIC Tx Key Contexts */ + uint32_t min_quic_tx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Tx Key Contexts */ + uint32_t max_quic_tx_key_ctxs; + /* Minimum guaranteed number of QUIC Rx Key Contexts */ + uint32_t min_quic_rx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Rx Key Contexts */ + uint32_t max_quic_rx_key_ctxs; } hwrm_func_vf_resource_cfg_input_t, *phwrm_func_vf_resource_cfg_input_t; -/* hwrm_func_vf_resource_cfg_output (size:320b/40B) */ +/* hwrm_func_vf_resource_cfg_output (size:384b/48B) */ typedef struct hwrm_func_vf_resource_cfg_output { /* The specific error status for the command. */ @@ -17504,16 +18444,20 @@ uint16_t reserved_stat_ctx; /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; - /* Actual number of Tx Key Contexts reserved */ - uint32_t reserved_tx_key_ctxs; - /* Actual number of Rx Key Contexts reserved */ - uint32_t reserved_rx_key_ctxs; + /* Actual number of KTLS Tx Key Contexts reserved */ + uint32_t reserved_ktls_tx_key_ctxs; + /* Actual number of KTLS Rx Key Contexts reserved */ + uint32_t reserved_ktls_rx_key_ctxs; + /* Actual number of QUIC Tx Key Contexts reserved */ + uint32_t reserved_quic_tx_key_ctxs; + /* Actual number of QUIC Rx Key Contexts reserved */ + uint32_t reserved_quic_rx_key_ctxs; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17597,11 +18541,17 @@ uint16_t cq_entry_size; /* Maximum number of VNIC context entries supported for this function. */ uint16_t vnic_max_vnic_entries; - /* Maximum number of Ring table context entries supported for this function. */ + /* + * Maximum number of Ring table context entries supported for this + * function. + */ uint16_t vnic_max_ring_table_entries; /* Number of bytes that must be allocated for each context entry. */ uint16_t vnic_entry_size; - /* Maximum number of statistic context entries supported for this function. */ + /* + * Maximum number of statistic context entries supported for this + * function. + */ uint32_t stat_max_entries; /* Number of bytes that must be allocated for each context entry. */ uint16_t stat_entry_size; @@ -17623,7 +18573,8 @@ * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size * * Where: - * num_vnics is the number of VNICs allocated in the VNIC backing store + * num_vnics is the number of VNICs allocated in the VNIC backing + * store * num_l2_tx_rings is the number of L2 rings in the QP backing store * num_roce_qps is the number of RoCE QPs in the QP backing store * tqm_min_size is tqm_min_entries_per_ring reported by @@ -17788,13 +18739,18 @@ * function. */ uint32_t rkc_max_entries; + /* + * Additional number of RoCE QP context entries required for this + * function to support fast QP destroy feature. + */ + uint16_t fast_qpmd_qp_num_entries; /* Reserved for future. */ - uint8_t rsvd1[7]; + uint8_t rsvd1[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17910,12 +18866,12 @@ * This bit must be '1' for the vnic fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC UINT32_C(0x8) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC UINT32_C(0x8) /* * This bit must be '1' for the stat fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT UINT32_C(0x10) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT UINT32_C(0x10) /* * This bit must be '1' for the tqm_sp fields to be * configured. @@ -17965,7 +18921,7 @@ * This bit must be '1' for the mrav fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV UINT32_C(0x4000) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV UINT32_C(0x4000) /* * This bit must be '1' for the tim fields to be * configured. @@ -17996,6 +18952,11 @@ * fields to be configured. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC UINT32_C(0x100000) + /* + * This bit must be '1' for the number of QPs reserved for fast + * qp modify destroy feature to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP_FAST_QPMD UINT32_C(0x200000) /* QPC page size and level. */ uint8_t qpc_pg_size_qpc_lvl; /* QPC PBL indirect levels. */ @@ -18005,7 +18966,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 /* QPC page size. */ @@ -18033,7 +18997,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 /* SRQ page size. */ @@ -18061,7 +19028,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 /* CQ page size. */ @@ -18089,7 +19059,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 /* VNIC page size. */ @@ -18117,7 +19090,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 /* Stat page size. */ @@ -18145,7 +19121,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 /* TQM slow path page size. */ @@ -18173,7 +19152,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 /* TQM ring 0 page size. */ @@ -18201,7 +19183,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 /* TQM ring 1 page size. */ @@ -18229,7 +19214,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 /* TQM ring 2 page size. */ @@ -18257,7 +19245,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 /* TQM ring 3 page size. */ @@ -18285,7 +19276,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 /* TQM ring 4 page size. */ @@ -18313,7 +19307,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 /* TQM ring 5 page size. */ @@ -18341,7 +19338,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 /* TQM ring 6 page size. */ @@ -18369,7 +19369,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 /* TQM ring 7 page size. */ @@ -18397,7 +19400,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 /* MR/AV page size. */ @@ -18425,7 +19431,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 /* Timer page size. */ @@ -18492,11 +19501,11 @@ * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size * * Where: - * num_vnics is the number of VNICs allocated in the VNIC backing store - * num_l2_tx_rings is the number of L2 rings in the QP backing store - * num_roce_qps is the number of RoCE QPs in the QP backing store - * tqm_min_size is tqm_min_entries_per_ring reported by - * HWRM_FUNC_BACKING_STORE_QCAPS + * num_vnics is the number of VNICs allocated in the VNIC backing + * store num_l2_tx_rings is the number of L2 rings in the QP backing + * store num_roce_qps is the number of RoCE QPs in the QP backing + * store tqm_min_size is tqm_min_entries_per_ring reported by + * HWRM_FUNC_BACKING_STORE_QCAPS * * Note that TQM ring sizes cannot be extended while the system is * operational. If a PF driver needs to extend a TQM ring, it needs @@ -18782,7 +19791,10 @@ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 /* Tx KTLS context page size. */ @@ -18832,8 +19844,11 @@ /* 1GB. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G - /* Reserved for future. */ - uint8_t rsvd[2]; + /* + * Number of RoCE QP context entries reserved for this + * function to support fast QP modify destroy feature. + */ + uint16_t qp_num_fast_qpmd_entries; } hwrm_func_backing_store_cfg_input_t, *phwrm_func_backing_store_cfg_input_t; /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ @@ -18850,9 +19865,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -18940,12 +19955,12 @@ * This bit must be '1' for the vnic fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC UINT32_C(0x8) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC UINT32_C(0x8) /* * This bit must be '1' for the stat fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT UINT32_C(0x10) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT UINT32_C(0x10) /* * This bit must be '1' for the tqm_sp fields to be * configured. @@ -18995,7 +20010,7 @@ * This bit must be '1' for the mrav fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV UINT32_C(0x4000) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV UINT32_C(0x4000) /* * This bit must be '1' for the tim fields to be * configured. @@ -19026,6 +20041,11 @@ * fields to be configured. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC UINT32_C(0x100000) + /* + * This bit must be '1' for the number of QPs reserved for fast + * qp modify destroy feature to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP_FAST_QPMD UINT32_C(0x200000) /* QPC page size and level. */ uint8_t qpc_pg_size_qpc_lvl; /* QPC PBL indirect levels. */ @@ -19035,7 +20055,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 /* QPC page size. */ @@ -19063,7 +20086,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 /* SRQ page size. */ @@ -19091,7 +20117,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 /* CQ page size. */ @@ -19119,7 +20148,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 /* VNIC page size. */ @@ -19147,7 +20179,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 /* Stat page size. */ @@ -19175,7 +20210,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 /* TQM slow path page size. */ @@ -19203,7 +20241,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 /* TQM ring 0 page size. */ @@ -19231,7 +20272,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 /* TQM ring 1 page size. */ @@ -19259,7 +20303,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 /* TQM ring 2 page size. */ @@ -19287,7 +20334,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 /* TQM ring 3 page size. */ @@ -19315,7 +20365,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 /* TQM ring 4 page size. */ @@ -19343,7 +20396,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 /* TQM ring 5 page size. */ @@ -19371,7 +20427,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 /* TQM ring 6 page size. */ @@ -19399,7 +20458,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 /* TQM ring 7 page size. */ @@ -19427,7 +20489,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 /* MR/AV page size. */ @@ -19455,7 +20520,10 @@ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 /* Timer page size. */ @@ -19739,10 +20807,15 @@ /* 1GB. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G - uint8_t unused_1[5]; + /* + * Number of RoCE QP context entries required for this + * function to support fast QP modify destroy feature. + */ + uint16_t qp_num_fast_qpmd_entries; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as 1 + * is completely written to RAM. This field should be read as 1 * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field @@ -20106,7 +21179,7 @@ uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field @@ -20169,9 +21242,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -20317,9 +21390,9 @@ uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -20507,9 +21580,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -20637,7 +21710,9 @@ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K UINT32_C(0x2) /* 10Mhz sync in frequency. */ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M UINT32_C(0x3) - #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M + /* 25Mhz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_25M UINT32_C(0x4) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_25M uint8_t unused_0[3]; /* * Period in nanoseconds (ns) for external signal @@ -20689,9 +21764,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -20776,9 +21851,9 @@ uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -20920,9 +21995,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -21017,9 +22092,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -21030,7 +22105,7 @@ ***************************/ -/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */ +/* hwrm_func_key_ctx_alloc_input (size:384b/48B) */ typedef struct hwrm_func_key_ctx_alloc_input { /* The HWRM command request type. */ @@ -21063,9 +22138,26 @@ uint64_t resp_addr; /* Function ID. */ uint16_t fid; - /* Number of Key Contexts to be allocated. */ + /* + * Number of Key Contexts to be allocated. + * When running in the XID partition mode, if the call is made by + * a VF driver, this field specifies the number of XIDs requested + * by the VF driver. The XID partitions are managed by the PF + * driver in XID partition mode and the VF command will be + * redirected to the PF driver. The PF driver may reduce this + * number if it cannot allocate a big enough block of XID + * partitions to satisfy the request. + * This field must not exceed the maximum batch size specified in + * the max_key_ctxs_alloc field of the HWRM_FUNC_QCAPS response, + * must not be zero, and must be integer multiples of the + * partition size specified in the ctxs_per_partition field of + * the HWRM_FUNC_QCAPS response. + */ uint16_t num_key_ctxs; - /* DMA buffer size in bytes. */ + /* + * DMA buffer size in bytes. This field in invalid in the XID + * partition mode. + */ uint32_t dma_bufr_size_bytes; /* Key Context type. */ uint8_t key_ctx_type; @@ -21079,11 +22171,24 @@ #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3) #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX uint8_t unused_0[7]; - /* Host DMA address to send back KTLS context IDs. */ + /* + * Host DMA address to send back KTLS context IDs. This field is + * invalid in the XID partition mode. + */ uint64_t host_dma_addr; + /* + * This field is only used by the PF driver that manages the XID + * partitions. This field specifies the starting XID of one or + * more contiguous XID partitions allocated by the PF driver. + * This field is not used by the VF driver. + * If the call is successful, this starting XID value will be + * returned in the partition_start_xid field of the response. + */ + uint32_t partition_start_xid; + uint8_t unused_1[4]; } hwrm_func_key_ctx_alloc_input_t, *phwrm_func_key_ctx_alloc_input_t; -/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */ +/* hwrm_func_key_ctx_alloc_output (size:192b/24B) */ typedef struct hwrm_func_key_ctx_alloc_output { /* The specific error status for the command. */ @@ -21094,7 +22199,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Actual number of Key Contexts allocated. */ + /* Number of Key Contexts that have been allocated. */ uint16_t num_key_ctxs_allocated; /* Control flags. */ uint8_t flags; @@ -21102,21 +22207,116 @@ * When set, it indicates that all key contexts allocated by this * command are contiguous. As a result, the driver has to read the * start context ID from the first entry of the DMA data buffer - * and figures out the end context ID by “start context ID + - * num_key_ctxs_allocated - 1”. + * and figures out the end context ID by 'start context ID + + * num_key_ctxs_allocated - 1'. In XID partition mode, + * this bit should always be set. */ #define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS UINT32_C(0x1) - uint8_t unused_0[4]; + uint8_t unused_0; + /* + * This field is only valid in the XID partition mode. It indicates + * the starting XID that has been allocated. + */ + uint32_t partition_start_xid; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } hwrm_func_key_ctx_alloc_output_t, *phwrm_func_key_ctx_alloc_output_t; +/************************** + * hwrm_func_key_ctx_free * + **************************/ + + +/* hwrm_func_key_ctx_free_input (size:256b/32B) */ + +typedef struct hwrm_func_key_ctx_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function ID. */ + uint16_t fid; + /* Key Context type. */ + uint8_t key_ctx_type; + /* KTLS Tx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0) + /* KTLS Rx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1) + /* QUIC Tx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_TX UINT32_C(0x2) + /* QUIC Rx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3) + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_LAST HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_RX + uint8_t unused_0; + /* Starting XID of the partition that needs to be freed. */ + uint32_t partition_start_xid; + /* + * Number of entries to be freed. + * When running in the XID partition mode, this field is only + * used by the PF driver that manages the XID partitions. + * The PF driver specifies the number of XIDs to be freed and + * this number is always equal to the number of XIDs previously + * allocated successfully using HWRM_FUNC_KEY_CTX_ALLOC. + * This field is not used by the VF driver. + */ + uint16_t num_entries; + uint8_t unused_1[6]; +} hwrm_func_key_ctx_free_input_t, *phwrm_func_key_ctx_free_input_t; + +/* hwrm_func_key_ctx_free_output (size:128b/16B) */ + +typedef struct hwrm_func_key_ctx_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t rsvd0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. + */ + uint8_t valid; +} hwrm_func_key_ctx_free_output_t, *phwrm_func_key_ctx_free_output_t; + /********************************** * hwrm_func_backing_store_cfg_v2 * **********************************/ @@ -21158,39 +22358,53 @@ /* Queue pair. */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP UINT32_C(0x0) /* Shared receive queue. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1) /* Completion queue. */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ UINT32_C(0x2) /* Virtual NIC. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3) /* Statistic context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT UINT32_C(0x4) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT UINT32_C(0x4) /* Slow-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) /* Fast-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) /* Memory Region and Memory Address Vector Context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe) /* TIM. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC UINT32_C(0x14) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM UINT32_C(0xf) + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TX_CK UINT32_C(0x13) + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RX_CK UINT32_C(0x14) /* Mid-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) /* SQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) /* RQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) /* SRQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) /* CQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC UINT32_C(0x1b) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_XID_PARTITION UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID UINT32_C(0xffff) #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID @@ -21199,8 +22413,14 @@ * which means "0" indicates the first instance. For backing * stores with single instance only, leave this field to 0. * 1. If the backing store type is MPC TQM ring, use the following - * instance value to MPC client mapping: + * instance value to map to MPC clients: * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) + * 2. If the backing store type is TBL_SCOPE, use the following + * instance value to map to table scope regions: + * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) + * 3. If the backing store type is XID partition, use the following + * instance value to map to context types: + * TX_CK (0), RX_CK (1) */ uint16_t instance; /* Control flags. */ @@ -21227,10 +22447,10 @@ * The size specified in the command will be the new size to be * configured. The operation is only valid when the specific backing * store has been configured before. Otherwise, the firmware will - * return an error. The driver needs to zero out the “entry_size”, - * “flags”, “page_dir”, and “page_size_pbl_level” fields, and the + * return an error. The driver needs to zero out the 'entry_size', + * 'flags', 'page_dir', and 'page_size_pbl_level' fields, and the * firmware will ignore these inputs. Further, the firmware expects - * the “num_entries” and any valid split entries to be no less than + * the 'num_entries' and any valid split entries to be no less than * the initial value that has been configured. If not, it will * return an error code. */ @@ -21295,7 +22515,9 @@ * | SRQ | srq_split_entries | * | CQ | cq_split_entries | * | VINC | vnic_split_entries | - * | MRAV | marv_split_entries | + * | MRAV | mrav_split_entries | + * | TS | ts_split_entries | + * | CK | ck_split_entries | */ uint32_t split_entry_0; /* Split entry #1. */ @@ -21320,7 +22542,7 @@ uint8_t rsvd0[7]; /* * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be + * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been completely * written. When writing a command completion or response to * an internal processor, the order of writes has to be such @@ -21370,46 +22592,69 @@ /* Queue pair. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP UINT32_C(0x0) /* Shared receive queue. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1) /* Completion queue. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ UINT32_C(0x2) /* Virtual NIC. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3) /* Statistic context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT UINT32_C(0x4) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT UINT32_C(0x4) /* Slow-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) /* Fast-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) /* Memory Region and Memory Address Vector Context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe) /* TIM. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TKC UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RKC UINT32_C(0x14) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM UINT32_C(0xf) + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TX_CK UINT32_C(0x13) + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RX_CK UINT32_C(0x14) /* Mid-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) /* SQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) /* RQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) /* SRQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) /* CQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_TKC UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_RKC UINT32_C(0x1b) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c) + /* VF XID partition in-use table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_XID_PARTITION_TABLE UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24) /* Invalid type. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID UINT32_C(0xffff) - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID /* * Instance of the backing store type. It is zero-based, * which means "0" indicates the first instance. For backing * stores with single instance only, leave this field to 0. + * 1. If the backing store type is MPC TQM ring, use the following + * instance value to map to MPC clients: + * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) + * 2. If the backing store type is TBL_SCOPE, use the following + * instance value to map to table scope regions: + * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) + * 3. If the backing store type is XID partition, use the following + * instance value to map to context types: + * TX_CK (0), RX_CK (1) */ uint16_t instance; uint8_t rsvd[4]; @@ -21429,33 +22674,47 @@ /* Type of backing store to be configured. */ uint16_t type; /* Queue pair. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP UINT32_C(0x0) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP UINT32_C(0x0) /* Shared receive queue. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1) /* Completion queue. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ UINT32_C(0x2) /* Virtual NIC. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3) /* Statistic context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT UINT32_C(0x4) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT UINT32_C(0x4) /* Slow-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5) /* Fast-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6) /* Memory Region and Memory Address Vector Context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe) /* TIM. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TKC UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RKC UINT32_C(0x14) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM UINT32_C(0xf) + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TX_CK UINT32_C(0x13) + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RX_CK UINT32_C(0x14) /* Mid-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_TKC UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_RKC UINT32_C(0x1b) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TBL_SCOPE UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_XID_PARTITION UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT_TRACE UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT2_TRACE UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT_TRACE UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT2_TRACE UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RIGP0_TRACE UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID UINT32_C(0xffff) #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID @@ -21463,6 +22722,15 @@ * Instance of the backing store type. It is zero-based, * which means "0" indicates the first instance. For backing * stores with single instance only, leave this field to 0. + * 1. If the backing store type is MPC TQM ring, use the following + * instance value to map to MPC clients: + * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) + * 2. If the backing store type is TBL_SCOPE, use the following + * instance value to map to table scope regions: + * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) + * 3. If the backing store type is XID partition, use the following + * instance value to map to context types: + * TX_CK (0), RX_CK (1) */ uint16_t instance; /* Control flags. */ @@ -21526,7 +22794,9 @@ * | SRQ | srq_split_entries | * | CQ | cq_split_entries | * | VINC | vnic_split_entries | - * | MRAV | marv_split_entries | + * | MRAV | mrav_split_entries | + * | TS | ts_split_entries | + * | CK | ck_split_entries | */ uint32_t split_entry_0; /* Split entry #1. */ @@ -21538,7 +22808,7 @@ uint8_t rsvd2[7]; /* * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be + * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been completely * written. When writing a command completion or response to * an internal processor, the order of writes has to be such @@ -21555,7 +22825,12 @@ uint32_t qp_num_l2_entries; /* Number of QP1 entries. */ uint32_t qp_num_qp1_entries; - uint64_t rsvd; + /* + * Number of RoCE QP context entries required for this + * function to support fast QP modify destroy feature. + */ + uint32_t qp_num_fast_qpmd_entries; + uint32_t rsvd; } qpc_split_entries_t, *pqpc_split_entries_t; /* Common structure to cast SRQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is SRQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ @@ -21598,6 +22873,37 @@ uint64_t rsvd2; } mrav_split_entries_t, *pmrav_split_entries_t; +/* Common structure to cast TBL_SCOPE split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is TBL_SCOPE. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* ts_split_entries (size:128b/16B) */ + +typedef struct ts_split_entries { + /* Max number of TBL_SCOPE region entries (QCAPS). */ + uint32_t region_num_entries; + /* tsid to configure (CFG). */ + uint8_t tsid; + /* + * Lkup static bucket count (power of 2). + * Array is indexed by enum cfa_dir + */ + uint8_t lkup_static_bkt_cnt_exp[2]; + uint8_t rsvd; + uint64_t rsvd2; +} ts_split_entries_t, *pts_split_entries_t; + +/* Common structure to cast crypto key split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is TX_CK or RX_CK. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* ck_split_entries (size:128b/16B) */ + +typedef struct ck_split_entries { + /* + * Number of QUIC backing store entries. That means the number of KTLS + * backing store entries is the difference between this number and the + * total number of crypto key entries. + */ + uint32_t num_quic_entries; + uint32_t rsvd; + uint64_t rsvd2; +} ck_split_entries_t, *pck_split_entries_t; + /************************************ * hwrm_func_backing_store_qcaps_v2 * ************************************/ @@ -21639,39 +22945,53 @@ /* Queue pair. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QP UINT32_C(0x0) /* Shared receive queue. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ UINT32_C(0x1) /* Completion queue. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ UINT32_C(0x2) /* Virtual NIC. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_VNIC UINT32_C(0x3) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_VNIC UINT32_C(0x3) /* Statistic context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_STAT UINT32_C(0x4) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_STAT UINT32_C(0x4) /* Slow-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) /* Fast-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) /* Memory Region and Memory Address Vector Context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MRAV UINT32_C(0xe) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MRAV UINT32_C(0xe) /* TIM. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TIM UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TKC UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RKC UINT32_C(0x14) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TIM UINT32_C(0xf) + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TX_CK UINT32_C(0x13) + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RX_CK UINT32_C(0x14) /* Mid-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) /* SQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) /* RQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) /* SRQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) /* CQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_TKC UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_RKC UINT32_C(0x1b) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_XID_PARTITION UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID UINT32_C(0xffff) #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID @@ -21694,39 +23014,53 @@ /* Queue pair. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QP UINT32_C(0x0) /* Shared receive queue. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1) /* Completion queue. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ UINT32_C(0x2) /* Virtual NIC. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3) /* Statistic context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_STAT UINT32_C(0x4) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_STAT UINT32_C(0x4) /* Slow-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5) /* Fast-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6) /* Memory Region and Memory Address Vector Context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe) /* TIM. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TIM UINT32_C(0xf) - /* KTLS Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TKC UINT32_C(0x13) - /* KTLS Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RKC UINT32_C(0x14) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TIM UINT32_C(0xf) + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TX_CK UINT32_C(0x13) + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RX_CK UINT32_C(0x14) /* Mid-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15) /* SQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) /* RQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) /* SRQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) /* CQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_TKC UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_RKC UINT32_C(0x1b) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TBL_SCOPE UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_XID_PARTITION UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT_TRACE UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT2_TRACE UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT_TRACE UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT2_TRACE UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RIGP0_TRACE UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID UINT32_C(0xffff) #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID @@ -21736,23 +23070,46 @@ uint32_t flags; /* * When set, it indicates the context type should be initialized - * with the “ctx_init_value” at the specified offset. + * with the 'ctx_init_value' at the specified offset. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT UINT32_C(0x1) /* When set, it indicates the context type is valid. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID UINT32_C(0x2) /* * When set, it indicates the region for this type is not a regular * context memory but a driver managed memory that is created, * initialized and managed by the driver. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_DRIVER_MANAGED_MEMORY UINT32_C(0x4) + /* + * When set, it indicates the support of the following capability + * that is specific to the QP type: + * - For 2-port adapters, the ability to extend the RoCE QP + * entries configured on a PF, during some network events such as + * Link Down. These additional entries count is included in the + * advertised 'max_num_entries'. + * - The count of RoCE QP entries, derived from 'max_num_entries' + * (max_num_entries - qp_num_qp1_entries - qp_num_l2_entries - + * qp_num_fast_qpmd_entries, note qp_num_fast_qpmd_entries is + * always zero when QPs are pseudo-statically allocated), includes + * the count of QPs that can be migrated from the other PF (e.g., + * during network link down). Therefore, during normal operation + * when both PFs are active, the supported number of RoCE QPs for + * each of the PF is half of the advertised value. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC UINT32_C(0x8) /* * Bit map of the valid instances associated with the * backing store type. * 1. If the backing store type is MPC TQM ring, use the following - * bit to MPC client mapping: + * bits to map to MPC clients: * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) + * 2. If the backing store type is TBL_SCOPE, use the following + * bits to map to table scope regions: + * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) + * 3. If the backing store type is VF XID partition in-use table, use + * the following bits to map to context types: + * TX_CK (0), RX_CK (1) */ uint32_t instance_bit_map; /* @@ -21799,7 +23156,37 @@ * | 4 | All four split entries have valid data. | */ uint8_t subtype_valid_cnt; - uint8_t rsvd2; + /* + * Bitmap that indicates if each of the 'split_entry' denotes an + * exact count (i.e., min = max). When the exact count bit is set, + * it indicates the exact number of entries as advertised has to be + * configured. The 'split_entry' to be set to contain exact count by + * this bitmap needs to be a valid split entry specified by + * 'subtype_valid_cnt'. + */ + uint8_t exact_cnt_bit_map; + /* + * When this bit is '1', it indicates 'split_entry_0' contains + * an exact count. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT UINT32_C(0x1) + /* + * When this bit is '1', it indicates 'split_entry_1' contains + * an exact count. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT UINT32_C(0x2) + /* + * When this bit is '1', it indicates 'split_entry_2' contains + * an exact count. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT UINT32_C(0x4) + /* + * When this bit is '1', it indicates 'split_entry_3' contains + * an exact count. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT UINT32_C(0x8) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_UNUSED_MASK UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_UNUSED_SFT 4 /* * Split entry #0. Note that the four split entries (as a group) * must be cast to a type-specific data structure first before @@ -21811,7 +23198,8 @@ * | SRQ | srq_split_entries | * | CQ | cq_split_entries | * | VINC | vnic_split_entries | - * | MRAV | marv_split_entries | + * | MRAV | mrav_split_entries | + * | TS | ts_split_entries | */ uint32_t split_entry_0; /* Split entry #1. */ @@ -21823,7 +23211,7 @@ uint8_t rsvd3[3]; /* * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be + * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been completely * written. When writing a command completion or response to * an internal processor, the order of writes has to be such @@ -21890,7 +23278,7 @@ */ #define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PACING_THRESHOLD_VALID UINT32_C(0x2) /* - * Specify primary function’s NQ ID to receive the doorbell pacing + * Specify primary function's NQ ID to receive the doorbell pacing * threshold crossing events. */ uint32_t primary_nq_id; @@ -21916,7 +23304,7 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -22088,9 +23476,10 @@ */ uint8_t dbr_throttling_aeq_arm_reg_val; uint8_t unused_3[3]; - uint32_t dbr_stat_db_max_fifo_depth; + /* This field indicates the maximum depth of the doorbell FIFO. */ + uint32_t dbr_stat_db_max_fifo_depth; /* - * Specifies primary function’s NQ ID. + * Specifies primary function's NQ ID. * A value of 0xFFFF FFFF indicates NQ ID is invalid. */ uint32_t primary_nq_id; @@ -22102,7 +23491,7 @@ uint8_t unused_4[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -22163,7 +23552,7 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -22258,9 +23647,9 @@ uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22328,7 +23717,7 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -22433,9 +23822,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22515,22 +23904,22 @@ uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } hwrm_func_synce_qcfg_output_t, *phwrm_func_synce_qcfg_output_t; -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ +/************************ + * hwrm_func_lag_create * + ************************/ -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +/* hwrm_func_lag_create_input (size:192b/24B) */ -typedef struct hwrm_func_vlan_qcfg_input { +typedef struct hwrm_func_lag_create_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22559,19 +23948,96 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint8_t enables; /* - * Function ID of the function that is being + * This bit must be '1' for the active_port_map field to be * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. */ - uint16_t fid; - uint8_t unused_0[6]; -} hwrm_func_vlan_qcfg_input_t, *phwrm_func_vlan_qcfg_input_t; + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x1) + /* + * This bit must be '1' for the member_port_map field to be + * configured. + */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x2) + /* This bit must be '1' for the aggr_mode field to be configured. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_AGGR_MODE UINT32_C(0x4) + /* rsvd1 is 5 b */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xf8) + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_RSVD1_SFT 3 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. The active_port_map must always be a subset of the + * member_port_map. An active port is eligible to send and receive + * traffic. + * + * If the LAG mode is active-backup, only one port can be an active + * port at a given time. All other ports in the member_port_map that + * are not the active port are backup port. When the active port + * fails, another member port takes over to become the active port. + * The driver should use HWRM_FUNC_LAG_UPDATE to update + * the active_port_map by only setting the port bit of the new active + * port. + * + * In active-active, balance_xor or 802_3_ad mode, all member ports + * can be active ports. If the driver determines that an active + * port is down or unable to function, it should use + * HWRM_FUNC_LAG_UPDATE to update the active_port_map by clearing + * the port bit that has failed. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. There must be at least 2 ports in the member ports and + * each must not be a member of another LAG. Note that on a 4-port + * device, there can be either 2 ports or 4 ports in the member ports. + * Using 3 member ports is not supported. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_LAST HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[4]; +} hwrm_func_lag_create_input_t, *phwrm_func_lag_create_input_t; -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +/* hwrm_func_lag_create_output (size:128b/16B) */ -typedef struct hwrm_func_vlan_qcfg_output { +typedef struct hwrm_func_lag_create_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22580,50 +24046,30 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint64_t unused_0; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; - /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. - */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * LAG ID of the created LAG. This LAG ID will also be returned + * in the HWRM_FUNC_QCFG response of all member ports. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint8_t unused_3[3]; + uint8_t fw_lag_id; + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_func_vlan_qcfg_output_t, *phwrm_func_vlan_qcfg_output_t; +} hwrm_func_lag_create_output_t, *phwrm_func_lag_create_output_t; -/********************** - * hwrm_func_vlan_cfg * - **********************/ +/************************ + * hwrm_func_lag_update * + ************************/ -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +/* hwrm_func_lag_update_input (size:192b/24B) */ -typedef struct hwrm_func_vlan_cfg_input { +typedef struct hwrm_func_lag_update_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22652,75 +24098,161 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Link aggregation group ID of the LAG to be updated. */ + uint8_t fw_lag_id; + uint8_t enables; /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. + * This bit must be '1' for the active_port_map field to be + * updated. */ - uint16_t fid; - uint8_t unused_0[2]; - uint32_t enables; + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x1) /* - * This bit must be '1' for the stag_vid field to be - * configured. + * This bit must be '1' for the member_port_map field to be + * updated. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) - /* - * This bit must be '1' for the ctag_vid field to be - * configured. + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x2) + /* This bit must be '1' for the aggr_mode field to be updated. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_AGGR_MODE UINT32_C(0x4) + /* rsvd1 is 5 b */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xf8) + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_RSVD1_SFT 3 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. The active_port_map must always be a subset of the + * member_port_map. An active port is eligible to send and receive + * traffic. + * + * If the LAG mode is active-backup, only one port can be an active + * port at a given time. All other ports in the member_port_map that + * are not the active port are backup port. When the active port + * fails, another member port takes over to become the active port. + * The driver should use HWRM_FUNC_LAG_UPDATE to update + * the active_port_map by only setting the port bit of the new active + * port. + * + * In active-active, balance_xor or 802_3_ad mode, all member ports + * can be active ports. If the driver determines that an active + * port is down or unable to function, it should use + * HWRM_FUNC_LAG_UPDATE to update the active_port_map by clearing + * the port bit that has failed. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) - /* - * This bit must be '1' for the stag_pcp field to be - * configured. + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. There must be at least 2 ports in the member ports and + * each must not be a member of another LAG. Note that on a 4-port + * device, there can be either 2 ports or 4 ports in the member ports. + * Using 3 member ports is not supported. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_LAST HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[3]; +} hwrm_func_lag_update_input_t, *phwrm_func_lag_update_input_t; + +/* hwrm_func_lag_update_output (size:128b/16B) */ + +typedef struct hwrm_func_lag_update_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This bit must be '1' for the ctag_pcp field to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + uint8_t valid; +} hwrm_func_lag_update_output_t, *phwrm_func_lag_update_output_t; + +/********************** + * hwrm_func_lag_free * + **********************/ + + +/* hwrm_func_lag_free_input (size:192b/24B) */ + +typedef struct hwrm_func_lag_free_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the stag_tpid field to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + uint16_t cmpl_ring; /* - * This bit must be '1' for the ctag_tpid field to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; + uint16_t seq_id; /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + uint16_t target_id; /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd1; - /* Future use. */ - uint32_t rsvd2; - uint8_t unused_3[4]; -} hwrm_func_vlan_cfg_input_t, *phwrm_func_vlan_cfg_input_t; + uint64_t resp_addr; + /* Link aggregation group ID of the LAG to be freed. */ + uint8_t fw_lag_id; + uint8_t unused_0[7]; +} hwrm_func_lag_free_input_t, *phwrm_func_lag_free_input_t; -/* hwrm_func_vlan_cfg_output (size:128b/16B) */ +/* hwrm_func_lag_free_output (size:128b/16B) */ -typedef struct hwrm_func_vlan_cfg_output { +typedef struct hwrm_func_lag_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22732,22 +24264,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_func_vlan_cfg_output_t, *phwrm_func_vlan_cfg_output_t; +} hwrm_func_lag_free_output_t, *phwrm_func_lag_free_output_t; -/******************************* - * hwrm_func_vf_vnic_ids_query * - *******************************/ +/********************** + * hwrm_func_lag_qcfg * + **********************/ -/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ +/* hwrm_func_lag_qcfg_input (size:192b/24B) */ -typedef struct hwrm_func_vf_vnic_ids_query_input { +typedef struct hwrm_func_lag_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22776,21 +24308,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This value is used to identify a Virtual Function (VF). - * The scope of VF ID is local within a PF. - */ - uint16_t vf_id; - uint8_t unused_0[2]; - /* Max number of vnic ids in vnic id table */ - uint32_t max_vnic_id_cnt; - /* This is the address for VF VNIC ID table */ - uint64_t vnic_id_tbl_addr; -} hwrm_func_vf_vnic_ids_query_input_t, *phwrm_func_vf_vnic_ids_query_input_t; + /* Link aggregation group ID of the LAG to be queried. */ + uint8_t fw_lag_id; + uint8_t unused_0[7]; +} hwrm_func_lag_qcfg_input_t, *phwrm_func_lag_qcfg_input_t; -/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ +/* hwrm_func_lag_qcfg_output (size:128b/16B) */ -typedef struct hwrm_func_vf_vnic_ids_query_output { +typedef struct hwrm_func_lag_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22800,30 +24325,697 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Actual number of vnic ids + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. The active_port_map must always be a subset of the + * member_port_map. An active port is eligible to send and receive + * traffic. * - * Each VNIC ID is written as a 32-bit number. + * If the LAG mode is active-backup, only one port can be an active + * port at a given time. All other ports in the member_port_map that + * are not the active port are backup port. When the active port + * fails, another member port takes over to become the active port. + * The driver should use HWRM_FUNC_LAG_UPDATE to update + * the active_port_map by only setting the port bit of the new active + * port. + * + * In active-active, balance_xor or 802_3_ad mode, all member ports + * can be active ports. If the driver determines that an active + * port is down or unable to function, it should use + * HWRM_FUNC_LAG_UPDATE to update the active_port_map by clearing + * the port bit that has failed. */ - uint32_t vnic_id_cnt; - uint8_t unused_0[3]; + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. There must be at least 2 ports in the member ports and + * each must not be a member of another LAG. Note that on a 4-port + * device, there can be either 2 ports or 4 ports in the member ports. + * Using 3 member ports is not supported. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_LAST HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_func_vf_vnic_ids_query_output_t, *phwrm_func_vf_vnic_ids_query_output_t; +} hwrm_func_lag_qcfg_output_t, *phwrm_func_lag_qcfg_output_t; -/*********************** - * hwrm_func_vf_bw_cfg * - ***********************/ +/************************** + * hwrm_func_lag_mode_cfg * + **************************/ -/* hwrm_func_vf_bw_cfg_input (size:960b/120B) */ +/* hwrm_func_lag_mode_cfg_input (size:192b/24B) */ -typedef struct hwrm_func_vf_bw_cfg_input { +typedef struct hwrm_func_lag_mode_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t enables; + /* + * This bit must be '1' for the link aggregation enable or + * disable flags to be configured. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_FLAGS UINT32_C(0x1) + /* + * This bit must be '1' for the active_port_map field to be + * configured. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x2) + /* + * This bit must be '1' for the member_port_map field to be + * configured. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x4) + /* This bit must be '1' for the aggr_mode field to be configured. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_AGGR_MODE UINT32_C(0x8) + /* This bit must be '1' for the lag id field to be configured. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_LAG_ID UINT32_C(0x10) + /* rsvd1 is 3 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xe0) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_RSVD1_SFT 5 + uint8_t flags; + /* + * If this bit is set to 1, the driver is requesting FW to disable + * link aggregation feature during run time. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_DISABLE UINT32_C(0x1) + /* + * If this bit is set to 1, the driver is requesting FW to enable + * link aggregation feature during run time. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_ENABLE UINT32_C(0x2) + /* rsvd2 is 6 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_RSVD2_MASK UINT32_C(0xfc) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_RSVD2_SFT 2 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "active port" is one of member ports which is eligible to + * send or receive the traffic. + * In the active-backup mode, only one member port is active port at + * any given time. If the active port fails, another member port + * automatically takes over the active role to ensure continuous + * network connectivity. + * In the active-active, balance_xor or 802_3_ad mode, all member ports + * could be active port, if link status on one port is down, driver + * needs to send the NIC a new active-port bitmap with marking this + * port as not active port. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "member port" refers to a front panel port that is added to + * the bond group as a slave device. These member ports are combined to + * create a logical bond interface. + * For a 4-port NIC, the LAG member port combination can consist of + * either two ports or four ports. However, it is important to note + * that the case with three ports in the same lag group is not + * supported. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. There could be a case to use multiple LAG groups, + * for example, if the NIC has four front panel ports, the lag feature + * can use up to two LAG groups, with two ports assigned to each group. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_LAST HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_802_3_AD + /* Link aggregation group idx being used. */ + uint8_t lag_id; + uint8_t unused_0[2]; +} hwrm_func_lag_mode_cfg_input_t, *phwrm_func_lag_mode_cfg_input_t; + +/* hwrm_func_lag_mode_cfg_output (size:128b/16B) */ + +typedef struct hwrm_func_lag_mode_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Link aggregation group idx being used. */ + uint8_t lag_id; + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_func_lag_mode_cfg_output_t, *phwrm_func_lag_mode_cfg_output_t; + +/*************************** + * hwrm_func_lag_mode_qcfg * + ***************************/ + + +/* hwrm_func_lag_mode_qcfg_input (size:192b/24B) */ + +typedef struct hwrm_func_lag_mode_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} hwrm_func_lag_mode_qcfg_input_t, *phwrm_func_lag_mode_qcfg_input_t; + +/* hwrm_func_lag_mode_qcfg_output (size:128b/16B) */ + +typedef struct hwrm_func_lag_mode_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t aggr_enabled; + /* + * This flag is used to query whether link aggregation is enabled + * or disabled during run time. + */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_ENABLED UINT32_C(0x1) + /* rsvd1 is 7 b */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_RSVD1_MASK UINT32_C(0xfe) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_RSVD1_SFT 1 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "active port" is one of member ports which is eligible to + * send or receive the traffic. + * In the active-backup mode, only one member port is active port at + * any given time. If the active port fails, another member port + * automatically takes over the active role to ensure continuous + * network connectivity. + * In the active-active, balance_xor or 802_3_ad mode, all member ports + * could be active port, if link status on one port is down, driver + * needs to send the NIC a new active-port bitmap with marking this + * port as not active port. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd2 is 4 b */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD2_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD2_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "member port" refers to a front panel port that is added to + * the bond group as a slave device. These member ports are combined to + * create a logical bond interface. + * For a 4-port NIC, the LAG member port combination can consist of + * either two ports or four ports. However, it is important to note + * that the case with three ports in the same lag group is not + * supported. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. There could be a case to use multiple LAG groups, + * for example, if the NIC has four front panel ports, the lag feature + * can use up to two LAG groups, with two ports assigned to each group. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD3_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD3_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_LAST HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_func_lag_mode_qcfg_output_t, *phwrm_func_lag_mode_qcfg_output_t; + +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ + + +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ + +typedef struct hwrm_func_vlan_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} hwrm_func_vlan_qcfg_input_t, *phwrm_func_vlan_qcfg_input_t; + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ + +typedef struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is + * specified in network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is + * specified in network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_func_vlan_qcfg_output_t, *phwrm_func_vlan_qcfg_output_t; + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ + +typedef struct hwrm_func_vlan_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[2]; + uint32_t enables; + /* + * This bit must be '1' for the stag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1) + /* + * This bit must be '1' for the ctag_vid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2) + /* + * This bit must be '1' for the stag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4) + /* + * This bit must be '1' for the ctag_pcp field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8) + /* + * This bit must be '1' for the stag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10) + /* + * This bit must be '1' for the ctag_tpid field to be + * configured. + */ + #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20) + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is + * specified in network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is + * specified in network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd1; + /* Future use. */ + uint32_t rsvd2; + uint8_t unused_3[4]; +} hwrm_func_vlan_cfg_input_t, *phwrm_func_vlan_cfg_input_t; + +/* hwrm_func_vlan_cfg_output (size:128b/16B) */ + +typedef struct hwrm_func_vlan_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_func_vlan_cfg_output_t, *phwrm_func_vlan_cfg_output_t; + +/******************************* + * hwrm_func_vf_vnic_ids_query * + *******************************/ + + +/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ + +typedef struct hwrm_func_vf_vnic_ids_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This value is used to identify a Virtual Function (VF). + * The scope of VF ID is local within a PF. + */ + uint16_t vf_id; + uint8_t unused_0[2]; + /* Max number of vnic ids in vnic id table */ + uint32_t max_vnic_id_cnt; + /* This is the address for VF VNIC ID table */ + uint64_t vnic_id_tbl_addr; +} hwrm_func_vf_vnic_ids_query_input_t, *phwrm_func_vf_vnic_ids_query_input_t; + +/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ + +typedef struct hwrm_func_vf_vnic_ids_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Actual number of vnic ids + * + * Each VNIC ID is written as a 32-bit number. + */ + uint32_t vnic_id_cnt; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_func_vf_vnic_ids_query_output_t, *phwrm_func_vf_vnic_ids_query_output_t; + +/*********************** + * hwrm_func_vf_bw_cfg * + ***********************/ + + +/* hwrm_func_vf_bw_cfg_input (size:960b/120B) */ + +typedef struct hwrm_func_vf_bw_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22918,9 +25110,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22989,8 +25181,8 @@ uint16_t resp_len; /* * The number of VF functions that are being queried. - * The inline response space allows the host to query up to 50 VFs' rate - * scale percentage + * The inline response space allows the host to query up to 50 VFs' + * rate scale percentage. */ uint16_t num_vfs; uint16_t unused[3]; @@ -23041,9 +25233,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -23088,11 +25280,11 @@ uint32_t flags; /* * When this bit is '1', the function driver is indicating - * that the IF state is changing to UP state. The call should + * that the IF state is changing to UP state. The call should * be made at the beginning of the driver's open call before - * resources are allocated. After making the call, the driver + * resources are allocated. After making the call, the driver * should check the response to see if any resources may have - * changed (see the response below). If the driver fails + * changed (see the response below). If the driver fails * the open call, the driver should make this call again with * this bit cleared to indicate that the IF state is not UP. * During the driver's close call when the IF state is changing @@ -23117,22 +25309,32 @@ uint32_t flags; /* * When this bit is '1', it indicates that the resources reserved - * for this function may have changed. The driver should check + * for this function may have changed. The driver should check * resource capabilities and reserve resources again before * allocating resources. */ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE UINT32_C(0x1) /* - * When this bit is '1', it indicates that the firmware got changed / reset. - * The driver should do complete re-initialization when that bit is set. + * When this bit is '1', it indicates that the firmware got changed / + * reset. The driver should do complete re-initialization when that + * bit is set. */ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE UINT32_C(0x2) + /* + * When this bit is '1', it indicates that capabilities + * for this function may have changed. The driver should + * query for changes to capabilities. + * The CAPS_CHANGE bit will only be set when it is safe for the + * driver to completely re-initialize all resources for the function + * including any children VFs. + */ + #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_CAPS_CHANGE UINT32_C(0x4) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -23321,9 +25523,9 @@ uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -23518,9 +25720,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -23678,9 +25880,9 @@ uint8_t unused_2[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -23691,7 +25893,7 @@ *********************/ -/* hwrm_port_phy_cfg_input (size:448b/56B) */ +/* hwrm_port_phy_cfg_input (size:512b/64B) */ typedef struct hwrm_port_phy_cfg_input { /* The HWRM command request type. */ @@ -23738,7 +25940,7 @@ * settings specified in this command. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1) - /* deprecated bit. Do not use!!! */ + /* deprecated bit. Do not use!!! */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED UINT32_C(0x2) /* * When this bit is set to '1', and the force_pam4_link_speed @@ -23798,33 +26000,33 @@ */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE UINT32_C(0x80) /* - * When set to 1, then the HWRM shall enable FEC autonegotitation - * on this port if supported. When enabled, at least one of the + * When set to 1, then the HWRM shall enable FEC autonegotiation + * on this port if supported. When enabled, at least one of the * FEC modes must be advertised by enabling the fec_clause_74_enable, * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable, - * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none + * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none * of the FEC mode is currently enabled, the HWRM shall choose * a default advertisement setting. * The default advertisement setting can be queried by calling - * hwrm_port_phy_qcfg. Note that the link speed must be + * hwrm_port_phy_qcfg. Note that the link speed must be * in autonegotiation mode for FEC autonegotiation to take effect. * When set to 0, then this flag shall be ignored. - * If FEC autonegotiation is not supported, then the HWRM shall ignore this - * flag. + * If FEC autonegotiation is not supported, then the HWRM shall + * ignore this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE UINT32_C(0x100) /* * When set to 1, then the HWRM shall disable FEC autonegotiation - * on this port and use forced FEC mode. In forced FEC mode, one + * on this port and use forced FEC mode. In forced FEC mode, one * or more FEC forced settings under the same clause can be set. * When set to 0, then this flag shall be ignored. - * If FEC autonegotiation is not supported, then the HWRM shall ignore this - * flag. + * If FEC autonegotiation is not supported, then the HWRM shall + * ignore this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE UINT32_C(0x200) /* - * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code) - * on this port if supported, by advertising FEC CLAUSE 74 if + * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire + * Code) on this port if supported, by advertising FEC CLAUSE 74 if * FEC autonegotiation is enabled or force enabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this @@ -23832,9 +26034,9 @@ */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE UINT32_C(0x400) /* - * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code) - * on this port if supported, by not advertising FEC CLAUSE 74 if - * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire + * Code) on this port if supported, by not advertising FEC CLAUSE 74 + * if FEC autonegotiation is enabled or force disabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this * flag. @@ -23844,8 +26046,8 @@ * When set to 1, then the HWRM shall enable FEC CLAUSE 91 * (Reed Solomon RS(528,514) for NRZ) on this port if supported, * by advertising FEC RS(528,514) if FEC autonegotiation is enabled - * or force enabled otherwise. In forced FEC mode, this flag - * will only take effect if the speed is NRZ. Additional + * or force enabled otherwise. In forced FEC mode, this flag + * will only take effect if the speed is NRZ. Additional * RS544 or RS272 flags (also under clause 91) may be set for PAM4 * in forced FEC mode. * When set to 0, then this flag shall be ignored. @@ -23857,8 +26059,8 @@ * When set to 1, then the HWRM shall disable FEC CLAUSE 91 * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by * not advertising RS(528,514) if FEC autonegotiation is enabled or - * force disabled otherwise. When set to 0, then this flag shall be - * ignored. If FEC RS(528,514) is not supported, then the HWRM + * force disabled otherwise. When set to 0, then this flag shall be + * ignored. If FEC RS(528,514) is not supported, then the HWRM * shall ignore this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE UINT32_C(0x2000) @@ -23886,7 +26088,7 @@ * on this port if supported, by advertising FEC RS544_1XN if * FEC autonegotiation is enabled or force enabled otherwise. * In forced mode, this flag will only take effect if the speed is - * PAM4. If this flag and fec_rs544_ieee_enable are set, the + * PAM4. If this flag and fec_rs544_ieee_enable are set, the * HWRM shall choose one of the RS544 modes. * When set to 0, then this flag shall be ignored. * If FEC RS544_1XN is not supported, then the HWRM shall ignore this @@ -23898,8 +26100,8 @@ * on this port if supported, by not advertising FEC RS544_1XN if * FEC autonegotiation is enabled or force disabled otherwise. * When set to 0, then this flag shall be ignored. - * If FEC RS544_1XN is not supported, then the HWRM shall ignore this - * flag. + * If FEC RS544_1XN is not supported, then the HWRM shall ignore + * this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE UINT32_C(0x10000) /* @@ -23907,7 +26109,7 @@ * on this port if supported, by advertising FEC RS(544,514) if * FEC autonegotiation is enabled or force enabled otherwise. * In forced mode, this flag will only take effect if the speed is - * PAM4. If this flag and fec_rs544_1xn_enable are set, the + * PAM4. If this flag and fec_rs544_1xn_enable are set, the * HWRM shall choose one of the RS544 modes. * When set to 0, then this flag shall be ignored. * If FEC RS(544,514) is not supported, then the HWRM shall ignore @@ -23928,8 +26130,8 @@ * on this port if supported, by advertising FEC RS272_1XN if * FEC autonegotiation is enabled or force enabled otherwise. * In forced mode, this flag will only take effect if the speed is - * PAM4. If this flag and fec_rs272_ieee_enable are set, the - * HWRM shall choose one of the RS272 modes. Note that RS272 + * PAM4. If this flag and fec_rs272_ieee_enable are set, the + * HWRM shall choose one of the RS272 modes. Note that RS272 * and RS544 modes cannot be set at the same time in forced FEC mode. * When set to 0, then this flag shall be ignored. * If FEC RS272_1XN is not supported, then the HWRM shall ignore this @@ -23950,8 +26152,8 @@ * on this port if supported, by advertising FEC RS(272,257) if * FEC autonegotiation is enabled or force enabled otherwise. * In forced mode, this flag will only take effect if the speed is - * PAM4. If this flag and fec_rs272_1xn_enable are set, the - * HWRM shall choose one of the RS272 modes. Note that RS272 + * PAM4. If this flag and fec_rs272_1xn_enable are set, the + * HWRM shall choose one of the RS272 modes. Note that RS272 * and RS544 modes cannot be set at the same time in forced FEC mode. * When set to 0, then this flag shall be ignored. * If FEC RS(272,257) is not supported, then the HWRM shall ignore @@ -24033,11 +26235,21 @@ * be configured. */ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK UINT32_C(0x1000) + /* + * This bit must be '1' for the force_link_speeds2 field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_LINK_SPEEDS2 UINT32_C(0x2000) + /* + * This bit must be '1' for the auto_link_speeds2_mask field to + * be configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEEDS2_MASK UINT32_C(0x4000) /* Port ID of port that is to be configured. */ uint16_t port_id; /* * This is the speed that will be used if the force - * bit is '1'. If unsupported speed is selected, an error + * bit is '1'. If unsupported speed is selected, an error * will be generated. */ uint16_t force_link_speed; @@ -24074,18 +26286,19 @@ /* Select all possible speeds for autoneg mode. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) /* - * Select only the auto_link_speed speed for autoneg mode. This mode has - * been DEPRECATED. An HWRM client should not use this mode. + * Select only the auto_link_speed speed for autoneg mode. This mode + * has been DEPRECATED. An HWRM client should not use this mode. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2) /* - * Select the auto_link_speed or any speed below that speed for autoneg. - * This mode has been DEPRECATED. An HWRM client should not use this mode. + * Select the auto_link_speed or any speed below that speed for + * autoneg. This mode has been DEPRECATED. An HWRM client should not + * use this mode. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) /* - * Select the speeds based on the corresponding link speed mask values - * that are provided. The included speeds are specified in the + * Select the speeds based on the corresponding link speed mask + * values that are provided. The included speeds are specified in the * auto_link_speed and auto_pam4_link_speed fields. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4) @@ -24133,10 +26346,29 @@ * 1, auto_pause bits should be ignored and should be set to 0. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4) - uint8_t unused_0; + /* + * This field is only used by management firmware to communicate with + * core firmware regarding phy_port_cfg. + * It mainly used to notify core firmware that management firmware is + * using port for NCSI over RMII communication or not. + */ + uint8_t mgmt_flag; + /* + * Bit denoting if management firmware is using the link for + * NCSI over RMII communication. + * When set to 1, management firmware is no longer using the given + * port. + * When set to 0, management firmware is using the given port. + */ + #define HWRM_PORT_PHY_CFG_INPUT_MGMT_FLAG_LINK_RELEASE UINT32_C(0x1) + /* + * Validity bit, set to 1 to indicate other bits in mgmt_flags are + * valid. + */ + #define HWRM_PORT_PHY_CFG_INPUT_MGMT_FLAG_MGMT_VALID UINT32_C(0x80) /* * This is the speed that will be used if the autoneg_mode - * is "one_speed" or "one_or_below". If an unsupported speed + * is "one_speed" or "one_or_below". If an unsupported speed * is selected, an error will be generated. */ uint16_t auto_link_speed; @@ -24165,7 +26397,7 @@ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB /* * This is a mask of link speeds that will be used if - * autoneg_mode is "mask". If unsupported speed is enabled + * autoneg_mode is "mask". If unsupported speed is enabled * an error will be generated. */ uint16_t auto_link_speed_mask; @@ -24206,7 +26438,7 @@ #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON /* This value controls the loopback setting for the PHY. */ uint8_t lpbk; - /* No loopback is selected. Normal operation. */ + /* No loopback is selected. Normal operation. */ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0) /* * The HW will be configured with local loopback such that @@ -24222,7 +26454,8 @@ /* * The HW will be configured with external loopback such that * host data is sent on the transmitter and based on the external - * loopback connection the data will be received without modification. + * loopback connection the data will be received without + * modification. */ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3) #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL @@ -24244,7 +26477,7 @@ uint8_t unused_1; /* * This value controls the pre-emphasis to be used for the - * link. Driver should not set this value (use + * link. Driver should not set this value (use * enable.preemphasis = 0) unless driver is sure of setting. * Normally HWRM FW will determine proper pre-emphasis. */ @@ -24275,7 +26508,7 @@ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40) /* * This is the speed that will be used if the force and force_pam4 - * bits are '1'. If unsupported speed is selected, an error + * bits are '1'. If unsupported speed is selected, an error * will be generated. */ uint16_t force_pam4_link_speed; @@ -24299,7 +26532,76 @@ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G UINT32_C(0x1) #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G UINT32_C(0x2) #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G UINT32_C(0x4) - uint8_t unused_2[2]; + /* + * This is the speed that will be used if the force_link_speeds2 + * bit is '1'. If unsupported speed is selected, an error + * will be generated. + */ + uint16_t force_link_speeds2; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_1GB UINT32_C(0xa) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_10GB UINT32_C(0x64) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_25GB UINT32_C(0xfa) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_40GB UINT32_C(0x190) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB UINT32_C(0x1f4) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB UINT32_C(0x3e8) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x1f5) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x3e9) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x7d1) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0xfa1) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x3ea) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x7d2) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0xfa2) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x1f42) + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_LAST HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 + /* + * This is a mask of link speeds that will be used if + * auto_link_speeds2_mask bit in the "enables" field is 1. + * If unsupported speed is enabled an error will be generated. + */ + uint16_t auto_link_speeds2_mask; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_1GB UINT32_C(0x1) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_10GB UINT32_C(0x2) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_25GB UINT32_C(0x4) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_40GB UINT32_C(0x8) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB UINT32_C(0x10) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB UINT32_C(0x20) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 UINT32_C(0x40) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 UINT32_C(0x80) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 UINT32_C(0x100) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 UINT32_C(0x200) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 UINT32_C(0x400) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 UINT32_C(0x800) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 UINT32_C(0x1000) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 UINT32_C(0x2000) + uint8_t unused_2[6]; } hwrm_port_phy_cfg_input_t, *phwrm_port_phy_cfg_input_t; /* hwrm_port_phy_cfg_output (size:128b/16B) */ @@ -24316,9 +26618,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -24344,7 +26646,7 @@ * but if a 0 is returned at any time then this should * be treated as an un recoverable failure, * - * retry interval in milli seconds is returned in opaque_1. + * retry interval in milliseconds is returned in opaque_1. * This specifies the time that user should wait before * issuing the next port_phy_cfg command. */ @@ -24423,9 +26725,11 @@ #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0 /* NRZ signaling */ #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ UINT32_C(0x0) - /* PAM4 signaling */ + /* PAM4-56 signaling */ #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 UINT32_C(0x1) - #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 + /* PAM4-112 signaling */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112 UINT32_C(0x2) + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112 /* This value indicates the current active FEC mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK UINT32_C(0xf0) #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4 @@ -24433,15 +26737,15 @@ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE (UINT32_C(0x0) << 4) /* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (UINT32_C(0x1) << 4) - /* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */ + /* FEC CLAUSE 91 RS(528,514) active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (UINT32_C(0x2) << 4) - /* FEC RS544_1XN active, autonegoatiated or forced. */ + /* FEC RS544_1XN active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (UINT32_C(0x3) << 4) - /* FEC RS(544,528) active, autonegoatiated or forced. */ + /* FEC RS(544,528) active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (UINT32_C(0x4) << 4) /* FEC RS272_1XN active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (UINT32_C(0x5) << 4) - /* FEC RS(272,257) active, autonegoatiated or forced. */ + /* FEC RS(272,257) active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (UINT32_C(0x6) << 4) #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE /* @@ -24472,6 +26776,10 @@ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8) /* 200Gb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0) + /* 400Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_400GB UINT32_C(0xfa0) + /* 800Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_800GB UINT32_C(0x1f40) /* 10Mb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff) #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB @@ -24571,13 +26879,14 @@ /* Select all possible speeds for autoneg mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) /* - * Select only the auto_link_speed speed for autoneg mode. This mode has - * been DEPRECATED. An HWRM client should not use this mode. + * Select only the auto_link_speed speed for autoneg mode. This mode + * has been DEPRECATED. An HWRM client should not use this mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2) /* - * Select the auto_link_speed or any speed below that speed for autoneg. - * This mode has been DEPRECATED. An HWRM client should not use this mode. + * Select the auto_link_speed or any speed below that speed for + * autoneg. This mode has been DEPRECATED. An HWRM client should not + * use this mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) /* @@ -24689,7 +26998,7 @@ #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON /* Current setting for loopback. */ uint8_t lpbk; - /* No loopback is selected. Normal operation. */ + /* No loopback is selected. Normal operation. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0) /* * The HW will be configured with local loopback such that @@ -24705,7 +27014,8 @@ /* * The HW will be configured with external loopback such that * host data is sent on the transmitter and based on the external - * loopback connection the data will be received without modification. + * loopback connection the data will be received without + * modification. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3) #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL @@ -24835,7 +27145,51 @@ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2 UINT32_C(0x26) /* 100G_BASEER2 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 UINT32_C(0x27) - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 + /* 400G_BASECR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR UINT32_C(0x28) + /* 100G_BASESR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR UINT32_C(0x29) + /* 100G_BASELR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR UINT32_C(0x2a) + /* 100G_BASEER */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER UINT32_C(0x2b) + /* 200G_BASECR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR2 UINT32_C(0x2c) + /* 200G_BASESR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR2 UINT32_C(0x2d) + /* 200G_BASELR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR2 UINT32_C(0x2e) + /* 200G_BASEER2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER2 UINT32_C(0x2f) + /* 400G_BASECR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR8 UINT32_C(0x30) + /* 200G_BASESR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR8 UINT32_C(0x31) + /* 400G_BASELR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR8 UINT32_C(0x32) + /* 400G_BASEER8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER8 UINT32_C(0x33) + /* 400G_BASECR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR4 UINT32_C(0x34) + /* 400G_BASESR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR4 UINT32_C(0x35) + /* 400G_BASELR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR4 UINT32_C(0x36) + /* 400G_BASEER4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER4 UINT32_C(0x37) + /* 800G_BASECR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASECR8 UINT32_C(0x38) + /* 800G_BASESR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASESR8 UINT32_C(0x39) + /* 800G_BASELR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASELR8 UINT32_C(0x3a) + /* 800G_BASEER8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEER8 UINT32_C(0x3b) + /* 800G_BASEFR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEFR8 UINT32_C(0x3c) + /* 800G_BASEDR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEDR8 UINT32_C(0x3d) + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEDR8 /* This value represents a media type. */ uint8_t media_type; /* Unknown */ @@ -24867,9 +27221,9 @@ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK UINT32_C(0xe0) #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5 /* - * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled. - * Speeds for autoneg with EEE mode enabled - * are based on eee_link_speed_mask. + * When set to 1, Energy Efficient Ethernet (EEE) mode is + * enabled. Speeds for autoneg with EEE mode enabled are based on + * eee_link_speed_mask. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED UINT32_C(0x20) /* @@ -24959,13 +27313,14 @@ /* Select all possible speeds for autoneg mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) /* - * Select only the auto_link_speed speed for autoneg mode. This mode has - * been DEPRECATED. An HWRM client should not use this mode. + * Select only the auto_link_speed speed for autoneg mode. This mode + * has been DEPRECATED. An HWRM client should not use this mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED UINT32_C(0x2) /* - * Select the auto_link_speed or any speed below that speed for autoneg. - * This mode has been DEPRECATED. An HWRM client should not use this mode. + * Select the auto_link_speed or any speed below that speed for + * autoneg. This mode has been DEPRECATED. An HWRM client should not + * use this mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) /* @@ -25047,43 +27402,55 @@ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP (UINT32_C(0xc) << 24) /* QSFP+ */ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS (UINT32_C(0xd) << 24) - /* QSFP28 */ + /* QSFP28/QSFP56 or later */ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 (UINT32_C(0x11) << 24) - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 + /* QSFP-DD */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPDD (UINT32_C(0x18) << 24) + /* QSFP112 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP112 (UINT32_C(0x1e) << 24) + /* SFP-DD CMIS */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFPDD (UINT32_C(0x1f) << 24) + /* SFP CMIS */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_CSFP (UINT32_C(0x20) << 24) + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_CSFP /* * This value represents the current configuration of * Forward Error Correction (FEC) on the port. */ uint16_t fec_cfg; /* - * When set to 1, then FEC is not supported on this port. If this flag - * is set to 1, then all other FEC configuration flags shall be ignored. - * When set to 0, then FEC is supported as indicated by other - * configuration flags. + * When set to 1, then FEC is not supported on this port. If this + * flag is set to 1, then all other FEC configuration flags shall be + * ignored. When set to 0, then FEC is supported as indicated by + * other configuration flags. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED UINT32_C(0x1) /* * When set to 1, then FEC autonegotiation is supported on this port. - * When set to 0, then FEC autonegotiation is not supported on this port. + * When set to 0, then FEC autonegotiation is not supported on this + * port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED UINT32_C(0x2) /* * When set to 1, then FEC autonegotiation is enabled on this port. * When set to 0, then FEC autonegotiation is disabled if supported. - * This flag should be ignored if FEC autonegotiation is not supported on this port. + * This flag should be ignored if FEC autonegotiation is not + * supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED UINT32_C(0x4) /* - * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port. - * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port. + * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this + * port. When set to 0, then FEC CLAUSE 74 (Fire Code) is not + * supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED UINT32_C(0x8) /* * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this * port. This means that FEC CLAUSE 74 is either advertised if * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled. - * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported. - * This flag should be ignored if FEC CLAUSE 74 is not supported on this port. + * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if + * supported. This flag should be ignored if FEC CLAUSE 74 is not + * supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED UINT32_C(0x10) /* @@ -25096,9 +27463,10 @@ * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for * NRZ) is enabled on this port. This means that FEC RS(528,514) is * either advertised if FEC autonegotiation is enabled or FEC - * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514) + * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514) * is disabled if supported. - * This flag should be ignored if FEC CLAUSE 91 is not supported on this port. + * This flag should be ignored if FEC CLAUSE 91 is not supported on + * this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED UINT32_C(0x40) /* @@ -25111,7 +27479,8 @@ * port. This means that FEC RS544_1XN is either advertised if * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled. * When set to 0, then FEC RS544_1XN is disabled if supported. - * This flag should be ignored if FEC RS544_1XN is not supported on this port. + * This flag should be ignored if FEC RS544_1XN is not supported on + * this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED UINT32_C(0x100) /* @@ -25123,8 +27492,9 @@ * When set to 1, then RS(544,514) is enabled on this * port. This means that FEC RS(544,514) is either advertised if * FEC autonegotiation is enabled or FEC RS(544,514) is force - * enabled. When set to 0, then FEC RS(544,514) is disabled if supported. - * This flag should be ignored if FEC RS(544,514) is not supported on this port. + * enabled. When set to 0, then FEC RS(544,514) is disabled if + * supported. This flag should be ignored if FEC RS(544,514) is not + * supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED UINT32_C(0x400) /* @@ -25136,8 +27506,10 @@ * When set to 1, then RS272_1XN is enabled on this * port. This means that FEC RS272_1XN is either advertised if * FEC autonegotiation is enabled or FEC RS272_1XN is force - * enabled. When set to 0, then FEC RS272_1XN is disabled if supported. - * This flag should be ignored if FEC RS272_1XN is not supported on this port. + * enabled. When set to 0, then FEC RS272_1XN is disabled if + * supported. + * This flag should be ignored if FEC RS272_1XN is not supported on + * this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED UINT32_C(0x1000) /* @@ -25149,8 +27521,10 @@ * When set to 1, then RS(272,257) is enabled on this * port. This means that FEC RS(272,257) is either advertised if * FEC autonegotiation is enabled or FEC RS(272,257) is force - * enabled. When set to 0, then FEC RS(272,257) is disabled if supported. - * This flag should be ignored if FEC RS(272,257) is not supported on this port. + * enabled. When set to 0, then FEC RS(272,257) is disabled if + * supported. + * This flag should be ignored if FEC RS(272,257) is not supported on + * this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED UINT32_C(0x4000) /* @@ -25172,6 +27546,11 @@ * trusted. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN UINT32_C(0x2) + /* + * When this bit is '1', speeds2 fields are used to get + * speed details. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SPEEDS2_SUPPORTED UINT32_C(0x4) /* * Up to 16 bytes of null padded ASCII string representing * PHY vendor. @@ -25237,12 +27616,125 @@ uint8_t link_down_reason; /* Remote fault */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_DOWN_REASON_RF UINT32_C(0x1) - uint8_t unused_0[7]; + /* + * The supported speeds for the port. This is a bit mask. + * For each speed that is supported, the corresponding + * bit will be set to '1'. This is valid only if speeds2_supported + * is set in option_flags + */ + uint16_t support_speeds2; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_1GB UINT32_C(0x1) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_10GB UINT32_C(0x2) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_25GB UINT32_C(0x4) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_40GB UINT32_C(0x8) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB UINT32_C(0x10) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB UINT32_C(0x20) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB_PAM4_56 UINT32_C(0x40) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_56 UINT32_C(0x80) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_56 UINT32_C(0x100) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_56 UINT32_C(0x200) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_112 UINT32_C(0x400) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_112 UINT32_C(0x800) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_112 UINT32_C(0x1000) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_800GB_PAM4_112 UINT32_C(0x2000) + /* + * Current setting of forced link speed. When the link speed is not + * being forced, this value shall be set to 0. + * This field is valid only if speeds2_supported is set in + * option_flags. + */ + uint16_t force_link_speeds2; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_1GB UINT32_C(0xa) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_10GB UINT32_C(0x64) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_25GB UINT32_C(0xfa) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_40GB UINT32_C(0x190) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB UINT32_C(0x1f4) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB UINT32_C(0x3e8) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x1f5) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x3e9) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x7d1) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0xfa1) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x3ea) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x7d2) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0xfa2) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x1f42) + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_LAST HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 + /* + * Current setting of auto_link speed_mask that is used to advertise + * speeds during autonegotiation. + * This field is only valid when auto_mode is set to "mask". + * and if speeds2_supported is set in option_flags + * The speeds specified in this field shall be a subset of + * supported speeds on this port. + */ + uint16_t auto_link_speeds2; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_1GB UINT32_C(0x1) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_10GB UINT32_C(0x2) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_25GB UINT32_C(0x4) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_40GB UINT32_C(0x8) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB UINT32_C(0x10) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB UINT32_C(0x20) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x40) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x80) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x100) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0x200) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x400) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x800) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0x1000) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x2000) + /* + * This field is indicate the number of lanes used to transfer + * data. If the link is down, the value is zero. + * This is valid only if speeds2_supported is set in option_flags. + */ + uint8_t active_lanes; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -25425,13 +27917,13 @@ */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI UINT32_C(0x20) /* - * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be - * configured. + * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to + * be configured. */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x40) /* - * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be - * configured. + * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to + * be configured. */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x80) /* @@ -25449,6 +27941,11 @@ * configured. */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE UINT32_C(0x400) + /* + * This bit must be '1' for the ptp_load_control field to + * be configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_LOAD_CONTROL UINT32_C(0x800) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -25458,7 +27955,7 @@ uint8_t ipg; /* This value controls the loopback setting for the MAC. */ uint8_t lpbk; - /* No loopback is selected. Normal operation. */ + /* No loopback is selected. Normal operation. */ #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0) /* * The HW will be configured with local loopback such that @@ -25623,7 +28120,25 @@ * of sync timer updates (measured in parts per billion). */ int32_t ptp_freq_adj_ppb; - uint8_t unused_1[4]; + uint8_t unused_1[3]; + /* + * This value controls how PTP configuration like freq_adj and + * phase are loaded in the hardware block. + */ + uint8_t ptp_load_control; + /* PTP configuration is not loaded in hardware. */ + #define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_NONE UINT32_C(0x0) + /* + * PTP configuration will be loaded immediately in the hardware + * block. By default, it will always be immediate. + */ + #define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_IMMEDIATE UINT32_C(0x1) + /* + * PTP configuration will loaded at the next Pulse per second (PPS) + * event in the hardware block. + */ + #define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_PPS_EVENT UINT32_C(0x2) + #define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_LAST HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_PPS_EVENT /* * This unsigned field specifies the phase offset to be applied * to the PHC (PTP Hardware Clock). This field is specified in @@ -25661,7 +28176,7 @@ uint8_t ipg; /* Current value of the loopback value. */ uint8_t lpbk; - /* No loopback is selected. Normal operation. */ + /* No loopback is selected. Normal operation. */ #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0) /* * The HW will be configured with local loopback such that @@ -25678,9 +28193,9 @@ uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -25759,7 +28274,7 @@ uint8_t ipg; /* The loopback setting for the MAC. */ uint8_t lpbk; - /* No loopback is selected. Normal operation. */ + /* No loopback is selected. Normal operation. */ #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0) /* * The HW will be configured with local loopback such that @@ -25947,20 +28462,35 @@ uint8_t unused_1; uint16_t port_svif_info; /* - * This field specifies the source virtual interface of the port being - * queried. Drivers can use this to program port svif field in the - * L2 context table + * This field specifies the source virtual interface of the port + * being queried. Drivers can use this to program port svif field in + * the L2 context table. */ #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK UINT32_C(0x7fff) #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0 /* This field specifies whether port_svif is valid or not */ #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID UINT32_C(0x8000) - uint8_t unused_2[5]; + /* + * This field indicates the configured load control for PTP + * time of day (TOD) block. + */ + uint8_t ptp_load_control; + /* Indicates the current load control is none. */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_NONE UINT32_C(0x0) + /* Indicates the current load control is immediate. */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_IMMEDIATE UINT32_C(0x1) + /* + * Indicates current load control is at next Pulse per Second (PPS) + * event. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_PPS_EVENT UINT32_C(0x2) + #define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_LAST HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_PPS_EVENT + uint8_t unused_2[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -26049,6 +28579,11 @@ * configured 64bit RTC. */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_RTC_CONFIGURED UINT32_C(0x20) + /* + * When this bit is set to '1', it indicates that current time + * exposed to driver is 64bit. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_64B_PHC_TIME UINT32_C(0x40) uint8_t unused_0[3]; /* * Offset of the PTP register for the lower 32 bits of timestamp @@ -26099,9 +28634,9 @@ uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -26541,9 +29076,9 @@ uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -26620,7 +29155,7 @@ } tx_port_stats_ext_t, *ptx_port_stats_ext_t; /* Port Rx Statistics extended Format */ -/* rx_port_stats_ext (size:3776b/472B) */ +/* rx_port_stats_ext (size:3904b/488B) */ typedef struct rx_port_stats_ext { /* Number of times link state changed to down */ @@ -26747,6 +29282,21 @@ * FEC function in the PHY */ uint64_t rx_fec_uncorrectable_blocks; + /* + * Total number of packets that are dropped due to not matching + * any RX filter rules. This value is zero on the non supported + * controllers. This counter is per controller, Firmware reports the + * same value on active ports. This counter does not include the + * packet discards because of no available buffers. + */ + uint64_t rx_filter_miss; + /* + * This field represents the number of FEC symbol errors by counting + * once for each 10-bit symbol corrected by FEC block. + * rx_fec_corrected_blocks will be incremented if all symbol errors in a + * codeword gets corrected. + */ + uint64_t rx_fec_symbol_err; } rx_port_stats_ext_t, *prx_port_stats_ext_t; /* @@ -27261,9 +29811,9 @@ #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED UINT32_C(0x1) /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -27336,16 +29886,15 @@ * statistics block in bytes. */ uint16_t pfc_wd_stat_size; - uint8_t flags; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; - uint8_t unused_0[4]; } hwrm_port_qstats_ext_pfc_wd_output_t, *phwrm_port_qstats_ext_pfc_wd_output_t; /************************* @@ -27353,7 +29902,7 @@ *************************/ -/* hwrm_port_lpbk_qstats_input (size:128b/16B) */ +/* hwrm_port_lpbk_qstats_input (size:256b/32B) */ typedef struct hwrm_port_lpbk_qstats_input { /* The HWRM command request type. */ @@ -27384,9 +29933,30 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * The size of the loopback statistics buffer passed in the + * loopback_stat_host_addr in bytes. + * Firmware will not exceed this size when it DMAs the + * statistics structure to the host. The actual DMA size + * will be returned in the response. + */ + uint16_t lpbk_stat_size; + uint8_t flags; + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_PORT_LPBK_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + uint8_t unused_0[5]; + /* + * This is the host address where + * loopback statistics will be stored + */ + uint64_t lpbk_stat_host_addr; } hwrm_port_lpbk_qstats_input_t, *phwrm_port_lpbk_qstats_input_t; -/* hwrm_port_lpbk_qstats_output (size:768b/96B) */ +/* hwrm_port_lpbk_qstats_output (size:128b/16B) */ typedef struct hwrm_port_lpbk_qstats_output { /* The specific error status for the command. */ @@ -27397,6 +29967,29 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* + * The size of the loopback statistics block in bytes DMA'ed by the + * firmware. Note that this size will never exceed the lpbk_stat_size + * field passed in by the driver in the hwrm_port_lpbk_qstats_input + * structure. + */ + uint16_t lpbk_stat_size; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} hwrm_port_lpbk_qstats_output_t, *phwrm_port_lpbk_qstats_output_t; + +/* Loopback Port Statistic Format */ +/* port_lpbk_stats (size:640b/80B) */ + +typedef struct port_lpbk_stats { /* Number of transmitted unicast frames */ uint64_t lpbk_ucast_frames; /* Number of transmitted multicast frames */ @@ -27409,24 +30002,15 @@ uint64_t lpbk_mcast_bytes; /* Number of transmitted bytes for broadcast traffic */ uint64_t lpbk_bcast_bytes; - /* Total Tx Drops for loopback traffic reported by STATS block */ - uint64_t tx_stat_discard; - /* Total Tx Error Drops for loopback traffic reported by STATS block */ - uint64_t tx_stat_error; - /* Total Rx Drops for loopback traffic reported by STATS block */ - uint64_t rx_stat_discard; - /* Total Rx Error Drops for loopback traffic reported by STATS block */ - uint64_t rx_stat_error; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} hwrm_port_lpbk_qstats_output_t, *phwrm_port_lpbk_qstats_output_t; + /* Number of dropped tx packets */ + uint64_t lpbk_tx_discards; + /* Number of error dropped tx packets */ + uint64_t lpbk_tx_errors; + /* Number of dropped rx packets */ + uint64_t lpbk_rx_discards; + /* Number of error dropped rx packets */ + uint64_t lpbk_rx_errors; +} port_lpbk_stats_t, *pport_lpbk_stats_t; /************************ * hwrm_port_ecn_qstats * @@ -27510,9 +30094,9 @@ uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -27617,7 +30201,8 @@ * RoCE associated TX/RX cos counters * CNP associated TX/RX cos counters * RoCE/CNP specific TX/RX flow counters - * Firmware will determine the RoCE/CNP cos queue based on qos profile. + * Firmware will determine the RoCE/CNP cos queue based on qos + * profile. * This flag is honored only when RoCE is enabled on that port. */ #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1) @@ -27638,9 +30223,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -27651,7 +30236,7 @@ ****************************/ -/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ +/* hwrm_port_lpbk_clr_stats_input (size:192b/24B) */ typedef struct hwrm_port_lpbk_clr_stats_input { /* The HWRM command request type. */ @@ -27682,6 +30267,9 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Port ID of port that is to be queried. */ + uint16_t port_id; + uint8_t unused_0[6]; } hwrm_port_lpbk_clr_stats_input_t, *phwrm_port_lpbk_clr_stats_input_t; /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ @@ -27698,9 +30286,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -27824,9 +30412,9 @@ uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -27873,7 +30461,7 @@ uint8_t unused_0[6]; } hwrm_port_phy_qcaps_input_t, *phwrm_port_phy_qcaps_input_t; -/* hwrm_port_phy_qcaps_output (size:256b/32B) */ +/* hwrm_port_phy_qcaps_output (size:320b/40B) */ typedef struct hwrm_port_phy_qcaps_output { /* The specific error status for the command. */ @@ -27902,9 +30490,9 @@ */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED UINT32_C(0x4) /* - * Indicates if the configuration of shared PHY settings is supported. - * In cases where a physical port is shared by multiple functions - * (e.g. NPAR, multihost, etc), the configuration of PHY + * Indicates if the configuration of shared PHY settings is + * supported. In cases where a physical port is shared by multiple + * functions (e.g. NPAR, multihost, etc), the configuration of PHY * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case. */ @@ -27912,7 +30500,7 @@ /* * If set to 1, it indicates that the port counters and extended * port counters will not reset when the firmware shuts down or - * resets the PHY. These counters will only be reset during power + * resets the PHY. These counters will only be reset during power * cycle or by calling HWRM_PORT_CLR_STATS. * If set to 0, the state of the counters is unspecified when * firmware shuts down or resets the PHY. @@ -28101,12 +30689,23 @@ * If set to 1, then this field indicates that * priority-based flow control is not supported. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED UINT32_C(0x2) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED UINT32_C(0x2) /* * If set to 1, then this field indicates that * bank based addressing is supported in firmware. */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED UINT32_C(0x4) + /* + * If set to 1, then this field indicates that + * supported_speed2 field is to be used in lieu of all + * supported_speed variants. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_SPEEDS2_SUPPORTED UINT32_C(0x8) + /* + * If set to 1, then this field indicates that + * the device does not support remote loopback. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_REMOTE_LPBK_UNSUPPORTED UINT32_C(0x10) /* * Number of internal ports for this device. This field allows the FW * to advertise how many internal ports are present. Manufacturing @@ -28115,11 +30714,85 @@ * option "HPTN_MODE" is set to 1. */ uint8_t internal_port_cnt; + uint8_t unused_0; + /* + * This is a bit mask to indicate what speeds are supported + * as forced speeds on this link. + * For each speed that can be forced on this link, the + * corresponding mask bit shall be set to '1'. + * This field is valid only if speeds2_supported bit is set in flags2 + */ + uint16_t supported_speeds2_force_mode; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_1GB UINT32_C(0x1) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_10GB UINT32_C(0x2) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_25GB UINT32_C(0x4) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_40GB UINT32_C(0x8) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB UINT32_C(0x10) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB UINT32_C(0x20) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 UINT32_C(0x40) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 UINT32_C(0x80) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 UINT32_C(0x100) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 UINT32_C(0x200) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 UINT32_C(0x400) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 UINT32_C(0x800) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 UINT32_C(0x1000) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 UINT32_C(0x2000) + /* + * This is a bit mask to indicate what speeds are supported + * for autonegotiation on this link. + * For each speed that can be autonegotiated on this link, the + * corresponding mask bit shall be set to '1'. + * This field is valid only if speeds2_supported bit is set in flags2 + */ + uint16_t supported_speeds2_auto_mode; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_1GB UINT32_C(0x1) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_10GB UINT32_C(0x2) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_25GB UINT32_C(0x4) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_40GB UINT32_C(0x8) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB UINT32_C(0x10) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB UINT32_C(0x20) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 UINT32_C(0x40) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 UINT32_C(0x80) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 UINT32_C(0x100) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 UINT32_C(0x200) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 UINT32_C(0x400) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 UINT32_C(0x800) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 UINT32_C(0x1000) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 UINT32_C(0x2000) + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -28208,9 +30881,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -28299,9 +30972,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -28378,9 +31051,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -28457,9 +31130,9 @@ uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -28851,9 +31524,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -29147,9 +31820,9 @@ uint8_t unused_4[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -29465,9 +32138,9 @@ uint8_t unused_4[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -29513,7 +32186,8 @@ uint64_t resp_data_addr; /* * Size of the buffer pointed to by resp_data_addr. The firmware may - * use this entire buffer or less than the entire buffer, but never more. + * use this entire buffer or less than the entire buffer, but never + * more. */ uint16_t data_len; uint16_t flags; @@ -29622,9 +32296,9 @@ uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -29669,13 +32343,20 @@ /* Host address where response diagnostic data is returned. */ uint64_t resp_data_addr; /* - * Size of the buffer pointed to by resp_data_addr. The firmware + * Size of the host buffer pointed to by resp_data_addr. The firmware * may use this entire buffer or less than the entire buffer, but * never more. */ uint16_t data_len; uint16_t unused_0; - uint32_t unused_1; + /* + * Ignored by the start command. + * In legacy buffer mode, this is ignored. The transfer starts + * at buffer offset zero and must be transferred in one command. + * In big buffer mode, this is the offset into the NIC buffer for + * the current retrieve command to start. + */ + uint32_t data_offset; /* Port ID of port where dsc dump to be collected. */ uint16_t port_id; /* Diag level specified by the user */ @@ -29708,20 +32389,48 @@ #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP UINT32_C(0xc) #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP /* - * This field is a lane number - * on which to collect the dsc dump + * This field is the lane number on which to collect the dsc dump. + * If this is 0xFFFF, the dsc dump will be collected for all lanes, + * if the hardware and firmware support this feature. */ uint16_t lane_number; - /* - * Configuration bits. - * Use enable bit to start dsc dump or retrieve dump - */ + /* Configuration bits. */ uint16_t dsc_dump_config; /* * Set 0 to retrieve the dsc dump * Set 1 to start the dsc dump + * Some configuration parameter for the dscdump report are + * set by the start request, and can not be modified until the + * retrieve operation is complete, on the next start. */ #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE UINT32_C(0x1) + /* + * Set 0 to limit the report size to 65535 bytes. + * Set 1 to allow a larger buffer size. + * This can only be set 1 in the start operation. + * If this is set 0 in the start operation, the firmware will + * assume it needs to only expose up to 65535 bytes of the report, + * and only allow a single retrieve operation to retrieve the + * entire report. This mode will truncate longer reports. + * If this is set 1 in the start operation, the firmware will + * report the full size of the report (up to the firmware's limit), + * permit retrieve operations to hold the buffer using the config + * defer_close, and honour the data_offset value so later data + * in the report can be retrieved. + */ + #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_BIG_BUFFER UINT32_C(0x2) + /* + * Set 0 on the last 'retrieve' to release the firmware buffer + * Set 1 on the other 'retrieve' to hold the firmware buffer + * This only affects retrieve operations. + * In big_buffer mode, this allows the driver or tool to tell + * the firmware to keep the report around, as it intends to read + * more of it in. The final read must set this to zero, to tell + * the firmware the report buffer can be released. + * This only works if the start request specified big_buffer as + * one; it is ignored otherwise. + */ + #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_DEFER_CLOSE UINT32_C(0x4) } hwrm_port_dsc_dump_input_t, *phwrm_port_dsc_dump_input_t; /* hwrm_port_dsc_dump_output (size:128b/16B) */ @@ -29735,15 +32444,49 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Total length of stored data. */ + /* + * Total length of stored data; if big_buffer is one, this + * only contains the lower 16 bits of the total length. + * In legacy buffer mode, this is zero in the 'start' response. + * In big buffer mode, this has the size of the report even + * in the 'start' response. + * In both modes, this contains the number of bytes written + * to the host in 'retrieve' responses. + */ uint16_t total_data_len; - uint16_t unused_0; - uint8_t unused_1[3]; + /* + * The upper 16 bits of the total length of stored data. + * In legacy buffer mode, this will always be zero. + * In big buffer mode, this will be populated even in the + * 'start' response. + * This is always zero for 'retrieve' responses. + */ + uint16_t total_data_len_high; + uint8_t unused_1[2]; + /* Result information bits. */ + uint8_t flags; + /* + * Set according to the start request's input big_buffer. + * If this is zero, it indicates the function is acting per + * legacy behaviour -- it will report a buffer size up to almost + * 64KiB, and allow only one retrieval request before releasing + * the firmware buffer containing the report (total_data_len_high + * will be zero). The request's data_offset field and defer_close + * and use_offset config flags are ignored. + * If this is one, it indicates support for (and request of) + * support for larger reports. The full 32b report size (up to the + * firmware buffer limit) is provided by the start response in + * total_data_len (low 16b) and total_data_len_high (high 16b), + * and retrieve requests may keep the buffer using the defer_close + * flag, and retrieve the later parts of the report using the + * data_offset field. + */ + #define HWRM_PORT_DSC_DUMP_OUTPUT_FLAGS_BIG_BUFFER UINT32_C(0x1) /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -29870,7 +32613,7 @@ uint8_t unused[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. When * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29985,7 +32728,7 @@ uint8_t unused[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. When * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -30040,7 +32783,7 @@ */ uint16_t client_id; /* - * Timeout in milli seconds, MDIO BUS will be released automatically + * Timeout in milliseconds, MDIO BUS will be released automatically * after this time, if another mdio acquire command is not received * within the timeout window from the same client. * A 0xFFFF will hold the bus until this bus is released. @@ -30069,9 +32812,9 @@ uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -30140,9 +32883,9 @@ uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -30187,10 +32930,20 @@ /* Modulation types of TX FIR: NRZ, PAM4. */ uint8_t mod_type; /* For NRZ */ - #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) /* For PAM4 */ - #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) - #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) + /* For Optical NRZ */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_NRZ UINT32_C(0x2) + /* For Optical PAM4 */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_PAM4 UINT32_C(0x3) + /* For DAC PAM4 112G */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4_112 UINT32_C(0x4) + /* For Optical PAM4 112G */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_PAM4_112G UINT32_C(0x5) + /* For LPO PAM4 112G */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LPO_PAM4_112G UINT32_C(0x6) + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LPO_PAM4_112G /* The lane mask of the lane TX FIR will be configured. */ uint8_t lane_mask; uint8_t unused_0[2]; @@ -30219,9 +32972,9 @@ uint8_t unused[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -30266,10 +33019,20 @@ /* Modulation types of TX FIR: NRZ, PAM4. */ uint8_t mod_type; /* For NRZ */ - #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) - /* For PAM4 */ - #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) - #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) + /* For PAM4 56G */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) + /* For Optical NRZ */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_NRZ UINT32_C(0x2) + /* For Optical PAM4 56G */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_PAM4 UINT32_C(0x3) + /* For DAC PAM4 112G */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4_112 UINT32_C(0x4) + /* For Optical PAM4 112G */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_PAM4_112 UINT32_C(0x5) + /* For LPO PAM4 112G */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LPO_PAM4_112 UINT32_C(0x6) + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LPO_PAM4_112 /* The ID of the lane TX FIR will be queried. */ uint8_t lane_id; uint8_t unused[6]; @@ -30297,9 +33060,9 @@ uint8_t unused[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -30403,9 +33166,9 @@ */ uint8_t ep2_min_bw; /* - * Specifies the maximum portion of the port's bandwidth that the set of - * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of - * the link bandwidth, from 0 to 100. A value of 0 indicates no + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no * maximum rate. */ uint8_t ep2_max_bw; @@ -30680,9 +33443,9 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -30761,14 +33524,89 @@ uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } hwrm_port_qcfg_output_t, *phwrm_port_qcfg_output_t; +/*********************** + * hwrm_port_mac_qcaps * + ***********************/ + + +/* hwrm_port_mac_qcaps_input (size:192b/24B) */ + +typedef struct hwrm_port_mac_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is being queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} hwrm_port_mac_qcaps_input_t, *phwrm_port_mac_qcaps_input_t; + +/* hwrm_port_mac_qcaps_output (size:128b/16B) */ + +typedef struct hwrm_port_mac_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* MAC capability flags */ + uint8_t flags; + /* + * If set to 1, then this field indicates that the + * MAC does not support local loopback. + */ + #define HWRM_PORT_MAC_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED UINT32_C(0x1) + /* + * If set to 1, then this field indicates that the + * MAC is capable of supporting remote loopback. + */ + #define HWRM_PORT_MAC_QCAPS_OUTPUT_FLAGS_REMOTE_LPBK_SUPPORTED UINT32_C(0x2) + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_port_mac_qcaps_output_t, *phwrm_port_mac_qcaps_output_t; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -31304,8 +34142,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31401,8 +34239,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31446,9 +34284,9 @@ uint64_t resp_addr; uint32_t flags; /* - * Enumeration denoting the RX, TX, or both directions applicable to the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * Enumeration denoting the RX, TX, or both directions applicable to + * the resource. This enumeration is used for resources that are + * similar for both TX and RX paths of the chip. */ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0 @@ -31505,8 +34343,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31605,8 +34443,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31705,8 +34543,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31856,8 +34694,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31901,9 +34739,9 @@ uint64_t resp_addr; uint32_t flags; /* - * Enumeration denoting the RX, TX, or both directions applicable to the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * Enumeration denoting the RX, TX, or both directions applicable to + * the resource. This enumeration is used for resources that are + * similar for both TX and RX paths of the chip. */ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0 @@ -31979,7 +34817,7 @@ */ uint8_t pri1_cos_queue_id; /* - * CoS Queue assigned to priority 2 This value can only + * CoS Queue assigned to priority 2. This value can only * be changed before traffic has started. */ uint8_t pri2_cos_queue_id; @@ -32026,8 +34864,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -32799,8 +35637,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -33613,8 +36451,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -33685,8 +36523,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -33770,8 +36608,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -33865,8 +36703,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -33950,8 +36788,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34073,8 +36911,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34175,7 +37013,7 @@ */ uint8_t tc1_pri_queue_id; /* - * pri assigned to MPLS TC(EXP) 2 This value can only + * pri assigned to MPLS TC(EXP) 2. This value can only * be changed before traffic has started. */ uint8_t tc2_pri_queue_id; @@ -34221,8 +37059,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34293,8 +37131,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34408,8 +37246,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34556,8 +37394,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34688,8 +37526,8 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34831,21 +37669,21 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } hwrm_queue_global_qcfg_output_t, *phwrm_queue_global_qcfg_output_t; -/******************* - * hwrm_vnic_alloc * - *******************/ +/**************************************** + * hwrm_queue_adptv_qos_rx_feature_qcfg * + ****************************************/ -/* hwrm_vnic_alloc_input (size:192b/24B) */ +/* hwrm_queue_adptv_qos_rx_feature_qcfg_input (size:128b/16B) */ -typedef struct hwrm_vnic_alloc_input { +typedef struct hwrm_queue_adptv_qos_rx_feature_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -34874,30 +37712,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * When this bit is '1', this VNIC is requested to - * be the default VNIC for this function. - */ - #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) - /* - * When this bit is '1', proxy VEE PF is requesting - * allocation of a default VNIC on behalf of virtio-net - * function given in virtio_net_fid field. - */ - #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID UINT32_C(0x2) - /* - * Virtio-net function's FID. - * This virtio-net function is requesting allocation of default - * VNIC through proxy VEE PF. - */ - uint16_t virtio_net_fid; - uint8_t unused_0[2]; -} hwrm_vnic_alloc_input_t, *phwrm_vnic_alloc_input_t; +} hwrm_queue_adptv_qos_rx_feature_qcfg_input_t, *phwrm_queue_adptv_qos_rx_feature_qcfg_input_t; -/* hwrm_vnic_alloc_output (size:128b/16B) */ +/* hwrm_queue_adptv_qos_rx_feature_qcfg_output (size:128b/16B) */ -typedef struct hwrm_vnic_alloc_output { +typedef struct hwrm_queue_adptv_qos_rx_feature_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -34906,27 +37725,155 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Logical vnic ID */ - uint32_t vnic_id; - uint8_t unused_0[3]; + /* + * Bitmask indicating which RX CoS queues are enabled or disabled. + * + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is not enabled. + * A value of 1 indicates that the queue is enabled. + */ + uint8_t queue_enable; + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED + /* + * Bitmask indicating which CoS queues are lossy or lossless. + * This setting is kept same across Rx and Tx directions, despite + * the name mentioning only Rx. Each bit represents a specific queue + * where bit 0 represents queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is lossy. + * A value of 1 indicates that the queue is lossless. + */ + uint8_t queue_mode; + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE UINT32_C(0x1) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSY UINT32_C(0x0) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSLESS UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE UINT32_C(0x2) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSY (UINT32_C(0x0) << 1) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSLESS (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE UINT32_C(0x4) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSY (UINT32_C(0x0) << 2) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSLESS (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE UINT32_C(0x8) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSY (UINT32_C(0x0) << 3) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSLESS (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE UINT32_C(0x10) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSY (UINT32_C(0x0) << 4) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSLESS (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE UINT32_C(0x20) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSY (UINT32_C(0x0) << 5) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSLESS (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE UINT32_C(0x40) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSY (UINT32_C(0x0) << 6) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSLESS (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE UINT32_C(0x80) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSY (UINT32_C(0x0) << 7) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSLESS (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSLESS + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_alloc_output_t, *phwrm_vnic_alloc_output_t; +} hwrm_queue_adptv_qos_rx_feature_qcfg_output_t, *phwrm_queue_adptv_qos_rx_feature_qcfg_output_t; -/******************** - * hwrm_vnic_update * - ********************/ +/*************************************** + * hwrm_queue_adptv_qos_rx_feature_cfg * + ***************************************/ -/* hwrm_vnic_update_input (size:256b/32B) */ +/* hwrm_queue_adptv_qos_rx_feature_cfg_input (size:192b/24B) */ -typedef struct hwrm_vnic_update_input { +typedef struct hwrm_queue_adptv_qos_rx_feature_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -34955,68 +37902,147 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Logical vnic ID */ - uint32_t vnic_id; uint32_t enables; + /* This bit must be '1' for the queue_enable field to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_ENABLES_QUEUE_ENABLE UINT32_C(0x1) + /* This bit must be '1' for the queue_mode field to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_ENABLES_QUEUE_MODE UINT32_C(0x2) /* - * This bit must be '1' for the vnic_state field to be - * configured. - */ - #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID UINT32_C(0x1) - /* - * This bit must be '1' for the mru field to be - * configured. - */ - #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID UINT32_C(0x2) - /* - * This bit must be '1' for the metadata_format_type field to be - * configured. - */ - #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID UINT32_C(0x4) - /* - * This will update the context variable with the same name if - * the corresponding enable is set. - */ - uint8_t vnic_state; - /* Normal operation state for the VNIC. */ - #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0) - /* All packets are dropped in this state. */ - #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1) - #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP - /* - * The metadata format type used in all the RX packet completions - * going through this VNIC. - */ - uint8_t metadata_format_type; - /* No metadata information. */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE UINT32_C(0x0) - /* - * Action record pointer (table_scope[4:0], act_rec_ptr[25:0], - * vtag[19:0]). - */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR UINT32_C(0x1) - /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID UINT32_C(0x2) - /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA UINT32_C(0x3) - /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS UINT32_C(0x4) - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS - /* - * The maximum receive unit of the vnic. - * Each vnic is associated with a function. - * The vnic mru value overwrites the mru setting of the - * associated function. - * The HWRM shall make sure that vnic mru does not exceed - * the mru of the port the function is associated with. - */ - uint16_t mru; - uint8_t unused_1[4]; -} hwrm_vnic_update_input_t, *phwrm_vnic_update_input_t; + * Bitmask indicating which RX CoS queues are enabled or disabled. + * + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is not enabled. + * A value of 1 indicates that the queue is enabled. + */ + uint8_t queue_enable; + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED + /* + * Bitmask indicating which CoS queues are lossy or lossless. + * This setting is kept symmetric (or same) across Tx and Rx. + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is lossy. + * A value of 1 indicates that the queue is lossless. + */ + uint8_t queue_mode; + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE UINT32_C(0x1) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSY UINT32_C(0x0) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSLESS UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE UINT32_C(0x2) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSY (UINT32_C(0x0) << 1) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSLESS (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE UINT32_C(0x4) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSY (UINT32_C(0x0) << 2) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSLESS (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE UINT32_C(0x8) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSY (UINT32_C(0x0) << 3) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSLESS (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE UINT32_C(0x10) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSY (UINT32_C(0x0) << 4) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSLESS (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE UINT32_C(0x20) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSY (UINT32_C(0x0) << 5) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSLESS (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE UINT32_C(0x40) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSY (UINT32_C(0x0) << 6) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSLESS (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE UINT32_C(0x80) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSY (UINT32_C(0x0) << 7) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSLESS (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSLESS + uint8_t unused_0[2]; +} hwrm_queue_adptv_qos_rx_feature_cfg_input_t, *phwrm_queue_adptv_qos_rx_feature_cfg_input_t; -/* hwrm_vnic_update_output (size:128b/16B) */ +/* hwrm_queue_adptv_qos_rx_feature_cfg_output (size:128b/16B) */ -typedef struct hwrm_vnic_update_output { +typedef struct hwrm_queue_adptv_qos_rx_feature_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35028,23 +38054,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_update_output_t, *phwrm_vnic_update_output_t; +} hwrm_queue_adptv_qos_rx_feature_cfg_output_t, *phwrm_queue_adptv_qos_rx_feature_cfg_output_t; -/****************** - * hwrm_vnic_free * - ******************/ +/**************************************** + * hwrm_queue_adptv_qos_tx_feature_qcfg * + ****************************************/ -/* hwrm_vnic_free_input (size:192b/24B) */ +/* hwrm_queue_adptv_qos_tx_feature_qcfg_input (size:128b/16B) */ -typedef struct hwrm_vnic_free_input { +typedef struct hwrm_queue_adptv_qos_tx_feature_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35073,14 +38098,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Logical vnic ID */ - uint32_t vnic_id; - uint8_t unused_0[4]; -} hwrm_vnic_free_input_t, *phwrm_vnic_free_input_t; +} hwrm_queue_adptv_qos_tx_feature_qcfg_input_t, *phwrm_queue_adptv_qos_tx_feature_qcfg_input_t; -/* hwrm_vnic_free_output (size:128b/16B) */ +/* hwrm_queue_adptv_qos_tx_feature_qcfg_output (size:128b/16B) */ -typedef struct hwrm_vnic_free_output { +typedef struct hwrm_queue_adptv_qos_tx_feature_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35089,25 +38111,90 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * Bitmask indicating which TX CoS queues are enabled or disabled. + * + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is not enabled. + * A value of 1 indicates that the queue is enabled. + */ + uint8_t queue_enable; + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_free_output_t, *phwrm_vnic_free_output_t; +} hwrm_queue_adptv_qos_tx_feature_qcfg_output_t, *phwrm_queue_adptv_qos_tx_feature_qcfg_output_t; -/***************** - * hwrm_vnic_cfg * - *****************/ +/*************************************** + * hwrm_queue_adptv_qos_tx_feature_cfg * + ***************************************/ -/* hwrm_vnic_cfg_input (size:384b/48B) */ +/* hwrm_queue_adptv_qos_tx_feature_cfg_input (size:192b/24B) */ -typedef struct hwrm_vnic_cfg_input { +typedef struct hwrm_queue_adptv_qos_tx_feature_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35136,268 +38223,370 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + uint32_t enables; + /* This bit must be '1' for the queue_enable field to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_ENABLES_QUEUE_ENABLE UINT32_C(0x1) /* - * When this bit is '1', the VNIC is requested to - * be the default VNIC for the function. + * Bitmask indicating which TX CoS queues are enabled or disabled. + * + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is not enabled. + * A value of 1 indicates that the queue is enabled. + */ + uint8_t queue_enable; + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED + uint8_t unused_0[3]; +} hwrm_queue_adptv_qos_tx_feature_cfg_input_t, *phwrm_queue_adptv_qos_tx_feature_cfg_input_t; + +/* hwrm_queue_adptv_qos_tx_feature_cfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_tx_feature_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT UINT32_C(0x1) + uint8_t valid; +} hwrm_queue_adptv_qos_tx_feature_cfg_output_t, *phwrm_queue_adptv_qos_tx_feature_cfg_output_t; + +/******************** + * hwrm_queue_qcaps * + ********************/ + + +/* hwrm_queue_qcaps_input (size:128b/16B) */ + +typedef struct hwrm_queue_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When this bit is '1', the VNIC is being configured to - * strip VLAN in the RX path. - * If set to '0', then VLAN stripping is disabled on - * this VNIC. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2) + uint16_t cmpl_ring; /* - * When this bit is '1', the VNIC is being configured to - * buffer receive packets in the hardware until the host - * posts new receive buffers. - * If set to '0', then bd_stall is being configured to be - * disabled on this VNIC. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4) + uint16_t seq_id; /* - * When this bit is '1', the VNIC is being configured to - * receive both RoCE and non-RoCE traffic. - * If set to '0', then this VNIC is not configured to be - * operating in dual VNIC mode. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8) + uint16_t target_id; /* - * When this flag is set to '1', the VNIC is requested to - * be configured to receive only RoCE traffic. - * If this flag is set to '0', then this flag shall be - * ignored by the HWRM. - * If roce_dual_vnic_mode flag is set to '1' - * or roce_mirroring_capable_vnic_mode flag to 1, - * then the HWRM client shall not set this flag to '1'. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10) + uint64_t resp_addr; +} hwrm_queue_qcaps_input_t, *phwrm_queue_qcaps_input_t; + +/* hwrm_queue_qcaps_output (size:256b/32B) */ + +typedef struct hwrm_queue_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Adaptive QoS RX feature parameter capability flags. */ + uint32_t rx_feature_params; /* - * When a VNIC uses one destination ring group for certain - * application (e.g. Receive Flow Steering) where - * exact match is used to direct packets to a VNIC with one - * destination ring group only, there is no need to configure - * RSS indirection table for that VNIC as only one destination - * ring group is used. - * - * This flag is used to enable a mode where - * RSS is enabled in the VNIC using a RSS context - * for computing RSS hash but the RSS indirection table is - * not configured using hwrm_vnic_rss_cfg. - * - * If this mode is enabled, then the driver should not program - * RSS indirection table for the RSS context that is used for - * computing RSS hash only. + * When this bit is '1' the capability to configure queue_enable + * is supported. + * If set to '0', then the capability to configure queue_enable + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20) + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_FEATURE_PARAMS_QUEUE_ENABLE_CAP UINT32_C(0x1) /* - * When this bit is '1', the VNIC is being configured to - * receive both RoCE and non-RoCE traffic, but forward only the - * RoCE traffic further. Also, RoCE traffic can be mirrored to - * L2 driver. + * When this bit is '1' the capability to configure queue_mode + * is supported. + * If set to '0', then the capability to configure queue_mode + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE UINT32_C(0x40) + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_FEATURE_PARAMS_QUEUE_MODE_CAP UINT32_C(0x2) + /* Adaptive QoS TX feature parameter capability flags. */ + uint32_t tx_feature_params; /* - * When this bit is '1' it enables ring selection using the incoming - * spif and lcos for the packet. + * When this bit is '1' the capability to configure queue_enable + * is supported. + * If set to '0', then the capability to configure queue_enable + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x80) - uint32_t enables; + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_FEATURE_PARAMS_QUEUE_ENABLE_CAP UINT32_C(0x1) /* - * This bit must be '1' for the dflt_ring_grp field to be - * configured. + * The maximum number of queues that can be configured on this device. + * Valid values range from 1 through 8. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP UINT32_C(0x1) + uint8_t max_configurable_queues; + uint8_t unused_0[3]; + /* Adaptive QoS RX tuning parameter capability flags. */ + uint32_t rx_tuning_params; /* - * This bit must be '1' for the rss_rule field to be - * configured. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE UINT32_C(0x2) + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_WFQ_COST_CAP UINT32_C(0x1) /* - * This bit must be '1' for the cos_rule field to be - * configured. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE UINT32_C(0x4) + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_WFQ_UPPER_FACTOR_CAP UINT32_C(0x2) /* - * This bit must be '1' for the lb_rule field to be - * configured. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE UINT32_C(0x8) + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_HYST_WINDOW_SIZE_FACTOR_CAP UINT32_C(0x4) /* - * This bit must be '1' for the mru field to be - * configured. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU UINT32_C(0x10) + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_PCIE_BW_EFF_CAP UINT32_C(0x8) /* - * This bit must be '1' for the default_rx_ring_id field to be - * configured. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID UINT32_C(0x20) + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_XOFF_HEADROOM_FACTOR_CAP UINT32_C(0x10) /* - * This bit must be '1' for the default_cmpl_ring_id field to be - * configured. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID UINT32_C(0x40) - /* This bit must be '1' for the queue_id field to be configured. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID UINT32_C(0x80) - /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE UINT32_C(0x100) - /* This bit must be '1' for the l2_cqe_mode field to be configured. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_L2_CQE_MODE UINT32_C(0x200) - /* Logical vnic ID */ - uint16_t vnic_id; + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_MIN_LATENCY_CAP UINT32_C(0x20) /* - * Default Completion ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules and if - * there is no COS rule. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - uint16_t dflt_ring_grp; + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_MAX_LATENCY_CAP UINT32_C(0x40) /* - * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if - * there is no RSS rule. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - uint16_t rss_rule; + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_MIN_LATENCY_CAP UINT32_C(0x80) /* - * RSS ID for COS rule/table structure. 0xFF... (All Fs) if - * there is no COS rule. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - uint16_t cos_rule; + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_MAX_LATENCY_CAP UINT32_C(0x100) /* - * RSS ID for load balancing rule/table structure. - * 0xFF... (All Fs) if there is no LB rule. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - uint16_t lb_rule; + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_PIPE_COS_LATENCY_CAP UINT32_C(0x200) /* - * The maximum receive unit of the vnic. - * Each vnic is associated with a function. - * The vnic mru value overwrites the mru setting of the - * associated function. - * The HWRM shall make sure that vnic mru does not exceed - * the mru of the port the function is associated with. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - uint16_t mru; + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_PIPE_COS_LATENCY_CAP UINT32_C(0x400) /* - * Default Rx ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules. - * The aggregation ring associated with the Rx ring is - * implied based on the Rx ring specified when the - * aggregation ring was allocated. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - uint16_t default_rx_ring_id; + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_COS_SHARED_MIN_RATIO_CAP UINT32_C(0x800) /* - * Default completion ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - uint16_t default_cmpl_ring_id; + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_RSVD_CELLS_LIMIT_RATIO_CAP UINT32_C(0x1000) /* - * When specified, only incoming packets classified to the specified CoS - * queue ID will be arriving on this VNIC. Packet priority to CoS mapping - * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode, - * ntuple filters with VNIC destination specified are invalid since they - * conflict with the CoS to VNIC steering rules in this mode. - * - * If this field is not specified, packet to VNIC steering will be - * subject to the standard L2 filter rules and any additional ntuple - * filter rules with destination VNIC specified. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - uint16_t queue_id; + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_SHAPER_REFILL_TIMER_CAP UINT32_C(0x2000) + /* Adaptive QoS TX tuning parameter capability flags. */ + uint32_t tx_tuning_params; /* - * If the device supports the RX V2 and RX TPA start V2 completion - * records as indicated by the HWRM_VNIC_QCAPS command, this field is - * used to specify the two RX checksum modes supported by these - * completion records. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - uint8_t rx_csum_v2_mode; + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_WFQ_COST_CAP UINT32_C(0x1) /* - * When configured with this checksum mode, the number of header - * groups in the delivered packet with a valid IP checksum and - * the number of header groups in the delivered packet with a valid - * L4 checksum are reported. Valid checksums are counted from the - * outermost header group to the innermost header group, stopping at - * the first error. This is the default checksum mode supported if - * the driver doesn't explicitly configure the RX checksum mode. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_WFQ_UPPER_FACTOR_CAP UINT32_C(0x2) /* - * When configured with this checksum mode, the checksum status is - * reported using 'all ok' mode. In the RX completion record, one - * bit indicates if the IP checksum is valid for all the parsed - * header groups with an IP checksum. Another bit indicates if the - * L4 checksum is valid for all the parsed header groups with an L4 - * checksum. The number of header groups that were parsed by the - * chip and passed in the delivered packet is also reported. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1) + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_HYST_WINDOW_SIZE_FACTOR_CAP UINT32_C(0x4) /* - * Any rx_csum_v2_mode value larger than or equal to this is not - * valid + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) - #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_RSVD_CELLS_LIMIT_RATIO_CAP UINT32_C(0x8) /* - * If the device supports different L2 RX CQE modes, as indicated by - * the HWRM_VNIC_QCAPS command, this field is used to configure the - * CQE mode. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - uint8_t l2_cqe_mode; + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_L2_MIN_LATENCY_CAP UINT32_C(0x10) /* - * When configured with this cqe mode, A normal (32B) CQE - * will be generated. This is the default mode. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0) + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_L2_MAX_LATENCY_CAP UINT32_C(0x20) /* - * When configured with this cqe mode, A compressed (16B) CQE - * will be generated. In this mode TPA and HDS are not supported. - * Host drivers should not configure the TPA and HDS along with - * compressed mode, per VNIC. FW returns error, if host drivers - * try to configure the VNIC with compressed mode and (TPA or HDS). - * The compressed completion does not include PTP data. Host - * drivers should not use this mode to receive the PTP data. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1) + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_ROCE_MIN_LATENCY_CAP UINT32_C(0x40) /* - * When configured with this cqe mode, HW generates either a 32B - * completion or a 16B completion depending on use case within a - * VNIC. For ex. a simple L2 packet could use the compressed form - * while a PTP packet on the same VNIC would use the 32B form. + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. */ - #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED UINT32_C(0x2) - #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_LAST HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED - uint8_t unused0[4]; -} hwrm_vnic_cfg_input_t, *phwrm_vnic_cfg_input_t; - -/* hwrm_vnic_cfg_output (size:128b/16B) */ - -typedef struct hwrm_vnic_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_ROCE_MAX_LATENCY_CAP UINT32_C(0x80) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_MAX_TBM_CELLS_PRERESERVED_CAP UINT32_C(0x100) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_SHAPER_REFILL_TIMER_CAP UINT32_C(0x200) + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_cfg_output_t, *phwrm_vnic_cfg_output_t; +} hwrm_queue_qcaps_output_t, *phwrm_queue_qcaps_output_t; -/****************** - * hwrm_vnic_qcfg * - ******************/ +/*************************************** + * hwrm_queue_adptv_qos_rx_tuning_qcfg * + ***************************************/ -/* hwrm_vnic_qcfg_input (size:256b/32B) */ +/* hwrm_queue_adptv_qos_rx_tuning_qcfg_input (size:128b/16B) */ -typedef struct hwrm_vnic_qcfg_input { +typedef struct hwrm_queue_adptv_qos_rx_tuning_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35426,22 +38615,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the vf_id_valid field to be - * configured. - */ - #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) - /* Logical vnic ID */ - uint32_t vnic_id; - /* ID of Virtual Function whose VNIC resource is being queried. */ - uint16_t vf_id; - uint8_t unused_0[6]; -} hwrm_vnic_qcfg_input_t, *phwrm_vnic_qcfg_input_t; +} hwrm_queue_adptv_qos_rx_tuning_qcfg_input_t, *phwrm_queue_adptv_qos_rx_tuning_qcfg_input_t; -/* hwrm_vnic_qcfg_output (size:256b/32B) */ +/* hwrm_queue_adptv_qos_rx_tuning_qcfg_output (size:576b/72B) */ -typedef struct hwrm_vnic_qcfg_output { +typedef struct hwrm_queue_adptv_qos_rx_tuning_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35450,166 +38628,265 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Default Completion ring for the VNIC. */ - uint16_t dflt_ring_grp; - /* - * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if - * there is no RSS rule. - */ - uint16_t rss_rule; - /* - * RSS ID for COS rule/table structure. 0xFF... (All Fs) if - * there is no COS rule. - */ - uint16_t cos_rule; - /* - * RSS ID for load balancing rule/table structure. - * 0xFF... (All Fs) if there is no LB rule. - */ - uint16_t lb_rule; - /* The maximum receive unit of the vnic. */ - uint16_t mru; - uint8_t unused_0[2]; - uint32_t flags; + /* Indicates max credit as required by hardware. */ + uint32_t wfq_cost; /* - * When this bit is '1', the VNIC is the default VNIC for - * the function. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT UINT32_C(0x1) - /* - * When this bit is '1', the VNIC is configured to - * strip VLAN in the RX path. - * If set to '0', then VLAN stripping is disabled on - * this VNIC. + * Specifies a factor that determines the upper bound for each + * cos_wfq_credit_weight. */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2) + uint32_t wfq_upper_factor; /* - * When this bit is '1', the VNIC is configured to - * buffer receive packets in the hardware until the host - * posts new receive buffers. - * If set to '0', then bd_stall is disabled on - * this VNIC. + * The algorithm multiplies this factor by the MRU size to compute the + * hysteresis window size which in turn is used in deassert + * threshold calculations. */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4) + uint32_t hyst_window_size_factor; /* - * When this bit is '1', the VNIC is configured to - * receive both RoCE and non-RoCE traffic. - * If set to '0', then this VNIC is not configured to - * operate in dual VNIC mode. + * Specifies PCIe BW efficiency in the range of 0-100%. System + * characterization determines the value of this parameter. A value of + * less than 100% accounts for internal PCIe over-subscription. The + * algorithm uses this parameter to determine the PCIe BW available + * for transferring received packets to the host. */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8) + uint32_t pcie_bw_eff; + /* Scales the number of cells for xoff. */ + uint32_t xoff_headroom_factor; /* - * When this flag is set to '1', the VNIC is configured to - * receive only RoCE traffic. - * When this flag is set to '0', the VNIC is not configured - * to receive only RoCE traffic. - * If roce_dual_vnic_mode flag and this flag both are set - * to '1', then it is an invalid configuration of the - * VNIC. The HWRM should not allow that type of - * mis-configuration by HWRM clients. + * It is used to calculate the number of reserved cells for cos queues + * configured for L2. Its value is derived from system + * characterization. */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10) + uint32_t l2_min_latency; /* - * When a VNIC uses one destination ring group for certain - * application (e.g. Receive Flow Steering) where - * exact match is used to direct packets to a VNIC with one - * destination ring group only, there is no need to configure - * RSS indirection table for that VNIC as only one destination - * ring group is used. - * - * When this bit is set to '1', then the VNIC is enabled in a - * mode where RSS is enabled in the VNIC using a RSS context - * for computing RSS hash but the RSS indirection table is - * not configured. + * It is used to calculate the number of shared cells for cos queues + * configured for L2. Its value is derived from system + * characterization. */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20) + uint32_t l2_max_latency; /* - * When this bit is '1', the VNIC is configured to - * receive both RoCE and non-RoCE traffic, but forward only - * RoCE traffic further. Also RoCE traffic can be mirrored to - * L2 driver. + * It is used to calculate the number of reserved cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE UINT32_C(0x40) + uint32_t roce_min_latency; /* - * When this bit is '0', VNIC is in normal operation state. - * When this bit is '1', VNIC drops all the received packets. + * It is used to calculate the number of shared cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE UINT32_C(0x80) - /* When this bit is '1' it indicates port cos_mapping_mode enabled. */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x100) + uint32_t roce_max_latency; /* - * When returned with a valid CoS Queue id, the CoS Queue/VNIC association - * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS - * queue association. + * The algorithm uses this parameter to calculate the number of cells + * to be excluded from the total buffer pool to account for the + * latency of pipeline post RE_DEC to PCIe block. Its value is derived + * from system characterization. */ - uint16_t queue_id; + uint32_t l2_pipe_cos_latency; /* - * If the device supports the RX V2 and RX TPA start V2 completion - * records as indicated by the HWRM_VNIC_QCAPS command, this field is - * used to specify the current RX checksum mode configured for all the - * RX rings of a VNIC. + * The algorithm uses this parameter to calculate the number of cells + * to be excluded from the total buffer pool to account for the + * latency of pipeline post RE_DEC to PCIe block. Its value is derived + * from system characterization. */ - uint8_t rx_csum_v2_mode; + uint32_t roce_pipe_cos_latency; + /* Sets the minimum number of shared cells each cos queue can have. */ + uint32_t cos_shared_min_ratio; /* - * This value indicates that the VNIC is configured to use the - * default RX checksum mode for all the rings associated with this - * VNIC. + * The parameter limits the total reserved cells. If the computed + * total reserved cells becomes larger than rsvd_cells_limit_ratio x + * port_cells_avail, then the reserved cells are set to the limit + * value. Its range of values is 0-50%. */ - #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) + uint32_t rsvd_cells_limit_ratio; /* - * This value indicates that the VNIC is configured to use the RX - * checksum ‘all_ok’ mode for all the rings associated with this - * VNIC. + * This parameter is used to compute the time interval for + * replenishing the shaper credit buckets for all RX cos queues. */ - #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1) + uint32_t shaper_refill_timer; + uint8_t unused_0[7]; /* - * Any rx_csum_v2_mode value larger than or equal to this is not - * valid + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) - #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX + uint8_t valid; +} hwrm_queue_adptv_qos_rx_tuning_qcfg_output_t, *phwrm_queue_adptv_qos_rx_tuning_qcfg_output_t; + +/************************************** + * hwrm_queue_adptv_qos_rx_tuning_cfg * + **************************************/ + + +/* hwrm_queue_adptv_qos_rx_tuning_cfg_input (size:640b/80B) */ + +typedef struct hwrm_queue_adptv_qos_rx_tuning_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If the device supports different L2 RX CQE modes, as indicated by - * the HWRM_VNIC_QCAPS command, this field is used to convey the - * configured CQE mode. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t l2_cqe_mode; + uint16_t cmpl_ring; /* - * This value indicates that the VNIC is configured with normal - * (32B) CQE mode. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0) + uint16_t seq_id; /* - * This value indicates that the VNIC is configured with compressed - * (16B) CQE mode. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1) + uint16_t target_id; /* - * This value indicates that the VNIC is configured with mixed - * CQE mode. HW generates either a 32B completion or a 16B - * completion depending on use case within a VNIC. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2) - #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_LAST HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED - uint8_t unused_1[3]; + uint64_t resp_addr; + uint32_t enables; + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_WFQ_COST UINT32_C(0x1) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_WFQ_UPPER_FACTOR UINT32_C(0x2) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_HYST_WINDOW_SIZE_FACTOR UINT32_C(0x4) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_PCIE_BW_EFF UINT32_C(0x8) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_XOFF_HEADROOM_FACTOR UINT32_C(0x10) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_MIN_LATENCY UINT32_C(0x20) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_MAX_LATENCY UINT32_C(0x40) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_MIN_LATENCY UINT32_C(0x80) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_MAX_LATENCY UINT32_C(0x100) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_PIPE_COS_LATENCY UINT32_C(0x200) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_PIPE_COS_LATENCY UINT32_C(0x400) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_COS_SHARED_MIN_RATIO UINT32_C(0x800) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_RSVD_CELLS_LIMIT_RATIO UINT32_C(0x1000) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_SHAPER_REFILL_TIMER UINT32_C(0x2000) + /* Indicates max credit as required by hardware. */ + uint32_t wfq_cost; + /* + * Specifies a factor that determines the upper bound for each + * cos_wfq_credit_weight. + */ + uint32_t wfq_upper_factor; + /* + * The algorithm multiplies this factor by the MRU size to compute the + * hysteresis window size which in turn is used in deassert + * threshold calculations. + */ + uint32_t hyst_window_size_factor; + /* + * Specifies PCIe BW efficiency in the range of 0-100%. System + * characterization determines the value of this parameter. A value of + * less than 100% accounts for internal PCIe over-subscription. The + * algorithm uses this parameter to determine the PCIe BW available + * for transferring received packets to the host. + */ + uint32_t pcie_bw_eff; + /* Scales the number of cells for xoff. */ + uint32_t xoff_headroom_factor; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_max_latency; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_max_latency; + /* + * The algorithm uses this parameter to calculate the number of cells + * to be excluded from the total buffer pool to account for the + * latency of pipeline post RE_DEC to PCIe block. Its value is derived + * from system characterization. + */ + uint32_t l2_pipe_cos_latency; + /* + * The algorithm uses this parameter to calculate the number of cells + * to be excluded from the total buffer pool to account for the + * latency of pipeline post RE_DEC to PCIe block. Its value is derived + * from system characterization. + */ + uint32_t roce_pipe_cos_latency; + /* Sets the minimum number of shared cells each cos queue can have. */ + uint32_t cos_shared_min_ratio; + /* + * The parameter limits the total reserved cells. If the computed + * total reserved cells becomes larger than rsvd_cells_limit_ratio x + * port_cells_avail, then the reserved cells are set to the limit + * value. Its range of values is 0-50%. + */ + uint32_t rsvd_cells_limit_ratio; + /* + * This parameter is used to compute the time interval for + * replenishing the shaper credit buckets for all RX cos queues. + */ + uint32_t shaper_refill_timer; + uint8_t unused_0[4]; +} hwrm_queue_adptv_qos_rx_tuning_cfg_input_t, *phwrm_queue_adptv_qos_rx_tuning_cfg_input_t; + +/* hwrm_queue_adptv_qos_rx_tuning_cfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_rx_tuning_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_qcfg_output_t, *phwrm_vnic_qcfg_output_t; +} hwrm_queue_adptv_qos_rx_tuning_cfg_output_t, *phwrm_queue_adptv_qos_rx_tuning_cfg_output_t; -/******************* - * hwrm_vnic_qcaps * - *******************/ +/*************************************** + * hwrm_queue_adptv_qos_tx_tuning_qcfg * + ***************************************/ -/* hwrm_vnic_qcaps_input (size:192b/24B) */ +/* hwrm_queue_adptv_qos_tx_tuning_qcfg_input (size:128b/16B) */ -typedef struct hwrm_vnic_qcaps_input { +typedef struct hwrm_queue_adptv_qos_tx_tuning_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35638,13 +38915,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - uint8_t unused_0[4]; -} hwrm_vnic_qcaps_input_t, *phwrm_vnic_qcaps_input_t; +} hwrm_queue_adptv_qos_tx_tuning_qcfg_input_t, *phwrm_queue_adptv_qos_tx_tuning_qcfg_input_t; -/* hwrm_vnic_qcaps_output (size:192b/24B) */ +/* hwrm_queue_adptv_qos_tx_tuning_qcfg_output (size:448b/56B) */ -typedef struct hwrm_vnic_qcaps_output { +typedef struct hwrm_queue_adptv_qos_tx_tuning_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -35653,231 +38928,76 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The maximum receive unit that is settable on a vnic. */ - uint16_t mru; - uint8_t unused_0[2]; - uint32_t flags; - /* Unused. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED UINT32_C(0x1) - /* - * When this bit is '1', the capability of stripping VLAN in - * the RX path is supported on VNIC(s). - * If set to '0', then VLAN stripping capability is - * not supported on VNIC(s). - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP UINT32_C(0x2) - /* - * When this bit is '1', the capability to buffer receive - * packets in the hardware until the host posts new receive buffers - * is supported on VNIC(s). - * If set to '0', then bd_stall capability is not supported - * on VNIC(s). - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP UINT32_C(0x4) - /* - * When this bit is '1', the capability to - * receive both RoCE and non-RoCE traffic on VNIC(s) is - * supported. - * If set to '0', then the capability to receive - * both RoCE and non-RoCE traffic on VNIC(s) is - * not supported. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP UINT32_C(0x8) - /* - * When this bit is set to '1', the capability to configure - * a VNIC to receive only RoCE traffic is supported. - * When this flag is set to '0', the VNIC capability to - * configure to receive only RoCE traffic is not supported. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP UINT32_C(0x10) - /* - * When this bit is set to '1', then the capability to enable - * a VNIC in a mode where RSS context without configuring - * RSS indirection table is supported (for RSS hash computation). - * When this bit is set to '0', then a VNIC can not be configured - * with a mode to enable RSS context without configuring RSS - * indirection table. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP UINT32_C(0x20) - /* - * When this bit is '1', the capability to - * mirror the RoCE traffic is supported. - * If set to '0', then the capability to mirror the - * RoCE traffic is not supported. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP UINT32_C(0x40) - /* - * When this bit is '1', the outermost RSS hashing capability - * is supported. If set to '0', then the outermost RSS hashing - * capability is not supported. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP UINT32_C(0x80) - /* - * When this bit is '1', it indicates that firmware supports the - * ability to steer incoming packets from one CoS queue to one - * VNIC. This optional feature can then be enabled - * using HWRM_VNIC_CFG on any VNIC. This feature is only - * available when NVM option “enable_cos_classification” is set - * to 1. If set to '0', firmware does not support this feature. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP UINT32_C(0x100) - /* - * When this bit is '1', it indicates that HW and firmware supports - * the use of RX V2 and RX TPA start V2 completion records for all - * the RX rings of a VNIC. Once set, this feature is mandatory to - * be used for the RX rings of the VNIC. Additionally, two new RX - * checksum features supported by these completion records can be - * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the - * HW and the firmware does not support this feature. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP UINT32_C(0x200) - /* - * When this bit is '1', it indicates that HW and firmware support - * vnic state change. Host drivers can change the vnic state using - * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not - * support this feature. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP UINT32_C(0x400) - /* - * When this bit is '1', it indicates that firmware supports - * virtio-net functions default VNIC allocation using - * HWRM_VNIC_ALLOC. - * This capability is available only on Proxy VEE PF. If set to '0', - * firmware does not support this feature. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP UINT32_C(0x800) - /* - * When this bit is set '1', then the capability to configure the - * metadata format in the RX completion is supported for the VNIC. - * When this bit is set to '0', then the capability to configure - * the metadata format in the RX completion is not supported for - * the VNIC. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP UINT32_C(0x1000) - /* - * When this bit is set '1', it indicates that firmware returns - * INVALID_PARAM error, if host drivers choose invalid hash type - * bit combinations in vnic_rss_cfg. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP UINT32_C(0x2000) - /* - * When this bit is set '1', it indicates that firmware supports - * the hash_type include and exclude flags in hwrm_vnic_rss_cfg. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP UINT32_C(0x4000) - /* - * When this bit is '1', it indicates that HW is capable of using - * Toeplitz algorithm. This mode uses Toeplitz algorithm and - * provided Toeplitz hash key to hash the packets according to the - * configured hash type and hash mode. The Toeplitz hash results and - * the provided Toeplitz RSS indirection table are used to determine - * the RSS rings. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP UINT32_C(0x8000) - /* - * When this bit is '1', it indicates that HW is capable of using - * XOR algorithm. This mode uses XOR algorithm to hash the packets - * according to the configured hash type and hash mode. The XOR - * hash results and the provided XOR RSS indirection table are - * used to determine the RSS rings. Host drivers provided hash key - * is not honored in this mode. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_XOR_CAP UINT32_C(0x10000) - /* - * When this bit is '1', it indicates that HW is capable of using - * checksum algorithm. In this mode, HW uses inner packets checksum - * algorithm to distribute the packets across the rings and Toeplitz - * algorithm to calculate the hash to convey it in the RX - * completions. Host drivers should provide Toeplitz hash key. - * As HW uses innermost packets checksum to distribute the packets - * across the rings, host drivers can't convey hash mode to choose - * outer headers to calculate Toeplitz hash. FW will fail such - * configuration. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP UINT32_C(0x20000) - /* - * When this bit is '1' HW supports hash calculation - * based on IPV6 flow labels. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP UINT32_C(0x40000) - /* - * When this bit is '1', it indicates that HW and firmware supports - * the use of RX V3 and RX TPA start V3 completion records for all - * the RX rings of a VNIC. Once set, this feature is mandatory to - * be used for the RX rings of the VNIC. If set to '0', the - * HW and the firmware does not support this feature. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V3_CAP UINT32_C(0x80000) + /* Indicates max credit as required by hardware. */ + uint32_t wfq_cost; /* - * When this bit is '1' HW supports different RX CQE record types. - * Host drivers can choose the mode based on their application - * requirements like performance, TPA, HDS and PTP. - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP UINT32_C(0x100000) - /* - * When this bit is '1' HW supports hash calculation - * based on IPv4 IPSEC AH SPI field. + * Specifies a factor that determines the upper bound for each + * cos_wfq_credit_weight. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP UINT32_C(0x200000) + uint32_t wfq_upper_factor; /* - * When this bit is '1' HW supports hash calculation - * based on IPv4 IPSEC ESP SPI field. + * The algorithm multiplies this factor by the MRU size to compute the + * hysteresis window size which in turn is used in deassert + * threshold calculations. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP UINT32_C(0x400000) + uint32_t hyst_window_size_factor; /* - * When this bit is '1' HW supports hash calculation - * based on IPv6 IPSEC AH SPI field. + * The parameter limits the total reserved cells. If the computed + * total reserved cells becomes larger than rsvd_cells_limit_ratio x + * port_cells_avail, then the reserved cells are set to the limit + * value. Its range of values is 0-50%. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP UINT32_C(0x800000) + uint32_t rsvd_cells_limit_ratio; /* - * When this bit is '1' HW supports hash calculation - * based on IPv6 IPSEC ESP SPI field. + * It is used to calculate the number of reserved cells for cos queues + * configured for L2. Its value is derived from system + * characterization. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP UINT32_C(0x1000000) + uint32_t l2_min_latency; /* - * When outermost_rss_cap is '1' and this bit is '1', the outermost - * RSS hash mode may be set on a PF or trusted VF. - * When outermost_rss_cap is '1' and this bit is '0', the outermost - * RSS hash mode may be set on a PF. + * It is used to calculate the number of shared cells for cos queues + * configured for L2. Its value is derived from system + * characterization. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP UINT32_C(0x2000000) + uint32_t l2_max_latency; /* - * When this bit is '1' it indicates HW is capable of enabling ring - * selection using the incoming spif and lcos for the packet. + * It is used to calculate the number of reserved cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x4000000) + uint32_t roce_min_latency; /* - * When this bit is '1', it indicates controller enabled - * RSS profile TCAM mode. + * It is used to calculate the number of shared cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_PROF_TCAM_MODE_ENABLED UINT32_C(0x8000000) - /* When this bit is '1' FW supports VNIC hash mode. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP UINT32_C(0x10000000) + uint32_t roce_max_latency; + /* Specifies the number of reserved cells TRP requires per cos queue. */ + uint32_t max_tbm_cells_prereserved; /* - * This field advertises the maximum concurrent TPA aggregations - * supported by the VNIC on new devices that support TPA v2 or v3. - * '0' means that both the TPA v2 and v3 are not supported. + * This parameter is used to compute the time interval for + * replenishing the shaper credit buckets for all TX cos queues. */ - uint16_t max_aggs_supported; - uint8_t unused_1[5]; + uint32_t shaper_refill_timer; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_qcaps_output_t, *phwrm_vnic_qcaps_output_t; +} hwrm_queue_adptv_qos_tx_tuning_qcfg_output_t, *phwrm_queue_adptv_qos_tx_tuning_qcfg_output_t; -/********************* - * hwrm_vnic_tpa_cfg * - *********************/ +/************************************** + * hwrm_queue_adptv_qos_tx_tuning_cfg * + **************************************/ -/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ +/* hwrm_queue_adptv_qos_tx_tuning_cfg_input (size:512b/64B) */ -typedef struct hwrm_vnic_tpa_cfg_input { +typedef struct hwrm_queue_adptv_qos_tx_tuning_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -35906,148 +39026,84 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) of - * non-tunneled TCP packets. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA UINT32_C(0x1) - /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) of - * tunneled TCP packets. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA UINT32_C(0x2) - /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) according - * to Windows Receive Segment Coalescing (RSC) rules. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4) - /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) according - * to Linux Generic Receive Offload (GRO) rules. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO UINT32_C(0x8) - /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for TCP - * packets with IP ECN set to non-zero. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10) - /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * GRE tunneled TCP packets only if all packets have the - * same GRE sequence. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20) - /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * TCP/IPv4 packets with consecutively increasing IPIDs. - * In other words, the last packet that is being - * aggregated to an already existing aggregation context - * shall have IPID 1 more than the IPID of the last packet - * that was aggregated in that aggregation context. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40) - /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) - * value. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80) - /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC shall DMA payload data using GRO rules. - * When this bit is '0', the VNIC shall DMA payload data - * using the more efficient LRO rules of filling all - * aggregation buffers. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO UINT32_C(0x100) uint32_t enables; - /* - * This bit must be '1' for the max_agg_segs field to be - * configured. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1) - /* - * This bit must be '1' for the max_aggs field to be - * configured. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2) - /* - * This bit must be '1' for the max_agg_timer field to be - * configured. - */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4) - /* deprecated bit. Do not use!!! */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8) - /* Logical vnic ID */ - uint16_t vnic_id; - /* - * This is the maximum number of TCP segments that can - * be aggregated (unit is Log2). Max value is 31. On new - * devices supporting TPA v2, the unit is multiples of 4 and - * valid values are > 0 and <= 63. - */ - uint16_t max_agg_segs; - /* 1 segment */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) - /* 2 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) - /* 4 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) - /* 8 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) - /* Any segment size larger than this is not valid */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX - /* - * This is the maximum number of aggregations this VNIC is - * allowed (unit is Log2). Max value is 7. On new devices - * supporting TPA v2, this is in unit of 1 and must be > 0 - * and <= max_aggs_supported in the hwrm_vnic_qcaps response - * to enable TPA v2. - */ - uint16_t max_aggs; - /* 1 aggregation */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0) - /* 2 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1) - /* 4 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2) - /* 8 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3) - /* 16 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4) - /* Any aggregation size larger than this is not valid */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7) - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX - uint8_t unused_0[2]; - /* - * This is the maximum amount of time allowed for - * an aggregation context to complete after it was initiated. - */ - uint32_t max_agg_timer; - /* - * This is the minimum amount of payload length required to - * start an aggregation context. This field is deprecated and - * should be set to 0. The minimum length is set by firmware - * and can be queried using hwrm_vnic_tpa_qcfg. - */ - uint32_t min_agg_len; -} hwrm_vnic_tpa_cfg_input_t, *phwrm_vnic_tpa_cfg_input_t; + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_WFQ_COST UINT32_C(0x1) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_WFQ_UPPER_FACTOR UINT32_C(0x2) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_HYST_WINDOW_SIZE_FACTOR UINT32_C(0x4) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_RSVD_CELLS_LIMIT_RATIO UINT32_C(0x8) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_L2_MIN_LATENCY UINT32_C(0x10) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_L2_MAX_LATENCY UINT32_C(0x20) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_ROCE_MIN_LATENCY UINT32_C(0x40) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_ROCE_MAX_LATENCY UINT32_C(0x80) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_MAX_TBM_CELLS_PRERESERVED UINT32_C(0x100) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_SHAPER_REFILL_TIMER UINT32_C(0x200) + /* Indicates max credit as required by hardware. */ + uint32_t wfq_cost; + /* + * Specifies a factor that determines the upper bound for each + * cos_wfq_credit_weight. + */ + uint32_t wfq_upper_factor; + /* + * The algorithm multiplies this factor by the MRU size to compute the + * hysteresis window size which in turn is used in deassert + * threshold calculations. + */ + uint32_t hyst_window_size_factor; + /* + * The parameter limits the total reserved cells. If the computed + * total reserved cells becomes larger than rsvd_cells_limit_ratio x + * port_cells_avail, then the reserved cells are set to the limit + * value. Its range of values is 0-50%. + */ + uint32_t rsvd_cells_limit_ratio; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_max_latency; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_max_latency; + /* Specifies the number of reserved cells TRP requires per cos queue. */ + uint32_t max_tbm_cells_prereserved; + /* + * This parameter is used to compute the time interval for + * replenishing the shaper credit buckets for all TX cos queues. + */ + uint32_t shaper_refill_timer; + uint8_t unused_0[4]; +} hwrm_queue_adptv_qos_tx_tuning_cfg_input_t, *phwrm_queue_adptv_qos_tx_tuning_cfg_input_t; -/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ +/* hwrm_queue_adptv_qos_tx_tuning_cfg_output (size:128b/16B) */ -typedef struct hwrm_vnic_tpa_cfg_output { +typedef struct hwrm_queue_adptv_qos_tx_tuning_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36059,22 +39115,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_tpa_cfg_output_t, *phwrm_vnic_tpa_cfg_output_t; +} hwrm_queue_adptv_qos_tx_tuning_cfg_output_t, *phwrm_queue_adptv_qos_tx_tuning_cfg_output_t; -/********************** - * hwrm_vnic_tpa_qcfg * - **********************/ +/********************************** + * hwrm_queue_pfcwd_timeout_qcaps * + **********************************/ -/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ +/* hwrm_queue_pfcwd_timeout_qcaps_input (size:128b/16B) */ -typedef struct hwrm_vnic_tpa_qcfg_input { +typedef struct hwrm_queue_pfcwd_timeout_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -36103,14 +39159,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Logical vnic ID */ - uint16_t vnic_id; - uint8_t unused_0[6]; -} hwrm_vnic_tpa_qcfg_input_t, *phwrm_vnic_tpa_qcfg_input_t; +} hwrm_queue_pfcwd_timeout_qcaps_input_t, *phwrm_queue_pfcwd_timeout_qcaps_input_t; -/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ +/* hwrm_queue_pfcwd_timeout_qcaps_output (size:128b/16B) */ -typedef struct hwrm_vnic_tpa_qcfg_output { +typedef struct hwrm_queue_pfcwd_timeout_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36119,126 +39172,90 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) of - * non-tunneled TCP packets. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA UINT32_C(0x1) - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) of - * tunneled TCP packets. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA UINT32_C(0x2) - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) according - * to Windows Receive Segment Coalescing (RSC) rules. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4) - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) according - * to Linux Generic Receive Offload (GRO) rules. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO UINT32_C(0x8) - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) for TCP - * packets with IP ECN set to non-zero. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10) - /* - * When this bit is '1', the VNIC is configured to - * perform transparent packet aggregation (TPA) for - * GRE tunneled TCP packets only if all packets have the - * same GRE sequence. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20) - /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC is configured to - * perform transparent packet aggregation (TPA) for - * TCP/IPv4 packets with consecutively increasing IPIDs. - * In other words, the last packet that is being - * aggregated to an already existing aggregation context - * shall have IPID 1 more than the IPID of the last packet - * that was aggregated in that aggregation context. - */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40) + /* Max configurable pfc watchdog timeout value in msec. */ + uint32_t max_pfcwd_timeout; + uint8_t unused_0[3]; /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC is configured to - * perform transparent packet aggregation (TPA) for - * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) - * value. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80) + uint8_t valid; +} hwrm_queue_pfcwd_timeout_qcaps_output_t, *phwrm_queue_pfcwd_timeout_qcaps_output_t; + +/******************************** + * hwrm_queue_pfcwd_timeout_cfg * + ********************************/ + + +/* hwrm_queue_pfcwd_timeout_cfg_input (size:192b/24B) */ + +typedef struct hwrm_queue_pfcwd_timeout_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This is the maximum number of TCP segments that can - * be aggregated (unit is Log2). Max value is 31. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t max_agg_segs; - /* 1 segment */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) - /* 2 segments */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) - /* 4 segments */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) - /* 8 segments */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) - /* Any segment size larger than this is not valid */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_LAST HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX + uint16_t cmpl_ring; /* - * This is the maximum number of aggregations this VNIC is - * allowed (unit is Log2). Max value is 7 + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t max_aggs; - /* 1 aggregation */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0) - /* 2 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1) - /* 4 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2) - /* 8 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3) - /* 16 aggregations */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4) - /* Any aggregation size larger than this is not valid */ - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7) - #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_LAST HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX + uint16_t seq_id; /* - * This is the maximum amount of time allowed for - * an aggregation context to complete after it was initiated. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint32_t max_agg_timer; + uint16_t target_id; /* - * This is the minimum amount of payload length required to - * start an aggregation context. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t min_agg_len; + uint64_t resp_addr; + /* pfc watchdog timeout value in msec. */ + uint32_t pfcwd_timeout_value; + uint8_t unused_0[4]; +} hwrm_queue_pfcwd_timeout_cfg_input_t, *phwrm_queue_pfcwd_timeout_cfg_input_t; + +/* hwrm_queue_pfcwd_timeout_cfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_pfcwd_timeout_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_tpa_qcfg_output_t, *phwrm_vnic_tpa_qcfg_output_t; +} hwrm_queue_pfcwd_timeout_cfg_output_t, *phwrm_queue_pfcwd_timeout_cfg_output_t; -/********************* - * hwrm_vnic_rss_cfg * - *********************/ +/********************************* + * hwrm_queue_pfcwd_timeout_qcfg * + *********************************/ -/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ +/* hwrm_queue_pfcwd_timeout_qcfg_input (size:128b/16B) */ -typedef struct hwrm_vnic_rss_cfg_input { +typedef struct hwrm_queue_pfcwd_timeout_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -36267,204 +39284,206 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t hash_type; +} hwrm_queue_pfcwd_timeout_qcfg_input_t, *phwrm_queue_pfcwd_timeout_qcfg_input_t; + +/* hwrm_queue_pfcwd_timeout_qcfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_pfcwd_timeout_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Current configured pfc watchdog timeout value in msec. */ + uint32_t pfcwd_timeout_value; + uint8_t unused_0[3]; /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv4 - * packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of TCP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of UDP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv6 addresses of IPv6 - * packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of TCP/IPv6 packets. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + uint8_t valid; +} hwrm_queue_pfcwd_timeout_qcfg_output_t, *phwrm_queue_pfcwd_timeout_qcfg_output_t; + +/******************* + * hwrm_vnic_alloc * + *******************/ + + +/* hwrm_vnic_alloc_input (size:192b/24B) */ + +typedef struct hwrm_vnic_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of UDP/IPv6 packets. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + uint16_t cmpl_ring; /* - * When this bit is '1', the RSS hash shall be computed - * over source, destination IPv6 addresses and flow label of IPv6 - * packets. Hash type ipv6 and ipv6_flow_label are mutually - * exclusive. HW does not include the flow_label in hash - * calculation for the packets that are matching tcp_ipv6 and - * udp_ipv6 hash types. Host drivers should set this bit based on - * rss_ipv6_flow_label_cap. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL UINT32_C(0x40) + uint16_t seq_id; /* - * When this bit is '1', the RSS hash shall be computed over - * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC - * AH/IPv4 packets. Host drivers should set this bit based on - * rss_ipsec_ah_spi_ipv4_cap. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 UINT32_C(0x80) + uint16_t target_id; /* - * When this bit is '1', the RSS hash shall be computed over - * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC - * ESP/IPv4 packets. Host drivers should set this bit based on - * rss_ipsec_esp_spi_ipv4_cap. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 UINT32_C(0x100) + uint64_t resp_addr; + uint32_t flags; /* - * When this bit is '1', the RSS hash shall be computed over - * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC - * AH/IPv6 packets. Host drivers should set this bit based on - * rss_ipsec_ah_spi_ipv6_cap. + * When this bit is '1', this VNIC is requested to + * be the default VNIC for this function. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6 UINT32_C(0x200) + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) /* - * When this bit is '1', the RSS hash shall be computed over - * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC - * ESP/IPv6 packets. Host drivers should set this bit based on - * rss_ipsec_esp_spi_ipv6_cap. + * When this bit is '1', proxy VEE PF is requesting + * allocation of a default VNIC on behalf of virtio-net + * function given in virtio_net_fid field. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6 UINT32_C(0x400) - /* VNIC ID of VNIC associated with RSS table being configured. */ - uint16_t vnic_id; + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID UINT32_C(0x2) /* - * Specifies which VNIC ring table pair to configure. - * Valid values range from 0 to 7. + * Virtio-net function's FID. + * This virtio-net function is requesting allocation of default + * VNIC through proxy VEE PF. */ - uint8_t ring_table_pair_index; + uint16_t virtio_net_fid; + uint8_t unused_0[2]; +} hwrm_vnic_alloc_input_t, *phwrm_vnic_alloc_input_t; + +/* hwrm_vnic_alloc_output (size:128b/16B) */ + +typedef struct hwrm_vnic_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[3]; /* - * Flags to specify different RSS hash modes. Global RSS hash mode is - * indicated when vnic_id and rss_ctx_idx fields are set to value of - * 0xffff. Only PF can initiate global RSS hash mode setting changes. - * VNIC RSS hash mode is indicated with valid vnic_id and rss_ctx_idx, - * if FW is VNIC_RSS_HASH_MODE capable. FW configures the mode based - * on first come first serve order. Global RSS hash mode and VNIC RSS - * hash modes are mutually exclusive. FW returns invalid error - * if FW receives conflicting requests. To change the current hash - * mode, the mode associated drivers need to be unloaded and apply - * the new configuration. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t hash_mode_flags; + uint8_t valid; +} hwrm_vnic_alloc_output_t, *phwrm_vnic_alloc_output_t; + +/******************** + * hwrm_vnic_update * + ********************/ + + +/* hwrm_vnic_update_input (size:256b/32B) */ + +typedef struct hwrm_vnic_update_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable, - * innermost_4 and innermost_2 hash modes are used to configure - * the tuple mode. When this bit is '1' and FW is not - * VNIC_RSS_HASH_MODE capable, It indicates using current RSS hash - * mode setting configured in the device otherwise. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1) + uint16_t cmpl_ring; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 4 tuples {l3.src, l3.dest, - * l4.src, l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2) + uint16_t seq_id; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4) + uint16_t target_id; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, - * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8) + uint64_t resp_addr; + /* Logical vnic ID */ + uint32_t vnic_id; + uint32_t enables; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * This bit must be '1' for the vnic_state field to be + * configured. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10) - /* This is the address for rss ring group table */ - uint64_t ring_grp_tbl_addr; - /* This is the address for rss hash key table */ - uint64_t hash_key_tbl_addr; - /* Index to the rss indirection table. */ - uint16_t rss_ctx_idx; - uint8_t flags; + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID UINT32_C(0x1) /* - * When this bit is '1', it indicates that the hash_type field is - * interpreted as a change relative the current configuration. Each - * '1' bit in hash_type represents a header to add to the current - * hash. Zeroes designate the hash_type state bits that should remain - * unchanged, if possible. If this constraint on the existing state - * cannot be satisfied, then the implementation should preference - * adding other headers so as to honor the request to add the - * specified headers. It is an error to set this flag concurrently - * with hash_type_exclude. + * This bit must be '1' for the mru field to be + * configured. */ - #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE UINT32_C(0x1) + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID UINT32_C(0x2) /* - * When this bit is '1', it indicates that the hash_type field is - * interpreted as a change relative the current configuration. Each - * '1' bit in hash_type represents a header to remove from the - * current hash. Zeroes designate the hash_type state bits that - * should remain unchanged, if possible. If this constraint on the - * existing state cannot be satisfied, then the implementation should - * preference removing other headers so as to honor the request to - * remove the specified headers. It is an error to set this flag - * concurrently with hash_type_include. + * This bit must be '1' for the metadata_format_type field to be + * configured. */ - #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE UINT32_C(0x2) - uint8_t ring_select_mode; + #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID UINT32_C(0x4) /* - * In this mode, HW uses Toeplitz algorithm and provided Toeplitz - * hash key to hash the packets according to the configured hash - * type and hash mode. The Toeplitz hash results and the provided - * Toeplitz RSS indirection table are used to determine the RSS - * rings. + * This will update the context variable with the same name if + * the corresponding enable is set. */ - #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ UINT32_C(0x0) + uint8_t vnic_state; + /* Normal operation state for the VNIC. */ + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0) + /* All packets are dropped in this state. */ + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1) + #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP /* - * In this mode, HW uses XOR algorithm to hash the packets according - * to the configured hash type and hash mode. The XOR hash results - * and the provided XOR RSS indirection table are used to determine - * the RSS rings. Host drivers provided hash key is not honored in - * this mode. + * The metadata format type used in all the RX packet completions + * going through this VNIC. This value is product specific. Refer to + * the L2 HSI completion ring structures for the detailed + * descriptions. For Thor and Thor2, it corresponds to 'meta_format' + * in 'rx_pkt_cmpl_hi' and 'rx_pkt_v3_cmpl_hi', respectively. */ - #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_XOR UINT32_C(0x1) + uint8_t metadata_format_type; + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 /* - * In this mode, HW uses inner packets checksum algorithm to - * distribute the packets across the rings and Toeplitz algorithm - * to calculate the hash to convey it in the RX completions. Host - * drivers should provide Toeplitz hash key. As HW uses innermost - * packets checksum to distribute the packets across the rings, - * host drivers can't convey hash mode to choose outer headers to - * calculate Toeplitz hash. FW will fail such configuration. + * The maximum receive unit of the vnic. + * Each vnic is associated with a function. + * The vnic mru value overwrites the mru setting of the + * associated function. + * The HWRM shall make sure that vnic mru does not exceed + * the mru of the port the function is associated with. */ - #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM UINT32_C(0x2) - #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_LAST HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM + uint16_t mru; uint8_t unused_1[4]; -} hwrm_vnic_rss_cfg_input_t, *phwrm_vnic_rss_cfg_input_t; +} hwrm_vnic_update_input_t, *phwrm_vnic_update_input_t; -/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ +/* hwrm_vnic_update_output (size:128b/16B) */ -typedef struct hwrm_vnic_rss_cfg_output { +typedef struct hwrm_vnic_update_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36476,41 +39495,23 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_vnic_rss_cfg_output_t, *phwrm_vnic_rss_cfg_output_t; - -/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ - -typedef struct hwrm_vnic_rss_cfg_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* - * Unable to change global RSS mode to outer due to all active - * interfaces are not ready to support outer RSS hashing. - */ - #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY UINT32_C(0x1) - #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY - uint8_t unused_0[7]; -} hwrm_vnic_rss_cfg_cmd_err_t, *phwrm_vnic_rss_cfg_cmd_err_t; +} hwrm_vnic_update_output_t, *phwrm_vnic_update_output_t; -/********************** - * hwrm_vnic_rss_qcfg * - **********************/ +/****************** + * hwrm_vnic_free * + ******************/ -/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ +/* hwrm_vnic_free_input (size:192b/24B) */ -typedef struct hwrm_vnic_rss_qcfg_input { +typedef struct hwrm_vnic_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -36539,22 +39540,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Index to the rss indirection table. This field is used as a lookup - * for chips before Thor - i.e. Cumulus and Whitney. - */ - uint16_t rss_ctx_idx; - /* - * VNIC ID of VNIC associated with RSS table being queried. This field - * is used as a lookup for Thor and later chips. - */ - uint16_t vnic_id; + /* Logical vnic ID */ + uint32_t vnic_id; uint8_t unused_0[4]; -} hwrm_vnic_rss_qcfg_input_t, *phwrm_vnic_rss_qcfg_input_t; +} hwrm_vnic_free_input_t, *phwrm_vnic_free_input_t; -/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ +/* hwrm_vnic_free_output (size:128b/16B) */ -typedef struct hwrm_vnic_rss_qcfg_output { +typedef struct hwrm_vnic_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36563,178 +39556,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t hash_type; - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv4 - * packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of TCP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of UDP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv6 addresses of IPv6 - * packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of TCP/IPv6 packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of UDP/IPv6 packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) - /* - * When this bit is '1', the RSS hash shall be computed - * over source, destination IPv6 addresses and flow label of IPv6 - * packets. Hash type ipv6 and ipv6_flow_label are mutually - * exclusive. HW does not include the flow_label in hash - * calculation for the packets that are matching tcp_ipv6 and - * udp_ipv6 hash types. This bit will be '0' if - * rss_ipv6_flow_label_cap is '0'. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6_FLOW_LABEL UINT32_C(0x40) - /* - * When this bit is '1', the RSS hash shall be computed over - * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC - * AH/IPv4 packets. This bit will be '0' if rss_ipsec_ah_spi_ipv4_cap - * is '0'. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV4 UINT32_C(0x80) - /* - * When this bit is '1', the RSS hash shall be computed over - * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC - * ESP/IPv4 packets. This bit will be '0' if - * rss_ipsec_esp_spi_ipv4_cap is '0'. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV4 UINT32_C(0x100) - /* - * When this bit is '1', the RSS hash shall be computed over - * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC - * AH/IPv6 packets. This bit will be '0' if - * rss_ipsec_ah_spi_ipv6_cap is '0'. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV6 UINT32_C(0x200) - /* - * When this bit is '1', the RSS hash shall be computed over - * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC - * ESP/IPv6 packets. This bit will be '0' if - * rss_ipsec_esp_spi_ipv6_cap is '0'. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV6 UINT32_C(0x400) - uint8_t unused_0[4]; - /* This is the value of rss hash key */ - uint32_t hash_key[10]; - /* - * Flags to specify different RSS hash modes. Setting rss_ctx_idx to - * the value of 0xffff implies a global RSS configuration query. - * hash_mode_flags are only valid for global RSS configuration query. - * Only the PF can initiate a global RSS configuration query. - * The query request fails if any VNIC is configured with hash mode - * and rss_ctx_idx is 0xffff. - */ - uint8_t hash_mode_flags; - /* - * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable, - * it indicates VNIC's configured RSS hash mode. - * When this bit is '1' and FW is not VNIC_RSS_HASH_MODE capable, - * It indicates using current RSS hash mode setting configured in the - * device. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 4 tuples {l3.src, l3.dest, - * l4.src, l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, - * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10) - uint8_t ring_select_mode; - /* - * In this mode, HW uses Toeplitz algorithm and provided Toeplitz - * hash key to hash the packets according to the configured hash - * type and hash mode. The Toeplitz hash results and the provided - * Toeplitz RSS indirection table are used to determine the RSS - * rings. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ UINT32_C(0x0) - /* - * In this mode, HW uses XOR algorithm to hash the packets according - * to the configured hash type and hash mode. The XOR hash results - * and the provided XOR RSS indirection table are used to determine - * the RSS rings. Host drivers provided hash key is not honored in - * this mode. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_XOR UINT32_C(0x1) - /* - * In this mode, HW uses inner packets checksum algorithm to - * distribute the packets across the rings and Toeplitz algorithm - * to calculate the hash to convey it in the RX completions. Host - * drivers should provide Toeplitz hash key. As HW uses innermost - * packets checksum to distribute the packets across the rings, - * host drivers can't convey hash mode to choose outer headers to - * calculate Toeplitz hash. FW will fail such configuration. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM UINT32_C(0x2) - #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_LAST HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM - uint8_t unused_1[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_rss_qcfg_output_t, *phwrm_vnic_rss_qcfg_output_t; +} hwrm_vnic_free_output_t, *phwrm_vnic_free_output_t; -/************************** - * hwrm_vnic_plcmodes_cfg * - **************************/ +/***************** + * hwrm_vnic_cfg * + *****************/ -/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ +/* hwrm_vnic_cfg_input (size:384b/48B) */ -typedef struct hwrm_vnic_plcmodes_cfg_input { +typedef struct hwrm_vnic_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -36765,131 +39605,243 @@ uint64_t resp_addr; uint32_t flags; /* - * When this bit is '1', the VNIC shall be configured to - * use regular placement algorithm. - * By default, the regular placement algorithm shall be - * enabled on the VNIC. + * When this bit is '1', the VNIC is requested to + * be the default VNIC for the function. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1) + #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT UINT32_C(0x1) /* - * When this bit is '1', the VNIC shall be configured - * use the jumbo placement algorithm. + * When this bit is '1', the VNIC is being configured to + * strip VLAN in the RX path. + * If set to '0', then VLAN stripping is disabled on + * this VNIC. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2) + #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2) /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for IPv4 packets according - * to the following rules: - * # If the packet is identified as TCP/IPv4, then the - * packet is split at the beginning of the TCP payload. - * # If the packet is identified as UDP/IPv4, then the - * packet is split at the beginning of UDP payload. - * # If the packet is identified as non-TCP and non-UDP - * IPv4 packet, then the packet is split at the beginning - * of the upper layer protocol header carried in the IPv4 - * packet. + * When this bit is '1', the VNIC is being configured to + * buffer receive packets in the hardware until the host + * posts new receive buffers. + * If set to '0', then bd_stall is being configured to be + * disabled on this VNIC. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 UINT32_C(0x4) + #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4) /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for IPv6 packets according - * to the following rules: - * # If the packet is identified as TCP/IPv6, then the - * packet is split at the beginning of the TCP payload. - * # If the packet is identified as UDP/IPv6, then the - * packet is split at the beginning of UDP payload. - * # If the packet is identified as non-TCP and non-UDP - * IPv6 packet, then the packet is split at the beginning - * of the upper layer protocol header carried in the IPv6 - * packet. + * When this bit is '1', the VNIC is being configured to + * receive both RoCE and non-RoCE traffic. + * If set to '0', then this VNIC is not configured to be + * operating in dual VNIC mode. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 UINT32_C(0x8) + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8) /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for FCoE packets at the - * beginning of FC payload. + * When this flag is set to '1', the VNIC is requested to + * be configured to receive only RoCE traffic. + * If this flag is set to '0', then this flag shall be + * ignored by the HWRM. + * If roce_dual_vnic_mode flag is set to '1' + * or roce_mirroring_capable_vnic_mode flag to 1, + * then the HWRM client shall not set this flag to '1'. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE UINT32_C(0x10) + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10) /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for RoCE packets at the - * beginning of RoCE payload (after BTH/GRH headers). + * When a VNIC uses one destination ring group for certain + * application (e.g. Receive Flow Steering) where + * exact match is used to direct packets to a VNIC with one + * destination ring group only, there is no need to configure + * RSS indirection table for that VNIC as only one destination + * ring group is used. + * + * This flag is used to enable a mode where + * RSS is enabled in the VNIC using a RSS context + * for computing RSS hash but the RSS indirection table is + * not configured using hwrm_vnic_rss_cfg. + * + * If this mode is enabled, then the driver should not program + * RSS indirection table for the RSS context that is used for + * computing RSS hash only. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE UINT32_C(0x20) + #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20) /* - * When this bit is '1', the VNIC shall be configured use the virtio - * placement algorithm. This feature can only be configured when - * proxy mode is supported on the function. + * When this bit is '1', the VNIC is being configured to + * receive both RoCE and non-RoCE traffic, but forward only the + * RoCE traffic further. Also, RoCE traffic can be mirrored to + * L2 driver. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT UINT32_C(0x40) + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE UINT32_C(0x40) + /* + * When this bit is '1' it enables ring selection using the incoming + * spif and lcos for the packet. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x80) uint32_t enables; /* - * This bit must be '1' for the jumbo_thresh_valid field to be + * This bit must be '1' for the dflt_ring_grp field to be * configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID UINT32_C(0x1) + #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP UINT32_C(0x1) /* - * This bit must be '1' for the hds_offset_valid field to be + * This bit must be '1' for the rss_rule field to be * configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID UINT32_C(0x2) + #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE UINT32_C(0x2) /* - * This bit must be '1' for the hds_threshold_valid field to be + * This bit must be '1' for the cos_rule field to be * configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID UINT32_C(0x4) + #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE UINT32_C(0x4) /* - * This bit must be '1' for the max_bds_valid field to be + * This bit must be '1' for the lb_rule field to be * configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID UINT32_C(0x8) + #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE UINT32_C(0x8) + /* + * This bit must be '1' for the mru field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU UINT32_C(0x10) + /* + * This bit must be '1' for the default_rx_ring_id field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID UINT32_C(0x20) + /* + * This bit must be '1' for the default_cmpl_ring_id field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID UINT32_C(0x40) + /* This bit must be '1' for the queue_id field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID UINT32_C(0x80) + /* + * This bit must be '1' for the rx_csum_v2_mode field to be + * configured. + */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE UINT32_C(0x100) + /* This bit must be '1' for the l2_cqe_mode field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_L2_CQE_MODE UINT32_C(0x200) /* Logical vnic ID */ - uint32_t vnic_id; + uint16_t vnic_id; /* - * When jumbo placement algorithm is enabled, this value - * is used to determine the threshold for jumbo placement. - * Packets with length larger than this value will be - * placed according to the jumbo placement algorithm. + * Default Completion ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules and if + * there is no COS rule. */ - uint16_t jumbo_thresh; + uint16_t dflt_ring_grp; /* - * This value is used to determine the offset into - * packet buffer where the split data (payload) will be - * placed according to one of HDS placement algorithm. + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if + * there is no RSS rule. + */ + uint16_t rss_rule; + /* + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if + * there is no COS rule. + */ + uint16_t cos_rule; + /* + * RSS ID for load balancing rule/table structure. + * 0xFF... (All Fs) if there is no LB rule. + */ + uint16_t lb_rule; + /* + * The maximum receive unit of the vnic. + * Each vnic is associated with a function. + * The vnic mru value overwrites the mru setting of the + * associated function. + * The HWRM shall make sure that vnic mru does not exceed + * the mru of the port the function is associated with. + */ + uint16_t mru; + /* + * Default Rx ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules. + * The aggregation ring associated with the Rx ring is + * implied based on the Rx ring specified when the + * aggregation ring was allocated. + */ + uint16_t default_rx_ring_id; + /* + * Default completion ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules. + */ + uint16_t default_cmpl_ring_id; + /* + * When specified, only incoming packets classified to the specified + * CoS queue ID will be arriving on this VNIC. Packet priority to CoS + * mapping rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this + * mode, ntuple filters with VNIC destination specified are invalid + * since they conflict with the CoS to VNIC steering rules in this + * mode. * - * The lengths of packet buffers provided for split data - * shall be larger than this value. + * If this field is not specified, packet to VNIC steering will be + * subject to the standard L2 filter rules and any additional ntuple + * filter rules with destination VNIC specified. */ - uint16_t hds_offset; + uint16_t queue_id; /* - * When one of the HDS placement algorithm is enabled, this - * value is used to determine the threshold for HDS - * placement. - * Packets with length larger than this value will be - * placed according to the HDS placement algorithm. - * This value shall be in multiple of 4 bytes. + * If the device supports the RX V2 and RX TPA start V2 completion + * records as indicated by the HWRM_VNIC_QCAPS command, this field is + * used to specify the two RX checksum modes supported by these + * completion records. */ - uint16_t hds_threshold; + uint8_t rx_csum_v2_mode; /* - * When virtio placement algorithm is enabled, this - * value is used to determine the maximum number of BDs - * that can be used to place an Rx Packet. - * If an incoming packet does not fit in the buffers described - * by the max BDs, the packet will be dropped and an error - * will be reported in the completion. Valid values for this - * field are between 1 and 8. If the VNIC uses header-data- - * separation and/or TPA with buffer spanning enabled, valid - * values for this field are between 2 and 8. - * This feature can only be configured when proxy mode is - * supported on the function. + * When configured with this checksum mode, the number of header + * groups in the delivered packet with a valid IP checksum and + * the number of header groups in the delivered packet with a valid + * L4 checksum are reported. Valid checksums are counted from the + * outermost header group to the innermost header group, stopping at + * the first error. This is the default checksum mode supported if + * the driver doesn't explicitly configure the RX checksum mode. */ - uint16_t max_bds; - uint8_t unused_0[4]; -} hwrm_vnic_plcmodes_cfg_input_t, *phwrm_vnic_plcmodes_cfg_input_t; + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) + /* + * When configured with this checksum mode, the checksum status is + * reported using 'all ok' mode. In the RX completion record, one + * bit indicates if the IP checksum is valid for all the parsed + * header groups with an IP checksum. Another bit indicates if the + * L4 checksum is valid for all the parsed header groups with an L4 + * checksum. The number of header groups that were parsed by the + * chip and passed in the delivered packet is also reported. + */ + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1) + /* + * Any rx_csum_v2_mode value larger than or equal to this is not + * valid + */ + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX + /* + * If the device supports different L2 RX CQE modes, as indicated by + * the HWRM_VNIC_QCAPS command, this field is used to configure the + * CQE mode. + */ + uint8_t l2_cqe_mode; + /* + * When configured with this cqe mode, A normal (32B) CQE + * will be generated. This is the default mode. + */ + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0) + /* + * When configured with this cqe mode, A compressed (16B) CQE + * will be generated. In this mode TPA and HDS are not supported. + * Host drivers should not configure the TPA and HDS along with + * compressed mode, per VNIC. FW returns error, if host drivers + * try to configure the VNIC with compressed mode and (TPA or HDS). + * The compressed completion does not include PTP data. Host + * drivers should not use this mode to receive the PTP data. + */ + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1) + /* + * When configured with this cqe mode, HW generates either a 32B + * completion or a 16B completion depending on use case within a + * VNIC. For ex. a simple L2 packet could use the compressed form + * while a PTP packet on the same VNIC would use the 32B form. + */ + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED UINT32_C(0x2) + #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_LAST HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED + uint8_t unused0[4]; +} hwrm_vnic_cfg_input_t, *phwrm_vnic_cfg_input_t; -/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ +/* hwrm_vnic_cfg_output (size:128b/16B) */ -typedef struct hwrm_vnic_plcmodes_cfg_output { +typedef struct hwrm_vnic_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36901,23 +39853,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_plcmodes_cfg_output_t, *phwrm_vnic_plcmodes_cfg_output_t; +} hwrm_vnic_cfg_output_t, *phwrm_vnic_cfg_output_t; -/*************************** - * hwrm_vnic_plcmodes_qcfg * - ***************************/ +/****************** + * hwrm_vnic_qcfg * + ******************/ -/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */ +/* hwrm_vnic_qcfg_input (size:256b/32B) */ -typedef struct hwrm_vnic_plcmodes_qcfg_input { +typedef struct hwrm_vnic_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -36946,14 +39897,22 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vf_id_valid field to be + * configured. + */ + #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) /* Logical vnic ID */ uint32_t vnic_id; - uint8_t unused_0[4]; -} hwrm_vnic_plcmodes_qcfg_input_t, *phwrm_vnic_plcmodes_qcfg_input_t; + /* ID of Virtual Function whose VNIC resource is being queried. */ + uint16_t vf_id; + uint8_t unused_0[6]; +} hwrm_vnic_qcfg_input_t, *phwrm_vnic_qcfg_input_t; -/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */ +/* hwrm_vnic_qcfg_output (size:256b/32B) */ -typedef struct hwrm_vnic_plcmodes_qcfg_output { +typedef struct hwrm_vnic_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -36962,107 +39921,187 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Default Completion ring for the VNIC. */ + uint16_t dflt_ring_grp; + /* + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if + * there is no RSS rule. + */ + uint16_t rss_rule; + /* + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if + * there is no COS rule. + */ + uint16_t cos_rule; + /* + * RSS ID for load balancing rule/table structure. + * 0xFF... (All Fs) if there is no LB rule. + */ + uint16_t lb_rule; + /* The maximum receive unit of the vnic. */ + uint16_t mru; + uint8_t unused_0[2]; uint32_t flags; + /* + * When this bit is '1', the VNIC is the default VNIC for + * the function. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT UINT32_C(0x1) /* * When this bit is '1', the VNIC is configured to - * use regular placement algorithm. + * strip VLAN in the RX path. + * If set to '0', then VLAN stripping is disabled on + * this VNIC. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1) + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2) /* * When this bit is '1', the VNIC is configured to - * use the jumbo placement algorithm. + * buffer receive packets in the hardware until the host + * posts new receive buffers. + * If set to '0', then bd_stall is disabled on + * this VNIC. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4) /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for IPv4 packets. + * When this bit is '1', the VNIC is configured to + * receive both RoCE and non-RoCE traffic. + * If set to '0', then this VNIC is not configured to + * operate in dual VNIC mode. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 UINT32_C(0x4) + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8) /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for IPv6 packets. + * When this flag is set to '1', the VNIC is configured to + * receive only RoCE traffic. + * When this flag is set to '0', the VNIC is not configured + * to receive only RoCE traffic. + * If roce_dual_vnic_mode flag and this flag both are set + * to '1', then it is an invalid configuration of the + * VNIC. The HWRM should not allow that type of + * mis-configuration by HWRM clients. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 UINT32_C(0x8) + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10) /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for FCoE packets. + * When a VNIC uses one destination ring group for certain + * application (e.g. Receive Flow Steering) where + * exact match is used to direct packets to a VNIC with one + * destination ring group only, there is no need to configure + * RSS indirection table for that VNIC as only one destination + * ring group is used. + * + * When this bit is set to '1', then the VNIC is enabled in a + * mode where RSS is enabled in the VNIC using a RSS context + * for computing RSS hash but the RSS indirection table is + * not configured. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE UINT32_C(0x10) + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20) /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for RoCE packets. + * When this bit is '1', the VNIC is configured to + * receive both RoCE and non-RoCE traffic, but forward only + * RoCE traffic further. Also RoCE traffic can be mirrored to + * L2 driver. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE UINT32_C(0x20) + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE UINT32_C(0x40) /* - * When this bit is '1', the VNIC is configured - * to be the default VNIC of the requesting function. + * When this bit is '0', VNIC is in normal operation state. + * When this bit is '1', VNIC drops all the received packets. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC UINT32_C(0x40) + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE UINT32_C(0x80) + /* When this bit is '1' it indicates port cos_mapping_mode enabled. */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x100) /* - * When this bit is '1', the VNIC is configured to use the virtio - * placement algorithm. This feature can only be configured when - * proxy mode is supported on the function. + * When returned with a valid CoS Queue id, the CoS Queue/VNIC + * association is valid. Otherwise it will return 0xFFFF to indicate no + * VNIC/CoS queue association. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT UINT32_C(0x80) + uint16_t queue_id; /* - * When jumbo placement algorithm is enabled, this value - * is used to determine the threshold for jumbo placement. - * Packets with length larger than this value will be - * placed according to the jumbo placement algorithm. + * If the device supports the RX V2 and RX TPA start V2 completion + * records as indicated by the HWRM_VNIC_QCAPS command, this field is + * used to specify the current RX checksum mode configured for all the + * RX rings of a VNIC. */ - uint16_t jumbo_thresh; + uint8_t rx_csum_v2_mode; /* - * This value is used to determine the offset into - * packet buffer where the split data (payload) will be - * placed according to one of HDS placement algorithm. - * - * The lengths of packet buffers provided for split data - * shall be larger than this value. + * This value indicates that the VNIC is configured to use the + * default RX checksum mode for all the rings associated with this + * VNIC. */ - uint16_t hds_offset; + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) /* - * When one of the HDS placement algorithm is enabled, this - * value is used to determine the threshold for HDS - * placement. - * Packets with length larger than this value will be - * placed according to the HDS placement algorithm. - * This value shall be in multiple of 4 bytes. + * This value indicates that the VNIC is configured to use the RX + * checksum 'all_ok' mode for all the rings associated with this + * VNIC. */ - uint16_t hds_threshold; + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1) /* - * When virtio placement algorithm is enabled, this - * value is used to determine the maximum number of BDs - * that can be used to place an Rx Packet. - * If an incoming packet does not fit in the buffers described - * by the max BDs, the packet will be dropped and an error - * will be reported in the completion. Valid values for this - * field are between 1 and 8. If the VNIC uses header-data- - * separation and/or TPA with buffer spanning enabled, valid - * values for this field are between 2 and 8. - * This feature can only be configured when proxy mode is supported - * on the function + * Any rx_csum_v2_mode value larger than or equal to this is not + * valid */ - uint16_t max_bds; - uint8_t unused_0[3]; + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX + /* + * If the device supports different L2 RX CQE modes, as indicated by + * the HWRM_VNIC_QCAPS command, this field is used to convey the + * configured CQE mode. + */ + uint8_t l2_cqe_mode; + /* + * This value indicates that the VNIC is configured with normal + * (32B) CQE mode. + */ + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0) + /* + * This value indicates that the VNIC is configured with compressed + * (16B) CQE mode. + */ + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1) + /* + * This value indicates that the VNIC is configured with mixed + * CQE mode. HW generates either a 32B completion or a 16B + * completion depending on use case within a VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_LAST HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED + /* + * This field conveys the metadata format type that has been + * configured. This value is product specific. Refer to the L2 HSI + * completion ring structures for the detailed descriptions. For Thor + * and Thor2, it corresponds to 'meta_format' in 'rx_pkt_cmpl_hi' and + * 'rx_pkt_v3_cmpl_hi', respectively. + */ + uint8_t metadata_format_type; + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_LAST HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 + /* This field conveys the VNIC operation state. */ + uint8_t vnic_state; + /* Normal operation state. */ + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_NORMAL UINT32_C(0x0) + /* Drop all packets. */ + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP UINT32_C(0x1) + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_LAST HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP + uint8_t unused_1; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_plcmodes_qcfg_output_t, *phwrm_vnic_plcmodes_qcfg_output_t; +} hwrm_vnic_qcfg_output_t, *phwrm_vnic_qcfg_output_t; -/********************************** - * hwrm_vnic_rss_cos_lb_ctx_alloc * - **********************************/ +/******************* + * hwrm_vnic_qcaps * + *******************/ -/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ +/* hwrm_vnic_qcaps_input (size:192b/24B) */ -typedef struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { +typedef struct hwrm_vnic_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -37091,11 +40130,13 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_vnic_rss_cos_lb_ctx_alloc_input_t, *phwrm_vnic_rss_cos_lb_ctx_alloc_input_t; + uint32_t enables; + uint8_t unused_0[4]; +} hwrm_vnic_qcaps_input_t, *phwrm_vnic_qcaps_input_t; -/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ +/* hwrm_vnic_qcaps_output (size:192b/24B) */ -typedef struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { +typedef struct hwrm_vnic_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -37104,27 +40145,233 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* rss_cos_lb_ctx_id is 16 b */ - uint16_t rss_cos_lb_ctx_id; - uint8_t unused_0[5]; + /* The maximum receive unit that is settable on a vnic. */ + uint16_t mru; + uint8_t unused_0[2]; + uint32_t flags; + /* Unused. */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED UINT32_C(0x1) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ + * When this bit is '1', the capability of stripping VLAN in + * the RX path is supported on VNIC(s). + * If set to '0', then VLAN stripping capability is + * not supported on VNIC(s). + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP UINT32_C(0x2) + /* + * When this bit is '1', the capability to buffer receive + * packets in the hardware until the host posts new receive buffers + * is supported on VNIC(s). + * If set to '0', then bd_stall capability is not supported + * on VNIC(s). + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP UINT32_C(0x4) + /* + * When this bit is '1', the capability to + * receive both RoCE and non-RoCE traffic on VNIC(s) is + * supported. + * If set to '0', then the capability to receive + * both RoCE and non-RoCE traffic on VNIC(s) is + * not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP UINT32_C(0x8) + /* + * When this bit is set to '1', the capability to configure + * a VNIC to receive only RoCE traffic is supported. + * When this flag is set to '0', the VNIC capability to + * configure to receive only RoCE traffic is not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP UINT32_C(0x10) + /* + * When this bit is set to '1', then the capability to enable + * a VNIC in a mode where RSS context without configuring + * RSS indirection table is supported (for RSS hash computation). + * When this bit is set to '0', then a VNIC can not be configured + * with a mode to enable RSS context without configuring RSS + * indirection table. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP UINT32_C(0x20) + /* + * When this bit is '1', the capability to + * mirror the RoCE traffic is supported. + * If set to '0', then the capability to mirror the + * RoCE traffic is not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP UINT32_C(0x40) + /* + * When this bit is '1', the outermost RSS hashing capability + * is supported. If set to '0', then the outermost RSS hashing + * capability is not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP UINT32_C(0x80) + /* + * When this bit is '1', it indicates that firmware supports the + * ability to steer incoming packets from one CoS queue to one + * VNIC. This optional feature can then be enabled + * using HWRM_VNIC_CFG on any VNIC. This feature is only + * available when NVM option 'enable_cos_classification' is set + * to 1. If set to '0', firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP UINT32_C(0x100) + /* + * When this bit is '1', it indicates that HW and firmware supports + * the use of RX V2 and RX TPA start V2 completion records for all + * the RX rings of a VNIC. Once set, this feature is mandatory to + * be used for the RX rings of the VNIC. Additionally, two new RX + * checksum features supported by these completion records can be + * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the + * HW and the firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP UINT32_C(0x200) + /* + * When this bit is '1', it indicates that HW and firmware support + * vnic state change. Host drivers can change the vnic state using + * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not + * support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP UINT32_C(0x400) + /* + * When this bit is '1', it indicates that firmware supports + * virtio-net functions default VNIC allocation using + * HWRM_VNIC_ALLOC. + * This capability is available only on Proxy VEE PF. If set to '0', + * firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP UINT32_C(0x800) + /* + * When this bit is set '1', then the capability to configure the + * metadata format in the RX completion is supported for the VNIC. + * When this bit is set to '0', then the capability to configure + * the metadata format in the RX completion is not supported for + * the VNIC. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP UINT32_C(0x1000) + /* + * When this bit is set '1', it indicates that firmware returns + * INVALID_PARAM error, if host drivers choose invalid hash type + * bit combinations in vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP UINT32_C(0x2000) + /* + * When this bit is set '1', it indicates that firmware supports + * the hash_type include and exclude flags in hwrm_vnic_rss_cfg. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that HW is capable of using + * Toeplitz algorithm. This mode uses Toeplitz algorithm and + * provided Toeplitz hash key to hash the packets according to the + * configured hash type and hash mode. The Toeplitz hash results and + * the provided Toeplitz RSS indirection table are used to determine + * the RSS rings. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP UINT32_C(0x8000) + /* + * When this bit is '1', it indicates that HW is capable of using + * XOR algorithm. This mode uses 'XOR' algorithm to hash the packets + * according to the configured hash type and hash mode. The XOR + * hash results and the provided XOR RSS indirection table are + * used to determine the RSS rings. Host drivers provided hash key + * is not honored in this mode. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_XOR_CAP UINT32_C(0x10000) + /* + * When this bit is '1', it indicates that HW is capable of using + * checksum algorithm. In this mode, HW uses inner packets checksum + * algorithm to distribute the packets across the rings and Toeplitz + * algorithm to calculate the hash to convey it in the RX + * completions. Host drivers should provide Toeplitz hash key. + * As HW uses innermost packets checksum to distribute the packets + * across the rings, host drivers can't convey hash mode to choose + * outer headers to calculate Toeplitz hash. FW will fail such + * configuration. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP UINT32_C(0x20000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPV6 flow labels. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP UINT32_C(0x40000) + /* + * When this bit is '1', it indicates that HW and firmware supports + * the use of RX V3 and RX TPA start V3 completion records for all + * the RX rings of a VNIC. Once set, this feature is mandatory to + * be used for the RX rings of the VNIC. If set to '0', the + * HW and the firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V3_CAP UINT32_C(0x80000) + /* + * When this bit is '1' HW supports different RX CQE record types. + * Host drivers can choose the mode based on their application + * requirements like performance, TPA, HDS and PTP. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP UINT32_C(0x100000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv4 IPSEC AH SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP UINT32_C(0x200000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv4 IPSEC ESP SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP UINT32_C(0x400000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv6 IPSEC AH SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP UINT32_C(0x800000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv6 IPSEC ESP SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP UINT32_C(0x1000000) + /* + * When outermost_rss_cap is '1' and this bit is '1', the outermost + * RSS hash mode may be set on a PF or trusted VF. + * When outermost_rss_cap is '1' and this bit is '0', the outermost + * RSS hash mode may be set on a PF. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP UINT32_C(0x2000000) + /* + * When this bit is '1' it indicates HW is capable of enabling ring + * selection using the incoming spif and lcos for the packet. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x4000000) + /* + * When this bit is '1', it indicates controller enabled + * RSS profile TCAM mode. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_PROF_TCAM_MODE_ENABLED UINT32_C(0x8000000) + /* When this bit is '1' FW supports VNIC hash mode. */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP UINT32_C(0x10000000) + /* When this bit is set to '1', hardware supports tunnel TPA. */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_HW_TUNNEL_TPA_CAP UINT32_C(0x20000000) + /* + * This field advertises the maximum concurrent TPA aggregations + * supported by the VNIC on new devices that support TPA v2 or v3. + * '0' means that both the TPA v2 and v3 are not supported. + */ + uint16_t max_aggs_supported; + uint8_t unused_1[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ uint8_t valid; -} hwrm_vnic_rss_cos_lb_ctx_alloc_output_t, *phwrm_vnic_rss_cos_lb_ctx_alloc_output_t; +} hwrm_vnic_qcaps_output_t, *phwrm_vnic_qcaps_output_t; -/********************************* - * hwrm_vnic_rss_cos_lb_ctx_free * - *********************************/ +/********************* + * hwrm_vnic_tpa_cfg * + *********************/ -/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ +/* hwrm_vnic_tpa_cfg_input (size:384b/48B) */ -typedef struct hwrm_vnic_rss_cos_lb_ctx_free_input { +typedef struct hwrm_vnic_tpa_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -37153,14 +40400,247 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* rss_cos_lb_ctx_id is 16 b */ - uint16_t rss_cos_lb_ctx_id; - uint8_t unused_0[6]; -} hwrm_vnic_rss_cos_lb_ctx_free_input_t, *phwrm_vnic_rss_cos_lb_ctx_free_input_t; + uint32_t flags; + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) of + * non-tunneled TCP packets. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA UINT32_C(0x1) + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) of + * tunneled TCP packets. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA UINT32_C(0x2) + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) according + * to Windows Receive Segment Coalescing (RSC) rules. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4) + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) according + * to Linux Generic Receive Offload (GRO) rules. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO UINT32_C(0x8) + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for TCP + * packets with IP ECN set to non-zero. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10) + /* + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * GRE tunneled TCP packets only if all packets have the + * same GRE sequence. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20) + /* + * When this bit is '1' and the GRO mode is enabled, + * the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * TCP/IPv4 packets with consecutively increasing IPIDs. + * In other words, the last packet that is being + * aggregated to an already existing aggregation context + * shall have IPID 1 more than the IPID of the last packet + * that was aggregated in that aggregation context. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40) + /* + * When this bit is '1' and the GRO mode is enabled, + * the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) + * value. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80) + /* + * When this bit is '1' and the GRO mode is enabled, + * the VNIC shall DMA payload data using GRO rules. + * When this bit is '0', the VNIC shall DMA payload data + * using the more efficient LRO rules of filling all + * aggregation buffers. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO UINT32_C(0x100) + uint32_t enables; + /* + * This bit must be '1' for the max_agg_segs field to be + * configured. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1) + /* + * This bit must be '1' for the max_aggs field to be + * configured. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2) + /* + * This bit must be '1' for the max_agg_timer field to be + * configured. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4) + /* deprecated bit. Do not use!!! */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8) + /* + * This bit must be '1' for the tnl_tpa_en_bitmap field to be + * configured. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_TNL_TPA_EN UINT32_C(0x10) + /* Logical vnic ID */ + uint16_t vnic_id; + /* + * This is the maximum number of TCP segments that can + * be aggregated (unit is Log2). Max value is 31. On new + * devices supporting TPA v2, the unit is multiples of 4 and + * valid values are > 0 and <= 63. + */ + uint16_t max_agg_segs; + /* 1 segment */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) + /* 2 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) + /* 4 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) + /* 8 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) + /* Any segment size larger than this is not valid */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX + /* + * This is the maximum number of aggregations this VNIC is + * allowed (unit is Log2). Max value is 7. On new devices + * supporting TPA v2, this is in unit of 1 and must be > 0 + * and <= max_aggs_supported in the hwrm_vnic_qcaps response + * to enable TPA v2. + */ + uint16_t max_aggs; + /* 1 aggregation */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0) + /* 2 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1) + /* 4 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2) + /* 8 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3) + /* 16 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4) + /* Any aggregation size larger than this is not valid */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7) + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX + uint8_t unused_0[2]; + /* + * This is the maximum amount of time allowed for + * an aggregation context to complete after it was initiated. + */ + uint32_t max_agg_timer; + /* + * This is the minimum amount of payload length required to + * start an aggregation context. This field is deprecated and + * should be set to 0. The minimum length is set by firmware + * and can be queried using hwrm_vnic_tpa_qcfg. + */ + uint32_t min_agg_len; + /* + * If the device supports hardware tunnel TPA feature, as indicated by + * the HWRM_VNIC_QCAPS command, this field is used to configure the + * tunnel types to be enabled. Each bit corresponds to a specific + * tunnel type. If a bit is set to '1', then the associated tunnel + * type is enabled; otherwise, it is disabled. + */ + uint32_t tnl_tpa_en_bitmap; + /* + * When this bit is '1', enable VXLAN encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN UINT32_C(0x1) + /* + * When this bit is set to '1', enable GENEVE encapsulated packets + * for aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GENEVE UINT32_C(0x2) + /* + * When this bit is set to '1', enable NVGRE encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_NVGRE UINT32_C(0x4) + /* + * When this bit is set to '1', enable GRE encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE UINT32_C(0x8) + /* + * When this bit is set to '1', enable IPV4 encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV4 UINT32_C(0x10) + /* + * When this bit is set to '1', enable IPV6 encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV6 UINT32_C(0x20) + /* + * When this bit is '1', enable VXLAN_GPE encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE UINT32_C(0x40) + /* + * When this bit is '1', enable VXLAN_CUSTOMER1 encapsulated packets + * for aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1 UINT32_C(0x80) + /* + * When this bit is '1', enable GRE_CUSTOMER1 encapsulated packets + * for aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE_CUST1 UINT32_C(0x100) + /* + * When this bit is '1', enable UPAR1 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR1 UINT32_C(0x200) + /* + * When this bit is '1', enable UPAR2 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR2 UINT32_C(0x400) + /* + * When this bit is '1', enable UPAR3 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR3 UINT32_C(0x800) + /* + * When this bit is '1', enable UPAR4 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR4 UINT32_C(0x1000) + /* + * When this bit is '1', enable UPAR5 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR5 UINT32_C(0x2000) + /* + * When this bit is '1', enable UPAR6 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR6 UINT32_C(0x4000) + /* + * When this bit is '1', enable UPAR7 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR7 UINT32_C(0x8000) + /* + * When this bit is '1', enable UPAR8 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR8 UINT32_C(0x10000) + uint8_t unused_1[4]; +} hwrm_vnic_tpa_cfg_input_t, *phwrm_vnic_tpa_cfg_input_t; -/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ +/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ -typedef struct hwrm_vnic_rss_cos_lb_ctx_free_output { +typedef struct hwrm_vnic_tpa_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -37172,22 +40652,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_vnic_rss_cos_lb_ctx_free_output_t, *phwrm_vnic_rss_cos_lb_ctx_free_output_t; +} hwrm_vnic_tpa_cfg_output_t, *phwrm_vnic_tpa_cfg_output_t; -/******************* - * hwrm_ring_alloc * - *******************/ +/********************** + * hwrm_vnic_tpa_qcfg * + **********************/ -/* hwrm_ring_alloc_input (size:704b/88B) */ +/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ -typedef struct hwrm_ring_alloc_input { +typedef struct hwrm_vnic_tpa_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -37216,412 +40696,235 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; + /* Logical vnic ID */ + uint16_t vnic_id; + uint8_t unused_0[6]; +} hwrm_vnic_tpa_qcfg_input_t, *phwrm_vnic_tpa_qcfg_input_t; + +/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ + +typedef struct hwrm_vnic_tpa_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; /* - * This bit must be '1' for the ring_arb_cfg field to be - * configured. + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) of + * non-tunneled TCP packets. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG UINT32_C(0x2) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA UINT32_C(0x1) /* - * This bit must be '1' for the stat_ctx_id_valid field to be - * configured. + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) of + * tunneled TCP packets. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID UINT32_C(0x8) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA UINT32_C(0x2) /* - * This bit must be '1' for the max_bw_valid field to be - * configured. + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) according + * to Windows Receive Segment Coalescing (RSC) rules. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID UINT32_C(0x20) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4) /* - * This bit must be '1' for the rx_ring_id field to be - * configured. + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) according + * to Linux Generic Receive Offload (GRO) rules. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID UINT32_C(0x40) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO UINT32_C(0x8) /* - * This bit must be '1' for the nq_ring_id field to be - * configured. + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) for TCP + * packets with IP ECN set to non-zero. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID UINT32_C(0x80) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10) /* - * This bit must be '1' for the rx_buf_size field to be - * configured. + * When this bit is '1', the VNIC is configured to + * perform transparent packet aggregation (TPA) for + * GRE tunneled TCP packets only if all packets have the + * same GRE sequence. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID UINT32_C(0x100) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20) /* - * This bit must be '1' for the schq_id field to be - * configured. + * When this bit is '1' and the GRO mode is enabled, + * the VNIC is configured to + * perform transparent packet aggregation (TPA) for + * TCP/IPv4 packets with consecutively increasing IPIDs. + * In other words, the last packet that is being + * aggregated to an already existing aggregation context + * shall have IPID 1 more than the IPID of the last packet + * that was aggregated in that aggregation context. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID UINT32_C(0x200) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40) /* - * This bit must be '1' for the mpc_chnls_type field to be - * configured. + * When this bit is '1' and the GRO mode is enabled, + * the VNIC is configured to + * perform transparent packet aggregation (TPA) for + * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) + * value. */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE UINT32_C(0x400) - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - /* RX Aggregation Ring */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) - /* Notification Queue */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80) /* - * This field controls the number of packets transmitted before a TX - * completion is generated. Non-zero values for the field are only - * valid if HWRM_FUNC_QCAPS indicates that the TX coalesced completion - * records capability is supported. - */ - uint8_t cmpl_coal_cnt; - /* Generates a legacy TX completion on every packet. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0) - /* Generates a TX coalesced completion for up to 4 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4 UINT32_C(0x1) - /* Generates a TX coalesced completion for up to 8 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8 UINT32_C(0x2) - /* Generates a TX coalesced completion for up to 12 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12 UINT32_C(0x3) - /* Generates a TX coalesced completion for up to 16 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16 UINT32_C(0x4) - /* Generates a TX coalesced completion for up to 24 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24 UINT32_C(0x5) - /* Generates a TX coalesced completion for up to 32 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32 UINT32_C(0x6) - /* Generates a TX coalesced completion for up to 48 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48 UINT32_C(0x7) - /* Generates a TX coalesced completion for up to 64 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64 UINT32_C(0x8) - /* Generates a TX coalesced completion for up to 96 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96 UINT32_C(0x9) - /* Generates a TX coalesced completion for up to 128 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa) - /* Generates a TX coalesced completion for up to 192 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb) - /* Generates a TX coalesced completion for up to 256 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc) - /* Generates a TX coalesced completion for up to 320 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd) - /* Generates a TX coalesced completion for up to 384 TX packets. */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe) - /* Generates a TX coalesced completion up to the last packet. (Maximum coalescing). */ - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf) - #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_LAST HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX - /* Ring allocation flags. */ - uint16_t flags; - /* - * For Rx rings, the incoming packet data can be placed at either - * a 0B or 2B offset from the start of the Rx packet buffer. When - * '1', the received packet will be padded with 2B of zeros at the - * front of the packet. Note that this flag is only used for - * Rx rings and is ignored for all other rings included Rx - * Aggregation rings. - */ - #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1) - /* - * When the HW Doorbell Drop Recovery feature is enabled, - * HW can flag false CQ overflow when CQ consumer index - * doorbells are dropped when there really wasn't any overflow. - * The CQE values could have already been processed by the driver, - * but HW doesn't know about this because of the doorbell drop. - * To avoid false detection of CQ overflow events, - * it is recommended that CQ overflow detection is disabled - * by the driver when HW based doorbell recovery is enabled. - */ - #define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x2) - /* - * Used with enhanced Doorbell Pacing feature, when set to '1' - * this flag indicates that the NQ id that's allocated should be - * used for DBR pacing notifications. - */ - #define HWRM_RING_ALLOC_INPUT_FLAGS_NQ_DBR_PACING UINT32_C(0x4) - /* - * Host driver should set this flag bit to '1' to enable - * two-completion TX packet timestamp feature. By enabling this - * per QP flag and enabling stamp bit in TX BD lflags, host drivers - * expect two completions, one for regular TX completion and the - * other completion with timestamp. For a QP with both completion - * coalescing and timestamp completion features enabled, completion - * coalescing takes place on regular TX completions. The timestamp - * completions are not coalesced and a separate timestamp completion - * is generated for each packet with stamp bit set in the TX BD - * lflags. - */ - #define HWRM_RING_ALLOC_INPUT_FLAGS_TX_PKT_TS_CMPL_ENABLE UINT32_C(0x8) - /* - * This value is a pointer to the page table for the - * Ring. - */ - uint64_t page_tbl_addr; - /* First Byte Offset of the first entry in the first page. */ - uint32_t fbo; - /* - * Actual page size in 2^page_size. The supported range is increments - * in powers of 2 from 16 bytes to 1GB. - * - 4 = 16 B - * Page size is 16 B. - * - 12 = 4 KB - * Page size is 4 KB. - * - 13 = 8 KB - * Page size is 8 KB. - * - 16 = 64 KB - * Page size is 64 KB. - * - 21 = 2 MB - * Page size is 2 MB. - * - 22 = 4 MB - * Page size is 4 MB. - * - 30 = 1 GB - * Page size is 1 GB. - */ - uint8_t page_size; - /* - * This value indicates the depth of page table. - * For this version of the specification, value other than 0 or - * 1 shall be considered as an invalid value. - * When the page_tbl_depth = 0, then it is treated as a - * special case with the following. - * 1. FBO and page size fields are not valid. - * 2. page_tbl_addr is the physical address of the first - * element of the ring. - */ - uint8_t page_tbl_depth; - /* Used by a PF driver to associate a SCHQ with one of its TX rings. */ - uint16_t schq_id; - /* - * Number of 16B units in the ring. Minimum size for - * a ring is 16 16B entries. - */ - uint32_t length; - /* - * Logical ring number for the ring to be allocated. - * This value determines the position in the doorbell - * area where the update to the ring will be made. - * - * For completion rings, this value is also the MSI-X - * vector number for the function the completion ring is - * associated with. - */ - uint16_t logical_id; - /* - * This field is used only when ring_type is a TX ring. - * This value indicates what completion ring the TX ring - * is associated with. + * This is the maximum number of TCP segments that can + * be aggregated (unit is Log2). Max value is 31. */ - uint16_t cmpl_ring_id; + uint16_t max_agg_segs; + /* 1 segment */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) + /* 2 segments */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) + /* 4 segments */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) + /* 8 segments */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) + /* Any segment size larger than this is not valid */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_LAST HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX /* - * This field is used only when ring_type is a TX ring. - * This value indicates what CoS queue the TX ring - * is associated with. + * This is the maximum number of aggregations this VNIC is + * allowed (unit is Log2). Max value is 7 */ - uint16_t queue_id; + uint16_t max_aggs; + /* 1 aggregation */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0) + /* 2 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1) + /* 4 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2) + /* 8 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3) + /* 16 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4) + /* Any aggregation size larger than this is not valid */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_LAST HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX /* - * When allocating a Rx ring or Rx aggregation ring, this field - * specifies the size of the buffer descriptors posted to the ring. + * This is the maximum amount of time allowed for + * an aggregation context to complete after it was initiated. */ - uint16_t rx_buf_size; + uint32_t max_agg_timer; /* - * When allocating an Rx aggregation ring, this field - * specifies the associated Rx ring ID. + * This is the minimum amount of payload length required to + * start an aggregation context. */ - uint16_t rx_ring_id; + uint32_t min_agg_len; /* - * When allocating a completion ring, this field - * specifies the associated NQ ring ID. + * If the device supports hardware tunnel TPA feature, as indicated by + * the HWRM_VNIC_QCAPS command, this field conveys the bitmap of the + * tunnel types that have been configured. Each bit corresponds to a + * specific tunnel type. If a bit is set to '1', then the associated + * tunnel type is enabled; otherwise, it is disabled. */ - uint16_t nq_ring_id; + uint32_t tnl_tpa_en_bitmap; /* - * This field is used only when ring_type is a TX ring. - * This field is used to configure arbitration related - * parameters for a TX ring. + * When this bit is '1', enable VXLAN encapsulated packets for + * aggregation. */ - uint16_t ring_arb_cfg; - /* Arbitration policy used for the ring. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK UINT32_C(0xf) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0 + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN UINT32_C(0x1) /* - * Use strict priority for the TX ring. - * Priority value is specified in arb_policy_param + * When this bit is set to '1', enable GENEVE encapsulated packets + * for aggregation. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP UINT32_C(0x1) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GENEVE UINT32_C(0x2) /* - * Use weighted fair queue arbitration for the TX ring. - * Weight is specified in arb_policy_param + * When this bit is set to '1', enable NVGRE encapsulated packets + * for aggregation.. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ UINT32_C(0x2) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ - /* Reserved field. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK UINT32_C(0xf0) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4 + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_NVGRE UINT32_C(0x4) /* - * Arbitration policy specific parameter. - * # For strict priority arbitration policy, this field - * represents a priority value. If set to 0, then the priority - * is not specified and the HWRM is allowed to select - * any priority for this TX ring. - * # For weighted fair queue arbitration policy, this field - * represents a weight value. If set to 0, then the weight - * is not specified and the HWRM is allowed to select - * any weight for this TX ring. + * When this bit is set to '1', enable GRE encapsulated packets + * for aggregation.. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK UINT32_C(0xff00) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 - uint16_t unused_3; + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE UINT32_C(0x8) /* - * This field is reserved for the future use. - * It shall be set to 0. + * When this bit is set to '1', enable IPV4 encapsulated packets + * for aggregation.. */ - uint32_t reserved3; + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV4 UINT32_C(0x10) /* - * This field is used only when ring_type is a TX ring. - * This input indicates what statistics context this ring - * should be associated with. + * When this bit is set to '1', enable IPV6 encapsulated packets + * for aggregation.. */ - uint32_t stat_ctx_id; + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV6 UINT32_C(0x20) /* - * This field is reserved for the future use. - * It shall be set to 0. + * When this bit is '1', enable VXLAN_GPE encapsulated packets for + * aggregation. */ - uint32_t reserved4; + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE UINT32_C(0x40) /* - * This field is used only when ring_type is a TX ring - * to specify maximum BW allocated to the TX ring. - * The HWRM will translate this value into byte counter and - * time interval used for this ring inside the device. + * When this bit is '1', enable VXLAN_CUSTOMER1 encapsulated packets + * for aggregation. */ - uint32_t max_bw; - /* The bandwidth value. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1 UINT32_C(0x80) /* - * This field is used only when ring_type is a Completion ring. - * This value indicates what interrupt mode should be used - * on this completion ring. - * Note: In the legacy interrupt mode, no more than 16 - * completion rings are allowed. + * When this bit is '1', enable GRE_CUSTOMER1 encapsulated packets + * for aggregation. */ - uint8_t int_mode; - /* Legacy INTA (deprecated) */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0) - /* Reserved */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1) - /* MSI-X */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2) - /* No Interrupt - Polled mode */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3) - #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST HWRM_RING_ALLOC_INPUT_INT_MODE_POLL - /* Midpath channel type */ - uint8_t mpc_chnls_type; + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE_CUST1 UINT32_C(0x100) /* - * Indicate the TX ring alloc MPC channel type is a MPC channel - * with destination to the TX crypto engine block. + * When this bit is '1', enable UPAR1 encapsulated packets for + * aggregation. */ - #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR1 UINT32_C(0x200) /* - * Indicate the RX ring alloc MPC channel type is a MPC channel - * with destination to the RX crypto engine block. + * When this bit is '1', enable UPAR2 encapsulated packets for + * aggregation. */ - #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR2 UINT32_C(0x400) /* - * Indicate the RX ring alloc MPC channel type is a MPC channel - * with destination to the TX configurable flow processing block. + * When this bit is '1', enable UPAR3 encapsulated packets for + * aggregation. */ - #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR3 UINT32_C(0x800) /* - * Indicate the RX ring alloc MPC channel type is a MPC channel - * with destination to the RX configurable flow processing block. + * When this bit is '1', enable UPAR4 encapsulated packets for + * aggregation. */ - #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3) + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR4 UINT32_C(0x1000) /* - * Indicate the RX ring alloc MPC channel type is a MPC channel - * with destination to the primate processor block. + * When this bit is '1', enable UPAR5 encapsulated packets for + * aggregation. */ - #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4) - #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE - uint8_t unused_4[2]; + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR5 UINT32_C(0x2000) /* - * The cq_handle is specified when allocating a completion ring. For - * devices that support NQs, this cq_handle will be included in the - * NQE to specify which CQ should be read to retrieve the completion - * record. + * When this bit is '1', enable UPAR6 encapsulated packets for + * aggregation. */ - uint64_t cq_handle; -} hwrm_ring_alloc_input_t, *phwrm_ring_alloc_input_t; - -/* hwrm_ring_alloc_output (size:128b/16B) */ - -typedef struct hwrm_ring_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR6 UINT32_C(0x4000) /* - * Physical number of ring allocated. - * This value shall be unique for a ring type. + * When this bit is '1', enable UPAR7 encapsulated packets for + * aggregation. */ - uint16_t ring_id; - /* Logical number of ring allocated. */ - uint16_t logical_ring_id; + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR7 UINT32_C(0x8000) /* - * This field will tell whether to use ping or pong buffer - * for first push operation. + * When this bit is '1', enable UPAR8 encapsulated packets for + * aggregation. */ - uint8_t push_buffer_index; - /* Start push from ping buffer index */ - #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER UINT32_C(0x0) - /* Start push from pong buffer index */ - #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER UINT32_C(0x1) - #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER - uint8_t unused_0[2]; + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR8 UINT32_C(0x10000) + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_ring_alloc_output_t, *phwrm_ring_alloc_output_t; +} hwrm_vnic_tpa_qcfg_output_t, *phwrm_vnic_tpa_qcfg_output_t; -/****************** - * hwrm_ring_free * - ******************/ +/********************* + * hwrm_vnic_rss_cfg * + *********************/ -/* hwrm_ring_free_input (size:256b/32B) */ +/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ -typedef struct hwrm_ring_free_input { +typedef struct hwrm_vnic_rss_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -37650,307 +40953,209 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - /* RX Aggregation Ring */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) - /* Notification Queue */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5) - #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST HWRM_RING_FREE_INPUT_RING_TYPE_NQ - uint8_t flags; + uint32_t hash_type; /* - * If this bit is set to '1', ring_id in this command belongs to - * virtio function. prod_idx in this command corresponds to doorbell - * producer index. opaque field in this command needs to be inserted - * by firmware in VEE_FLUSH completion record. - * Firmware will poll the corresponding ring context to reach the - * given producer index before sending successful response. It will - * finish the completion using VEE_FLUSH completion record. - * - * If this bit is '0', firmware will not treat ring_id as virtio - * ring and ignore prod_idx, opaque fields. - * - * This feature is not applicable for L2 or RoCE. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. */ - #define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1) - #define HWRM_RING_FREE_INPUT_FLAGS_LAST HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID - /* Physical number of ring allocated. */ - uint16_t ring_id; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) /* - * Ring BD producer index posted by the virtio block. - * This field is valid if virtio_ring_valid flag is set. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. */ - uint32_t prod_idx; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) /* - * User defined opaque field to be inserted into VEE_FLUSH completion - * record. This field is valid if virtio_ring_valid flag is set. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. */ - uint32_t opaque; - uint32_t unused_1; -} hwrm_ring_free_input_t, *phwrm_ring_free_input_t; - -/* hwrm_ring_free_output (size:128b/16B) */ - -typedef struct hwrm_ring_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv6 addresses of IPv6 + * packets. */ - uint8_t valid; -} hwrm_ring_free_output_t, *phwrm_ring_free_output_t; - -/******************* - * hwrm_ring_reset * - *******************/ - - -/* hwrm_ring_reset_input (size:192b/24B) */ - -typedef struct hwrm_ring_reset_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. */ - uint16_t cmpl_ring; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. */ - uint16_t seq_id; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * When this bit is '1', the RSS hash shall be computed + * over source, destination IPv6 addresses and flow label of IPv6 + * packets. Hash type ipv6 and ipv6_flow_label are mutually + * exclusive. HW does not include the flow_label in hash + * calculation for the packets that are matching tcp_ipv6 and + * udp_ipv6 hash types. Host drivers should set this bit based on + * rss_ipv6_flow_label_cap. */ - uint16_t target_id; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL UINT32_C(0x40) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv4 packets. Host drivers should set this bit based on + * rss_ipsec_ah_spi_ipv4_cap. */ - uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 UINT32_C(0x80) /* - * Rx Ring Group. This is to reset rx and aggregation in an atomic - * operation. Completion ring associated with this ring group is - * not reset. + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv4 packets. Host drivers should set this bit based on + * rss_ipsec_esp_spi_ipv4_cap. */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6) - #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP - uint8_t unused_0; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 UINT32_C(0x100) /* - * Physical number of the ring. When ring type is rx_ring_grp, ring id - * actually refers to ring group id. + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv6 packets. Host drivers should set this bit based on + * rss_ipsec_ah_spi_ipv6_cap. */ - uint16_t ring_id; - uint8_t unused_1[4]; -} hwrm_ring_reset_input_t, *phwrm_ring_reset_input_t; - -/* hwrm_ring_reset_output (size:128b/16B) */ - -typedef struct hwrm_ring_reset_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6 UINT32_C(0x200) /* - * This field will tell whether to use ping or pong buffer - * for first push operation. + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv6 packets. Host drivers should set this bit based on + * rss_ipsec_esp_spi_ipv6_cap. */ - uint8_t push_buffer_index; - /* Start push from ping buffer index */ - #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER UINT32_C(0x0) - /* Start push from pong buffer index */ - #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER UINT32_C(0x1) - #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER - uint8_t unused_0[3]; - /* Position of consumer index after ring reset completes. */ - uint8_t consumer_idx[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} hwrm_ring_reset_output_t, *phwrm_ring_reset_output_t; - -/***************** - * hwrm_ring_cfg * - *****************/ - - -/* hwrm_ring_cfg_input (size:320b/40B) */ - -typedef struct hwrm_ring_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6 UINT32_C(0x400) + /* VNIC ID of VNIC associated with RSS table being configured. */ + uint16_t vnic_id; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Specifies which VNIC ring table pair to configure. + * Valid values range from 0 to 7. */ - uint16_t cmpl_ring; + uint8_t ring_table_pair_index; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Flags to specify different RSS hash modes. Global RSS hash mode is + * indicated when vnic_id and rss_ctx_idx fields are set to value of + * 0xffff. Only PF can initiate global RSS hash mode setting changes. + * VNIC RSS hash mode is indicated with valid vnic_id and rss_ctx_idx, + * if FW is VNIC_RSS_HASH_MODE capable. FW configures the mode based + * on first come first serve order. Global RSS hash mode and VNIC RSS + * hash modes are mutually exclusive. FW returns invalid error + * if FW receives conflicting requests. To change the current hash + * mode, the mode associated drivers need to be unloaded and apply + * the new configuration. */ - uint16_t seq_id; + uint8_t hash_mode_flags; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable, + * innermost_4 and innermost_2 hash modes are used to configure + * the tuple mode. When this bit is '1' and FW is not + * VNIC_RSS_HASH_MODE capable, It indicates using current RSS hash + * mode setting configured in the device otherwise. */ - uint16_t target_id; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. */ - uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* TX Ring (TR) */ - #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2) - #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST HWRM_RING_CFG_INPUT_RING_TYPE_RX - uint8_t unused_0; - /* Physical number of the ring. */ - uint16_t ring_id; - /* Ring config enable bits. */ - uint16_t enables; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2) /* - * For Rx rings, the incoming packet data can be placed at either - * a 0B, 2B, 10B or 12B offset from the start of the Rx packet - * buffer. - * When '1', the received packet will be padded with 2B, 10B or 12B - * of zeros at the front of the packet. The exact offset is specified - * by rx_sop_pad_bytes parameter. - * When '0', the received packet will not be padded. - * Note that this flag is only used for Rx rings and is ignored - * for all other rings included Rx Aggregation rings. + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. */ - #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE UINT32_C(0x1) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4) /* - * Proxy mode enable, for Tx, Rx and Rx aggregation rings only. - * When rings are allocated, the PCI function on which driver issues - * HWRM_RING_CFG command is assumed to own the rings. Hardware takes - * the buffer descriptors (BDs) from those rings is assumed to issue - * packet payload DMA using same PCI function. When proxy mode is - * enabled, hardware can perform payload DMA using another PCI - * function on same or different host. - * When set to '0', the PCI function on which driver issues - * HWRM_RING_CFG command is used for host payload DMA operation. - * When set to '1', the host PCI function specified by proxy_fid is - * used for host payload DMA operation. + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. */ - #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE UINT32_C(0x2) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8) /* - * Tx ring packet source interface override, for Tx rings only. - * When TX rings are allocated, the PCI function on which driver - * issues HWRM_RING_CFG is assumed to be source interface of - * packets sent from TX ring. - * When set to '1', the host PCI function specified by proxy_fid - * is used as source interface of the transmitted packets. + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. */ - #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE UINT32_C(0x4) - /* The schq_id field is valid */ - #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID UINT32_C(0x8) - /* Update completion ring ID associated with Tx or Rx ring. */ - #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE UINT32_C(0x10) + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10) + /* This is the address for rss ring group table */ + uint64_t ring_grp_tbl_addr; + /* This is the address for rss hash key table */ + uint64_t hash_key_tbl_addr; + /* Index to the rss indirection table. */ + uint16_t rss_ctx_idx; + uint8_t flags; /* - * When set to '1', metadata value provided by tx_metadata - * field in this command is inserted in the lb_header_metadata - * QP context field. When set to '0', no change done to metadata. - * Firmware rejects the tx ring metadata programming with - * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD - * metadata feature is not disabled. + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to add to the current + * hash. Zeroes designate the hash_type state bits that should remain + * unchanged, if possible. If this constraint on the existing state + * cannot be satisfied, then the implementation should preference + * adding other headers so as to honor the request to add the + * specified headers. It is an error to set this flag concurrently + * with hash_type_exclude. */ - #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA UINT32_C(0x20) + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE UINT32_C(0x1) /* - * Proxy function FID value. - * This value is only used when either proxy_mode_enable flag or - * tx_proxy_svif_override is set to '1'. - * When proxy_mode_enable is set to '1', it identifies a host PCI - * function used for host payload DMA operations. - * When tx_proxy_src_intf is set to '1', it identifies a host PCI - * function as source interface for all transmitted packets from - * the TX ring. + * When this bit is '1', it indicates that the hash_type field is + * interpreted as a change relative the current configuration. Each + * '1' bit in hash_type represents a header to remove from the + * current hash. Zeroes designate the hash_type state bits that + * should remain unchanged, if possible. If this constraint on the + * existing state cannot be satisfied, then the implementation should + * preference removing other headers so as to honor the request to + * remove the specified headers. It is an error to set this flag + * concurrently with hash_type_include. */ - uint16_t proxy_fid; + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE UINT32_C(0x2) /* - * Identifies the new scheduler queue (SCHQ) to associate with the - * ring. Only valid for Tx rings. - * A value of zero indicates that the Tx ring should be associated - * with the default scheduler queue (SCHQ). + * When this bit is '1', it indicates that the support of setting + * ipsec hash_types by the host drivers. */ - uint16_t schq_id; + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT UINT32_C(0x4) + uint8_t ring_select_mode; /* - * This field is valid for TX or Rx rings. This value identifies the - * new completion ring ID to associate with the TX or Rx ring. + * In this mode, HW uses Toeplitz algorithm and provided Toeplitz + * hash key to hash the packets according to the configured hash + * type and hash mode. The Toeplitz hash results and the provided + * Toeplitz RSS indirection table are used to determine the RSS + * rings. */ - uint16_t cmpl_ring_id; + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ UINT32_C(0x0) /* - * Rx SOP padding amount in bytes. - * This value is only used when rx_sop_pad_enable flag is set to '1'. + * In this mode, HW uses XOR algorithm to hash the packets according + * to the configured hash type and hash mode. The XOR hash results + * and the provided XOR RSS indirection table are used to determine + * the RSS rings. Host drivers provided hash key is not honored in + * this mode. */ - uint8_t rx_sop_pad_bytes; - uint8_t unused_1[3]; + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_XOR UINT32_C(0x1) /* - * When tx_metadata enable bit is set, value specified in this field - * is copied to lb_header_metadata in the QP context. + * In this mode, HW uses inner packets checksum algorithm to + * distribute the packets across the rings and Toeplitz algorithm + * to calculate the hash to convey it in the RX completions. Host + * drivers should provide Toeplitz hash key. As HW uses innermost + * packets checksum to distribute the packets across the rings, + * host drivers can't convey hash mode to choose outer headers to + * calculate Toeplitz hash. FW will fail such configuration. */ - uint32_t tx_metadata; - uint8_t unused_2[4]; -} hwrm_ring_cfg_input_t, *phwrm_ring_cfg_input_t; + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM UINT32_C(0x2) + #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_LAST HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM + uint8_t unused_1[4]; +} hwrm_vnic_rss_cfg_input_t, *phwrm_vnic_rss_cfg_input_t; -/* hwrm_ring_cfg_output (size:128b/16B) */ +/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ -typedef struct hwrm_ring_cfg_output { +typedef struct hwrm_vnic_rss_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -37962,23 +41167,41 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_ring_cfg_output_t, *phwrm_ring_cfg_output_t; +} hwrm_vnic_rss_cfg_output_t, *phwrm_vnic_rss_cfg_output_t; -/****************** - * hwrm_ring_qcfg * - ******************/ +/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ + +typedef struct hwrm_vnic_rss_cfg_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* + * Unable to change global RSS mode to outer due to all active + * interfaces are not ready to support outer RSS hashing. + */ + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY UINT32_C(0x1) + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY + uint8_t unused_0[7]; +} hwrm_vnic_rss_cfg_cmd_err_t, *phwrm_vnic_rss_cfg_cmd_err_t; +/********************** + * hwrm_vnic_rss_qcfg * + **********************/ -/* hwrm_ring_qcfg_input (size:192b/24B) */ -typedef struct hwrm_ring_qcfg_input { +/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ + +typedef struct hwrm_vnic_rss_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -38007,21 +41230,22 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* TX Ring (TR) */ - #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2) - #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST HWRM_RING_QCFG_INPUT_RING_TYPE_RX - uint8_t unused_0[5]; - /* Physical number of the ring. */ - uint16_t ring_id; -} hwrm_ring_qcfg_input_t, *phwrm_ring_qcfg_input_t; + /* + * Index to the rss indirection table. This field is used as a lookup + * for chips before Thor - i.e. Cumulus and Whitney. + */ + uint16_t rss_ctx_idx; + /* + * VNIC ID of VNIC associated with RSS table being queried. This field + * is used as a lookup for Thor and later chips. + */ + uint16_t vnic_id; + uint8_t unused_0[4]; +} hwrm_vnic_rss_qcfg_input_t, *phwrm_vnic_rss_qcfg_input_t; -/* hwrm_ring_qcfg_output (size:256b/32B) */ +/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ -typedef struct hwrm_ring_qcfg_output { +typedef struct hwrm_vnic_rss_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -38030,95 +41254,178 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Ring config enable bits. */ - uint16_t enables; + uint32_t hash_type; /* - * For Rx rings, the incoming packet data can be placed at either - * a 0B, 2B, 10B or 12B offset from the start of the Rx packet - * buffer. - * When '1', the received packet will be padded with 2B, 10B or 12B - * of zeros at the front of the packet. The exact offset is specified - * by rx_sop_pad_bytes parameter. - * When '0', the received packet will not be padded. - * Note that this flag is only used for Rx rings and is ignored - * for all other rings included Rx Aggregation rings. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. */ - #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE UINT32_C(0x1) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) /* - * Proxy mode enable, for Tx, Rx and Rx aggregation rings only. - * When rings are allocated, the PCI function on which driver issues - * HWRM_RING_CFG command is assumed to own the rings. Hardware takes - * the buffer descriptors (BDs) from those rings is assumed to issue - * packet payload DMA using same PCI function. When proxy mode is - * enabled, hardware can perform payload DMA using another PCI - * function on same or different host. - * When set to '0', the PCI function on which driver issues - * HWRM_RING_CFG command is used for host payload DMA operation. - * When set to '1', the host PCI function specified by proxy_fid is - * used for host payload DMA operation. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. */ - #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE UINT32_C(0x2) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) /* - * Tx ring packet source interface override, for Tx rings only. - * When TX rings are allocated, the PCI function on which driver - * issues HWRM_RING_CFG is assumed to be source interface of - * packets sent from TX ring. - * When set to '1', the host PCI function specified by proxy_fid is - * used as source interface of the transmitted packets. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. */ - #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE UINT32_C(0x4) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* - * Proxy function FID value. - * This value is only used when either proxy_mode_enable flag or - * tx_proxy_svif_override is set to '1'. - * When proxy_mode_enable is set to '1', it identifies a host PCI - * function used for host payload DMA operations. - * When tx_proxy_src_intf is set to '1', it identifies a host PCI - * function as source interface for all transmitted packets from the TX - * ring. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv6 addresses of IPv6 + * packets. */ - uint16_t proxy_fid; + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) /* - * Identifies the new scheduler queue (SCHQ) to associate with the - * ring. Only valid for Tx rings. - * A value of zero indicates that the Tx ring should be associated with - * the default scheduler queue (SCHQ). + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. */ - uint16_t schq_id; + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) /* - * This field is used when ring_type is a TX or Rx ring. - * This value indicates what completion ring the TX or Rx ring - * is associated with. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. */ - uint16_t cmpl_ring_id; + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) /* - * Rx SOP padding amount in bytes. - * This value is only used when rx_sop_pad_enable flag is set to '1'. + * When this bit is '1', the RSS hash shall be computed + * over source, destination IPv6 addresses and flow label of IPv6 + * packets. Hash type ipv6 and ipv6_flow_label are mutually + * exclusive. HW does not include the flow_label in hash + * calculation for the packets that are matching tcp_ipv6 and + * udp_ipv6 hash types. This bit will be '0' if + * rss_ipv6_flow_label_cap is '0'. */ - uint8_t rx_sop_pad_bytes; - uint8_t unused_0[3]; - /* lb_header_metadata in the QP context is copied to this field. */ - uint32_t tx_metadata; - uint8_t unused_1[7]; + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6_FLOW_LABEL UINT32_C(0x40) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv4 packets. This bit will be '0' if rss_ipsec_ah_spi_ipv4_cap + * is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV4 UINT32_C(0x80) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv4 packets. This bit will be '0' if + * rss_ipsec_esp_spi_ipv4_cap is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV4 UINT32_C(0x100) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv6 packets. This bit will be '0' if + * rss_ipsec_ah_spi_ipv6_cap is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV6 UINT32_C(0x200) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv6 packets. This bit will be '0' if + * rss_ipsec_esp_spi_ipv6_cap is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV6 UINT32_C(0x400) + uint8_t unused_0[4]; + /* This is the value of rss hash key */ + uint32_t hash_key[10]; + /* + * Flags to specify different RSS hash modes. Setting rss_ctx_idx to + * the value of 0xffff implies a global RSS configuration query. + * hash_mode_flags are only valid for global RSS configuration query. + * Only the PF can initiate a global RSS configuration query. + * The query request fails if any VNIC is configured with hash mode + * and rss_ctx_idx is 0xffff. + */ + uint8_t hash_mode_flags; + /* + * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable, + * it indicates VNIC's configured RSS hash mode. + * When this bit is '1' and FW is not VNIC_RSS_HASH_MODE capable, + * It indicates using current RSS hash mode setting configured in the + * device. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10) + uint8_t ring_select_mode; + /* + * In this mode, HW uses Toeplitz algorithm and provided Toeplitz + * hash key to hash the packets according to the configured hash + * type and hash mode. The Toeplitz hash results and the provided + * Toeplitz RSS indirection table are used to determine the RSS + * rings. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ UINT32_C(0x0) + /* + * In this mode, HW uses XOR algorithm to hash the packets according + * to the configured hash type and hash mode. The XOR hash results + * and the provided XOR RSS indirection table are used to determine + * the RSS rings. Host drivers provided hash key is not honored in + * this mode. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_XOR UINT32_C(0x1) + /* + * In this mode, HW uses inner packets checksum algorithm to + * distribute the packets across the rings and Toeplitz algorithm + * to calculate the hash to convey it in the RX completions. Host + * drivers should provide Toeplitz hash key. As HW uses innermost + * packets checksum to distribute the packets across the rings, + * host drivers can't convey hash mode to choose outer headers to + * calculate Toeplitz hash. FW will fail such configuration. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM UINT32_C(0x2) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_LAST HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM + uint8_t unused_1[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_ring_qcfg_output_t, *phwrm_ring_qcfg_output_t; +} hwrm_vnic_rss_qcfg_output_t, *phwrm_vnic_rss_qcfg_output_t; /************************** - * hwrm_ring_aggint_qcaps * + * hwrm_vnic_plcmodes_cfg * **************************/ -/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ +/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ -typedef struct hwrm_ring_aggint_qcaps_input { +typedef struct hwrm_vnic_plcmodes_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -38147,165 +41454,133 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_ring_aggint_qcaps_input_t, *phwrm_ring_aggint_qcaps_input_t; - -/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ - -typedef struct hwrm_ring_aggint_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t cmpl_params; + uint32_t flags; /* - * When this bit is set to '1', int_lat_tmr_min can be configured - * on completion rings. - */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN UINT32_C(0x1) - /* - * When this bit is set to '1', int_lat_tmr_max can be configured - * on completion rings. + * When this bit is '1', the VNIC shall be configured to + * use regular placement algorithm. + * By default, the regular placement algorithm shall be + * enabled on the VNIC. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX UINT32_C(0x2) + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1) /* - * When this bit is set to '1', timer_reset can be enabled - * on completion rings. + * When this bit is '1', the VNIC shall be configured + * use the jumbo placement algorithm. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET UINT32_C(0x4) + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2) /* - * When this bit is set to '1', ring_idle can be enabled - * on completion rings. + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for IPv4 packets according + * to the following rules: + * # If the packet is identified as TCP/IPv4, then the + * packet is split at the beginning of the TCP payload. + * # If the packet is identified as UDP/IPv4, then the + * packet is split at the beginning of UDP payload. + * # If the packet is identified as non-TCP and non-UDP + * IPv4 packet, then the packet is split at the beginning + * of the upper layer protocol header carried in the IPv4 + * packet. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE UINT32_C(0x8) + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 UINT32_C(0x4) /* - * When this bit is set to '1', num_cmpl_dma_aggr can be configured - * on completion rings. + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for IPv6 packets according + * to the following rules: + * # If the packet is identified as TCP/IPv6, then the + * packet is split at the beginning of the TCP payload. + * # If the packet is identified as UDP/IPv6, then the + * packet is split at the beginning of UDP payload. + * # If the packet is identified as non-TCP and non-UDP + * IPv6 packet, then the packet is split at the beginning + * of the upper layer protocol header carried in the IPv6 + * packet. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR UINT32_C(0x10) + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 UINT32_C(0x8) /* - * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured - * on completion rings. + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for FCoE packets at the + * beginning of FC payload. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT UINT32_C(0x20) + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE UINT32_C(0x10) /* - * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured - * on completion rings. + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for RoCE packets at the + * beginning of RoCE payload (after BTH/GRH headers). */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR UINT32_C(0x40) + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE UINT32_C(0x20) /* - * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured - * on completion rings. + * When this bit is '1', the VNIC shall be configured use the virtio + * placement algorithm. This feature can only be configured when + * proxy mode is supported on the function. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT UINT32_C(0x80) + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT UINT32_C(0x40) + uint32_t enables; /* - * When this bit is set to '1', num_cmpl_aggr_int can be configured - * on completion rings. + * This bit must be '1' for the jumbo_thresh_valid field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT UINT32_C(0x100) - uint32_t nq_params; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID UINT32_C(0x1) /* - * When this bit is set to '1', int_lat_tmr_min can be configured - * on notification queues. + * This bit must be '1' for the hds_offset_valid field to be + * configured. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN UINT32_C(0x1) - /* Minimum value for num_cmpl_dma_aggr */ - uint16_t num_cmpl_dma_aggr_min; - /* Maximum value for num_cmpl_dma_aggr */ - uint16_t num_cmpl_dma_aggr_max; - /* Minimum value for num_cmpl_dma_aggr_during_int */ - uint16_t num_cmpl_dma_aggr_during_int_min; - /* Maximum value for num_cmpl_dma_aggr_during_int */ - uint16_t num_cmpl_dma_aggr_during_int_max; - /* Minimum value for cmpl_aggr_dma_tmr */ - uint16_t cmpl_aggr_dma_tmr_min; - /* Maximum value for cmpl_aggr_dma_tmr */ - uint16_t cmpl_aggr_dma_tmr_max; - /* Minimum value for cmpl_aggr_dma_tmr_during_int */ - uint16_t cmpl_aggr_dma_tmr_during_int_min; - /* Maximum value for cmpl_aggr_dma_tmr_during_int */ - uint16_t cmpl_aggr_dma_tmr_during_int_max; - /* Minimum value for int_lat_tmr_min */ - uint16_t int_lat_tmr_min_min; - /* Maximum value for int_lat_tmr_min */ - uint16_t int_lat_tmr_min_max; - /* Minimum value for int_lat_tmr_max */ - uint16_t int_lat_tmr_max_min; - /* Maximum value for int_lat_tmr_max */ - uint16_t int_lat_tmr_max_max; - /* Minimum value for num_cmpl_aggr_int */ - uint16_t num_cmpl_aggr_int_min; - /* Maximum value for num_cmpl_aggr_int */ - uint16_t num_cmpl_aggr_int_max; - /* The units for timer parameters, in nanoseconds. */ - uint16_t timer_units; - uint8_t unused_0[1]; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID UINT32_C(0x2) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This bit must be '1' for the hds_threshold_valid field to be + * configured. */ - uint8_t valid; -} hwrm_ring_aggint_qcaps_output_t, *phwrm_ring_aggint_qcaps_output_t; - -/************************************** - * hwrm_ring_cmpl_ring_qaggint_params * - **************************************/ - - -/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ - -typedef struct hwrm_ring_cmpl_ring_qaggint_params_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID UINT32_C(0x4) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This bit must be '1' for the max_bds_valid field to be + * configured. */ - uint16_t cmpl_ring; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID UINT32_C(0x8) + /* Logical vnic ID */ + uint32_t vnic_id; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * When jumbo placement algorithm is enabled, this value + * is used to determine the threshold for jumbo placement. + * Packets with length larger than this value will be + * placed according to the jumbo placement algorithm. */ - uint16_t seq_id; + uint16_t jumbo_thresh; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This value is used to determine the offset into + * packet buffer where the split data (payload) will be + * placed according to one of HDS placement algorithm. + * + * The lengths of packet buffers provided for split data + * shall be larger than this value. */ - uint16_t target_id; + uint16_t hds_offset; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * When one of the HDS placement algorithm is enabled, this + * value is used to determine the threshold for HDS + * placement. + * Packets with length larger than this value will be + * placed according to the HDS placement algorithm. + * This value shall be in multiple of 4 bytes. */ - uint64_t resp_addr; - /* Physical number of completion ring. */ - uint16_t ring_id; - uint16_t flags; - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK UINT32_C(0x3) - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0 + uint16_t hds_threshold; /* - * Set this flag to 1 when querying parameters on a notification - * queue. Set this flag to 0 when querying parameters on a - * completion queue or completion ring. + * When virtio placement algorithm is enabled, this + * value is used to determine the maximum number of BDs + * that can be used to place an Rx Packet. + * If an incoming packet does not fit in the buffers described + * by the max BDs, the packet will be dropped and an error + * will be reported in the completion. Valid values for this + * field are between 1 and 8. If the VNIC uses header-data- + * separation and/or TPA with buffer spanning enabled, valid + * values for this field are between 2 and 8. + * This feature can only be configured when proxy mode is + * supported on the function. */ - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ UINT32_C(0x4) + uint16_t max_bds; uint8_t unused_0[4]; -} hwrm_ring_cmpl_ring_qaggint_params_input_t, *phwrm_ring_cmpl_ring_qaggint_params_input_t; +} hwrm_vnic_plcmodes_cfg_input_t, *phwrm_vnic_plcmodes_cfg_input_t; -/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ +/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ -typedef struct hwrm_ring_cmpl_ring_qaggint_params_output { +typedef struct hwrm_vnic_plcmodes_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -38314,69 +41589,26 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint16_t flags; - /* - * When this bit is set to '1', interrupt max - * timer is reset whenever a completion is received. - */ - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET UINT32_C(0x1) - /* - * When this bit is set to '1', ring idle mode - * aggregation will be enabled. - */ - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE UINT32_C(0x2) - /* - * Number of completions to aggregate before DMA - * during the normal mode. - */ - uint16_t num_cmpl_dma_aggr; - /* - * Number of completions to aggregate before DMA - * during the interrupt mode. - */ - uint16_t num_cmpl_dma_aggr_during_int; - /* - * Timer used to aggregate completions before - * DMA during the normal mode (not in interrupt mode). - */ - uint16_t cmpl_aggr_dma_tmr; - /* - * Timer used to aggregate completions before - * DMA when in interrupt mode. - */ - uint16_t cmpl_aggr_dma_tmr_during_int; - /* Minimum time between two interrupts. */ - uint16_t int_lat_tmr_min; - /* - * Maximum wait time spent aggregating - * completions before signaling the interrupt after the - * interrupt is enabled. - */ - uint16_t int_lat_tmr_max; - /* - * Minimum number of completions aggregated before signaling - * an interrupt. - */ - uint16_t num_cmpl_aggr_int; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_ring_cmpl_ring_qaggint_params_output_t, *phwrm_ring_cmpl_ring_qaggint_params_output_t; +} hwrm_vnic_plcmodes_cfg_output_t, *phwrm_vnic_plcmodes_cfg_output_t; -/***************************************** - * hwrm_ring_cmpl_ring_cfg_aggint_params * - *****************************************/ +/*************************** + * hwrm_vnic_plcmodes_qcfg * + ***************************/ -/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ +/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */ -typedef struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { +typedef struct hwrm_vnic_plcmodes_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -38405,128 +41637,123 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Physical number of completion ring. */ - uint16_t ring_id; - uint16_t flags; - /* - * When this bit is set to '1', interrupt latency max - * timer is reset whenever a completion is received. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET UINT32_C(0x1) - /* - * When this bit is set to '1', ring idle mode - * aggregation will be enabled. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE UINT32_C(0x2) - /* - * Set this flag to 1 when configuring parameters on a - * notification queue. Set this flag to 0 when configuring - * parameters on a completion queue or completion ring. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ UINT32_C(0x4) - /* - * Number of completions to aggregate before DMA - * during the normal mode. - */ - uint16_t num_cmpl_dma_aggr; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[4]; +} hwrm_vnic_plcmodes_qcfg_input_t, *phwrm_vnic_plcmodes_qcfg_input_t; + +/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */ + +typedef struct hwrm_vnic_plcmodes_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; /* - * Number of completions to aggregate before DMA - * during the interrupt mode. + * When this bit is '1', the VNIC is configured to + * use regular placement algorithm. */ - uint16_t num_cmpl_dma_aggr_during_int; + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1) /* - * Timer used to aggregate completions before - * DMA during the normal mode (not in interrupt mode). + * When this bit is '1', the VNIC is configured to + * use the jumbo placement algorithm. */ - uint16_t cmpl_aggr_dma_tmr; + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2) /* - * Timer used to aggregate completions before - * DMA while in interrupt mode. + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for IPv4 packets. */ - uint16_t cmpl_aggr_dma_tmr_during_int; - /* Minimum time between two interrupts. */ - uint16_t int_lat_tmr_min; + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 UINT32_C(0x4) /* - * Maximum wait time spent aggregating - * completions before signaling the interrupt after the - * interrupt is enabled. + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for IPv6 packets. */ - uint16_t int_lat_tmr_max; + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 UINT32_C(0x8) /* - * Minimum number of completions aggregated before signaling - * an interrupt. + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for FCoE packets. */ - uint16_t num_cmpl_aggr_int; + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE UINT32_C(0x10) /* - * Bitfield that indicates which parameters are to be applied. Only - * required when configuring devices with notification queues, and - * used in that case to set certain parameters on completion queues - * and others on notification queues. + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for RoCE packets. */ - uint16_t enables; + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE UINT32_C(0x20) /* - * This bit must be '1' for the num_cmpl_dma_aggr field to be - * configured. + * When this bit is '1', the VNIC is configured + * to be the default VNIC of the requesting function. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR UINT32_C(0x1) + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC UINT32_C(0x40) /* - * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be - * configured. + * When this bit is '1', the VNIC is configured to use the virtio + * placement algorithm. This feature can only be configured when + * proxy mode is supported on the function. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT UINT32_C(0x2) + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT UINT32_C(0x80) /* - * This bit must be '1' for the cmpl_aggr_dma_tmr field to be - * configured. + * When jumbo placement algorithm is enabled, this value + * is used to determine the threshold for jumbo placement. + * Packets with length larger than this value will be + * placed according to the jumbo placement algorithm. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR UINT32_C(0x4) + uint16_t jumbo_thresh; /* - * This bit must be '1' for the int_lat_tmr_min field to be - * configured. + * This value is used to determine the offset into + * packet buffer where the split data (payload) will be + * placed according to one of HDS placement algorithm. + * + * The lengths of packet buffers provided for split data + * shall be larger than this value. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN UINT32_C(0x8) + uint16_t hds_offset; /* - * This bit must be '1' for the int_lat_tmr_max field to be - * configured. + * When one of the HDS placement algorithm is enabled, this + * value is used to determine the threshold for HDS + * placement. + * Packets with length larger than this value will be + * placed according to the HDS placement algorithm. + * This value shall be in multiple of 4 bytes. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX UINT32_C(0x10) + uint16_t hds_threshold; /* - * This bit must be '1' for the num_cmpl_aggr_int field to be - * configured. + * When virtio placement algorithm is enabled, this + * value is used to determine the maximum number of BDs + * that can be used to place an Rx Packet. + * If an incoming packet does not fit in the buffers described + * by the max BDs, the packet will be dropped and an error + * will be reported in the completion. Valid values for this + * field are between 1 and 8. If the VNIC uses header-data- + * separation and/or TPA with buffer spanning enabled, valid + * values for this field are between 2 and 8. + * This feature can only be configured when proxy mode is supported + * on the function */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT UINT32_C(0x20) - uint8_t unused_0[4]; -} hwrm_ring_cmpl_ring_cfg_aggint_params_input_t, *phwrm_ring_cmpl_ring_cfg_aggint_params_input_t; - -/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ - -typedef struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint16_t max_bds; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_ring_cmpl_ring_cfg_aggint_params_output_t, *phwrm_ring_cmpl_ring_cfg_aggint_params_output_t; +} hwrm_vnic_plcmodes_qcfg_output_t, *phwrm_vnic_plcmodes_qcfg_output_t; -/*********************** - * hwrm_ring_grp_alloc * - ***********************/ +/********************************** + * hwrm_vnic_rss_cos_lb_ctx_alloc * + **********************************/ -/* hwrm_ring_grp_alloc_input (size:192b/24B) */ +/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ -typedef struct hwrm_ring_grp_alloc_input { +typedef struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -38555,32 +41782,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This value identifies the CR associated with the ring - * group. - */ - uint16_t cr; - /* - * This value identifies the main RR associated with the ring - * group. - */ - uint16_t rr; - /* - * This value identifies the aggregation RR associated with - * the ring group. If this value is 0xFF... (All Fs), then no - * Aggregation ring will be set. - */ - uint16_t ar; - /* - * This value identifies the statistics context associated - * with the ring group. - */ - uint16_t sc; -} hwrm_ring_grp_alloc_input_t, *phwrm_ring_grp_alloc_input_t; +} hwrm_vnic_rss_cos_lb_ctx_alloc_input_t, *phwrm_vnic_rss_cos_lb_ctx_alloc_input_t; -/* hwrm_ring_grp_alloc_output (size:128b/16B) */ +/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ -typedef struct hwrm_ring_grp_alloc_output { +typedef struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -38589,31 +41795,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This is the ring group ID value. Use this value to program - * the default ring group for the VNIC or as table entries - * in an RSS/COS context. - */ - uint32_t ring_group_id; - uint8_t unused_0[3]; + /* rss_cos_lb_ctx_id is 16 b */ + uint16_t rss_cos_lb_ctx_id; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_ring_grp_alloc_output_t, *phwrm_ring_grp_alloc_output_t; +} hwrm_vnic_rss_cos_lb_ctx_alloc_output_t, *phwrm_vnic_rss_cos_lb_ctx_alloc_output_t; -/********************** - * hwrm_ring_grp_free * - **********************/ +/********************************* + * hwrm_vnic_rss_cos_lb_ctx_free * + *********************************/ -/* hwrm_ring_grp_free_input (size:192b/24B) */ +/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ -typedef struct hwrm_ring_grp_free_input { +typedef struct hwrm_vnic_rss_cos_lb_ctx_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -38642,14 +41844,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This is the ring group ID value. */ - uint32_t ring_group_id; - uint8_t unused_0[4]; -} hwrm_ring_grp_free_input_t, *phwrm_ring_grp_free_input_t; + /* rss_cos_lb_ctx_id is 16 b */ + uint16_t rss_cos_lb_ctx_id; + uint8_t unused_0[6]; +} hwrm_vnic_rss_cos_lb_ctx_free_input_t, *phwrm_vnic_rss_cos_lb_ctx_free_input_t; -/* hwrm_ring_grp_free_output (size:128b/16B) */ +/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ -typedef struct hwrm_ring_grp_free_output { +typedef struct hwrm_vnic_rss_cos_lb_ctx_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -38661,22 +41863,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_ring_grp_free_output_t, *phwrm_ring_grp_free_output_t; +} hwrm_vnic_rss_cos_lb_ctx_free_output_t, *phwrm_vnic_rss_cos_lb_ctx_free_output_t; -/************************ - * hwrm_ring_schq_alloc * - ************************/ +/******************* + * hwrm_ring_alloc * + *******************/ -/* hwrm_ring_schq_alloc_input (size:1088b/136B) */ +/* hwrm_ring_alloc_input (size:704b/88B) */ -typedef struct hwrm_ring_schq_alloc_input { +typedef struct hwrm_ring_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -38707,415 +41909,372 @@ uint64_t resp_addr; uint32_t enables; /* - * This bit must be '1' for the tqm_ring0 fields to be + * This bit must be '1' for the ring_arb_cfg field to be * configured. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG UINT32_C(0x2) /* - * This bit must be '1' for the tqm_ring1 fields to be + * This bit must be '1' for the stat_ctx_id_valid field to be * configured. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2) + #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID UINT32_C(0x8) /* - * This bit must be '1' for the tqm_ring2 fields to be + * This bit must be '1' for the max_bw_valid field to be * configured. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4) + #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID UINT32_C(0x20) /* - * This bit must be '1' for the tqm_ring3 fields to be + * This bit must be '1' for the rx_ring_id field to be * configured. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8) + #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID UINT32_C(0x40) /* - * This bit must be '1' for the tqm_ring4 fields to be + * This bit must be '1' for the nq_ring_id field to be * configured. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10) + #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID UINT32_C(0x80) /* - * This bit must be '1' for the tqm_ring5 fields to be + * This bit must be '1' for the rx_buf_size field to be * configured. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20) + #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID UINT32_C(0x100) /* - * This bit must be '1' for the tqm_ring6 fields to be + * This bit must be '1' for the schq_id field to be * configured. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40) + #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID UINT32_C(0x200) /* - * This bit must be '1' for the tqm_ring7 fields to be + * This bit must be '1' for the mpc_chnls_type field to be * configured. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80) - /* Reserved for future use. */ - uint32_t reserved; - /* TQM ring 0 page size and level. */ - uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; - /* TQM ring 0 PBL indirect levels. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE UINT32_C(0x400) /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * This bit must be '1' for the steering_tag field to be + * configured. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 - /* TQM ring 0 page size. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G - /* TQM ring 1 page size and level. */ - uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; - /* TQM ring 1 PBL indirect levels. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_ENABLES_STEERING_TAG_VALID UINT32_C(0x800) + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* RX Aggregation Ring */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) + /* Notification Queue */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * This field controls the number of packets transmitted before a TX + * completion is generated. Non-zero values for the field are only + * valid if HWRM_FUNC_QCAPS indicates that the TX coalesced completion + * records capability is supported. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 - /* TQM ring 1 page size. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G - /* TQM ring 2 page size and level. */ - uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; - /* TQM ring 2 PBL indirect levels. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1) + uint8_t cmpl_coal_cnt; + /* Generates a legacy TX completion on every packet. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0) + /* Generates a TX coalesced completion for up to 4 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4 UINT32_C(0x1) + /* Generates a TX coalesced completion for up to 8 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8 UINT32_C(0x2) + /* Generates a TX coalesced completion for up to 12 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12 UINT32_C(0x3) + /* Generates a TX coalesced completion for up to 16 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16 UINT32_C(0x4) + /* Generates a TX coalesced completion for up to 24 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24 UINT32_C(0x5) + /* Generates a TX coalesced completion for up to 32 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32 UINT32_C(0x6) + /* Generates a TX coalesced completion for up to 48 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48 UINT32_C(0x7) + /* Generates a TX coalesced completion for up to 64 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64 UINT32_C(0x8) + /* Generates a TX coalesced completion for up to 96 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96 UINT32_C(0x9) + /* Generates a TX coalesced completion for up to 128 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa) + /* Generates a TX coalesced completion for up to 192 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb) + /* Generates a TX coalesced completion for up to 256 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc) + /* Generates a TX coalesced completion for up to 320 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd) + /* Generates a TX coalesced completion for up to 384 TX packets. */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe) + /* Generates a TX coalesced completion up to the last packet. (Maximum coalescing). */ + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf) + #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_LAST HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX + /* Ring allocation flags. */ + uint16_t flags; /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * For Rx rings, the incoming packet data can be placed at either + * a 0B or 2B offset from the start of the Rx packet buffer. When + * '1', the received packet will be padded with 2B of zeros at the + * front of the packet. Note that this flag is only used for + * Rx rings and is ignored for all other rings included Rx + * Aggregation rings. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 - /* TQM ring 2 page size. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G - /* TQM ring 3 page size and level. */ - uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; - /* TQM ring 3 PBL indirect levels. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1) /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * When the HW Doorbell Drop Recovery feature is enabled, + * HW can flag false CQ overflow when CQ consumer index + * doorbells are dropped when there really wasn't any overflow. + * The CQE values could have already been processed by the driver, + * but HW doesn't know about this because of the doorbell drop. + * To avoid false detection of CQ overflow events, + * it is recommended that CQ overflow detection is disabled + * by the driver when HW based doorbell recovery is enabled. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 - /* TQM ring 3 page size. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G - /* TQM ring 4 page size and level. */ - uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; - /* TQM ring 4 PBL indirect levels. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x2) /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * Used with enhanced Doorbell Pacing feature, when set to '1' + * this flag indicates that the NQ id that's allocated should be + * used for DBR pacing notifications. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 - /* TQM ring 4 page size. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G - /* TQM ring 5 page size and level. */ - uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; - /* TQM ring 5 PBL indirect levels. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_FLAGS_NQ_DBR_PACING UINT32_C(0x4) /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * Host driver should set this flag bit to '1' to enable + * two-completion TX packet timestamp feature. By enabling this + * per QP flag and enabling stamp bit in TX BD lflags, host drivers + * expect two completions, one for regular TX completion and the + * other completion with timestamp. For a QP with both completion + * coalescing and timestamp completion features enabled, completion + * coalescing takes place on regular TX completions. The timestamp + * completions are not coalesced and a separate timestamp completion + * is generated for each packet with stamp bit set in the TX BD + * lflags. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 - /* TQM ring 5 page size. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G - /* TQM ring 6 page size and level. */ - uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; - /* TQM ring 6 PBL indirect levels. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_FLAGS_TX_PKT_TS_CMPL_ENABLE UINT32_C(0x8) /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * This value is a pointer to the page table for the + * Ring. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 - /* TQM ring 6 page size. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G - /* TQM ring 7 page size and level. */ - uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; - /* TQM ring 7 PBL indirect levels. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK UINT32_C(0xf) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1) + uint64_t page_tbl_addr; + /* First Byte Offset of the first entry in the first page. */ + uint32_t fbo; /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * Actual page size in 2^page_size. The supported range is increments + * in powers of 2 from 16 bytes to 1GB. + * - 4 = 16 B + * Page size is 16 B. + * - 12 = 4 KB + * Page size is 4 KB. + * - 13 = 8 KB + * Page size is 8 KB. + * - 16 = 64 KB + * Page size is 64 KB. + * - 21 = 2 MB + * Page size is 2 MB. + * - 22 = 4 MB + * Page size is 4 MB. + * - 30 = 1 GB + * Page size is 1 GB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 - /* TQM ring 7 page size. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G - /* TQM ring 0 page directory. */ - uint64_t tqm_ring0_page_dir; - /* TQM ring 1 page directory. */ - uint64_t tqm_ring1_page_dir; - /* TQM ring 2 page directory. */ - uint64_t tqm_ring2_page_dir; - /* TQM ring 3 page directory. */ - uint64_t tqm_ring3_page_dir; - /* TQM ring 4 page directory. */ - uint64_t tqm_ring4_page_dir; - /* TQM ring 5 page directory. */ - uint64_t tqm_ring5_page_dir; - /* TQM ring 6 page directory. */ - uint64_t tqm_ring6_page_dir; - /* TQM ring 7 page directory. */ - uint64_t tqm_ring7_page_dir; + uint8_t page_size; /* - * Number of TQM ring 0 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SCHQ and then reallocate it. + * This value indicates the depth of page table. + * For this version of the specification, value other than 0 or + * 1 shall be considered as an invalid value. + * When the page_tbl_depth = 0, then it is treated as a + * special case with the following. + * 1. FBO and page size fields are not valid. + * 2. page_tbl_addr is the physical address of the first + * element of the ring. */ - uint32_t tqm_ring0_num_entries; + uint8_t page_tbl_depth; + /* Used by a PF driver to associate a SCHQ with one of its TX rings. */ + uint16_t schq_id; /* - * Number of TQM ring 1 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SCHQ and then reallocate it. + * Number of 16B units in the ring. Minimum size for + * a ring is 16 16B entries. */ - uint32_t tqm_ring1_num_entries; + uint32_t length; /* - * Number of TQM ring 2 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. + * Logical ring number for the ring to be allocated. + * This value determines the position in the doorbell + * area where the update to the ring will be made. * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SCHQ and then reallocate it. + * For completion rings, this value is also the MSI-X + * vector number for the function the completion ring is + * associated with. */ - uint32_t tqm_ring2_num_entries; + uint16_t logical_id; /* - * Number of TQM ring 3 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SCHQ and then reallocate it. + * This field is used only when ring_type is a TX ring. + * This value indicates what completion ring the TX ring + * is associated with. */ - uint32_t tqm_ring3_num_entries; + uint16_t cmpl_ring_id; /* - * Number of TQM ring 4 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SCHQ and then reallocate it. + * This field is used only when ring_type is a TX ring. + * This value indicates what CoS queue the TX ring + * is associated with. */ - uint32_t tqm_ring4_num_entries; + uint16_t queue_id; /* - * Number of TQM ring 5 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SCHQ and then reallocate it. + * When allocating a Rx ring or Rx aggregation ring, this field + * specifies the size of the buffer descriptors posted to the ring. */ - uint32_t tqm_ring5_num_entries; + uint16_t rx_buf_size; /* - * Number of TQM ring 6 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SCHQ and then reallocate it. + * When allocating an Rx aggregation ring, this field + * specifies the associated Rx ring ID. */ - uint32_t tqm_ring6_num_entries; + uint16_t rx_ring_id; /* - * Number of TQM ring 7 entries. - * - * TQM fastpath rings should be sized large enough to accommodate the - * maximum number of QPs (either L2 or RoCE, or both if shared) - * that can be enqueued to the TQM ring. - * - * Note that TQM ring sizes cannot be extended while the system is - * operational. If a PF driver needs to extend a TQM ring, it needs - * to delete the SCHQ and then reallocate it. + * When allocating a completion ring, this field + * specifies the associated NQ ring ID. */ - uint32_t tqm_ring7_num_entries; - /* Number of bytes that have been allocated for each context entry. */ - uint16_t tqm_entry_size; - uint8_t unused_0[6]; -} hwrm_ring_schq_alloc_input_t, *phwrm_ring_schq_alloc_input_t; - -/* hwrm_ring_schq_alloc_output (size:128b/16B) */ - -typedef struct hwrm_ring_schq_alloc_output { + uint16_t nq_ring_id; + /* + * This field is used only when ring_type is a TX ring. + * This field is used to configure arbitration related + * parameters for a TX ring. + */ + uint16_t ring_arb_cfg; + /* Arbitration policy used for the ring. */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK UINT32_C(0xf) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0 + /* + * Use strict priority for the TX ring. + * Priority value is specified in arb_policy_param + */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP UINT32_C(0x1) + /* + * Use weighted fair queue arbitration for the TX ring. + * Weight is specified in arb_policy_param + */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ UINT32_C(0x2) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ + /* Reserved field. */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK UINT32_C(0xf0) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4 + /* + * Arbitration policy specific parameter. + * # For strict priority arbitration policy, this field + * represents a priority value. If set to 0, then the priority + * is not specified and the HWRM is allowed to select + * any priority for this TX ring. + * # For weighted fair queue arbitration policy, this field + * represents a weight value. If set to 0, then the weight + * is not specified and the HWRM is allowed to select + * any weight for this TX ring. + */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK UINT32_C(0xff00) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint32_t reserved3; + /* + * This field is used only when ring_type is a TX ring. + * This input indicates what statistics context this ring + * should be associated with. + */ + uint32_t stat_ctx_id; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint32_t reserved4; + /* + * This field is used only when ring_type is a TX ring + * to specify maximum BW allocated to the TX ring. + * The HWRM will translate this value into byte counter and + * time interval used for this ring inside the device. + */ + uint32_t max_bw; + /* The bandwidth value. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID + /* + * This field is used only when ring_type is a Completion ring. + * This value indicates what interrupt mode should be used + * on this completion ring. + * Note: In the legacy interrupt mode, no more than 16 + * completion rings are allowed. + */ + uint8_t int_mode; + /* Legacy INTA (deprecated) */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0) + /* Reserved */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1) + /* MSI-X */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2) + /* No Interrupt - Polled mode */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3) + #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST HWRM_RING_ALLOC_INPUT_INT_MODE_POLL + /* Midpath channel type */ + uint8_t mpc_chnls_type; + /* + * Indicate the TX ring alloc MPC channel type is a MPC channel + * with destination to the TX crypto engine block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the RX crypto engine block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the TX configurable flow processing block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the RX configurable flow processing block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3) + /* + * Indicate the RX ring alloc MPC channel type is a MPC channel + * with destination to the primate processor block. + */ + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4) + #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE + uint8_t unused_4[2]; + /* + * The cq_handle is specified when allocating a completion ring. For + * devices that support NQs, this cq_handle will be included in the + * NQE to specify which CQ should be read to retrieve the completion + * record. + */ + uint64_t cq_handle; +} hwrm_ring_alloc_input_t, *phwrm_ring_alloc_input_t; + +/* hwrm_ring_alloc_output (size:128b/16B) */ + +typedef struct hwrm_ring_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39125,30 +42284,41 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * This is an identifier for the SCHQ to be used in other HWRM commands - * that need to reference this SCHQ. This value is greater than zero - * (i.e. a schq_id of zero references the default SCHQ). + * Physical number of ring allocated. + * This value shall be unique for a ring type. */ - uint16_t schq_id; - uint8_t unused_0[5]; + uint16_t ring_id; + /* Logical number of ring allocated. */ + uint16_t logical_ring_id; + /* + * This field will tell whether to use ping or pong buffer + * for first push operation. + */ + uint8_t push_buffer_index; + /* Start push from ping buffer index */ + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER UINT32_C(0x0) + /* Start push from pong buffer index */ + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER UINT32_C(0x1) + #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER + uint8_t unused_0[2]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_ring_schq_alloc_output_t, *phwrm_ring_schq_alloc_output_t; +} hwrm_ring_alloc_output_t, *phwrm_ring_alloc_output_t; -/********************** - * hwrm_ring_schq_cfg * - **********************/ +/****************** + * hwrm_ring_free * + ******************/ -/* hwrm_ring_schq_cfg_input (size:768b/96B) */ +/* hwrm_ring_free_input (size:256b/32B) */ -typedef struct hwrm_ring_schq_cfg_input { +typedef struct hwrm_ring_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39177,106 +42347,56 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* RX Aggregation Ring */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) + /* Notification Queue */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5) + #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST HWRM_RING_FREE_INPUT_RING_TYPE_NQ + uint8_t flags; /* - * Identifies the SCHQ being configured. A schq_id of zero refers to - * the default SCHQ. - */ - uint16_t schq_id; - /* - * This field is an 8 bit bitmap that indicates which TCs are enabled - * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents - * traffic class 7. - */ - uint8_t tc_enabled; - uint8_t unused_0; - uint32_t flags; - /* The tc_max_bw array and the max_bw parameters are valid */ - #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED UINT32_C(0x1) - /* The tc_min_bw array is valid */ - #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED UINT32_C(0x2) - /* Maximum bandwidth of the traffic class, specified in Mbps. */ - uint32_t max_bw_tc0; - /* Maximum bandwidth of the traffic class, specified in Mbps. */ - uint32_t max_bw_tc1; - /* Maximum bandwidth of the traffic class, specified in Mbps. */ - uint32_t max_bw_tc2; - /* Maximum bandwidth of the traffic class, specified in Mbps. */ - uint32_t max_bw_tc3; - /* Maximum bandwidth of the traffic class, specified in Mbps. */ - uint32_t max_bw_tc4; - /* Maximum bandwidth of the traffic class, specified in Mbps. */ - uint32_t max_bw_tc5; - /* Maximum bandwidth of the traffic class, specified in Mbps. */ - uint32_t max_bw_tc6; - /* Maximum bandwidth of the traffic class, specified in Mbps. */ - uint32_t max_bw_tc7; - /* - * Bandwidth reservation for the traffic class, specified in Mbps. - * A value of zero signifies that traffic belonging to this class - * shares the bandwidth reservation for the same traffic class of - * the default SCHQ. - */ - uint32_t min_bw_tc0; - /* - * Bandwidth reservation for the traffic class, specified in Mbps. - * A value of zero signifies that traffic belonging to this class - * shares the bandwidth reservation for the same traffic class of - * the default SCHQ. - */ - uint32_t min_bw_tc1; - /* - * Bandwidth reservation for the traffic class, specified in Mbps. - * A value of zero signifies that traffic belonging to this class - * shares the bandwidth reservation for the same traffic class of - * the default SCHQ. - */ - uint32_t min_bw_tc2; - /* - * Bandwidth reservation for the traffic class, specified in Mbps. - * A value of zero signifies that traffic belonging to this class - * shares the bandwidth reservation for the same traffic class of - * the default SCHQ. - */ - uint32_t min_bw_tc3; - /* - * Bandwidth reservation for the traffic class, specified in Mbps. - * A value of zero signifies that traffic belonging to this class - * shares the bandwidth reservation for the same traffic class of - * the default SCHQ. - */ - uint32_t min_bw_tc4; - /* - * Bandwidth reservation for the traffic class, specified in Mbps. - * A value of zero signifies that traffic belonging to this class - * shares the bandwidth reservation for the same traffic class of - * the default SCHQ. - */ - uint32_t min_bw_tc5; - /* - * Bandwidth reservation for the traffic class, specified in Mbps. - * A value of zero signifies that traffic belonging to this class - * shares the bandwidth reservation for the same traffic class of - * the default SCHQ. + * If this bit is set to '1', ring_id in this command belongs to + * virtio function. prod_idx in this command corresponds to doorbell + * producer index. opaque field in this command needs to be inserted + * by firmware in VEE_FLUSH completion record. + * Firmware will poll the corresponding ring context to reach the + * given producer index before sending successful response. It will + * finish the completion using VEE_FLUSH completion record. + * + * If this bit is '0', firmware will not treat ring_id as virtio + * ring and ignore prod_idx, opaque fields. + * + * This feature is not applicable for L2 or RoCE. */ - uint32_t min_bw_tc6; + #define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1) + #define HWRM_RING_FREE_INPUT_FLAGS_LAST HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID + /* Physical number of ring allocated. */ + uint16_t ring_id; /* - * Bandwidth reservation for the traffic class, specified in Mbps. - * A value of zero signifies that traffic belonging to this class - * shares the bandwidth reservation for the same traffic class of - * the default SCHQ. + * Ring BD producer index posted by the virtio block. + * This field is valid if virtio_ring_valid flag is set. */ - uint32_t min_bw_tc7; + uint32_t prod_idx; /* - * Indicates the max bandwidth for all enabled traffic classes in - * this SCHQ, specified in Mbps. + * User defined opaque field to be inserted into VEE_FLUSH completion + * record. This field is valid if virtio_ring_valid flag is set. */ - uint32_t max_bw; - uint8_t unused_1[4]; -} hwrm_ring_schq_cfg_input_t, *phwrm_ring_schq_cfg_input_t; + uint32_t opaque; + uint32_t unused_1; +} hwrm_ring_free_input_t, *phwrm_ring_free_input_t; -/* hwrm_ring_schq_cfg_output (size:128b/16B) */ +/* hwrm_ring_free_output (size:128b/16B) */ -typedef struct hwrm_ring_schq_cfg_output { +typedef struct hwrm_ring_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39288,22 +42408,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_ring_schq_cfg_output_t, *phwrm_ring_schq_cfg_output_t; +} hwrm_ring_free_output_t, *phwrm_ring_free_output_t; -/*********************** - * hwrm_ring_schq_free * - ***********************/ +/******************* + * hwrm_ring_reset * + *******************/ -/* hwrm_ring_schq_free_input (size:192b/24B) */ +/* hwrm_ring_reset_input (size:192b/24B) */ -typedef struct hwrm_ring_schq_free_input { +typedef struct hwrm_ring_reset_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39332,14 +42452,35 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Identifies the SCHQ being freed. */ - uint16_t schq_id; - uint8_t unused_0[6]; -} hwrm_ring_schq_free_input_t, *phwrm_ring_schq_free_input_t; + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* + * Rx Ring Group. This is to reset rx and aggregation in an atomic + * operation. Completion ring associated with this ring group is + * not reset. + */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6) + #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP + uint8_t unused_0; + /* + * Physical number of the ring. When ring type is rx_ring_grp, ring id + * actually refers to ring group id. + */ + uint16_t ring_id; + uint8_t unused_1[4]; +} hwrm_ring_reset_input_t, *phwrm_ring_reset_input_t; -/* hwrm_ring_schq_free_output (size:128b/16B) */ +/* hwrm_ring_reset_output (size:128b/16B) */ -typedef struct hwrm_ring_schq_free_output { +typedef struct hwrm_ring_reset_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39348,46 +42489,37 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * This field will tell whether to use ping or pong buffer + * for first push operation. + */ + uint8_t push_buffer_index; + /* Start push from ping buffer index */ + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER UINT32_C(0x0) + /* Start push from pong buffer index */ + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER UINT32_C(0x1) + #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER + uint8_t unused_0[3]; + /* Position of consumer index after ring reset completes. */ + uint8_t consumer_idx[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_ring_schq_free_output_t, *phwrm_ring_schq_free_output_t; - -/* - * special reserved flow ID to identify per function default - * flows for vSwitch offload - */ -#define DEFAULT_FLOW_ID 0xFFFFFFFFUL -/* - * special reserved flow ID to identify per function RoCEv1 - * flows - */ -#define ROCEV1_FLOW_ID 0xFFFFFFFEUL -/* - * special reserved flow ID to identify per function RoCEv2 - * flows - */ -#define ROCEV2_FLOW_ID 0xFFFFFFFDUL -/* - * special reserved flow ID to identify per function RoCEv2 - * CNP flows - */ -#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL +} hwrm_ring_reset_output_t, *phwrm_ring_reset_output_t; -/**************************** - * hwrm_cfa_l2_filter_alloc * - ****************************/ +/***************** + * hwrm_ring_cfg * + *****************/ -/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ +/* hwrm_ring_cfg_input (size:320b/40B) */ -typedef struct hwrm_cfa_l2_filter_alloc_input { +typedef struct hwrm_ring_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39416,342 +42548,106 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + /* Ring Type. */ + uint8_t ring_type; + /* TX Ring (TR) */ + #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2) + #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST HWRM_RING_CFG_INPUT_RING_TYPE_RX + uint8_t unused_0; + /* Physical number of the ring. */ + uint16_t ring_id; + /* Ring config enable bits. */ + uint16_t enables; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * For Rx rings, the incoming packet data can be placed at either + * a 0B, 2B, 10B or 12B offset from the start of the Rx packet + * buffer. + * When '1', the received packet will be padded with 2B, 10B or 12B + * of zeros at the front of the packet. The exact offset is specified + * by rx_sop_pad_bytes parameter. + * When '0', the received packet will not be padded. + * Note that this flag is only used for Rx rings and is ignored + * for all other rings included Rx Aggregation rings. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX + #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE UINT32_C(0x1) /* - * Setting of this flag indicates the applicability to the loopback - * path. + * Proxy mode enable, for Tx, Rx and Rx aggregation rings only. + * When rings are allocated, the PCI function on which driver issues + * HWRM_RING_CFG command is assumed to own the rings. Hardware takes + * the buffer descriptors (BDs) from those rings is assumed to issue + * packet payload DMA using same PCI function. When proxy mode is + * enabled, hardware can perform payload DMA using another PCI + * function on same or different host. + * When set to '0', the PCI function on which driver issues + * HWRM_RING_CFG command is used for host payload DMA operation. + * When set to '1', the host PCI function specified by proxy_fid is + * used for host payload DMA operation. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x2) + #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE UINT32_C(0x2) /* - * Setting of this flag indicates drop action. If this flag is not - * set, then it should be considered accept action. + * Tx ring packet source interface override, for Tx rings only. + * When TX rings are allocated, the PCI function on which driver + * issues HWRM_RING_CFG is assumed to be source interface of + * packets sent from TX ring. + * When set to '1', the host PCI function specified by proxy_fid + * is used as source interface of the transmitted packets. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x4) + #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE UINT32_C(0x4) + /* The schq_id field is valid */ + #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID UINT32_C(0x8) + /* Update completion ring ID associated with Tx or Rx ring. */ + #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE UINT32_C(0x10) /* - * If this flag is set, all t_l2_* fields are invalid - * and they should not be specified. - * If this flag is set, then l2_* fields refer to - * fields of outermost L2 header. + * When set to '1', metadata value provided by tx_metadata + * field in this command is inserted in the lb_header_metadata + * QP context field. When set to '0', no change done to metadata. + * Firmware rejects the tx ring metadata programming with + * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD + * metadata feature is not disabled. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST UINT32_C(0x8) + #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA UINT32_C(0x20) /* - * Enumeration denoting NO_ROCE_L2 to support old drivers. - * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic + * Proxy function FID value. + * This value is only used when either proxy_mode_enable flag or + * tx_proxy_svif_override is set to '1'. + * When proxy_mode_enable is set to '1', it identifies a host PCI + * function used for host payload DMA operations. + * When tx_proxy_src_intf is set to '1', it identifies a host PCI + * function as source interface for all transmitted packets from + * the TX ring. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK UINT32_C(0x30) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4 - /* To support old drivers */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 (UINT32_C(0x0) << 4) - /* Only L2 traffic */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 (UINT32_C(0x1) << 4) - /* Roce & L2 traffic */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE (UINT32_C(0x2) << 4) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE + uint16_t proxy_fid; /* - * Setting of this flag indicates that no XDP filter is created with - * L2 filter. - * 0 - legacy behavior, XDP filter is created with L2 filter - * 1 - XDP filter won't be created with L2 filter + * Identifies the new scheduler queue (SCHQ) to associate with the + * ring. Only valid for Tx rings. + * A value of zero indicates that the Tx ring should be associated + * with the default scheduler queue (SCHQ). */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE UINT32_C(0x40) + uint16_t schq_id; /* - * Setting this flag to 1 indicate the L2 fields in this command - * pertain to source fields. Setting this flag to 0 indicate the - * L2 fields in this command pertain to the destination fields - * and this is the default/legacy behavior. + * This field is valid for TX or Rx rings. This value identifies the + * new completion ring ID to associate with the TX or Rx ring. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID UINT32_C(0x80) - uint32_t enables; + uint16_t cmpl_ring_id; /* - * This bit must be '1' for the l2_addr field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x1) - /* - * This bit must be '1' for the l2_addr_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK UINT32_C(0x2) - /* - * This bit must be '1' for the l2_ovlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN UINT32_C(0x4) - /* - * This bit must be '1' for the l2_ovlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK UINT32_C(0x8) - /* - * This bit must be '1' for the l2_ivlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x10) - /* - * This bit must be '1' for the l2_ivlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK UINT32_C(0x20) - /* - * This bit must be '1' for the t_l2_addr field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR UINT32_C(0x40) - /* - * This bit must be '1' for the t_l2_addr_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK UINT32_C(0x80) - /* - * This bit must be '1' for the t_l2_ovlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN UINT32_C(0x100) - /* - * This bit must be '1' for the t_l2_ovlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK UINT32_C(0x200) - /* - * This bit must be '1' for the t_l2_ivlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN UINT32_C(0x400) - /* - * This bit must be '1' for the t_l2_ivlan_mask field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK UINT32_C(0x800) - /* - * This bit must be '1' for the src_type field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE UINT32_C(0x1000) - /* - * This bit must be '1' for the src_id field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID UINT32_C(0x2000) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4000) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000) - /* - * This bit must be '1' for the num_vlans field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS UINT32_C(0x20000) - /* - * This bit must be '1' for the t_num_vlans field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS UINT32_C(0x40000) - /* - * This value sets the match value for the L2 MAC address. - * Destination MAC address for RX path. - * Source MAC address for TX path. - */ - uint8_t l2_addr[6]; - /* This value sets the match value for the number of VLANs. */ - uint8_t num_vlans; - /* - * This value sets the match value for the number of VLANs - * in the tunnel headers. - */ - uint8_t t_num_vlans; - /* - * This value sets the mask value for the L2 address. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint8_t l2_addr_mask[6]; - /* This value sets VLAN ID value for outer VLAN. */ - uint16_t l2_ovlan; - /* - * This value sets the mask value for the ovlan id. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint16_t l2_ovlan_mask; - /* This value sets VLAN ID value for inner VLAN. */ - uint16_t l2_ivlan; - /* - * This value sets the mask value for the ivlan id. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint16_t l2_ivlan_mask; - uint8_t unused_1[2]; - /* - * This value sets the match value for the tunnel - * L2 MAC address. - * Destination MAC address for RX path. - * Source MAC address for TX path. - */ - uint8_t t_l2_addr[6]; - uint8_t unused_2[2]; - /* - * This value sets the mask value for the tunnel L2 - * address. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint8_t t_l2_addr_mask[6]; - /* This value sets VLAN ID value for tunnel outer VLAN. */ - uint16_t t_l2_ovlan; - /* - * This value sets the mask value for the tunnel ovlan id. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint16_t t_l2_ovlan_mask; - /* This value sets VLAN ID value for tunnel inner VLAN. */ - uint16_t t_l2_ivlan; - /* - * This value sets the mask value for the tunnel ivlan id. - * A value of 0 will mask the corresponding bit from - * compare. - */ - uint16_t t_l2_ivlan_mask; - /* This value identifies the type of source of the packet. */ - uint8_t src_type; - /* Network port */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0) - /* Physical function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1) - /* Virtual function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2) - /* Virtual NIC of a function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3) - /* Embedded processor for CFA management */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4) - /* Embedded processor for OOB management */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5) - /* Embedded processor for RoCE */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6) - /* Embedded processor for network proxy functions */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG - uint8_t unused_3; - /* - * This value is the id of the source. - * For a network port, it represents port_id. - * For a physical function, it represents fid. - * For a virtual function, it represents vf_id. - * For a vnic, it represents vnic_id. - * For embedded processors, this id is not valid. - * - * Notes: - * 1. The function ID is implied if it src_id is - * not provided for a src_type that is either - */ - uint32_t src_id; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) - /* - * Enhance Generic Routing Encapsulation (GRE version 1) inside IP - * datagram payload - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) - /* - * IPV6 over virtual eXtensible Local Area Network with GPE header - * (IPV6oVXLANGPE) - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - /* Any tunneled traffic */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_4; - /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. - */ - uint16_t dst_id; - /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. - */ - uint16_t mirror_vnic_id; - /* - * This hint is provided to help in placing - * the filter in the filter table. + * Rx SOP padding amount in bytes. + * This value is only used when rx_sop_pad_enable flag is set to '1'. */ - uint8_t pri_hint; - /* No preference */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0) - /* Above the given filter */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER UINT32_C(0x1) - /* Below the given filter */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER UINT32_C(0x2) - /* As high as possible */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX UINT32_C(0x3) - /* As low as possible */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN UINT32_C(0x4) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN - uint8_t unused_5; - uint32_t unused_6; + uint8_t rx_sop_pad_bytes; + uint8_t unused_1[3]; /* - * This is the ID of the filter that goes along with - * the pri_hint. - * - * This field is valid only for the following values. - * 1 - Above the given filter - * 2 - Below the given filter + * When tx_metadata enable bit is set, value specified in this field + * is copied to lb_header_metadata in the QP context. */ - uint64_t l2_filter_id_hint; -} hwrm_cfa_l2_filter_alloc_input_t, *phwrm_cfa_l2_filter_alloc_input_t; + uint32_t tx_metadata; + uint8_t unused_2[4]; +} hwrm_ring_cfg_input_t, *phwrm_ring_cfg_input_t; -/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ +/* hwrm_ring_cfg_output (size:128b/16B) */ -typedef struct hwrm_cfa_l2_filter_alloc_output { +typedef struct hwrm_ring_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39760,43 +42656,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. - */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) - /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) - /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -39806,16 +42666,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_l2_filter_alloc_output_t, *phwrm_cfa_l2_filter_alloc_output_t; +} hwrm_ring_cfg_output_t, *phwrm_ring_cfg_output_t; -/*************************** - * hwrm_cfa_l2_filter_free * - ***************************/ +/****************** + * hwrm_ring_qcfg * + ******************/ -/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ +/* hwrm_ring_qcfg_input (size:192b/24B) */ -typedef struct hwrm_cfa_l2_filter_free_input { +typedef struct hwrm_ring_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39844,16 +42704,21 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; -} hwrm_cfa_l2_filter_free_input_t, *phwrm_cfa_l2_filter_free_input_t; + /* Ring Type. */ + uint8_t ring_type; + /* TX Ring (TR) */ + #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2) + #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST HWRM_RING_QCFG_INPUT_RING_TYPE_RX + uint8_t unused_0[5]; + /* Physical number of the ring. */ + uint16_t ring_id; +} hwrm_ring_qcfg_input_t, *phwrm_ring_qcfg_input_t; -/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ +/* hwrm_ring_qcfg_output (size:256b/32B) */ -typedef struct hwrm_cfa_l2_filter_free_output { +typedef struct hwrm_ring_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -39862,7 +42727,76 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Ring config enable bits. */ + uint16_t enables; + /* + * For Rx rings, the incoming packet data can be placed at either + * a 0B, 2B, 10B or 12B offset from the start of the Rx packet + * buffer. + * When '1', the received packet will be padded with 2B, 10B or 12B + * of zeros at the front of the packet. The exact offset is specified + * by rx_sop_pad_bytes parameter. + * When '0', the received packet will not be padded. + * Note that this flag is only used for Rx rings and is ignored + * for all other rings included Rx Aggregation rings. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE UINT32_C(0x1) + /* + * Proxy mode enable, for Tx, Rx and Rx aggregation rings only. + * When rings are allocated, the PCI function on which driver issues + * HWRM_RING_CFG command is assumed to own the rings. Hardware takes + * the buffer descriptors (BDs) from those rings is assumed to issue + * packet payload DMA using same PCI function. When proxy mode is + * enabled, hardware can perform payload DMA using another PCI + * function on same or different host. + * When set to '0', the PCI function on which driver issues + * HWRM_RING_CFG command is used for host payload DMA operation. + * When set to '1', the host PCI function specified by proxy_fid is + * used for host payload DMA operation. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE UINT32_C(0x2) + /* + * Tx ring packet source interface override, for Tx rings only. + * When TX rings are allocated, the PCI function on which driver + * issues HWRM_RING_CFG is assumed to be source interface of + * packets sent from TX ring. + * When set to '1', the host PCI function specified by proxy_fid is + * used as source interface of the transmitted packets. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE UINT32_C(0x4) + /* + * Proxy function FID value. + * This value is only used when either proxy_mode_enable flag or + * tx_proxy_svif_override is set to '1'. + * When proxy_mode_enable is set to '1', it identifies a host PCI + * function used for host payload DMA operations. + * When tx_proxy_src_intf is set to '1', it identifies a host PCI + * function as source interface for all transmitted packets from the TX + * ring. + */ + uint16_t proxy_fid; + /* + * Identifies the new scheduler queue (SCHQ) to associate with the + * ring. Only valid for Tx rings. + * A value of zero indicates that the Tx ring should be associated with + * the default scheduler queue (SCHQ). + */ + uint16_t schq_id; + /* + * This field is used when ring_type is a TX or Rx ring. + * This value indicates what completion ring the TX or Rx ring + * is associated with. + */ + uint16_t cmpl_ring_id; + /* + * Rx SOP padding amount in bytes. + * This value is only used when rx_sop_pad_enable flag is set to '1'. + */ + uint8_t rx_sop_pad_bytes; + uint8_t unused_0[3]; + /* lb_header_metadata in the QP context is copied to this field. */ + uint32_t tx_metadata; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -39872,16 +42806,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_l2_filter_free_output_t, *phwrm_cfa_l2_filter_free_output_t; +} hwrm_ring_qcfg_output_t, *phwrm_ring_qcfg_output_t; /************************** - * hwrm_cfa_l2_filter_cfg * + * hwrm_ring_aggint_qcaps * **************************/ -/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ +/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ -typedef struct hwrm_cfa_l2_filter_cfg_input { +typedef struct hwrm_ring_aggint_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -39910,97 +42844,236 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; +} hwrm_ring_aggint_qcaps_input_t, *phwrm_ring_aggint_qcaps_input_t; + +/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ + +typedef struct hwrm_ring_aggint_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t cmpl_params; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * When this bit is set to '1', int_lat_tmr_min can be configured + * on completion rings. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN UINT32_C(0x1) /* - * Setting of this flag indicates drop action. If this flag is not - * set, then it should be considered accept action. + * When this bit is set to '1', int_lat_tmr_max can be configured + * on completion rings. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2) + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX UINT32_C(0x2) /* - * Enumeration denoting NO_ROCE_L2 to support old drivers. - * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic + * When this bit is set to '1', timer_reset can be enabled + * on completion rings. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK UINT32_C(0xc) - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2 - /* To support old drivers */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 (UINT32_C(0x0) << 2) - /* Only L2 traffic */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 (UINT32_C(0x1) << 2) - /* Roce & L2 traffic */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE (UINT32_C(0x2) << 2) - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE - uint32_t enables; + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET UINT32_C(0x4) /* - * This bit must be '1' for the dst_id field to be - * configured. + * When this bit is set to '1', ring_idle can be enabled + * on completion rings. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID UINT32_C(0x1) + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE UINT32_C(0x8) /* - * This bit must be '1' for the new_mirror_vnic_id field to be - * configured. + * When this bit is set to '1', num_cmpl_dma_aggr can be configured + * on completion rings. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2) + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR UINT32_C(0x10) /* - * This value identifies a set of CFA data structures used for an L2 - * context. + * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be + * configured on completion rings. */ - uint64_t l2_filter_id; + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT UINT32_C(0x20) /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. + * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured + * on completion rings. */ - uint32_t dst_id; + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR UINT32_C(0x40) /* - * New Logical VNIC ID of the VNIC where traffic is - * mirrored. + * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be + * configured on completion rings. */ - uint32_t new_mirror_vnic_id; -} hwrm_cfa_l2_filter_cfg_input_t, *phwrm_cfa_l2_filter_cfg_input_t; - -/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ - -typedef struct hwrm_cfa_l2_filter_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT UINT32_C(0x80) + /* + * When this bit is set to '1', num_cmpl_aggr_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT UINT32_C(0x100) + uint32_t nq_params; + /* + * When this bit is set to '1', int_lat_tmr_min can be configured + * on notification queues. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN UINT32_C(0x1) + /* Minimum value for num_cmpl_dma_aggr */ + uint16_t num_cmpl_dma_aggr_min; + /* Maximum value for num_cmpl_dma_aggr */ + uint16_t num_cmpl_dma_aggr_max; + /* Minimum value for num_cmpl_dma_aggr_during_int */ + uint16_t num_cmpl_dma_aggr_during_int_min; + /* Maximum value for num_cmpl_dma_aggr_during_int */ + uint16_t num_cmpl_dma_aggr_during_int_max; + /* Minimum value for cmpl_aggr_dma_tmr */ + uint16_t cmpl_aggr_dma_tmr_min; + /* Maximum value for cmpl_aggr_dma_tmr */ + uint16_t cmpl_aggr_dma_tmr_max; + /* Minimum value for cmpl_aggr_dma_tmr_during_int */ + uint16_t cmpl_aggr_dma_tmr_during_int_min; + /* Maximum value for cmpl_aggr_dma_tmr_during_int */ + uint16_t cmpl_aggr_dma_tmr_during_int_max; + /* Minimum value for int_lat_tmr_min */ + uint16_t int_lat_tmr_min_min; + /* Maximum value for int_lat_tmr_min */ + uint16_t int_lat_tmr_min_max; + /* Minimum value for int_lat_tmr_max */ + uint16_t int_lat_tmr_max_min; + /* Maximum value for int_lat_tmr_max */ + uint16_t int_lat_tmr_max_max; + /* Minimum value for num_cmpl_aggr_int */ + uint16_t num_cmpl_aggr_int_min; + /* Maximum value for num_cmpl_aggr_int */ + uint16_t num_cmpl_aggr_int_max; + /* The units for timer parameters, in nanoseconds. */ + uint16_t timer_units; + uint8_t unused_0[1]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_ring_aggint_qcaps_output_t, *phwrm_ring_aggint_qcaps_output_t; + +/************************************** + * hwrm_ring_cmpl_ring_qaggint_params * + **************************************/ + + +/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ + +typedef struct hwrm_ring_cmpl_ring_qaggint_params_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Physical number of completion ring. */ + uint16_t ring_id; + uint16_t flags; + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK UINT32_C(0x3) + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0 + /* + * Set this flag to 1 when querying parameters on a notification + * queue. Set this flag to 0 when querying parameters on a + * completion queue or completion ring. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ UINT32_C(0x4) + uint8_t unused_0[4]; +} hwrm_ring_cmpl_ring_qaggint_params_input_t, *phwrm_ring_cmpl_ring_qaggint_params_input_t; + +/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ + +typedef struct hwrm_ring_cmpl_ring_qaggint_params_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + uint16_t flags; + /* + * When this bit is set to '1', interrupt max + * timer is reset whenever a completion is received. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET UINT32_C(0x1) + /* + * When this bit is set to '1', ring idle mode + * aggregation will be enabled. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE UINT32_C(0x2) + /* + * Number of completions to aggregate before DMA + * during the normal mode. + */ + uint16_t num_cmpl_dma_aggr; + /* + * Number of completions to aggregate before DMA + * during the interrupt mode. + */ + uint16_t num_cmpl_dma_aggr_during_int; + /* + * Timer used to aggregate completions before + * DMA during the normal mode (not in interrupt mode). + */ + uint16_t cmpl_aggr_dma_tmr; + /* + * Timer used to aggregate completions before + * DMA when in interrupt mode. + */ + uint16_t cmpl_aggr_dma_tmr_during_int; + /* Minimum time between two interrupts. */ + uint16_t int_lat_tmr_min; + /* + * Maximum wait time spent aggregating + * completions before signaling the interrupt after the + * interrupt is enabled. + */ + uint16_t int_lat_tmr_max; + /* + * Minimum number of completions aggregated before signaling + * an interrupt. + */ + uint16_t num_cmpl_aggr_int; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_cfa_l2_filter_cfg_output_t, *phwrm_cfa_l2_filter_cfg_output_t; +} hwrm_ring_cmpl_ring_qaggint_params_output_t, *phwrm_ring_cmpl_ring_qaggint_params_output_t; -/*************************** - * hwrm_cfa_l2_set_rx_mask * - ***************************/ +/***************************************** + * hwrm_ring_cmpl_ring_cfg_aggint_params * + *****************************************/ -/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ +/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ -typedef struct hwrm_cfa_l2_set_rx_mask_input { +typedef struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40029,127 +43102,101 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* VNIC ID */ - uint32_t vnic_id; - uint32_t mask; + /* Physical number of completion ring. */ + uint16_t ring_id; + uint16_t flags; /* - * When this bit is '1', the function is requested to accept - * multi-cast packets specified by the multicast addr table. + * When this bit is set to '1', interrupt latency max + * timer is reset whenever a completion is received. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST UINT32_C(0x2) + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET UINT32_C(0x1) /* - * When this bit is '1', the function is requested to accept - * all multi-cast packets. + * When this bit is set to '1', ring idle mode + * aggregation will be enabled. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST UINT32_C(0x4) + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE UINT32_C(0x2) /* - * When this bit is '1', the function is requested to accept - * broadcast packets. + * Set this flag to 1 when configuring parameters on a + * notification queue. Set this flag to 0 when configuring + * parameters on a completion queue or completion ring. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST UINT32_C(0x8) + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ UINT32_C(0x4) /* - * When this bit is '1', the function is requested to be - * put in the promiscuous mode. - * - * The HWRM should accept any function to set up - * promiscuous mode. - * - * The HWRM shall follow the semantics below for the - * promiscuous mode support. - * # When partitioning is not enabled on a port - * (i.e. single PF on the port), then the PF shall - * be allowed to be in the promiscuous mode. When the - * PF is in the promiscuous mode, then it shall - * receive all host bound traffic on that port. - * # When partitioning is enabled on a port - * (i.e. multiple PFs per port) and a PF on that - * port is in the promiscuous mode, then the PF - * receives all traffic within that partition as - * identified by a unique identifier for the - * PF (e.g. S-Tag). If a unique outer VLAN - * for the PF is specified, then the setting of - * promiscuous mode on that PF shall result in the - * PF receiving all host bound traffic with matching - * outer VLAN. - * # A VF shall can be set in the promiscuous mode. - * In the promiscuous mode, the VF does not receive any - * traffic unless a unique outer VLAN for the - * VF is specified. If a unique outer VLAN - * for the VF is specified, then the setting of - * promiscuous mode on that VF shall result in the - * VF receiving all host bound traffic with the - * matching outer VLAN. - * # The HWRM shall allow the setting of promiscuous - * mode on a function independently from the - * promiscuous mode settings on other functions. + * Number of completions to aggregate before DMA + * during the normal mode. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS UINT32_C(0x10) + uint16_t num_cmpl_dma_aggr; /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for the outermost Layer 2 destination MAC - * address field. + * Number of completions to aggregate before DMA + * during the interrupt mode. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST UINT32_C(0x20) + uint16_t num_cmpl_dma_aggr_during_int; /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for the VLAN-tagged packets that match the - * TPID and VID fields of VLAN tags in the VLAN tag - * table specified in this command. + * Timer used to aggregate completions before + * DMA during the normal mode (not in interrupt mode). */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY UINT32_C(0x40) + uint16_t cmpl_aggr_dma_tmr; /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for non-VLAN tagged packets and VLAN-tagged - * packets that match the TPID and VID fields of VLAN - * tags in the VLAN tag table specified in this command. + * Timer used to aggregate completions before + * DMA while in interrupt mode. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN UINT32_C(0x80) + uint16_t cmpl_aggr_dma_tmr_during_int; + /* Minimum time between two interrupts. */ + uint16_t int_lat_tmr_min; /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for non-VLAN tagged packets and VLAN-tagged - * packets matching any VLAN tag. - * - * If this flag is set, then the HWRM shall ignore - * VLAN tags specified in vlan_tag_tbl. - * - * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan - * flags is set, then the HWRM shall ignore - * VLAN tags specified in vlan_tag_tbl. - * - * The HWRM client shall set at most one flag out of - * vlanonly, vlan_nonvlan, and anyvlan_nonvlan. + * Maximum wait time spent aggregating + * completions before signaling the interrupt after the + * interrupt is enabled. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN UINT32_C(0x100) - /* This is the address for mcast address tbl. */ - uint64_t mc_tbl_addr; + uint16_t int_lat_tmr_max; /* - * This value indicates how many entries in mc_tbl are valid. - * Each entry is 6 bytes. + * Minimum number of completions aggregated before signaling + * an interrupt. */ - uint32_t num_mc_entries; - uint8_t unused_0[4]; + uint16_t num_cmpl_aggr_int; /* - * This is the address for VLAN tag table. - * Each VLAN entry in the table is 4 bytes of a VLAN tag - * including TPID, PCP, DEI, and VID fields in network byte - * order. + * Bitfield that indicates which parameters are to be applied. Only + * required when configuring devices with notification queues, and + * used in that case to set certain parameters on completion queues + * and others on notification queues. */ - uint64_t vlan_tag_tbl_addr; + uint16_t enables; /* - * This value indicates how many entries in vlan_tag_tbl are - * valid. Each entry is 4 bytes. + * This bit must be '1' for the num_cmpl_dma_aggr field to be + * configured. */ - uint32_t num_vlan_tags; - uint8_t unused_1[4]; -} hwrm_cfa_l2_set_rx_mask_input_t, *phwrm_cfa_l2_set_rx_mask_input_t; + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR UINT32_C(0x1) + /* + * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to + * be configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT UINT32_C(0x2) + /* + * This bit must be '1' for the cmpl_aggr_dma_tmr field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR UINT32_C(0x4) + /* + * This bit must be '1' for the int_lat_tmr_min field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN UINT32_C(0x8) + /* + * This bit must be '1' for the int_lat_tmr_max field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX UINT32_C(0x10) + /* + * This bit must be '1' for the num_cmpl_aggr_int field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT UINT32_C(0x20) + uint8_t unused_0[4]; +} hwrm_ring_cmpl_ring_cfg_aggint_params_input_t, *phwrm_ring_cmpl_ring_cfg_aggint_params_input_t; -/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ +/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ -typedef struct hwrm_cfa_l2_set_rx_mask_output { +typedef struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -40162,38 +43209,21 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_cfa_l2_set_rx_mask_output_t, *phwrm_cfa_l2_set_rx_mask_output_t; - -/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ - -typedef struct hwrm_cfa_l2_set_rx_mask_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* Unable to complete operation due to conflict with Ntuple Filter */ - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR UINT32_C(0x1) - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR - uint8_t unused_0[7]; -} hwrm_cfa_l2_set_rx_mask_cmd_err_t, *phwrm_cfa_l2_set_rx_mask_cmd_err_t; +} hwrm_ring_cmpl_ring_cfg_aggint_params_output_t, *phwrm_ring_cmpl_ring_cfg_aggint_params_output_t; -/******************************* - * hwrm_cfa_vlan_antispoof_cfg * - *******************************/ +/*********************** + * hwrm_ring_grp_alloc * + ***********************/ -/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */ +/* hwrm_ring_grp_alloc_input (size:192b/24B) */ -typedef struct hwrm_cfa_vlan_antispoof_cfg_input { +typedef struct hwrm_ring_grp_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40223,27 +43253,31 @@ */ uint64_t resp_addr; /* - * Function ID of the function that is being configured. - * Only valid for a VF FID configured by the PF. + * This value identifies the CR associated with the ring + * group. */ - uint16_t fid; - uint8_t unused_0[2]; - /* Number of VLAN entries in the vlan_tag_mask_tbl. */ - uint32_t num_vlan_entries; + uint16_t cr; /* - * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN - * antispoof table. Each table entry contains the 16-bit TPID - * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask, - * all in network order to match hwrm_cfa_l2_set_rx_mask. - * For an individual VLAN entry, the mask value should be 0xfff - * for the 12-bit VLAN ID. + * This value identifies the main RR associated with the ring + * group. */ - uint64_t vlan_tag_mask_tbl_addr; -} hwrm_cfa_vlan_antispoof_cfg_input_t, *phwrm_cfa_vlan_antispoof_cfg_input_t; + uint16_t rr; + /* + * This value identifies the aggregation RR associated with + * the ring group. If this value is 0xFF... (All Fs), then no + * Aggregation ring will be set. + */ + uint16_t ar; + /* + * This value identifies the statistics context associated + * with the ring group. + */ + uint16_t sc; +} hwrm_ring_grp_alloc_input_t, *phwrm_ring_grp_alloc_input_t; -/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */ +/* hwrm_ring_grp_alloc_output (size:128b/16B) */ -typedef struct hwrm_cfa_vlan_antispoof_cfg_output { +typedef struct hwrm_ring_grp_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -40252,26 +43286,31 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * This is the ring group ID value. Use this value to program + * the default ring group for the VNIC or as table entries + * in an RSS/COS context. + */ + uint32_t ring_group_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_cfa_vlan_antispoof_cfg_output_t, *phwrm_cfa_vlan_antispoof_cfg_output_t; +} hwrm_ring_grp_alloc_output_t, *phwrm_ring_grp_alloc_output_t; -/******************************** - * hwrm_cfa_vlan_antispoof_qcfg * - ********************************/ +/********************** + * hwrm_ring_grp_free * + **********************/ -/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */ +/* hwrm_ring_grp_free_input (size:192b/24B) */ -typedef struct hwrm_cfa_vlan_antispoof_qcfg_input { +typedef struct hwrm_ring_grp_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40300,31 +43339,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being queried. - * Only valid for a VF FID queried by the PF. - */ - uint16_t fid; - uint8_t unused_0[2]; - /* - * Maximum number of VLAN entries the firmware is allowed to DMA - * to vlan_tag_mask_tbl. - */ - uint32_t max_vlan_entries; - /* - * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN - * antispoof table to which firmware will DMA to. Each table - * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only), - * 16-bit VLAN ID, and a 16-bit mask, all in network order to - * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry, - * the mask value should be 0xfff for the 12-bit VLAN ID. - */ - uint64_t vlan_tag_mask_tbl_addr; -} hwrm_cfa_vlan_antispoof_qcfg_input_t, *phwrm_cfa_vlan_antispoof_qcfg_input_t; + /* This is the ring group ID value. */ + uint32_t ring_group_id; + uint8_t unused_0[4]; +} hwrm_ring_grp_free_input_t, *phwrm_ring_grp_free_input_t; -/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */ +/* hwrm_ring_grp_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_vlan_antispoof_qcfg_output { +typedef struct hwrm_ring_grp_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -40333,28 +43355,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */ - uint32_t num_vlan_entries; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_cfa_vlan_antispoof_qcfg_output_t, *phwrm_cfa_vlan_antispoof_qcfg_output_t; +} hwrm_ring_grp_free_output_t, *phwrm_ring_grp_free_output_t; -/******************************** - * hwrm_cfa_tunnel_filter_alloc * - ********************************/ +/************************ + * hwrm_ring_schq_alloc * + ************************/ -/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ +/* hwrm_ring_schq_alloc_input (size:1088b/136B) */ -typedef struct hwrm_cfa_tunnel_filter_alloc_input { +typedef struct hwrm_ring_schq_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40383,202 +43402,417 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * Setting of this flag indicates the applicability to the loopback - * path. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1) uint32_t enables; /* - * This bit must be '1' for the l2_filter_id field to be + * This bit must be '1' for the tqm_ring0 fields to be * configured. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1) /* - * This bit must be '1' for the l2_addr field to be + * This bit must be '1' for the tqm_ring1 fields to be * configured. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2) /* - * This bit must be '1' for the l2_ivlan field to be + * This bit must be '1' for the tqm_ring2 fields to be * configured. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4) /* - * This bit must be '1' for the l3_addr field to be + * This bit must be '1' for the tqm_ring3 fields to be * configured. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR UINT32_C(0x8) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8) /* - * This bit must be '1' for the l3_addr_type field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE UINT32_C(0x10) - /* - * This bit must be '1' for the t_l3_addr_type field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE UINT32_C(0x20) - /* - * This bit must be '1' for the t_l3_addr field to be + * This bit must be '1' for the tqm_ring4 fields to be * configured. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR UINT32_C(0x40) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10) /* - * This bit must be '1' for the tunnel_type field to be + * This bit must be '1' for the tqm_ring5 fields to be * configured. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x80) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20) /* - * This bit must be '1' for the vni field to be + * This bit must be '1' for the tqm_ring6 fields to be * configured. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI UINT32_C(0x100) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40) /* - * This bit must be '1' for the dst_vnic_id field to be + * This bit must be '1' for the tqm_ring7 fields to be * configured. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID UINT32_C(0x200) + #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80) + /* Reserved for future use. */ + uint32_t reserved; + /* TQM ring 0 page size and level. */ + uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; + /* TQM ring 0 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1) /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x400) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 + /* TQM ring 0 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G + /* TQM ring 1 page size and level. */ + uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; + /* TQM ring 1 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1) /* - * This value identifies a set of CFA data structures used for an L2 - * context. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - uint64_t l2_filter_id; + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 + /* TQM ring 1 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G + /* TQM ring 2 page size and level. */ + uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; + /* TQM ring 2 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1) /* - * This value sets the match value for the inner L2 - * MAC address. - * Destination MAC address for RX path. - * Source MAC address for TX path. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - uint8_t l2_addr[6]; + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 + /* TQM ring 2 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G + /* TQM ring 3 page size and level. */ + uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; + /* TQM ring 3 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1) /* - * This value sets VLAN ID value for inner VLAN. - * Only 12-bits of VLAN ID are used in setting the filter. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - uint16_t l2_ivlan; + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 + /* TQM ring 3 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G + /* TQM ring 4 page size and level. */ + uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; + /* TQM ring 4 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1) /* - * The value of inner destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - uint32_t l3_addr[4]; + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 + /* TQM ring 4 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G + /* TQM ring 5 page size and level. */ + uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; + /* TQM ring 5 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1) /* - * The value of tunnel destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - uint32_t t_l3_addr[4]; + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 + /* TQM ring 5 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G + /* TQM ring 6 page size and level. */ + uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; + /* TQM ring 6 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1) /* - * This value indicates the type of inner IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - uint8_t l3_addr_type; + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 + /* TQM ring 6 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G + /* TQM ring 7 page size and level. */ + uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; + /* TQM ring 7 PBL indirect levels. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1) /* - * This value indicates the type of tunnel IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - uint8_t t_l3_addr_type; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 + /* TQM ring 7 page size. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G + /* TQM ring 0 page directory. */ + uint64_t tqm_ring0_page_dir; + /* TQM ring 1 page directory. */ + uint64_t tqm_ring1_page_dir; + /* TQM ring 2 page directory. */ + uint64_t tqm_ring2_page_dir; + /* TQM ring 3 page directory. */ + uint64_t tqm_ring3_page_dir; + /* TQM ring 4 page directory. */ + uint64_t tqm_ring4_page_dir; + /* TQM ring 5 page directory. */ + uint64_t tqm_ring5_page_dir; + /* TQM ring 6 page directory. */ + uint64_t tqm_ring6_page_dir; + /* TQM ring 7 page directory. */ + uint64_t tqm_ring7_page_dir; /* - * Enhance Generic Routing Encapsulation (GRE version 1) inside IP - * datagram payload + * Number of TQM ring 0 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) + uint32_t tqm_ring0_num_entries; /* - * IPV6 over virtual eXtensible Local Area Network with GPE header - * (IPV6oVXLANGPE) + * Number of TQM ring 1 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - /* Any tunneled traffic */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint32_t tqm_ring1_num_entries; /* - * tunnel_flags allows the user to indicate the tunnel tag detection - * for the tunnel type specified in tunnel_type. + * Number of TQM ring 2 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. */ - uint8_t tunnel_flags; + uint32_t tqm_ring2_num_entries; /* - * If the tunnel_type is geneve, then this bit indicates if we - * need to match the geneve OAM packet. - * If the tunnel_type is nvgre or gre, then this bit indicates if - * we need to detect checksum present bit in geneve header. - * If the tunnel_type is mpls, then this bit indicates if we need - * to match mpls packet with explicit IPV4/IPV6 null header. + * Number of TQM ring 3 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR UINT32_C(0x1) + uint32_t tqm_ring3_num_entries; /* - * If the tunnel_type is geneve, then this bit indicates if we - * need to detect the critical option bit set in the oam packet. - * If the tunnel_type is nvgre or gre, then this bit indicates - * if we need to match nvgre packets with key present bit set in - * gre header. - * If the tunnel_type is mpls, then this bit indicates if we - * need to match mpls packet with S bit from inner/second label. + * Number of TQM ring 4 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 UINT32_C(0x2) + uint32_t tqm_ring4_num_entries; /* - * If the tunnel_type is geneve, then this bit indicates if we - * need to match geneve packet with extended header bit set in - * geneve header. - * If the tunnel_type is nvgre or gre, then this bit indicates - * if we need to match nvgre packets with sequence number - * present bit set in gre header. - * If the tunnel_type is mpls, then this bit indicates if we - * need to match mpls packet with S bit from out/first label. + * Number of TQM ring 5 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 UINT32_C(0x4) + uint32_t tqm_ring5_num_entries; /* - * Virtual Network Identifier (VNI). Only valid with - * tunnel_types VXLAN, NVGRE, and Geneve. - * Only lower 24-bits of VNI field are used - * in setting up the filter. + * Number of TQM ring 6 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. */ - uint32_t vni; - /* Logical VNIC ID of the destination VNIC. */ - uint32_t dst_vnic_id; + uint32_t tqm_ring6_num_entries; /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. + * Number of TQM ring 7 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SCHQ and then reallocate it. */ - uint32_t mirror_vnic_id; -} hwrm_cfa_tunnel_filter_alloc_input_t, *phwrm_cfa_tunnel_filter_alloc_input_t; + uint32_t tqm_ring7_num_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t tqm_entry_size; + uint8_t unused_0[6]; +} hwrm_ring_schq_alloc_input_t, *phwrm_ring_schq_alloc_input_t; -/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ +/* hwrm_ring_schq_alloc_output (size:128b/16B) */ -typedef struct hwrm_cfa_tunnel_filter_alloc_output { +typedef struct hwrm_ring_schq_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -40587,59 +43821,31 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint64_t tunnel_filter_id; - /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. - */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) - /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. + * This is an identifier for the SCHQ to be used in other HWRM commands + * that need to reference this SCHQ. This value is greater than zero + * (i.e. a schq_id of zero references the default SCHQ). */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX - uint8_t unused_0[3]; + uint16_t schq_id; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_cfa_tunnel_filter_alloc_output_t, *phwrm_cfa_tunnel_filter_alloc_output_t; +} hwrm_ring_schq_alloc_output_t, *phwrm_ring_schq_alloc_output_t; -/******************************* - * hwrm_cfa_tunnel_filter_free * - *******************************/ +/********************** + * hwrm_ring_schq_cfg * + **********************/ -/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ +/* hwrm_ring_schq_cfg_input (size:768b/96B) */ -typedef struct hwrm_cfa_tunnel_filter_free_input { +typedef struct hwrm_ring_schq_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40668,123 +43874,106 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint64_t tunnel_filter_id; -} hwrm_cfa_tunnel_filter_free_input_t, *phwrm_cfa_tunnel_filter_free_input_t; - -/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ - -typedef struct hwrm_cfa_tunnel_filter_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * Identifies the SCHQ being configured. A schq_id of zero refers to + * the default SCHQ. */ - uint8_t valid; -} hwrm_cfa_tunnel_filter_free_output_t, *phwrm_cfa_tunnel_filter_free_output_t; - -/*************************************** - * hwrm_cfa_redirect_tunnel_type_alloc * - ***************************************/ - - -/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */ - -typedef struct hwrm_cfa_redirect_tunnel_type_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint16_t schq_id; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This field is an 8 bit bitmap that indicates which TCs are enabled + * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents + * traffic class 7. */ - uint16_t cmpl_ring; + uint8_t tc_enabled; + uint8_t unused_0; + uint32_t flags; + /* The tc_max_bw array and the max_bw parameters are valid */ + #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED UINT32_C(0x1) + /* The tc_bw_reservation array is valid */ + #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_RESERVATION_ENABLED UINT32_C(0x2) + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc0; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc1; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc2; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc3; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc4; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc5; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc6; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc7; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Bandwidth reservation for the traffic class, specified in percent. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. */ - uint16_t seq_id; + uint32_t tc_bw_reservation0; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Bandwidth reservation for the traffic class, specified in percent. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. */ - uint16_t target_id; + uint32_t tc_bw_reservation1; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Bandwidth reservation for the traffic class, specified in percent. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. */ - uint64_t resp_addr; - /* The destination function id, to whom the traffic is redirected. */ - uint16_t dest_fid; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + uint32_t tc_bw_reservation2; /* - * Enhance Generic Routing Encapsulation (GRE version 1) inside IP - * datagram payload + * Bandwidth reservation for the traffic class, specified in percent. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) + uint32_t tc_bw_reservation3; /* - * IPV6 over virtual eXtensible Local Area Network with GPE header - * (IPV6oVXLANGPE) + * Bandwidth reservation for the traffic class, specified in percent. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - /* Tunnel alloc flags. */ - uint8_t flags; + uint32_t tc_bw_reservation4; /* - * Setting of this flag indicates modify existing redirect tunnel - * to new destination function ID. + * Bandwidth reservation for the traffic class, specified in percent. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST UINT32_C(0x1) - uint8_t unused_0[4]; -} hwrm_cfa_redirect_tunnel_type_alloc_input_t, *phwrm_cfa_redirect_tunnel_type_alloc_input_t; + uint32_t tc_bw_reservation5; + /* + * Bandwidth reservation for the traffic class, specified in percent. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t tc_bw_reservation6; + /* + * Bandwidth reservation for the traffic class, specified in percent. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SCHQ. + */ + uint32_t tc_bw_reservation7; + /* + * Indicates the max bandwidth for all enabled traffic classes in + * this SCHQ, specified in Mbps. + */ + uint32_t max_bw; + uint8_t unused_1[4]; +} hwrm_ring_schq_cfg_input_t, *phwrm_ring_schq_cfg_input_t; -/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */ +/* hwrm_ring_schq_cfg_output (size:128b/16B) */ -typedef struct hwrm_cfa_redirect_tunnel_type_alloc_output { +typedef struct hwrm_ring_schq_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -40797,22 +43986,21 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_cfa_redirect_tunnel_type_alloc_output_t, *phwrm_cfa_redirect_tunnel_type_alloc_output_t; +} hwrm_ring_schq_cfg_output_t, *phwrm_ring_schq_cfg_output_t; -/************************************** - * hwrm_cfa_redirect_tunnel_type_free * - **************************************/ +/*********************** + * hwrm_ring_schq_free * + ***********************/ -/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */ +/* hwrm_ring_schq_free_input (size:192b/24B) */ -typedef struct hwrm_cfa_redirect_tunnel_type_free_input { +typedef struct hwrm_ring_schq_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40841,53 +44029,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The destination function id, to whom the traffic is redirected. */ - uint16_t dest_fid; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) - /* - * Enhance Generic Routing Encapsulation (GRE version 1) inside IP - * datagram payload - */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) - /* - * IPV6 over virtual eXtensible Local Area Network with GPE header - * (IPV6oVXLANGPE) - */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0[5]; -} hwrm_cfa_redirect_tunnel_type_free_input_t, *phwrm_cfa_redirect_tunnel_type_free_input_t; + /* Identifies the SCHQ being freed. */ + uint16_t schq_id; + uint8_t unused_0[6]; +} hwrm_ring_schq_free_input_t, *phwrm_ring_schq_free_input_t; -/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */ +/* hwrm_ring_schq_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_redirect_tunnel_type_free_output { +typedef struct hwrm_ring_schq_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -40900,22 +44049,42 @@ /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_cfa_redirect_tunnel_type_free_output_t, *phwrm_cfa_redirect_tunnel_type_free_output_t; +} hwrm_ring_schq_free_output_t, *phwrm_ring_schq_free_output_t; -/************************************** - * hwrm_cfa_redirect_tunnel_type_info * - **************************************/ +/* + * special reserved flow ID to identify per function default + * flows for vSwitch offload + */ +#define DEFAULT_FLOW_ID 0xFFFFFFFFUL +/* + * special reserved flow ID to identify per function RoCEv1 + * flows + */ +#define ROCEV1_FLOW_ID 0xFFFFFFFEUL +/* + * special reserved flow ID to identify per function RoCEv2 + * flows + */ +#define ROCEV2_FLOW_ID 0xFFFFFFFDUL +/* + * special reserved flow ID to identify per function RoCEv2 + * CNP flows + */ +#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL +/**************************** + * hwrm_cfa_l2_filter_alloc * + ****************************/ -/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */ -typedef struct hwrm_cfa_redirect_tunnel_type_info_input { +/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ + +typedef struct hwrm_cfa_l2_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -40944,271 +44113,342 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The source function id. */ - uint16_t src_fid; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + uint32_t flags; /* - * Enhance Generic Routing Encapsulation (GRE version 1) inside IP - * datagram payload + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX /* - * IPV6 over virtual eXtensible Local Area Network with GPE header - * (IPV6oVXLANGPE) + * Setting of this flag indicates the applicability to the loopback + * path. */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0[5]; -} hwrm_cfa_redirect_tunnel_type_info_input_t, *phwrm_cfa_redirect_tunnel_type_info_input_t; - -/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */ - -typedef struct hwrm_cfa_redirect_tunnel_type_info_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* The destination function id, to whom the traffic is redirected. */ - uint16_t dest_fid; - uint8_t unused_0[5]; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x2) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ - uint8_t valid; -} hwrm_cfa_redirect_tunnel_type_info_output_t, *phwrm_cfa_redirect_tunnel_type_info_output_t; - -/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ - -typedef struct hwrm_vxlan_ipv4_hdr { - /* IPv4 version and header length. */ - uint8_t ver_hlen; - /* IPv4 header length */ - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf) - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 - /* Version */ - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0) - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 - /* IPv4 type of service. */ - uint8_t tos; - /* IPv4 identification. */ - uint16_t ip_id; - /* IPv4 flags and offset. */ - uint16_t flags_frag_offset; - /* IPv4 TTL. */ - uint8_t ttl; - /* IPv4 protocol. */ - uint8_t protocol; - /* IPv4 source address. */ - uint32_t src_ip_addr; - /* IPv4 destination address. */ - uint32_t dest_ip_addr; -} hwrm_vxlan_ipv4_hdr_t, *phwrm_vxlan_ipv4_hdr_t; - -/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ - -typedef struct hwrm_vxlan_ipv6_hdr { - /* IPv6 version, traffic class and flow label. */ - uint32_t ver_tc_flow_label; - /* IPv6 version shift */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT UINT32_C(0x1c) - /* IPv6 version mask */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK UINT32_C(0xf0000000) - /* IPv6 TC shift */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT UINT32_C(0x14) - /* IPv6 TC mask */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK UINT32_C(0xff00000) - /* IPv6 flow label shift */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT UINT32_C(0x0) - /* IPv6 flow label mask */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK UINT32_C(0xfffff) - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK - /* IPv6 payload length. */ - uint16_t payload_len; - /* IPv6 next header. */ - uint8_t next_hdr; - /* IPv6 TTL. */ - uint8_t ttl; - /* IPv6 source address. */ - uint32_t src_ip_addr[4]; - /* IPv6 destination address. */ - uint32_t dest_ip_addr[4]; -} hwrm_vxlan_ipv6_hdr_t, *phwrm_vxlan_ipv6_hdr_t; - -/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ - -typedef struct hwrm_cfa_encap_data_vxlan { - /* Source MAC address. */ - uint8_t src_mac_addr[6]; - /* reserved. */ - uint16_t unused_0; - /* Destination MAC address. */ - uint8_t dst_mac_addr[6]; - /* Number of VLAN tags. */ - uint8_t num_vlan_tags; - /* reserved. */ - uint8_t unused_1; - /* Outer VLAN TPID. */ - uint16_t ovlan_tpid; - /* Outer VLAN TCI. */ - uint16_t ovlan_tci; - /* Inner VLAN TPID. */ - uint16_t ivlan_tpid; - /* Inner VLAN TCI. */ - uint16_t ivlan_tci; - /* L3 header fields. */ - uint32_t l3[10]; - /* IP version mask. */ - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf) - /* IP version 4. */ - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4) - /* IP version 6. */ - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6) - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 - /* UDP source port. */ - uint16_t src_port; - /* UDP destination port. */ - uint16_t dst_port; - /* VXLAN Network Identifier. */ - uint32_t vni; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x4) /* - * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN - * header. + * If this flag is set, all t_l2_* fields are invalid + * and they should not be specified. + * If this flag is set, then l2_* fields refer to + * fields of outermost L2 header. */ - uint8_t hdr_rsvd0[3]; - /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */ - uint8_t hdr_rsvd1; - /* VXLAN header flags field. */ - uint8_t hdr_flags; - uint8_t unused[3]; -} hwrm_cfa_encap_data_vxlan_t, *phwrm_cfa_encap_data_vxlan_t; - -/******************************* - * hwrm_cfa_encap_record_alloc * - *******************************/ - - -/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ - -typedef struct hwrm_cfa_encap_record_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST UINT32_C(0x8) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Enumeration denoting NO_ROCE_L2 to support old drivers. + * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic */ - uint16_t cmpl_ring; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK UINT32_C(0x30) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4 + /* To support old drivers */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 (UINT32_C(0x0) << 4) + /* Only L2 traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 (UINT32_C(0x1) << 4) + /* Roce & L2 traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE (UINT32_C(0x2) << 4) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Setting of this flag indicates that no XDP filter is created with + * L2 filter. + * 0 - legacy behavior, XDP filter is created with L2 filter + * 1 - XDP filter won't be created with L2 filter */ - uint16_t seq_id; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE UINT32_C(0x40) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Setting this flag to 1 indicate the L2 fields in this command + * pertain to source fields. Setting this flag to 0 indicate the + * L2 fields in this command pertain to the destination fields + * and this is the default/legacy behavior. */ - uint16_t target_id; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID UINT32_C(0x80) + uint32_t enables; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This bit must be '1' for the l2_addr field to be + * configured. */ - uint64_t resp_addr; - uint32_t flags; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x1) /* - * Setting of this flag indicates the applicability to the loopback - * path. + * This bit must be '1' for the l2_addr_mask field to be + * configured. */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK UINT32_C(0x2) /* - * Setting of this flag indicates this encap record is external - * encap record. Resetting of this flag indicates this flag is - * internal encap record and this is the default setting. + * This bit must be '1' for the l2_ovlan field to be + * configured. */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL UINT32_C(0x2) - /* Encapsulation Type. */ - uint8_t encap_type; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN UINT32_C(0x4) + /* + * This bit must be '1' for the l2_ovlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK UINT32_C(0x8) + /* + * This bit must be '1' for the l2_ivlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x10) + /* + * This bit must be '1' for the l2_ivlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK UINT32_C(0x20) + /* + * This bit must be '1' for the t_l2_addr field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR UINT32_C(0x40) + /* + * This bit must be '1' for the t_l2_addr_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK UINT32_C(0x80) + /* + * This bit must be '1' for the t_l2_ovlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN UINT32_C(0x100) + /* + * This bit must be '1' for the t_l2_ovlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK UINT32_C(0x200) + /* + * This bit must be '1' for the t_l2_ivlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN UINT32_C(0x400) + /* + * This bit must be '1' for the t_l2_ivlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK UINT32_C(0x800) + /* + * This bit must be '1' for the src_type field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE UINT32_C(0x1000) + /* + * This bit must be '1' for the src_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID UINT32_C(0x2000) + /* + * This bit must be '1' for the tunnel_type field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4000) + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000) + /* + * This bit must be '1' for the num_vlans field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS UINT32_C(0x20000) + /* + * This bit must be '1' for the t_num_vlans field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS UINT32_C(0x40000) + /* + * This value sets the match value for the L2 MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. + */ + uint8_t l2_addr[6]; + /* This value sets the match value for the number of VLANs. */ + uint8_t num_vlans; + /* + * This value sets the match value for the number of VLANs + * in the tunnel headers. + */ + uint8_t t_num_vlans; + /* + * This value sets the mask value for the L2 address. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint8_t l2_addr_mask[6]; + /* This value sets VLAN ID value for outer VLAN. */ + uint16_t l2_ovlan; + /* + * This value sets the mask value for the ovlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t l2_ovlan_mask; + /* This value sets VLAN ID value for inner VLAN. */ + uint16_t l2_ivlan; + /* + * This value sets the mask value for the ivlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t l2_ivlan_mask; + uint8_t unused_1[2]; + /* + * This value sets the match value for the tunnel + * L2 MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. + */ + uint8_t t_l2_addr[6]; + uint8_t unused_2[2]; + /* + * This value sets the mask value for the tunnel L2 + * address. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint8_t t_l2_addr_mask[6]; + /* This value sets VLAN ID value for tunnel outer VLAN. */ + uint16_t t_l2_ovlan; + /* + * This value sets the mask value for the tunnel ovlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t t_l2_ovlan_mask; + /* This value sets VLAN ID value for tunnel inner VLAN. */ + uint16_t t_l2_ivlan; + /* + * This value sets the mask value for the tunnel ivlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t t_l2_ivlan_mask; + /* This value identifies the type of source of the packet. */ + uint8_t src_type; + /* Network port */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0) + /* Physical function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1) + /* Virtual function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2) + /* Virtual NIC of a function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3) + /* Embedded processor for CFA management */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4) + /* Embedded processor for OOB management */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5) + /* Embedded processor for RoCE */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6) + /* Embedded processor for network proxy functions */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG + uint8_t unused_3; + /* + * This value is the id of the source. + * For a network port, it represents port_id. + * For a physical function, it represents fid. + * For a virtual function, it represents vf_id. + * For a vnic, it represents vnic_id. + * For embedded processors, this id is not valid. + * + * Notes: + * 1. The function ID is implied if it src_id is + * not provided for a src_type that is either + */ + uint32_t src_id; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE UINT32_C(0x3) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) /* IP in IP */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP UINT32_C(0x4) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE UINT32_C(0x5) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS UINT32_C(0x6) - /* VLAN */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN UINT32_C(0x7) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE UINT32_C(0x8) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) /* * Enhance Generic Routing Encapsulation (GRE version 1) inside IP * datagram payload */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) /* * IPV6 over virtual eXtensible Local Area Network with GPE header * (IPV6oVXLANGPE) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE UINT32_C(0x10) - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE - uint8_t unused_0[3]; - /* This value is encap data used for the given encap type. */ - uint32_t encap_data[20]; -} hwrm_cfa_encap_record_alloc_input_t, *phwrm_cfa_encap_record_alloc_input_t; + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + /* Any tunneled traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_4; + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. + */ + uint16_t dst_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint16_t mirror_vnic_id; + /* + * This hint is provided to help in placing + * the filter in the filter table. + */ + uint8_t pri_hint; + /* No preference */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0) + /* Above the given filter */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER UINT32_C(0x1) + /* Below the given filter */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER UINT32_C(0x2) + /* As high as possible */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX UINT32_C(0x3) + /* As low as possible */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN UINT32_C(0x4) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN + uint8_t unused_5; + uint32_t unused_6; + /* + * This is the ID of the filter that goes along with + * the pri_hint. + * + * This field is valid only for the following values. + * 1 - Above the given filter + * 2 - Below the given filter + */ + uint64_t l2_filter_id_hint; +} hwrm_cfa_l2_filter_alloc_input_t, *phwrm_cfa_l2_filter_alloc_input_t; -/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ +/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ -typedef struct hwrm_cfa_encap_record_alloc_output { +typedef struct hwrm_cfa_l2_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41217,8 +44457,42 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint32_t encap_record_id; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -41229,16 +44503,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_encap_record_alloc_output_t, *phwrm_cfa_encap_record_alloc_output_t; +} hwrm_cfa_l2_filter_alloc_output_t, *phwrm_cfa_l2_filter_alloc_output_t; -/****************************** - * hwrm_cfa_encap_record_free * - ******************************/ +/*************************** + * hwrm_cfa_l2_filter_free * + ***************************/ -/* hwrm_cfa_encap_record_free_input (size:192b/24B) */ +/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ -typedef struct hwrm_cfa_encap_record_free_input { +typedef struct hwrm_cfa_l2_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -41267,14 +44541,16 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint32_t encap_record_id; - uint8_t unused_0[4]; -} hwrm_cfa_encap_record_free_input_t, *phwrm_cfa_encap_record_free_input_t; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; +} hwrm_cfa_l2_filter_free_input_t, *phwrm_cfa_l2_filter_free_input_t; -/* hwrm_cfa_encap_record_free_output (size:128b/16B) */ +/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_encap_record_free_output { +typedef struct hwrm_cfa_l2_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41293,16 +44569,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_encap_record_free_output_t, *phwrm_cfa_encap_record_free_output_t; +} hwrm_cfa_l2_filter_free_output_t, *phwrm_cfa_l2_filter_free_output_t; -/******************************** - * hwrm_cfa_ntuple_filter_alloc * - ********************************/ +/************************** + * hwrm_cfa_l2_filter_cfg * + **************************/ -/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ +/* hwrm_cfa_l2_filter_cfg_input (size:384b/48B) */ -typedef struct hwrm_cfa_ntuple_filter_alloc_input { +typedef struct hwrm_cfa_l2_filter_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -41333,321 +44609,279 @@ uint64_t resp_addr; uint32_t flags; /* - * Setting of this flag indicates the applicability to the loopback - * path. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX /* * Setting of this flag indicates drop action. If this flag is not * set, then it should be considered accept action. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x2) - /* - * Setting of this flag indicates that a meter is expected to be - * attached to this flow. This hint can be used when choosing the - * action record format required for the flow. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER UINT32_C(0x4) - /* - * Setting of this flag indicates that the dst_id field contains - * function ID. If this is not set it indicates dest_id is VNIC - * or VPORT. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID UINT32_C(0x8) - /* - * Setting of this flag indicates match on arp reply when ethertype - * is 0x0806. If this is not set it indicates no specific arp opcode - * matching. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY UINT32_C(0x10) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2) /* - * Setting of this flag indicates that the dst_id field contains RFS - * ring table index. If this is not set it indicates dst_id is VNIC - * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx - * can’t be set at the same time. + * Enumeration denoting NO_ROCE_L2 to support old drivers. + * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX UINT32_C(0x20) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK UINT32_C(0xc) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2 + /* To support old drivers */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 (UINT32_C(0x0) << 2) + /* Only L2 traffic */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 (UINT32_C(0x1) << 2) + /* Roce & L2 traffic */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE (UINT32_C(0x2) << 2) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE /* - * Setting of this flag indicates that when the ntuple filter is - * created, the L2 context should not be used in the filter. This - * allows packet from different L2 contexts to match and be directed - * to the same destination. + * Enumeration denoting how the L2 Context TCAM remap operation is + * updated. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT UINT32_C(0x40) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_MASK UINT32_C(0x30) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_SFT 4 + /* No change to remap opcode */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_NO_UPDATE (UINT32_C(0x0) << 4) + /* Bypass CFA Lookup */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_BYPASS_LKUP (UINT32_C(0x1) << 4) + /* Enable CFA Lookup */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_ENABLE_LKUP (UINT32_C(0x2) << 4) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_LAST HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_ENABLE_LKUP uint32_t enables; /* - * This bit must be '1' for the l2_filter_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) - /* - * This bit must be '1' for the ethertype field to be + * This bit must be '1' for the dst_id field to be * configured. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID UINT32_C(0x1) /* - * This bit must be '1' for the tunnel_type field to be + * This bit must be '1' for the new_mirror_vnic_id field to be * configured. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2) /* - * This bit must be '1' for the src_macaddr field to be - * configured. + * This bit must be '1' for the prof_func field to be configured in + * the remap entry. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_PROF_FUNC UINT32_C(0x4) /* - * This bit must be '1' for the ipaddr_type field to be - * configured. + * This bit must be '1' for the l2_context_id field to be configured + * in the remap entry. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x10) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_L2_CONTEXT_ID UINT32_C(0x8) /* - * This bit must be '1' for the src_ipaddr field to be - * configured. + * This value identifies a set of CFA data structures used for an L2 + * context. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x20) + uint64_t l2_filter_id; /* - * This bit must be '1' for the src_ipaddr_mask field to be - * configured. + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK UINT32_C(0x40) + uint32_t dst_id; /* - * This bit must be '1' for the dst_ipaddr field to be - * configured. + * New Logical VNIC ID of the VNIC where traffic is + * mirrored. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x80) + uint32_t new_mirror_vnic_id; /* - * This bit must be '1' for the dst_ipaddr_mask field to be - * configured. + * Profile function value to be programmed into the L2 context entry's + * remap. This will be used by the host application to program the CFA + * Profile TCAM entry for further classification. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK UINT32_C(0x100) + uint32_t prof_func; /* - * This bit must be '1' for the ip_protocol field to be - * configured. + * L2 context ID value to be programmed into the L2 context entry's + * remap. This will be used by the host application to program the CFA + * Lookup entry for further classification. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x200) + uint32_t l2_context_id; +} hwrm_cfa_l2_filter_cfg_input_t, *phwrm_cfa_l2_filter_cfg_input_t; + +/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ + +typedef struct hwrm_cfa_l2_filter_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This bit must be '1' for the src_port field to be - * configured. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x400) + uint8_t valid; +} hwrm_cfa_l2_filter_cfg_output_t, *phwrm_cfa_l2_filter_cfg_output_t; + +/*************************** + * hwrm_cfa_l2_set_rx_mask * + ***************************/ + + +/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ + +typedef struct hwrm_cfa_l2_set_rx_mask_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This bit must be '1' for the src_port_mask field to be - * configured. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK UINT32_C(0x800) + uint16_t cmpl_ring; /* - * This bit must be '1' for the dst_port field to be - * configured. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x1000) + uint16_t seq_id; /* - * This bit must be '1' for the dst_port_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK UINT32_C(0x2000) - /* - * This bit must be '1' for the pri_hint field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT UINT32_C(0x4000) - /* - * This bit must be '1' for the ntuple_filter_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID UINT32_C(0x8000) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x10000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x20000) - /* - * This bit must be '1' for the dst_macaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x40000) - /* This flag is deprecated. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX UINT32_C(0x80000) - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* - * This value indicates the source MAC address in - * the Ethernet header. - */ - uint8_t src_macaddr[6]; - /* This value indicates the ethertype in the Ethernet header. */ - uint16_t ethertype; - /* - * This value indicates the type of IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. - */ - uint8_t ip_addr_type; - /* invalid */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) - /* IPv4 */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) - /* IPv6 */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 - /* - * The value of protocol filed in IP header. - * Applies to UDP and TCP traffic. - * 6 - TCP - * 17 - UDP - * 1 - ICMP - * 58 - ICMPV6 - * 255 - RSVD - */ - uint8_t ip_protocol; - /* invalid */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) - /* TCP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) - /* UDP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) - /* ICMP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMP UINT32_C(0x1) - /* ICMPV6 */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMPV6 UINT32_C(0x3a) - /* RSVD */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD UINT32_C(0xff) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD - /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. - */ - uint16_t dst_id; - /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. - */ - uint16_t mirror_vnic_id; - /* - * This value indicates the tunnel type for this filter. - * If this field is not specified, then the filter shall - * apply to both non-tunneled and tunneled packets. - * If this field conflicts with the tunnel_type specified - * in the l2_filter_id, then the HWRM shall return an - * error for this command. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + uint16_t target_id; /* - * Enhance Generic Routing Encapsulation (GRE version 1) inside IP - * datagram payload + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) + uint64_t resp_addr; + /* VNIC ID */ + uint32_t vnic_id; + uint32_t mask; /* - * IPV6 over virtual eXtensible Local Area Network with GPE header - * (IPV6oVXLANGPE) + * When this bit is '1', the function is requested to accept + * multi-cast packets specified by the multicast addr table. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - /* Any tunneled traffic */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST UINT32_C(0x2) /* - * This hint is provided to help in placing - * the filter in the filter table. + * When this bit is '1', the function is requested to accept + * all multi-cast packets. */ - uint8_t pri_hint; - /* No preference */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0) - /* Above the given filter */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE UINT32_C(0x1) - /* Below the given filter */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW UINT32_C(0x2) - /* As high as possible */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST UINT32_C(0x3) - /* As low as possible */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST UINT32_C(0x4) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST UINT32_C(0x4) /* - * The value of source IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * When this bit is '1', the function is requested to accept + * broadcast packets. */ - uint32_t src_ipaddr[4]; + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST UINT32_C(0x8) /* - * The value of source IP address mask to be used in - * filtering. - * For IPv4, first four bytes represent the IP address mask. + * When this bit is '1', the function is requested to be + * put in the promiscuous mode. + * + * The HWRM should accept any function to set up + * promiscuous mode. + * + * The HWRM shall follow the semantics below for the + * promiscuous mode support. + * # When partitioning is not enabled on a port + * (i.e. single PF on the port), then the PF shall + * be allowed to be in the promiscuous mode. When the + * PF is in the promiscuous mode, then it shall + * receive all host bound traffic on that port. + * # When partitioning is enabled on a port + * (i.e. multiple PFs per port) and a PF on that + * port is in the promiscuous mode, then the PF + * receives all traffic within that partition as + * identified by a unique identifier for the + * PF (e.g. S-Tag). If a unique outer VLAN + * for the PF is specified, then the setting of + * promiscuous mode on that PF shall result in the + * PF receiving all host bound traffic with matching + * outer VLAN. + * # A VF shall can be set in the promiscuous mode. + * In the promiscuous mode, the VF does not receive any + * traffic unless a unique outer VLAN for the + * VF is specified. If a unique outer VLAN + * for the VF is specified, then the setting of + * promiscuous mode on that VF shall result in the + * VF receiving all host bound traffic with the + * matching outer VLAN. + * # The HWRM shall allow the setting of promiscuous + * mode on a function independently from the + * promiscuous mode settings on other functions. */ - uint32_t src_ipaddr_mask[4]; + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS UINT32_C(0x10) /* - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for the outermost Layer 2 destination MAC + * address field. */ - uint32_t dst_ipaddr[4]; + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST UINT32_C(0x20) /* - * The value of destination IP address mask to be used in - * filtering. - * For IPv4, first four bytes represent the IP address mask. + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for the VLAN-tagged packets that match the + * TPID and VID fields of VLAN tags in the VLAN tag + * table specified in this command. */ - uint32_t dst_ipaddr_mask[4]; + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY UINT32_C(0x40) /* - * The value of source port to be used in filtering. - * Applies to UDP and TCP traffic. + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for non-VLAN tagged packets and VLAN-tagged + * packets that match the TPID and VID fields of VLAN + * tags in the VLAN tag table specified in this command. */ - uint16_t src_port; + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN UINT32_C(0x80) /* - * The value of source port mask to be used in filtering. - * Applies to UDP and TCP traffic. + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for non-VLAN tagged packets and VLAN-tagged + * packets matching any VLAN tag. + * + * If this flag is set, then the HWRM shall ignore + * VLAN tags specified in vlan_tag_tbl. + * + * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan + * flags is set, then the HWRM shall ignore + * VLAN tags specified in vlan_tag_tbl. + * + * The HWRM client shall set at most one flag out of + * vlanonly, vlan_nonvlan, and anyvlan_nonvlan. */ - uint16_t src_port_mask; + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN UINT32_C(0x100) + /* This is the address for mcast address tbl. */ + uint64_t mc_tbl_addr; /* - * The value of destination port to be used in filtering. - * Applies to UDP and TCP traffic. + * This value indicates how many entries in mc_tbl are valid. + * Each entry is 6 bytes. */ - uint16_t dst_port; + uint32_t num_mc_entries; + uint8_t unused_0[4]; /* - * The value of destination port mask to be used in - * filtering. - * Applies to UDP and TCP traffic. + * This is the address for VLAN tag table. + * Each VLAN entry in the table is 4 bytes of a VLAN tag + * including TPID, PCP, DEI, and VID fields in network byte + * order. */ - uint16_t dst_port_mask; + uint64_t vlan_tag_tbl_addr; /* - * This is the ID of the filter that goes along with - * the pri_hint. + * This value indicates how many entries in vlan_tag_tbl are + * valid. Each entry is 4 bytes. */ - uint64_t ntuple_filter_id_hint; -} hwrm_cfa_ntuple_filter_alloc_input_t, *phwrm_cfa_ntuple_filter_alloc_input_t; + uint32_t num_vlan_tags; + uint8_t unused_1[4]; +} hwrm_cfa_l2_set_rx_mask_input_t, *phwrm_cfa_l2_set_rx_mask_input_t; -/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ +/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ -typedef struct hwrm_cfa_ntuple_filter_alloc_output { +typedef struct hwrm_cfa_l2_set_rx_mask_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41656,40 +44890,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; - /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. - */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) - /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) - /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -41699,32 +44900,32 @@ * written last. */ uint8_t valid; -} hwrm_cfa_ntuple_filter_alloc_output_t, *phwrm_cfa_ntuple_filter_alloc_output_t; +} hwrm_cfa_l2_set_rx_mask_output_t, *phwrm_cfa_l2_set_rx_mask_output_t; -/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ +/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ -typedef struct hwrm_cfa_ntuple_filter_alloc_cmd_err { +typedef struct hwrm_cfa_l2_set_rx_mask_cmd_err { /* * command specific error codes that goes to * the cmd_err field in Common HWRM Error Response. */ uint8_t code; /* Unknown error */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* Unable to complete operation due to conflict with Rx Mask VLAN */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR UINT32_C(0x1) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Unable to complete operation due to conflict with Ntuple Filter */ + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR UINT32_C(0x1) + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR uint8_t unused_0[7]; -} hwrm_cfa_ntuple_filter_alloc_cmd_err_t, *phwrm_cfa_ntuple_filter_alloc_cmd_err_t; +} hwrm_cfa_l2_set_rx_mask_cmd_err_t, *phwrm_cfa_l2_set_rx_mask_cmd_err_t; /******************************* - * hwrm_cfa_ntuple_filter_free * + * hwrm_cfa_vlan_antispoof_cfg * *******************************/ -/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ +/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */ -typedef struct hwrm_cfa_ntuple_filter_free_input { +typedef struct hwrm_cfa_vlan_antispoof_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -41753,13 +44954,28 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; -} hwrm_cfa_ntuple_filter_free_input_t, *phwrm_cfa_ntuple_filter_free_input_t; + /* + * Function ID of the function that is being configured. + * Only valid for a VF FID configured by the PF. + */ + uint16_t fid; + uint8_t unused_0[2]; + /* Number of VLAN entries in the vlan_tag_mask_tbl. */ + uint32_t num_vlan_entries; + /* + * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN + * antispoof table. Each table entry contains the 16-bit TPID + * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask, + * all in network order to match hwrm_cfa_l2_set_rx_mask. + * For an individual VLAN entry, the mask value should be 0xfff + * for the 12-bit VLAN ID. + */ + uint64_t vlan_tag_mask_tbl_addr; +} hwrm_cfa_vlan_antispoof_cfg_input_t, *phwrm_cfa_vlan_antispoof_cfg_input_t; -/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ +/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */ -typedef struct hwrm_cfa_ntuple_filter_free_output { +typedef struct hwrm_cfa_vlan_antispoof_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41778,16 +44994,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_ntuple_filter_free_output_t, *phwrm_cfa_ntuple_filter_free_output_t; +} hwrm_cfa_vlan_antispoof_cfg_output_t, *phwrm_cfa_vlan_antispoof_cfg_output_t; -/****************************** - * hwrm_cfa_ntuple_filter_cfg * - ******************************/ +/******************************** + * hwrm_cfa_vlan_antispoof_qcfg * + ********************************/ -/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ +/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */ -typedef struct hwrm_cfa_ntuple_filter_cfg_input { +typedef struct hwrm_cfa_vlan_antispoof_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -41816,75 +45032,31 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the new_dst_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1) - /* - * This bit must be '1' for the new_mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2) - /* - * This bit must be '1' for the new_meter_instance_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4) - uint32_t flags; - /* - * Setting this bit to 1 indicates that dest_id field contains FID. - * Setting this to 0 indicates that dest_id field contains VNIC or - * VPORT. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID UINT32_C(0x1) - /* - * Setting of this flag indicates that the new_dst_id field contains - * RFS ring table index. If this is not set it indicates new_dst_id - * is VNIC or VPORT or function ID. Note dest_fid and - * dest_rfs_ring_idx can’t be set at the same time. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX UINT32_C(0x2) - /* - * Setting of this flag indicates that when the ntuple filter is - * created, the L2 context should not be used in the filter. This - * allows packet from different L2 contexts to match and be directed - * to the same destination. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT UINT32_C(0x4) - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; /* - * If set, this value shall represent the new - * Logical VNIC ID of the destination VNIC for the RX - * path and new network port id of the destination port for - * the TX path. - */ - uint32_t new_dst_id; - /* - * New Logical VNIC ID of the VNIC where traffic is - * mirrored. + * Function ID of the function that is being queried. + * Only valid for a VF FID queried by the PF. */ - uint32_t new_mirror_vnic_id; + uint16_t fid; + uint8_t unused_0[2]; /* - * New meter to attach to the flow. Specifying the - * invalid instance ID is used to remove any existing - * meter from the flow. + * Maximum number of VLAN entries the firmware is allowed to DMA + * to vlan_tag_mask_tbl. */ - uint16_t new_meter_instance_id; + uint32_t max_vlan_entries; /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. + * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN + * antispoof table to which firmware will DMA to. Each table + * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only), + * 16-bit VLAN ID, and a 16-bit mask, all in network order to + * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry, + * the mask value should be 0xfff for the 12-bit VLAN ID. */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff) - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID - uint8_t unused_1[6]; -} hwrm_cfa_ntuple_filter_cfg_input_t, *phwrm_cfa_ntuple_filter_cfg_input_t; + uint64_t vlan_tag_mask_tbl_addr; +} hwrm_cfa_vlan_antispoof_qcfg_input_t, *phwrm_cfa_vlan_antispoof_qcfg_input_t; -/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ +/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */ -typedef struct hwrm_cfa_ntuple_filter_cfg_output { +typedef struct hwrm_cfa_vlan_antispoof_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -41893,7 +45065,9 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */ + uint32_t num_vlan_entries; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -41903,16 +45077,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_ntuple_filter_cfg_output_t, *phwrm_cfa_ntuple_filter_cfg_output_t; +} hwrm_cfa_vlan_antispoof_qcfg_output_t, *phwrm_cfa_vlan_antispoof_qcfg_output_t; -/************************** - * hwrm_cfa_em_flow_alloc * - **************************/ +/******************************** + * hwrm_cfa_tunnel_filter_alloc * + ********************************/ -/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */ +/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ -typedef struct hwrm_cfa_em_flow_alloc_input { +typedef struct hwrm_cfa_tunnel_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -41943,291 +45117,200 @@ uint64_t resp_addr; uint32_t flags; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * Setting of this flag indicates the applicability to the loopback + * path. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1) + uint32_t enables; /* - * Setting of this flag indicates enabling of a byte counter for a - * given flow. + * This bit must be '1' for the l2_filter_id field to be + * configured. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) /* - * Setting of this flag indicates enabling of a packet counter for a - * given flow. + * This bit must be '1' for the l2_addr field to be + * configured. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x2) /* - * Setting of this flag indicates de-capsulation action for the - * given flow. + * This bit must be '1' for the l2_ivlan field to be + * configured. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x4) /* - * Setting of this flag indicates encapsulation action for the - * given flow. + * This bit must be '1' for the l3_addr field to be + * configured. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR UINT32_C(0x8) /* - * Setting of this flag indicates drop action. If this flag is not - * set, then it should be considered accept action. + * This bit must be '1' for the l3_addr_type field to be + * configured. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20) - /* - * Setting of this flag indicates that a meter is expected to be - * attached to this flow. This hint can be used when choosing the - * action record format required for the flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40) - uint32_t enables; - /* - * This bit must be '1' for the l2_filter_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x2) - /* - * This bit must be '1' for the tunnel_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x4) - /* - * This bit must be '1' for the src_macaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8) - /* - * This bit must be '1' for the dst_macaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x10) - /* - * This bit must be '1' for the ovlan_vid field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x20) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE UINT32_C(0x10) /* - * This bit must be '1' for the ivlan_vid field to be + * This bit must be '1' for the t_l3_addr_type field to be * configured. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x40) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE UINT32_C(0x20) /* - * This bit must be '1' for the ethertype field to be + * This bit must be '1' for the t_l3_addr field to be * configured. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x80) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR UINT32_C(0x40) /* - * This bit must be '1' for the src_ipaddr field to be + * This bit must be '1' for the tunnel_type field to be * configured. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x100) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x80) /* - * This bit must be '1' for the dst_ipaddr field to be + * This bit must be '1' for the vni field to be * configured. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x200) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI UINT32_C(0x100) /* - * This bit must be '1' for the ipaddr_type field to be + * This bit must be '1' for the dst_vnic_id field to be * configured. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x400) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID UINT32_C(0x200) /* - * This bit must be '1' for the ip_protocol field to be + * This bit must be '1' for the mirror_vnic_id field to be * configured. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x800) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x400) /* - * This bit must be '1' for the src_port field to be - * configured. + * This value identifies a set of CFA data structures used for an L2 + * context. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x1000) + uint64_t l2_filter_id; /* - * This bit must be '1' for the dst_port field to be - * configured. + * This value sets the match value for the inner L2 + * MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x2000) + uint8_t l2_addr[6]; /* - * This bit must be '1' for the dst_id field to be - * configured. + * This value sets VLAN ID value for inner VLAN. + * Only 12-bits of VLAN ID are used in setting the filter. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x4000) + uint16_t l2_ivlan; /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. + * The value of inner destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x8000) + uint32_t l3_addr[4]; /* - * This bit must be '1' for the encap_record_id field to be - * configured. + * The value of tunnel destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID UINT32_C(0x10000) + uint32_t t_l3_addr[4]; /* - * This bit must be '1' for the meter_instance_id field to be - * configured. + * This value indicates the type of inner IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID UINT32_C(0x20000) + uint8_t l3_addr_type; /* - * This value identifies a set of CFA data structures used for an L2 - * context. + * This value indicates the type of tunnel IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. */ - uint64_t l2_filter_id; + uint8_t t_l3_addr_type; /* Tunnel Type. */ uint8_t tunnel_type; /* Non-tunnel */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) /* IP in IP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) /* * Enhance Generic Routing Encapsulation (GRE version 1) inside IP * datagram payload */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) /* * IPV6 over virtual eXtensible Local Area Network with GPE header * (IPV6oVXLANGPE) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) /* Any tunneled traffic */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0[3]; - /* - * Tunnel identifier. - * Virtual Network Identifier (VNI). Only valid with - * tunnel_types VXLAN, NVGRE, and Geneve. - * Only lower 24-bits of VNI field are used - * in setting up the filter. - */ - uint32_t tunnel_id; - /* - * This value indicates the source MAC address in - * the Ethernet header. - */ - uint8_t src_macaddr[6]; - /* The meter instance to attach to the flow. */ - uint16_t meter_instance_id; - /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID - /* - * This value indicates the destination MAC address in - * the Ethernet header. - */ - uint8_t dst_macaddr[6]; - /* - * This value indicates the VLAN ID of the outer VLAN tag - * in the Ethernet header. - */ - uint16_t ovlan_vid; - /* - * This value indicates the VLAN ID of the inner VLAN tag - * in the Ethernet header. - */ - uint16_t ivlan_vid; - /* This value indicates the ethertype in the Ethernet header. */ - uint16_t ethertype; - /* - * This value indicates the type of IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. - */ - uint8_t ip_addr_type; - /* invalid */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) - /* IPv4 */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) - /* IPv6 */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 - /* - * The value of protocol filed in IP header. - * Applies to UDP and TCP traffic. - * 6 - TCP - * 17 - UDP - */ - uint8_t ip_protocol; - /* invalid */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) - /* TCP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) - /* UDP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP - uint8_t unused_1[2]; + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL /* - * The value of source IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * tunnel_flags allows the user to indicate the tunnel tag detection + * for the tunnel type specified in tunnel_type. */ - uint32_t src_ipaddr[4]; + uint8_t tunnel_flags; /* - * big_endian = True - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * If the tunnel_type is geneve, then this bit indicates if we + * need to match the geneve OAM packet. + * If the tunnel_type is nvgre or gre, then this bit indicates if + * we need to detect checksum present bit in geneve header. + * If the tunnel_type is mpls, then this bit indicates if we need + * to match mpls packet with explicit IPV4/IPV6 null header. */ - uint32_t dst_ipaddr[4]; + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR UINT32_C(0x1) /* - * The value of source port to be used in filtering. - * Applies to UDP and TCP traffic. + * If the tunnel_type is geneve, then this bit indicates if we + * need to detect the critical option bit set in the oam packet. + * If the tunnel_type is nvgre or gre, then this bit indicates + * if we need to match nvgre packets with key present bit set in + * gre header. + * If the tunnel_type is mpls, then this bit indicates if we + * need to match mpls packet with S bit from inner/second label. */ - uint16_t src_port; + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 UINT32_C(0x2) /* - * The value of destination port to be used in filtering. - * Applies to UDP and TCP traffic. + * If the tunnel_type is geneve, then this bit indicates if we + * need to match geneve packet with extended header bit set in + * geneve header. + * If the tunnel_type is nvgre or gre, then this bit indicates + * if we need to match nvgre packets with sequence number + * present bit set in gre header. + * If the tunnel_type is mpls, then this bit indicates if we + * need to match mpls packet with S bit from out/first label. */ - uint16_t dst_port; + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 UINT32_C(0x4) /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. */ - uint16_t dst_id; + uint32_t vni; + /* Logical VNIC ID of the destination VNIC. */ + uint32_t dst_vnic_id; /* * Logical VNIC ID of the VNIC where traffic is * mirrored. */ - uint16_t mirror_vnic_id; - /* Logical ID of the encapsulation record. */ - uint32_t encap_record_id; - uint8_t unused_2[4]; -} hwrm_cfa_em_flow_alloc_input_t, *phwrm_cfa_em_flow_alloc_input_t; + uint32_t mirror_vnic_id; +} hwrm_cfa_tunnel_filter_alloc_input_t, *phwrm_cfa_tunnel_filter_alloc_input_t; -/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */ +/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ -typedef struct hwrm_cfa_em_flow_alloc_output { +typedef struct hwrm_cfa_tunnel_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42237,7 +45320,7 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* This value is an opaque id into CFA data structures. */ - uint64_t em_filter_id; + uint64_t tunnel_filter_id; /* * The flow id value in bit 0-29 is the actual ID of the flow * associated with this filter and it shall be used to match @@ -42247,28 +45330,28 @@ */ uint32_t flow_id; /* Indicate the flow id value. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 /* Indicate type of the flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) /* * If this bit set to 0, then it indicates that the flow is * internal flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) /* * If this bit is set to 1, then it indicates that the flow is * external flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT /* Indicate the flow direction. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -42279,16 +45362,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_em_flow_alloc_output_t, *phwrm_cfa_em_flow_alloc_output_t; +} hwrm_cfa_tunnel_filter_alloc_output_t, *phwrm_cfa_tunnel_filter_alloc_output_t; -/************************* - * hwrm_cfa_em_flow_free * - *************************/ +/******************************* + * hwrm_cfa_tunnel_filter_free * + *******************************/ -/* hwrm_cfa_em_flow_free_input (size:192b/24B) */ +/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ -typedef struct hwrm_cfa_em_flow_free_input { +typedef struct hwrm_cfa_tunnel_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42318,12 +45401,12 @@ */ uint64_t resp_addr; /* This value is an opaque id into CFA data structures. */ - uint64_t em_filter_id; -} hwrm_cfa_em_flow_free_input_t, *phwrm_cfa_em_flow_free_input_t; + uint64_t tunnel_filter_id; +} hwrm_cfa_tunnel_filter_free_input_t, *phwrm_cfa_tunnel_filter_free_input_t; -/* hwrm_cfa_em_flow_free_output (size:128b/16B) */ +/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_em_flow_free_output { +typedef struct hwrm_cfa_tunnel_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42342,16 +45425,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_em_flow_free_output_t, *phwrm_cfa_em_flow_free_output_t; +} hwrm_cfa_tunnel_filter_free_output_t, *phwrm_cfa_tunnel_filter_free_output_t; -/************************ - * hwrm_cfa_em_flow_cfg * - ************************/ +/*************************************** + * hwrm_cfa_redirect_tunnel_type_alloc * + ***************************************/ -/* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */ +/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */ -typedef struct hwrm_cfa_em_flow_cfg_input { +typedef struct hwrm_cfa_redirect_tunnel_type_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42380,55 +45463,60 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) /* - * This bit must be '1' for the new_dst_id field to be - * configured. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) /* - * This bit must be '1' for the new_mirror_vnic_id field to be - * configured. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + /* Tunnel alloc flags. */ + uint8_t flags; /* - * This bit must be '1' for the new_meter_instance_id field to be - * configured. + * Setting of this flag indicates modify existing redirect tunnel + * to new destination function ID. */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST UINT32_C(0x1) uint8_t unused_0[4]; - /* This value is an opaque id into CFA data structures. */ - uint64_t em_filter_id; - /* - * If set, this value shall represent the new - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. - */ - uint32_t new_dst_id; - /* - * New Logical VNIC ID of the VNIC where traffic is - * mirrored. - */ - uint32_t new_mirror_vnic_id; - /* - * New meter to attach to the flow. Specifying the - * invalid instance ID is used to remove any existing - * meter from the flow. - */ - uint16_t new_meter_instance_id; - /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff) - #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID - uint8_t unused_1[6]; -} hwrm_cfa_em_flow_cfg_input_t, *phwrm_cfa_em_flow_cfg_input_t; +} hwrm_cfa_redirect_tunnel_type_alloc_input_t, *phwrm_cfa_redirect_tunnel_type_alloc_input_t; -/* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */ +/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */ -typedef struct hwrm_cfa_em_flow_cfg_output { +typedef struct hwrm_cfa_redirect_tunnel_type_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42447,16 +45535,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_em_flow_cfg_output_t, *phwrm_cfa_em_flow_cfg_output_t; +} hwrm_cfa_redirect_tunnel_type_alloc_output_t, *phwrm_cfa_redirect_tunnel_type_alloc_output_t; -/************************ - * hwrm_cfa_meter_qcaps * - ************************/ +/************************************** + * hwrm_cfa_redirect_tunnel_type_free * + **************************************/ -/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */ +/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */ -typedef struct hwrm_cfa_meter_qcaps_input { +typedef struct hwrm_cfa_redirect_tunnel_type_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42485,11 +45573,53 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_cfa_meter_qcaps_input_t, *phwrm_cfa_meter_qcaps_input_t; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[5]; +} hwrm_cfa_redirect_tunnel_type_free_input_t, *phwrm_cfa_redirect_tunnel_type_free_input_t; -/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */ +/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_meter_qcaps_output { +typedef struct hwrm_cfa_redirect_tunnel_type_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42498,61 +45628,112 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; + uint8_t unused_0[7]; /* - * Enumeration denoting the clock at which the Meter is running - * with. This enumeration is used for resources that are similar - * for both TX and RX paths of the chip. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf) - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0 - /* 375 MHz */ - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0) - /* 625 MHz */ - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1) - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ - uint8_t unused_0[4]; + uint8_t valid; +} hwrm_cfa_redirect_tunnel_type_free_output_t, *phwrm_cfa_redirect_tunnel_type_free_output_t; + +/************************************** + * hwrm_cfa_redirect_tunnel_type_info * + **************************************/ + + +/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */ + +typedef struct hwrm_cfa_redirect_tunnel_type_info_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The minimum guaranteed number of tx meter profiles supported - * for this function. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t min_tx_profile; + uint16_t cmpl_ring; /* - * The maximum non-guaranteed number of tx meter profiles supported - * for this function. - */ - uint16_t max_tx_profile; - /* - * The minimum guaranteed number of rx meter profiles supported - * for this function. - */ - uint16_t min_rx_profile; - /* - * The maximum non-guaranteed number of rx meter profiles supported - * for this function. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t max_rx_profile; + uint16_t seq_id; /* - * The minimum guaranteed number of tx meter instances supported - * for this function. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t min_tx_instance; + uint16_t target_id; /* - * The maximum non-guaranteed number of tx meter instances supported - * for this function. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t max_tx_instance; + uint64_t resp_addr; + /* The source function id. */ + uint16_t src_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) /* - * The minimum guaranteed number of rx meter instances supported - * for this function. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - uint16_t min_rx_instance; + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) /* - * The maximum non-guaranteed number of rx meter instances supported - * for this function. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - uint16_t max_rx_instance; - uint8_t unused_1[7]; + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[5]; +} hwrm_cfa_redirect_tunnel_type_info_input_t, *phwrm_cfa_redirect_tunnel_type_info_input_t; + +/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */ + +typedef struct hwrm_cfa_redirect_tunnel_type_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -42562,16 +45743,121 @@ * written last. */ uint8_t valid; -} hwrm_cfa_meter_qcaps_output_t, *phwrm_cfa_meter_qcaps_output_t; +} hwrm_cfa_redirect_tunnel_type_info_output_t, *phwrm_cfa_redirect_tunnel_type_info_output_t; -/******************************** - * hwrm_cfa_meter_profile_alloc * - ********************************/ +/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ +typedef struct hwrm_vxlan_ipv4_hdr { + /* IPv4 version and header length. */ + uint8_t ver_hlen; + /* IPv4 header length */ + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf) + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 + /* Version */ + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0) + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 + /* IPv4 type of service. */ + uint8_t tos; + /* IPv4 identification. */ + uint16_t ip_id; + /* IPv4 flags and offset. */ + uint16_t flags_frag_offset; + /* IPv4 TTL. */ + uint8_t ttl; + /* IPv4 protocol. */ + uint8_t protocol; + /* IPv4 source address. */ + uint32_t src_ip_addr; + /* IPv4 destination address. */ + uint32_t dest_ip_addr; +} hwrm_vxlan_ipv4_hdr_t, *phwrm_vxlan_ipv4_hdr_t; -/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */ +/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ -typedef struct hwrm_cfa_meter_profile_alloc_input { +typedef struct hwrm_vxlan_ipv6_hdr { + /* IPv6 version, traffic class and flow label. */ + uint32_t ver_tc_flow_label; + /* IPv6 version shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT UINT32_C(0x1c) + /* IPv6 version mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK UINT32_C(0xf0000000) + /* IPv6 TC shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT UINT32_C(0x14) + /* IPv6 TC mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK UINT32_C(0xff00000) + /* IPv6 flow label shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT UINT32_C(0x0) + /* IPv6 flow label mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK UINT32_C(0xfffff) + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK + /* IPv6 payload length. */ + uint16_t payload_len; + /* IPv6 next header. */ + uint8_t next_hdr; + /* IPv6 TTL. */ + uint8_t ttl; + /* IPv6 source address. */ + uint32_t src_ip_addr[4]; + /* IPv6 destination address. */ + uint32_t dest_ip_addr[4]; +} hwrm_vxlan_ipv6_hdr_t, *phwrm_vxlan_ipv6_hdr_t; + +/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ + +typedef struct hwrm_cfa_encap_data_vxlan { + /* Source MAC address. */ + uint8_t src_mac_addr[6]; + /* reserved. */ + uint16_t unused_0; + /* Destination MAC address. */ + uint8_t dst_mac_addr[6]; + /* Number of VLAN tags. */ + uint8_t num_vlan_tags; + /* reserved. */ + uint8_t unused_1; + /* Outer VLAN TPID. */ + uint16_t ovlan_tpid; + /* Outer VLAN TCI. */ + uint16_t ovlan_tci; + /* Inner VLAN TPID. */ + uint16_t ivlan_tpid; + /* Inner VLAN TCI. */ + uint16_t ivlan_tci; + /* L3 header fields. */ + uint32_t l3[10]; + /* IP version mask. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf) + /* IP version 4. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4) + /* IP version 6. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6) + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 + /* UDP source port. */ + uint16_t src_port; + /* UDP destination port. */ + uint16_t dst_port; + /* VXLAN Network Identifier. */ + uint32_t vni; + /* + * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN + * header. + */ + uint8_t hdr_rsvd0[3]; + /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */ + uint8_t hdr_rsvd1; + /* VXLAN header flags field. */ + uint8_t hdr_flags; + uint8_t unused[3]; +} hwrm_cfa_encap_data_vxlan_t, *phwrm_cfa_encap_data_vxlan_t; + +/******************************* + * hwrm_cfa_encap_record_alloc * + *******************************/ + + +/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ + +typedef struct hwrm_cfa_encap_record_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42600,154 +45886,61 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; + uint32_t flags; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * Setting of this flag indicates the applicability to the loopback + * path. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX - /* The meter algorithm type. */ - uint8_t meter_type; - /* RFC 2697 (srTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0) - /* RFC 2698 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1) - /* RFC 4115 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1) /* - * This field is reserved for the future use. - * It shall be set to 0. + * Setting of this flag indicates this encap record is external + * encap record. Resetting of this flag indicates this flag is + * internal encap record and this is the default setting. */ - uint16_t reserved1; + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL UINT32_C(0x2) + /* Encapsulation Type. */ + uint8_t encap_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS UINT32_C(0x6) + /* VLAN */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9) /* - * This field is reserved for the future use. - * It shall be set to 0. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - uint32_t reserved2; - /* A meter rate specified in bytes-per-second. */ - uint32_t commit_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) - /* Raw value */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t commit_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) - /* Invalid value */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID - /* A meter rate specified in bytes-per-second. */ - uint32_t excess_peak_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) - /* Raw unit */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t excess_peak_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID -} hwrm_cfa_meter_profile_alloc_input_t, *phwrm_cfa_meter_profile_alloc_input_t; + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE UINT32_C(0x10) + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE + uint8_t unused_0[3]; + /* This value is encap data used for the given encap type. */ + uint32_t encap_data[20]; +} hwrm_cfa_encap_record_alloc_input_t, *phwrm_cfa_encap_record_alloc_input_t; -/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */ +/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ -typedef struct hwrm_cfa_meter_profile_alloc_output { +typedef struct hwrm_cfa_encap_record_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42756,15 +45949,9 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID - uint8_t unused_0[5]; + /* This value is an opaque id into CFA data structures. */ + uint32_t encap_record_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -42774,16 +45961,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_meter_profile_alloc_output_t, *phwrm_cfa_meter_profile_alloc_output_t; +} hwrm_cfa_encap_record_alloc_output_t, *phwrm_cfa_encap_record_alloc_output_t; -/******************************* - * hwrm_cfa_meter_profile_free * - *******************************/ +/****************************** + * hwrm_cfa_encap_record_free * + ******************************/ -/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */ +/* hwrm_cfa_encap_record_free_input (size:192b/24B) */ -typedef struct hwrm_cfa_meter_profile_free_input { +typedef struct hwrm_cfa_encap_record_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42812,33 +45999,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID - uint8_t unused_1[4]; -} hwrm_cfa_meter_profile_free_input_t, *phwrm_cfa_meter_profile_free_input_t; + /* This value is an opaque id into CFA data structures. */ + uint32_t encap_record_id; + uint8_t unused_0[4]; +} hwrm_cfa_encap_record_free_input_t, *phwrm_cfa_encap_record_free_input_t; -/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */ +/* hwrm_cfa_encap_record_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_meter_profile_free_output { +typedef struct hwrm_cfa_encap_record_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -42857,16 +46025,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_meter_profile_free_output_t, *phwrm_cfa_meter_profile_free_output_t; +} hwrm_cfa_encap_record_free_output_t, *phwrm_cfa_encap_record_free_output_t; -/****************************** - * hwrm_cfa_meter_profile_cfg * - ******************************/ +/******************************** + * hwrm_cfa_ntuple_filter_alloc * + ********************************/ -/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */ +/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ -typedef struct hwrm_cfa_meter_profile_cfg_input { +typedef struct hwrm_cfa_ntuple_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -42895,157 +46063,328 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; + uint32_t flags; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * Setting of this flag indicates the applicability to the loopback + * path. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX - /* The meter algorithm type. */ - uint8_t meter_type; - /* RFC 2697 (srTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0) - /* RFC 2698 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1) - /* RFC 4115 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1) /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x2) /* - * This field is reserved for the future use. - * It shall be set to 0. + * Setting of this flag indicates that a meter is expected to be + * attached to this flow. This hint can be used when choosing the + * action record format required for the flow. */ - uint32_t reserved; - /* A meter rate specified in bytes-per-second. */ - uint32_t commit_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) - /* Raw value */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t commit_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) - /* Invalid value */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID - /* A meter rate specified in bytes-per-second. */ - uint32_t excess_peak_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) - /* Raw unit */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t excess_peak_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID -} hwrm_cfa_meter_profile_cfg_input_t, *phwrm_cfa_meter_profile_cfg_input_t; + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER UINT32_C(0x4) + /* + * Setting of this flag indicates that the dst_id field contains + * function ID. If this is not set it indicates dest_id is VNIC + * or VPORT. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID UINT32_C(0x8) + /* + * Setting of this flag indicates match on arp reply when ethertype + * is 0x0806. If this is not set it indicates no specific arp opcode + * matching. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY UINT32_C(0x10) + /* + * Setting of this flag indicates that the dst_id field contains RFS + * ring table index. If this is not set it indicates dst_id is VNIC + * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx + * can't be set at the same time. Updated drivers should pass ring + * idx in the rfs_ring_tbl_idx field if the firmware indicates + * support for the new field in the HWRM_CFA_ADV_FLOW_MGMT_QCAPS + * response. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX UINT32_C(0x20) + /* + * Setting of this flag indicates that when the ntuple filter is + * created, the L2 context should not be used in the filter. This + * allows packet from different L2 contexts to match and be directed + * to the same destination. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT UINT32_C(0x40) + uint32_t enables; + /* + * This bit must be '1' for the l2_filter_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) + /* + * This bit must be '1' for the ethertype field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2) + /* + * This bit must be '1' for the tunnel_type field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4) + /* + * This bit must be '1' for the src_macaddr field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8) + /* + * This bit must be '1' for the ipaddr_type field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x10) + /* + * This bit must be '1' for the src_ipaddr field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x20) + /* + * This bit must be '1' for the src_ipaddr_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK UINT32_C(0x40) + /* + * This bit must be '1' for the dst_ipaddr field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x80) + /* + * This bit must be '1' for the dst_ipaddr_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK UINT32_C(0x100) + /* + * This bit must be '1' for the ip_protocol field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x200) + /* + * This bit must be '1' for the src_port field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x400) + /* + * This bit must be '1' for the src_port_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK UINT32_C(0x800) + /* + * This bit must be '1' for the dst_port field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x1000) + /* + * This bit must be '1' for the dst_port_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK UINT32_C(0x2000) + /* + * This bit must be '1' for the pri_hint field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT UINT32_C(0x4000) + /* + * This bit must be '1' for the ntuple_filter_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID UINT32_C(0x8000) + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x10000) + /* This flag is deprecated. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x20000) + /* + * This bit must be '1' for the dst_macaddr field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x40000) + /* + * This bit must be '1' for the rfs_ring_tbl_idx field to + * be configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX UINT32_C(0x80000) + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* + * This value indicates the source MAC address in + * the Ethernet header. + */ + uint8_t src_macaddr[6]; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; + /* + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + /* + * The value of protocol field in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP + * 1 - ICMP + * 58 - ICMPV6 + * 255 - RSVD + */ + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) + /* ICMP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMP UINT32_C(0x1) + /* ICMPV6 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMPV6 UINT32_C(0x3a) + /* RSVD */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD UINT32_C(0xff) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. + */ + uint16_t dst_id; + /* + * If set, this value shall represent the ring table + * index for receive flow steering. Note that this offset + * was formerly used for the mirror_vnic_id field, which + * is no longer supported. + */ + uint16_t rfs_ring_tbl_idx; + /* + * This value indicates the tunnel type for this filter. + * If this field is not specified, then the filter shall + * apply to both non-tunneled and tunneled packets. + * If this field conflicts with the tunnel_type specified + * in the l2_filter_id, then the HWRM shall return an + * error for this command. + */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + /* Any tunneled traffic */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + /* + * This hint is provided to help in placing + * the filter in the filter table. + */ + uint8_t pri_hint; + /* No preference */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0) + /* Above the given filter */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE UINT32_C(0x1) + /* Below the given filter */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW UINT32_C(0x2) + /* As high as possible */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST UINT32_C(0x3) + /* As low as possible */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST UINT32_C(0x4) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST + /* + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t src_ipaddr[4]; + /* + * The value of source IP address mask to be used in + * filtering. + * For IPv4, first four bytes represent the IP address mask. + */ + uint32_t src_ipaddr_mask[4]; + /* + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t dst_ipaddr[4]; + /* + * The value of destination IP address mask to be used in + * filtering. + * For IPv4, first four bytes represent the IP address mask. + */ + uint32_t dst_ipaddr_mask[4]; + /* + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t src_port; + /* + * The value of source port mask to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t src_port_mask; + /* + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t dst_port; + /* + * The value of destination port mask to be used in + * filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t dst_port_mask; + /* + * This is the ID of the filter that goes along with + * the pri_hint. + */ + uint64_t ntuple_filter_id_hint; +} hwrm_cfa_ntuple_filter_alloc_input_t, *phwrm_cfa_ntuple_filter_alloc_input_t; -/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */ +/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ -typedef struct hwrm_cfa_meter_profile_cfg_output { +typedef struct hwrm_cfa_ntuple_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -43054,7 +46393,40 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -43064,16 +46436,32 @@ * written last. */ uint8_t valid; -} hwrm_cfa_meter_profile_cfg_output_t, *phwrm_cfa_meter_profile_cfg_output_t; +} hwrm_cfa_ntuple_filter_alloc_output_t, *phwrm_cfa_ntuple_filter_alloc_output_t; -/********************************* - * hwrm_cfa_meter_instance_alloc * - *********************************/ +/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ + +typedef struct hwrm_cfa_ntuple_filter_alloc_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Unable to complete operation due to conflict with Rx Mask VLAN */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR UINT32_C(0x1) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR + uint8_t unused_0[7]; +} hwrm_cfa_ntuple_filter_alloc_cmd_err_t, *phwrm_cfa_ntuple_filter_alloc_cmd_err_t; +/******************************* + * hwrm_cfa_ntuple_filter_free * + *******************************/ -/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */ -typedef struct hwrm_cfa_meter_instance_alloc_input { +/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ + +typedef struct hwrm_cfa_ntuple_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -43102,33 +46490,13 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xffff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID - uint8_t unused_1[4]; -} hwrm_cfa_meter_instance_alloc_input_t, *phwrm_cfa_meter_instance_alloc_input_t; + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; +} hwrm_cfa_ntuple_filter_free_input_t, *phwrm_cfa_ntuple_filter_free_input_t; -/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */ +/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_meter_instance_alloc_output { +typedef struct hwrm_cfa_ntuple_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -43137,15 +46505,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value identifies a meter instance in CFA. */ - uint16_t meter_instance_id; - /* - * A value of 0xffff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -43155,16 +46515,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_meter_instance_alloc_output_t, *phwrm_cfa_meter_instance_alloc_output_t; +} hwrm_cfa_ntuple_filter_free_output_t, *phwrm_cfa_ntuple_filter_free_output_t; -/******************************* - * hwrm_cfa_meter_instance_cfg * - *******************************/ +/****************************** + * hwrm_cfa_ntuple_filter_cfg * + ******************************/ -/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */ +/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ -typedef struct hwrm_cfa_meter_instance_cfg_input { +typedef struct hwrm_cfa_ntuple_filter_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -43193,41 +46553,75 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; + uint32_t enables; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * This bit must be '1' for the new_dst_id field to be + * configured. */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX - uint8_t unused_0; + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1) /* - * This value identifies a new meter profile to be associated with - * the meter instance specified in this command. + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. */ - uint16_t meter_profile_id; + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2) /* - * A value of 0xffff is considered invalid and implies the - * profile is not configured. + * This bit must be '1' for the new_meter_instance_id field to be + * configured. */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4) + uint32_t flags; /* - * This value identifies the ID of a meter instance that needs to be - * updated with a new meter profile specified in this command. + * Setting this bit to 1 indicates that dest_id field contains FID. + * Setting this to 0 indicates that dest_id field contains VNIC or + * VPORT. */ - uint16_t meter_instance_id; - uint8_t unused_1[2]; -} hwrm_cfa_meter_instance_cfg_input_t, *phwrm_cfa_meter_instance_cfg_input_t; + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID UINT32_C(0x1) + /* + * Setting of this flag indicates that the new_dst_id field contains + * RFS ring table index. If this is not set it indicates new_dst_id + * is VNIC or VPORT or function ID. Note dest_fid and + * dest_rfs_ring_idx can't be set at the same time. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX UINT32_C(0x2) + /* + * Setting of this flag indicates that when the ntuple filter is + * created, the L2 context should not be used in the filter. This + * allows packet from different L2 contexts to match and be directed + * to the same destination. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT UINT32_C(0x4) + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; + /* + * If set, this value shall represent the new + * Logical VNIC ID of the destination VNIC for the RX + * path and new network port id of the destination port for + * the TX path. + */ + uint32_t new_dst_id; + /* + * New Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint32_t new_mirror_vnic_id; + /* + * New meter to attach to the flow. Specifying the + * invalid instance ID is used to remove any existing + * meter from the flow. + */ + uint16_t new_meter_instance_id; + /* + * A value of 0xfff is considered invalid and implies the + * instance is not configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff) + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID + uint8_t unused_1[6]; +} hwrm_cfa_ntuple_filter_cfg_input_t, *phwrm_cfa_ntuple_filter_cfg_input_t; -/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */ +/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ -typedef struct hwrm_cfa_meter_instance_cfg_output { +typedef struct hwrm_cfa_ntuple_filter_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -43246,16 +46640,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_meter_instance_cfg_output_t, *phwrm_cfa_meter_instance_cfg_output_t; +} hwrm_cfa_ntuple_filter_cfg_output_t, *phwrm_cfa_ntuple_filter_cfg_output_t; -/******************************** - * hwrm_cfa_meter_instance_free * - ********************************/ +/************************** + * hwrm_cfa_em_flow_alloc * + **************************/ -/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */ +/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */ -typedef struct hwrm_cfa_meter_instance_free_input { +typedef struct hwrm_cfa_em_flow_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -43284,233 +46678,206 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; + uint32_t flags; /* * Enumeration denoting the RX, TX type of the resource. * This enumeration is used for resources that are similar for both * TX and RX paths of the chip. */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) /* tx path */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) /* rx path */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter instance in CFA. */ - uint16_t meter_instance_id; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. + * Setting of this flag indicates enabling of a byte counter for a + * given flow. */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID - uint8_t unused_1[4]; -} hwrm_cfa_meter_instance_free_input_t, *phwrm_cfa_meter_instance_free_input_t; - -/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */ - -typedef struct hwrm_cfa_meter_instance_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * Setting of this flag indicates enabling of a packet counter for a + * given flow. */ - uint8_t valid; -} hwrm_cfa_meter_instance_free_output_t, *phwrm_cfa_meter_instance_free_output_t; - -/******************************* - * hwrm_cfa_decap_filter_alloc * - *******************************/ - - -/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ - -typedef struct hwrm_cfa_decap_filter_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Setting of this flag indicates de-capsulation action for the + * given flow. */ - uint16_t cmpl_ring; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Setting of this flag indicates encapsulation action for the + * given flow. */ - uint16_t seq_id; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ - uint16_t target_id; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Setting of this flag indicates that a meter is expected to be + * attached to this flow. This hint can be used when choosing the + * action record format required for the flow. */ - uint64_t resp_addr; - uint32_t flags; - /* ovs_tunnel is 1 b */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL UINT32_C(0x1) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40) uint32_t enables; + /* + * This bit must be '1' for the l2_filter_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) /* * This bit must be '1' for the tunnel_type field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x1) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x2) /* * This bit must be '1' for the tunnel_id field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x2) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x4) /* * This bit must be '1' for the src_macaddr field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x4) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8) /* * This bit must be '1' for the dst_macaddr field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x8) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x10) /* * This bit must be '1' for the ovlan_vid field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x10) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x20) /* * This bit must be '1' for the ivlan_vid field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x20) - /* - * This bit must be '1' for the t_ovlan_vid field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID UINT32_C(0x40) - /* - * This bit must be '1' for the t_ivlan_vid field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID UINT32_C(0x80) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x40) /* * This bit must be '1' for the ethertype field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x100) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x80) /* * This bit must be '1' for the src_ipaddr field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x200) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x100) /* * This bit must be '1' for the dst_ipaddr field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x400) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x200) /* * This bit must be '1' for the ipaddr_type field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x800) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x400) /* * This bit must be '1' for the ip_protocol field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x1000) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x800) /* * This bit must be '1' for the src_port field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x2000) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x1000) /* * This bit must be '1' for the dst_port field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x4000) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x2000) /* * This bit must be '1' for the dst_id field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x4000) /* * This bit must be '1' for the mirror_vnic_id field to be * configured. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x8000) /* - * Tunnel identifier. - * Virtual Network Identifier (VNI). Only valid with - * tunnel_types VXLAN, NVGRE, and Geneve. - * Only lower 24-bits of VNI field are used - * in setting up the filter. + * This bit must be '1' for the encap_record_id field to be + * configured. */ - uint32_t tunnel_id; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID UINT32_C(0x10000) + /* + * This bit must be '1' for the meter_instance_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID UINT32_C(0x20000) + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; /* Tunnel Type. */ uint8_t tunnel_type; /* Non-tunnel */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) /* IP in IP */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) /* * Enhance Generic Routing Encapsulation (GRE version 1) inside IP * datagram payload */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) /* * IPV6 over virtual eXtensible Local Area Network with GPE header * (IPV6oVXLANGPE) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) /* Any tunneled traffic */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0; - uint16_t unused_1; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[3]; + /* + * Tunnel identifier. + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. + */ + uint32_t tunnel_id; /* * This value indicates the source MAC address in * the Ethernet header. */ uint8_t src_macaddr[6]; - uint8_t unused_2[2]; + /* The meter instance to attach to the flow. */ + uint16_t meter_instance_id; + /* + * A value of 0xfff is considered invalid and implies the + * instance is not configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID /* * This value indicates the destination MAC address in * the Ethernet header. @@ -43526,16 +46893,6 @@ * in the Ethernet header. */ uint16_t ivlan_vid; - /* - * This value indicates the VLAN ID of the outer VLAN tag - * in the tunnel Ethernet header. - */ - uint16_t t_ovlan_vid; - /* - * This value indicates the VLAN ID of the inner VLAN tag - * in the tunnel Ethernet header. - */ - uint16_t t_ivlan_vid; /* This value indicates the ethertype in the Ethernet header. */ uint16_t ethertype; /* @@ -43546,36 +46903,36 @@ */ uint8_t ip_addr_type; /* invalid */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) /* IPv4 */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) /* IPv6 */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * The value of protocol filed in IP header. + * The value of protocol field in IP header. * Applies to UDP and TCP traffic. * 6 - TCP * 17 - UDP */ uint8_t ip_protocol; /* invalid */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) /* TCP */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) /* UDP */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP - uint16_t unused_3; - uint32_t unused_4; + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP + uint8_t unused_1[2]; /* * The value of source IP address to be used in filtering. * For IPv4, first four bytes represent the IP address. */ uint32_t src_ipaddr[4]; /* - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * big_endian = True + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ uint32_t dst_ipaddr[4]; /* @@ -43591,19 +46948,23 @@ /* * If set, this value shall represent the * Logical VNIC ID of the destination VNIC for the RX - * path. + * path and network port id of the destination port for + * the TX path. */ uint16_t dst_id; /* - * If set, this value shall represent the L2 context that matches the - * L2 information of the decap filter. + * Logical VNIC ID of the VNIC where traffic is + * mirrored. */ - uint16_t l2_ctxt_ref_id; -} hwrm_cfa_decap_filter_alloc_input_t, *phwrm_cfa_decap_filter_alloc_input_t; + uint16_t mirror_vnic_id; + /* Logical ID of the encapsulation record. */ + uint32_t encap_record_id; + uint8_t unused_2[4]; +} hwrm_cfa_em_flow_alloc_input_t, *phwrm_cfa_em_flow_alloc_input_t; -/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ +/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */ -typedef struct hwrm_cfa_decap_filter_alloc_output { +typedef struct hwrm_cfa_em_flow_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -43613,7 +46974,38 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* This value is an opaque id into CFA data structures. */ - uint32_t decap_filter_id; + uint64_t em_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -43624,16 +47016,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_decap_filter_alloc_output_t, *phwrm_cfa_decap_filter_alloc_output_t; +} hwrm_cfa_em_flow_alloc_output_t, *phwrm_cfa_em_flow_alloc_output_t; -/****************************** - * hwrm_cfa_decap_filter_free * - ******************************/ +/************************* + * hwrm_cfa_em_flow_free * + *************************/ -/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ +/* hwrm_cfa_em_flow_free_input (size:192b/24B) */ -typedef struct hwrm_cfa_decap_filter_free_input { +typedef struct hwrm_cfa_em_flow_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -43663,13 +47055,12 @@ */ uint64_t resp_addr; /* This value is an opaque id into CFA data structures. */ - uint32_t decap_filter_id; - uint8_t unused_0[4]; -} hwrm_cfa_decap_filter_free_input_t, *phwrm_cfa_decap_filter_free_input_t; + uint64_t em_filter_id; +} hwrm_cfa_em_flow_free_input_t, *phwrm_cfa_em_flow_free_input_t; -/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ +/* hwrm_cfa_em_flow_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_decap_filter_free_output { +typedef struct hwrm_cfa_em_flow_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -43688,16 +47079,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_decap_filter_free_output_t, *phwrm_cfa_decap_filter_free_output_t; +} hwrm_cfa_em_flow_free_output_t, *phwrm_cfa_em_flow_free_output_t; -/*********************** - * hwrm_cfa_flow_alloc * - ***********************/ +/************************ + * hwrm_cfa_em_flow_cfg * + ************************/ -/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ +/* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */ -typedef struct hwrm_cfa_flow_alloc_input { +typedef struct hwrm_cfa_em_flow_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -43726,273 +47117,179 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t flags; - /* tunnel is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1) - /* num_vlan is 2 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1 - /* no tags */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE (UINT32_C(0x0) << 1) - /* 1 tag */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE (UINT32_C(0x1) << 1) - /* 2 tags */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO (UINT32_C(0x2) << 1) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO - /* Enumeration denoting the Flow Type. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3 - /* L2 flow */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 (UINT32_C(0x0) << 3) - /* IPV4 flow */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 (UINT32_C(0x1) << 3) - /* IPV6 flow */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 (UINT32_C(0x2) << 3) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 + uint32_t enables; /* - * when set to 1, indicates TX flow offload for function specified - * in src_fid and the dst_fid should be set to invalid value. To - * indicate a VM to VM flow, both of the path_tx and path_rx flags - * need to be set. For virtio vSwitch offload case, the src_fid and - * dst_fid is set to the same fid value. For the SRIOV vSwitch - * offload case, the src_fid and dst_fid must be set to the same VF - * FID belong to the children VFs of the same PF to indicate VM to - * VM flow. + * This bit must be '1' for the new_dst_id field to be + * configured. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x40) + #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1) /* - * when set to 1, indicates RX flow offload for function specified - * in dst_fid and the src_fid should be set to invalid value. + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x80) + #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2) /* - * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan - * header is required and the VXLAN VNI value is stored in the first - * 24 bits of the dmac field. This flag is only valid when the flow - * direction is RX. + * This bit must be '1' for the new_meter_instance_id field to be + * configured. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI UINT32_C(0x100) + #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4) + uint8_t unused_0[4]; + /* This value is an opaque id into CFA data structures. */ + uint64_t em_filter_id; /* - * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci - * field. + * If set, this value shall represent the new + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN UINT32_C(0x200) + uint32_t new_dst_id; /* - * Tx Flow: vf fid. - * Rx Flow: pf fid. + * New Logical VNIC ID of the VNIC where traffic is + * mirrored. */ - uint16_t src_fid; - /* Tunnel handle valid when tunnel flag is set. */ - uint32_t tunnel_handle; - uint16_t action_flags; + uint32_t new_mirror_vnic_id; /* - * Setting of this flag indicates drop action. If this flag is not - * set, then it should be considered accept action. + * New meter to attach to the flow. Specifying the + * invalid instance ID is used to remove any existing + * meter from the flow. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD UINT32_C(0x1) - /* recycle is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE UINT32_C(0x2) + uint16_t new_meter_instance_id; /* - * Setting of this flag indicates drop action. If this flag is not - * set, then it should be considered accept action. + * A value of 0xfff is considered invalid and implies the + * instance is not configured. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP UINT32_C(0x4) - /* meter is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER UINT32_C(0x8) - /* tunnel is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL UINT32_C(0x10) - /* nat_src is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC UINT32_C(0x20) - /* nat_dest is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST UINT32_C(0x40) - /* nat_ipv4_address is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS UINT32_C(0x80) - /* l2_header_rewrite is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE UINT32_C(0x100) - /* ttl_decrement is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT UINT32_C(0x200) - /* - * If set to 1 and flow direction is TX, it indicates decap of L2 - * header and encap of tunnel header. If set to 1 and flow direction - * is RX, it indicates decap of tunnel header and encap L2 header. - * The type of tunnel is specified in the tunnel_type field. - */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP UINT32_C(0x400) - /* If set to 1, flow aging is enabled for this flow. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED UINT32_C(0x800) + #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff) + #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID + uint8_t unused_1[6]; +} hwrm_cfa_em_flow_cfg_input_t, *phwrm_cfa_em_flow_cfg_input_t; + +/* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */ + +typedef struct hwrm_cfa_em_flow_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * If set to 1 an attempt will be made to try to offload this flow - * to the most optimal flow table resource. If set to 0, the flow - * will be placed to the default flow table resource. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT UINT32_C(0x1000) + uint8_t valid; +} hwrm_cfa_em_flow_cfg_output_t, *phwrm_cfa_em_flow_cfg_output_t; + +/************************ + * hwrm_cfa_meter_qcaps * + ************************/ + + +/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */ + +typedef struct hwrm_cfa_meter_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If set to 1 there will be no attempt to allocate an on-chip try - * to offload this flow. If set to 0, which will keep compatibility - * with the older drivers, will cause the FW to attempt to allocate - * an on-chip flow counter for the newly created flow. This will - * keep the existing behavior with EM flows which always had an - * associated flow counter. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC UINT32_C(0x2000) + uint16_t cmpl_ring; /* - * Tx Flow: pf or vf fid. - * Rx Flow: vf fid. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t dst_fid; - /* VLAN tpid, valid when push_vlan flag is set. */ - uint16_t l2_rewrite_vlan_tpid; - /* VLAN tci, valid when push_vlan flag is set. */ - uint16_t l2_rewrite_vlan_tci; - /* Meter id, valid when meter flag is set. */ - uint16_t act_meter_id; - /* Flow with the same l2 context tcam key. */ - uint16_t ref_flow_handle; - /* This value sets the match value for the ethertype. */ - uint16_t ethertype; - /* valid when num tags is 1 or 2. */ - uint16_t outer_vlan_tci; - /* This value sets the match value for the Destination MAC address. */ - uint16_t dmac[3]; - /* valid when num tags is 2. */ - uint16_t inner_vlan_tci; - /* This value sets the match value for the Source MAC address. */ - uint16_t smac[3]; - /* The bit length of destination IP address mask. */ - uint8_t ip_dst_mask_len; - /* The bit length of source IP address mask. */ - uint8_t ip_src_mask_len; - /* The value of destination IPv4/IPv6 address. */ - uint32_t ip_dst[4]; - /* The source IPv4/IPv6 address. */ - uint32_t ip_src[4]; + uint16_t seq_id; /* - * The value of source port. - * Applies to UDP and TCP traffic. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t l4_src_port; + uint16_t target_id; /* - * The value of source port mask. - * Applies to UDP and TCP traffic. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t l4_src_port_mask; + uint64_t resp_addr; +} hwrm_cfa_meter_qcaps_input_t, *phwrm_cfa_meter_qcaps_input_t; + +/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */ + +typedef struct hwrm_cfa_meter_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; /* - * The value of destination port. - * Applies to UDP and TCP traffic. + * Enumeration denoting the clock at which the Meter is running + * with. This enumeration is used for resources that are similar + * for both TX and RX paths of the chip. */ - uint16_t l4_dst_port; + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf) + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0 + /* 375 MHz */ + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0) + /* 625 MHz */ + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1) + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ + uint8_t unused_0[4]; /* - * The value of destination port mask. - * Applies to UDP and TCP traffic. + * The minimum guaranteed number of tx meter profiles supported + * for this function. */ - uint16_t l4_dst_port_mask; + uint16_t min_tx_profile; /* - * NAT IPv4/6 address based on address type flag. - * 0 values are ignored. + * The maximum non-guaranteed number of tx meter profiles supported + * for this function. */ - uint32_t nat_ip_address[4]; - /* L2 header re-write Destination MAC address. */ - uint16_t l2_rewrite_dmac[3]; + uint16_t max_tx_profile; /* - * The NAT source/destination port based on direction flag. - * Applies to UDP and TCP traffic. - * 0 values are ignored. + * The minimum guaranteed number of rx meter profiles supported + * for this function. */ - uint16_t nat_port; - /* L2 header re-write Source MAC address. */ - uint16_t l2_rewrite_smac[3]; - /* The value of ip protocol. */ - uint8_t ip_proto; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + uint16_t min_rx_profile; /* - * Enhance Generic Routing Encapsulation (GRE version 1) inside IP - * datagram payload + * The maximum non-guaranteed number of rx meter profiles supported + * for this function. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) + uint16_t max_rx_profile; /* - * IPV6 over virtual eXtensible Local Area Network with GPE header - * (IPV6oVXLANGPE) + * The minimum guaranteed number of tx meter instances supported + * for this function. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - /* Any tunneled traffic */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL -} hwrm_cfa_flow_alloc_input_t, *phwrm_cfa_flow_alloc_input_t; - -/* hwrm_cfa_flow_alloc_output (size:256b/32B) */ - -typedef struct hwrm_cfa_flow_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Flow record index. */ - uint16_t flow_handle; - uint8_t unused_0[2]; + uint16_t min_tx_instance; /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. + * The maximum non-guaranteed number of tx meter instances supported + * for this function. */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) + uint16_t max_tx_instance; /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. + * The minimum guaranteed number of rx meter instances supported + * for this function. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) + uint16_t min_rx_instance; /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. + * The maximum non-guaranteed number of rx meter instances supported + * for this function. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; - uint32_t flow_counter_id; - uint8_t unused_1[3]; + uint16_t max_rx_instance; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -44002,44 +47299,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_flow_alloc_output_t, *phwrm_cfa_flow_alloc_output_t; - -/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ - -typedef struct hwrm_cfa_flow_alloc_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* No more L2 Context TCAM */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1) - /* No more action records */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2) - /* No more flow counters */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3) - /* No more wild-card TCAM */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4) - /* Hash collision in exact match tables */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5) - /* Key is already installed */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6) - /* Flow Context DB is out of resource */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7) - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB - uint8_t unused_0[7]; -} hwrm_cfa_flow_alloc_cmd_err_t, *phwrm_cfa_flow_alloc_cmd_err_t; +} hwrm_cfa_meter_qcaps_output_t, *phwrm_cfa_meter_qcaps_output_t; -/********************** - * hwrm_cfa_flow_free * - **********************/ +/******************************** + * hwrm_cfa_meter_profile_alloc * + ********************************/ -/* hwrm_cfa_flow_free_input (size:256b/32B) */ +/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */ -typedef struct hwrm_cfa_flow_free_input { +typedef struct hwrm_cfa_meter_profile_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44068,18 +47337,154 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow record index. */ - uint16_t flow_handle; - uint16_t unused_0; - /* Flow counter id to be freed. */ - uint32_t flow_counter_id; - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; -} hwrm_cfa_flow_free_input_t, *phwrm_cfa_flow_free_input_t; + uint8_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX + /* The meter algorithm type. */ + uint8_t meter_type; + /* RFC 2697 (srTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0) + /* RFC 2698 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1) + /* RFC 4115 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint16_t reserved1; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint32_t reserved2; + /* A meter rate specified in bytes-per-second. */ + uint32_t commit_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) + /* Raw value */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t commit_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) + /* Invalid value */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID + /* A meter rate specified in bytes-per-second. */ + uint32_t excess_peak_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) + /* Raw unit */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t excess_peak_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID +} hwrm_cfa_meter_profile_alloc_input_t, *phwrm_cfa_meter_profile_alloc_input_t; -/* hwrm_cfa_flow_free_output (size:256b/32B) */ +/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */ -typedef struct hwrm_cfa_flow_free_output { +typedef struct hwrm_cfa_meter_profile_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -44088,11 +47493,15 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* packet is 64 b */ - uint64_t packet; - /* byte is 64 b */ - uint64_t byte; - uint8_t unused_0[7]; + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; + /* + * A value of 0xfff is considered invalid and implies the + * profile is not configured. + */ + #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -44102,235 +47511,99 @@ * written last. */ uint8_t valid; -} hwrm_cfa_flow_free_output_t, *phwrm_cfa_flow_free_output_t; +} hwrm_cfa_meter_profile_alloc_output_t, *phwrm_cfa_meter_profile_alloc_output_t; -/* hwrm_cfa_flow_action_data (size:960b/120B) */ +/******************************* + * hwrm_cfa_meter_profile_free * + *******************************/ -typedef struct hwrm_cfa_flow_action_data { - uint16_t action_flags; - /* Setting of this flag indicates accept action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD UINT32_C(0x1) - /* Setting of this flag indicates recycle action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE UINT32_C(0x2) - /* Setting of this flag indicates drop action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP UINT32_C(0x4) - /* Setting of this flag indicates meter action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER UINT32_C(0x8) - /* Setting of this flag indicates tunnel action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL UINT32_C(0x10) + +/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */ + +typedef struct hwrm_cfa_meter_profile_free_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If set to 1 and flow direction is TX, it indicates decap of L2 - * header and encap of tunnel header. If set to 1 and flow direction - * is RX, it indicates decap of tunnel header and encap L2 header. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP UINT32_C(0x20) - /* Setting of this flag indicates ttl decrement action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT UINT32_C(0x40) - /* If set to 1, flow aging is enabled for this flow. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED UINT32_C(0x80) - /* Setting of this flag indicates encap action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP UINT32_C(0x100) - /* Setting of this flag indicates decap action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP UINT32_C(0x200) - /* Meter id. */ - uint16_t act_meter_id; - /* VNIC id. */ - uint16_t vnic_id; - /* vport number. */ - uint16_t vport_id; - /* The NAT source/destination. */ - uint16_t nat_port; - uint16_t unused_0[3]; - /* NAT IPv4/IPv6 address. */ - uint32_t nat_ip_address[4]; - /* Encapsulation Type. */ - uint8_t encap_type; - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6) - /* VLAN */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9) + uint16_t cmpl_ring; /* - * Enhance Generic Routing Encapsulation (GRE version 1) inside IP - * datagram payload + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb) + uint16_t seq_id; /* - * IPV6 over virtual eXtensible Local Area Network with GPE header - * (IPV6oVXLANGPE) + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE UINT32_C(0x10) - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE - uint8_t unused[7]; - /* This value is encap data for the associated encap type. */ - uint32_t encap_data[20]; -} hwrm_cfa_flow_action_data_t, *phwrm_cfa_flow_action_data_t; - -/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */ - -typedef struct hwrm_cfa_flow_tunnel_hdr_data { - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + uint16_t target_id; /* - * Enhance Generic Routing Encapsulation (GRE version 1) inside IP - * datagram payload + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) + uint64_t resp_addr; + uint8_t flags; /* - * IPV6 over virtual eXtensible Local Area Network with GPE header - * (IPV6oVXLANGPE) + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - /* Any tunneled traffic */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused[3]; + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; /* - * Tunnel identifier. - * Virtual Network Identifier (VNI). + * A value of 0xfff is considered invalid and implies the + * profile is not configured. */ - uint32_t tunnel_id; -} hwrm_cfa_flow_tunnel_hdr_data_t, *phwrm_cfa_flow_tunnel_hdr_data_t; - -/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */ - -typedef struct hwrm_cfa_flow_l4_key_data { - /* The value of source port. */ - uint16_t l4_src_port; - /* The value of destination port. */ - uint16_t l4_dst_port; - uint32_t unused; -} hwrm_cfa_flow_l4_key_data_t, *phwrm_cfa_flow_l4_key_data_t; + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID + uint8_t unused_1[4]; +} hwrm_cfa_meter_profile_free_input_t, *phwrm_cfa_meter_profile_free_input_t; -/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */ +/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_flow_l3_key_data { - /* The value of ip protocol. */ - uint8_t ip_protocol; +typedef struct hwrm_cfa_meter_profile_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; uint8_t unused_0[7]; - /* The value of destination IPv4/IPv6 address. */ - uint32_t ip_dst[4]; - /* The source IPv4/IPv6 address. */ - uint32_t ip_src[4]; - /* NAT IPv4/IPv6 address. */ - uint32_t nat_ip_address[4]; - uint64_t unused; -} hwrm_cfa_flow_l3_key_data_t, *phwrm_cfa_flow_l3_key_data_t; - -/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */ - -typedef struct hwrm_cfa_flow_l2_key_data { - /* Destination MAC address. */ - uint16_t dmac[3]; - uint16_t unused_0; - /* Source MAC address. */ - uint16_t smac[3]; - uint16_t unused_1; - /* L2 header re-write Destination MAC address. */ - uint16_t l2_rewrite_dmac[3]; - uint16_t unused_2; - /* L2 header re-write Source MAC address. */ - uint16_t l2_rewrite_smac[3]; - /* Ethertype. */ - uint16_t ethertype; - /* Number of VLAN tags. */ - uint16_t num_vlan_tags; - /* VLAN tpid. */ - uint16_t l2_rewrite_vlan_tpid; - /* VLAN tci. */ - uint16_t l2_rewrite_vlan_tci; - uint8_t unused_3[2]; - /* Outer VLAN TPID. */ - uint16_t ovlan_tpid; - /* Outer VLAN TCI. */ - uint16_t ovlan_tci; - /* Inner VLAN TPID. */ - uint16_t ivlan_tpid; - /* Inner VLAN TCI. */ - uint16_t ivlan_tci; - uint8_t unused[8]; -} hwrm_cfa_flow_l2_key_data_t, *phwrm_cfa_flow_l2_key_data_t; - -/* hwrm_cfa_flow_key_data (size:4160b/520B) */ - -typedef struct hwrm_cfa_flow_key_data { - /* Flow associated tunnel L2 header key info. */ - uint32_t t_l2_key_data[14]; - /* Flow associated tunnel L2 header mask info. */ - uint32_t t_l2_key_mask[14]; - /* Flow associated tunnel L3 header key info. */ - uint32_t t_l3_key_data[16]; - /* Flow associated tunnel L3 header mask info. */ - uint32_t t_l3_key_mask[16]; - /* Flow associated tunnel L4 header key info. */ - uint64_t t_l4_key_data; - /* Flow associated tunnel L4 header mask info. */ - uint64_t t_l4_key_mask; - /* Flow associated tunnel header info. */ - uint64_t tunnel_hdr; - /* Flow associated L2 header key info. */ - uint32_t l2_key_data[14]; - /* Flow associated L2 header mask info. */ - uint32_t l2_key_mask[14]; - /* Flow associated L3 header key info. */ - uint32_t l3_key_data[16]; - /* Flow associated L3 header mask info. */ - uint32_t l3_key_mask[16]; - /* Flow associated L4 header key info. */ - uint64_t l4_key_data; - /* Flow associated L4 header mask info. */ - uint64_t l4_key_mask; -} hwrm_cfa_flow_key_data_t, *phwrm_cfa_flow_key_data_t; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} hwrm_cfa_meter_profile_free_output_t, *phwrm_cfa_meter_profile_free_output_t; -/********************** - * hwrm_cfa_flow_info * - **********************/ +/****************************** + * hwrm_cfa_meter_profile_cfg * + ******************************/ -/* hwrm_cfa_flow_info_input (size:256b/32B) */ +/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */ -typedef struct hwrm_cfa_flow_info_input { +typedef struct hwrm_cfa_meter_profile_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44359,37 +47632,157 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow record index. */ - uint16_t flow_handle; - /* Max flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK UINT32_C(0xfff) - /* CNP flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT UINT32_C(0x1000) - /* RoCEv1 flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT UINT32_C(0x2000) - /* NIC flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_TX UINT32_C(0x3000) - /* RoCEv2 flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT UINT32_C(0x4000) - /* Direction rx = 1 */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX UINT32_C(0x8000) - /* CNP flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT_RX UINT32_C(0x9000) - /* RoCEv1 flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT_RX UINT32_C(0xa000) - /* NIC flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_RX UINT32_C(0xb000) - /* RoCEv2 flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX UINT32_C(0xc000) - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_LAST HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX - uint8_t unused_0[6]; - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; -} hwrm_cfa_flow_info_input_t, *phwrm_cfa_flow_info_input_t; + uint8_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX + /* The meter algorithm type. */ + uint8_t meter_type; + /* RFC 2697 (srTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0) + /* RFC 2698 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1) + /* RFC 4115 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; + /* + * A value of 0xfff is considered invalid and implies the + * profile is not configured. + */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint32_t reserved; + /* A meter rate specified in bytes-per-second. */ + uint32_t commit_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) + /* Raw value */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t commit_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) + /* Invalid value */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID + /* A meter rate specified in bytes-per-second. */ + uint32_t excess_peak_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) + /* Raw unit */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t excess_peak_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID +} hwrm_cfa_meter_profile_cfg_input_t, *phwrm_cfa_meter_profile_cfg_input_t; -/* hwrm_cfa_flow_info_output (size:5632b/704B) */ +/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */ -typedef struct hwrm_cfa_flow_info_output { +typedef struct hwrm_cfa_meter_profile_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -44398,39 +47791,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t flags; - /* When set to 1, indicates the configuration is the TX flow. */ - #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* When set to 1, indicates the configuration is the RX flow. */ - #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2) - /* profile is 8 b */ - uint8_t profile; - /* src_fid is 16 b */ - uint16_t src_fid; - /* dst_fid is 16 b */ - uint16_t dst_fid; - /* l2_ctxt_id is 16 b */ - uint16_t l2_ctxt_id; - /* em_info is 64 b */ - uint64_t em_info; - /* tcam_info is 64 b */ - uint64_t tcam_info; - /* vfp_tcam_info is 64 b */ - uint64_t vfp_tcam_info; - /* ar_id is 16 b */ - uint16_t ar_id; - /* flow_handle is 16 b */ - uint16_t flow_handle; - /* tunnel_handle is 32 b */ - uint32_t tunnel_handle; - /* The flow aging timer for the flow, the unit is 100 milliseconds */ - uint16_t flow_timer; - uint8_t unused_0[6]; - /* Flow associated L2, L3 and L4 headers info. */ - uint32_t flow_key_data[130]; - /* Flow associated action record info. */ - uint32_t flow_action_info[30]; - uint8_t unused_1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -44440,16 +47801,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_flow_info_output_t, *phwrm_cfa_flow_info_output_t; +} hwrm_cfa_meter_profile_cfg_output_t, *phwrm_cfa_meter_profile_cfg_output_t; -/*********************** - * hwrm_cfa_flow_flush * - ***********************/ +/********************************* + * hwrm_cfa_meter_instance_alloc * + *********************************/ -/* hwrm_cfa_flow_flush_input (size:256b/32B) */ +/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */ -typedef struct hwrm_cfa_flow_flush_input { +typedef struct hwrm_cfa_meter_instance_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44478,95 +47839,50 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* flags is 32 b */ - uint32_t flags; + uint8_t flags; /* - * Set to 1 to indicate the page size, page layers, and - * flow_handle_table_dma_addr fields are valid. The flow flush - * operation should only flush the flows from the flow table - * specified. This flag is set to 0 by older driver. For older - * firmware, setting this flag has no effect. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; /* - * Set to 1 to indicate flow flush operation to cleanup all the - * flows, meters, CFA context memory tables etc. This flag is set to - * 0 by older driver. For older firmware, setting this flag has no - * effect. + * A value of 0xffff is considered invalid and implies the + * profile is not configured. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL UINT32_C(0x2) + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID + uint8_t unused_1[4]; +} hwrm_cfa_meter_instance_alloc_input_t, *phwrm_cfa_meter_instance_alloc_input_t; + +/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */ + +typedef struct hwrm_cfa_meter_instance_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value identifies a meter instance in CFA. */ + uint16_t meter_instance_id; /* - * Set to 1 to indicate flow flush operation to cleanup all the - * flows by the caller. This flag is set to 0 by older driver. For - * older firmware, setting this flag has no effect. - */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT UINT32_C(0x4) - /* - * Set to 1 to indicate the flow counter IDs are included in the - * flow table. - */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC UINT32_C(0x8000000) - /* - * This specifies the size of flow handle entries provided by the - * driver in the flow table specified below. Only two flow handle - * size enums are defined. - */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK UINT32_C(0xc0000000) - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT 30 - /* The flow handle is 16bit */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT (UINT32_C(0x0) << 30) - /* The flow handle is 64bit */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT (UINT32_C(0x1) << 30) - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT - /* Specify page size of the flow table memory. */ - uint8_t page_size; - /* The page size is 4K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* The page size is 8K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* The page size is 64K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* The page size is 256K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* The page size is 1M */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* The page size is 2M */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* The page size is 4M */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* The page size is 1G */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G - /* FLow table memory indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * A value of 0xffff is considered invalid and implies the + * instance is not configured. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 - /* number of flows in the flow table */ - uint16_t num_flows; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; -} hwrm_cfa_flow_flush_input_t, *phwrm_cfa_flow_flush_input_t; - -/* hwrm_cfa_flow_flush_output (size:128b/16B) */ - -typedef struct hwrm_cfa_flow_flush_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -44576,16 +47892,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_flow_flush_output_t, *phwrm_cfa_flow_flush_output_t; +} hwrm_cfa_meter_instance_alloc_output_t, *phwrm_cfa_meter_instance_alloc_output_t; -/*********************** - * hwrm_cfa_flow_stats * - ***********************/ +/******************************* + * hwrm_cfa_meter_instance_cfg * + *******************************/ -/* hwrm_cfa_flow_stats_input (size:640b/80B) */ +/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */ -typedef struct hwrm_cfa_flow_stats_input { +typedef struct hwrm_cfa_meter_instance_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44614,94 +47930,41 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Number of valid flows in this command. */ - uint16_t num_flows; - /* - * Flow handle. - * For a listing of applicable flow_handle_0 values, see enumeration - * in hwrm_cfa_flow_info_input. - */ - uint16_t flow_handle_0; - /* - * Flow handle. - * For a listing of applicable flow_handle_1 values, see enumeration - * in hwrm_cfa_flow_info_input. - */ - uint16_t flow_handle_1; - /* - * Flow handle. - * For a listing of applicable flow_handle_2 values, see enumeration - * in hwrm_cfa_flow_info_input. - */ - uint16_t flow_handle_2; - /* - * Flow handle. - * For a listing of applicable flow_handle_3 values, see enumeration - * in hwrm_cfa_flow_info_input. - */ - uint16_t flow_handle_3; - /* - * Flow handle. - * For a listing of applicable flow_handle_4 values, see enumeration - * in hwrm_cfa_flow_info_input. - */ - uint16_t flow_handle_4; - /* - * Flow handle. - * For a listing of applicable flow_handle_5 values, see enumeration - * in hwrm_cfa_flow_info_input. - */ - uint16_t flow_handle_5; + uint8_t flags; /* - * Flow handle. - * For a listing of applicable flow_handle_6 values, see enumeration - * in hwrm_cfa_flow_info_input. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - uint16_t flow_handle_6; + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX + uint8_t unused_0; /* - * Flow handle. - * For a listing of applicable flow_handle_7 values, see enumeration - * in hwrm_cfa_flow_info_input. + * This value identifies a new meter profile to be associated with + * the meter instance specified in this command. */ - uint16_t flow_handle_7; + uint16_t meter_profile_id; /* - * Flow handle. - * For a listing of applicable flow_handle_8 values, see enumeration - * in hwrm_cfa_flow_info_input. + * A value of 0xffff is considered invalid and implies the + * profile is not configured. */ - uint16_t flow_handle_8; + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID /* - * Flow handle. - * For a listing of applicable flow_handle_9 values, see enumeration - * in hwrm_cfa_flow_info_input. + * This value identifies the ID of a meter instance that needs to be + * updated with a new meter profile specified in this command. */ - uint16_t flow_handle_9; - uint8_t unused_0[2]; - /* Flow ID of a flow. */ - uint32_t flow_id_0; - /* Flow ID of a flow. */ - uint32_t flow_id_1; - /* Flow ID of a flow. */ - uint32_t flow_id_2; - /* Flow ID of a flow. */ - uint32_t flow_id_3; - /* Flow ID of a flow. */ - uint32_t flow_id_4; - /* Flow ID of a flow. */ - uint32_t flow_id_5; - /* Flow ID of a flow. */ - uint32_t flow_id_6; - /* Flow ID of a flow. */ - uint32_t flow_id_7; - /* Flow ID of a flow. */ - uint32_t flow_id_8; - /* Flow ID of a flow. */ - uint32_t flow_id_9; -} hwrm_cfa_flow_stats_input_t, *phwrm_cfa_flow_stats_input_t; + uint16_t meter_instance_id; + uint8_t unused_1[2]; +} hwrm_cfa_meter_instance_cfg_input_t, *phwrm_cfa_meter_instance_cfg_input_t; -/* hwrm_cfa_flow_stats_output (size:1408b/176B) */ +/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */ -typedef struct hwrm_cfa_flow_stats_output { +typedef struct hwrm_cfa_meter_instance_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -44710,56 +47973,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* packet_0 is 64 b */ - uint64_t packet_0; - /* packet_1 is 64 b */ - uint64_t packet_1; - /* packet_2 is 64 b */ - uint64_t packet_2; - /* packet_3 is 64 b */ - uint64_t packet_3; - /* packet_4 is 64 b */ - uint64_t packet_4; - /* packet_5 is 64 b */ - uint64_t packet_5; - /* packet_6 is 64 b */ - uint64_t packet_6; - /* packet_7 is 64 b */ - uint64_t packet_7; - /* packet_8 is 64 b */ - uint64_t packet_8; - /* packet_9 is 64 b */ - uint64_t packet_9; - /* byte_0 is 64 b */ - uint64_t byte_0; - /* byte_1 is 64 b */ - uint64_t byte_1; - /* byte_2 is 64 b */ - uint64_t byte_2; - /* byte_3 is 64 b */ - uint64_t byte_3; - /* byte_4 is 64 b */ - uint64_t byte_4; - /* byte_5 is 64 b */ - uint64_t byte_5; - /* byte_6 is 64 b */ - uint64_t byte_6; - /* byte_7 is 64 b */ - uint64_t byte_7; - /* byte_8 is 64 b */ - uint64_t byte_8; - /* byte_9 is 64 b */ - uint64_t byte_9; - /* - * If a flow has been hit, the bit representing the flow will be 1. - * Likewise, if a flow has not, the bit representing the flow - * will be 0. Mapping will match flow numbers where bitX is for flowX - * (ex: bit 0 is flow0). This only applies for NIC flows. Upon - * reading of the flow, the bit will be cleared for the flow and only - * set again when traffic is received by the flow. - */ - uint16_t flow_hits; - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -44769,16 +47983,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_flow_stats_output_t, *phwrm_cfa_flow_stats_output_t; +} hwrm_cfa_meter_instance_cfg_output_t, *phwrm_cfa_meter_instance_cfg_output_t; -/*********************************** - * hwrm_cfa_flow_aging_timer_reset * - ***********************************/ +/******************************** + * hwrm_cfa_meter_instance_free * + ********************************/ -/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */ +/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */ -typedef struct hwrm_cfa_flow_aging_timer_reset_input { +typedef struct hwrm_cfa_meter_instance_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44807,21 +48021,33 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow record index. */ - uint16_t flow_handle; - uint8_t unused_0[2]; + uint8_t flags; /* - * New flow timer value for the flow specified in the ext_flow_handle. - * The flow timer unit is 100ms. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - uint32_t flow_timer; - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; -} hwrm_cfa_flow_aging_timer_reset_input_t, *phwrm_cfa_flow_aging_timer_reset_input_t; + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* This value identifies a meter instance in CFA. */ + uint16_t meter_instance_id; + /* + * A value of 0xfff is considered invalid and implies the + * instance is not configured. + */ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID + uint8_t unused_1[4]; +} hwrm_cfa_meter_instance_free_input_t, *phwrm_cfa_meter_instance_free_input_t; -/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */ +/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_flow_aging_timer_reset_output { +typedef struct hwrm_cfa_meter_instance_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -44840,16 +48066,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_flow_aging_timer_reset_output_t, *phwrm_cfa_flow_aging_timer_reset_output_t; +} hwrm_cfa_meter_instance_free_output_t, *phwrm_cfa_meter_instance_free_output_t; -/*************************** - * hwrm_cfa_flow_aging_cfg * - ***************************/ +/******************************* + * hwrm_cfa_decap_filter_alloc * + *******************************/ -/* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */ +/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ -typedef struct hwrm_cfa_flow_aging_cfg_input { +typedef struct hwrm_cfa_decap_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -44878,366 +48104,243 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The bit field to enable per flow aging configuration. */ - uint16_t enables; - /* - * This bit must be '1' for the tcp flow timer field to be - * configured - */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER UINT32_C(0x1) + uint32_t flags; + /* ovs_tunnel is 1 b */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL UINT32_C(0x1) + uint32_t enables; /* - * This bit must be '1' for the tcp finish timer field to be - * configured + * This bit must be '1' for the tunnel_type field to be + * configured. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER UINT32_C(0x2) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x1) /* - * This bit must be '1' for the udp flow timer field to be - * configured + * This bit must be '1' for the tunnel_id field to be + * configured. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER UINT32_C(0x4) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x2) /* - * This bit must be '1' for the eem dma interval field to be - * configured + * This bit must be '1' for the src_macaddr field to be + * configured. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL UINT32_C(0x8) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x4) /* - * This bit must be '1' for the eem notice interval field to be - * configured + * This bit must be '1' for the dst_macaddr field to be + * configured. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL UINT32_C(0x10) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x8) /* - * This bit must be '1' for the eem context memory maximum entries - * field to be configured + * This bit must be '1' for the ovlan_vid field to be + * configured. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES UINT32_C(0x20) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x10) /* - * This bit must be '1' for the eem context memory ID field to be - * configured + * This bit must be '1' for the ivlan_vid field to be + * configured. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID UINT32_C(0x40) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x20) /* - * This bit must be '1' for the eem context memory type field to be - * configured + * This bit must be '1' for the t_ovlan_vid field to be + * configured. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE UINT32_C(0x80) - uint8_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID UINT32_C(0x40) /* - * Enumeration denoting the enable, disable eem flow aging - * configuration. + * This bit must be '1' for the t_ivlan_vid field to be + * configured. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE (UINT32_C(0x0) << 1) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE (UINT32_C(0x1) << 1) - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE - uint8_t unused_0; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID UINT32_C(0x80) /* - * The flow aging timer for all TCP flows, the unit is 100 - * milliseconds. + * This bit must be '1' for the ethertype field to be + * configured. */ - uint32_t tcp_flow_timer; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x100) /* - * The TCP finished timer for all TCP flows, the unit is 100 - * milliseconds. + * This bit must be '1' for the src_ipaddr field to be + * configured. */ - uint32_t tcp_fin_timer; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x200) /* - * The flow aging timer for all UDP flows, the unit is 100 - * milliseconds. + * This bit must be '1' for the dst_ipaddr field to be + * configured. */ - uint32_t udp_flow_timer; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x400) /* - * The interval to dma eem ejection data to host memory, the unit is - * milliseconds. + * This bit must be '1' for the ipaddr_type field to be + * configured. */ - uint16_t eem_dma_interval; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x800) /* - * The interval to notify driver to read the eem ejection data, the - * unit is milliseconds. + * This bit must be '1' for the ip_protocol field to be + * configured. */ - uint16_t eem_notice_interval; - /* The maximum entries number in the eem context memory. */ - uint32_t eem_ctx_max_entries; - /* The context memory ID for eem flow aging. */ - uint16_t eem_ctx_id; - uint16_t eem_ctx_mem_type; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x1000) /* - * The content of context memory is eem ejection data, the size of - * each entry is 4 bytes. + * This bit must be '1' for the src_port field to be + * configured. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA UINT32_C(0x0) - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA - uint8_t unused_1[4]; -} hwrm_cfa_flow_aging_cfg_input_t, *phwrm_cfa_flow_aging_cfg_input_t; - -/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */ - -typedef struct hwrm_cfa_flow_aging_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x2000) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * This bit must be '1' for the dst_port field to be + * configured. */ - uint8_t valid; -} hwrm_cfa_flow_aging_cfg_output_t, *phwrm_cfa_flow_aging_cfg_output_t; - -/**************************** - * hwrm_cfa_flow_aging_qcfg * - ****************************/ - - -/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */ - -typedef struct hwrm_cfa_flow_aging_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x4000) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This bit must be '1' for the dst_id field to be + * configured. */ - uint16_t cmpl_ring; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit must be '1' for the mirror_vnic_id field to be + * configured. */ - uint16_t seq_id; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Tunnel identifier. + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. */ - uint16_t target_id; + uint32_t tunnel_id; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - uint64_t resp_addr; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) /* - * The direction for the flow aging configuration, 1 is rx path, 2 is - * tx path. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - uint8_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX - uint8_t unused_0[7]; -} hwrm_cfa_flow_aging_qcfg_input_t, *phwrm_cfa_flow_aging_qcfg_input_t; - -/* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */ - -typedef struct hwrm_cfa_flow_aging_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * The current flow aging timer for all TCP flows, the unit is 100 - * millisecond. - */ - uint32_t tcp_flow_timer; - /* - * The current TCP finished timer for all TCP flows, the unit is 100 - * millisecond. - */ - uint32_t tcp_fin_timer; - /* - * The current flow aging timer for all UDP flows, the unit is 100 - * millisecond. - */ - uint32_t udp_flow_timer; - /* - * The interval to dma eem ejection data to host memory, the unit is - * milliseconds. - */ - uint16_t eem_dma_interval; - /* - * The interval to notify driver to read the eem ejection data, the - * unit is milliseconds. - */ - uint16_t eem_notice_interval; - /* The maximum entries number in the eem context memory. */ - uint32_t eem_ctx_max_entries; - /* The context memory ID for eem flow aging. */ - uint16_t eem_ctx_id; - /* The context memory type for eem flow aging. */ - uint16_t eem_ctx_mem_type; - uint8_t unused_0[7]; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + /* Any tunneled traffic */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0; + uint16_t unused_1; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * This value indicates the source MAC address in + * the Ethernet header. */ - uint8_t valid; -} hwrm_cfa_flow_aging_qcfg_output_t, *phwrm_cfa_flow_aging_qcfg_output_t; - -/***************************** - * hwrm_cfa_flow_aging_qcaps * - *****************************/ - - -/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */ - -typedef struct hwrm_cfa_flow_aging_qcaps_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint8_t src_macaddr[6]; + uint8_t unused_2[2]; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This value indicates the destination MAC address in + * the Ethernet header. */ - uint16_t cmpl_ring; + uint8_t dst_macaddr[6]; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This value indicates the VLAN ID of the outer VLAN tag + * in the Ethernet header. */ - uint16_t seq_id; + uint16_t ovlan_vid; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This value indicates the VLAN ID of the inner VLAN tag + * in the Ethernet header. */ - uint16_t target_id; + uint16_t ivlan_vid; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This value indicates the VLAN ID of the outer VLAN tag + * in the tunnel Ethernet header. */ - uint64_t resp_addr; + uint16_t t_ovlan_vid; /* - * The direction for the flow aging configuration, 1 is rx path, 2 is - * tx path. + * This value indicates the VLAN ID of the inner VLAN tag + * in the tunnel Ethernet header. */ - uint8_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX - uint8_t unused_0[7]; -} hwrm_cfa_flow_aging_qcaps_input_t, *phwrm_cfa_flow_aging_qcaps_input_t; - -/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */ - -typedef struct hwrm_cfa_flow_aging_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + uint16_t t_ivlan_vid; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; /* - * The maximum flow aging timer for all TCP flows, the unit is 100 - * millisecond. + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. */ - uint32_t max_tcp_flow_timer; + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * The maximum TCP finished timer for all TCP flows, the unit is 100 - * millisecond. + * The value of protocol field in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP */ - uint32_t max_tcp_fin_timer; + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP + uint16_t unused_3; + uint32_t unused_4; /* - * The maximum flow aging timer for all UDP flows, the unit is 100 - * millisecond. + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - uint32_t max_udp_flow_timer; - /* The maximum aging flows that HW can support. */ - uint32_t max_aging_flows; - uint8_t unused_0[7]; + uint32_t src_ipaddr[4]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - uint8_t valid; -} hwrm_cfa_flow_aging_qcaps_output_t, *phwrm_cfa_flow_aging_qcaps_output_t; - -/********************************** - * hwrm_cfa_tcp_flag_process_qcfg * - **********************************/ - - -/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */ - -typedef struct hwrm_cfa_tcp_flag_process_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint32_t dst_ipaddr[4]; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint16_t cmpl_ring; + uint16_t src_port; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint16_t seq_id; + uint16_t dst_port; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path. */ - uint16_t target_id; + uint16_t dst_id; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If set, this value shall represent the L2 context that matches the + * L2 information of the decap filter. */ - uint64_t resp_addr; -} hwrm_cfa_tcp_flag_process_qcfg_input_t, *phwrm_cfa_tcp_flag_process_qcfg_input_t; + uint16_t l2_ctxt_ref_id; +} hwrm_cfa_decap_filter_alloc_input_t, *phwrm_cfa_decap_filter_alloc_input_t; -/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */ +/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ -typedef struct hwrm_cfa_tcp_flag_process_qcfg_output { +typedef struct hwrm_cfa_decap_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -45246,21 +48349,9 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The port 0 RX mirror action record ID. */ - uint16_t rx_ar_id_port0; - /* The port 1 RX mirror action record ID. */ - uint16_t rx_ar_id_port1; - /* - * The port 0 RX action record ID for TX TCP flag packets from - * loopback path. - */ - uint16_t tx_ar_id_port0; - /* - * The port 1 RX action record ID for TX TCP flag packets from - * loopback path. - */ - uint16_t tx_ar_id_port1; - uint8_t unused_0[7]; + /* This value is an opaque id into CFA data structures. */ + uint32_t decap_filter_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -45270,16 +48361,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_tcp_flag_process_qcfg_output_t, *phwrm_cfa_tcp_flag_process_qcfg_output_t; +} hwrm_cfa_decap_filter_alloc_output_t, *phwrm_cfa_decap_filter_alloc_output_t; -/************************** - * hwrm_cfa_vf_pair_alloc * - **************************/ +/****************************** + * hwrm_cfa_decap_filter_free * + ******************************/ -/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */ +/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ -typedef struct hwrm_cfa_vf_pair_alloc_input { +typedef struct hwrm_cfa_decap_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -45308,18 +48399,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_a_id; - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_b_id; + /* This value is an opaque id into CFA data structures. */ + uint32_t decap_filter_id; uint8_t unused_0[4]; - /* VF Pair name (32 byte string). */ - char pair_name[32]; -} hwrm_cfa_vf_pair_alloc_input_t, *phwrm_cfa_vf_pair_alloc_input_t; +} hwrm_cfa_decap_filter_free_input_t, *phwrm_cfa_decap_filter_free_input_t; -/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */ +/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_vf_pair_alloc_output { +typedef struct hwrm_cfa_decap_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -45338,16 +48425,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_vf_pair_alloc_output_t, *phwrm_cfa_vf_pair_alloc_output_t; +} hwrm_cfa_decap_filter_free_output_t, *phwrm_cfa_decap_filter_free_output_t; -/************************* - * hwrm_cfa_vf_pair_free * - *************************/ +/*********************** + * hwrm_cfa_flow_alloc * + ***********************/ -/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */ +/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ -typedef struct hwrm_cfa_vf_pair_free_input { +typedef struct hwrm_cfa_flow_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -45376,263 +48463,227 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* VF Pair name (32 byte string). */ - char pair_name[32]; -} hwrm_cfa_vf_pair_free_input_t, *phwrm_cfa_vf_pair_free_input_t; - -/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */ - -typedef struct hwrm_cfa_vf_pair_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. - */ - uint8_t valid; -} hwrm_cfa_vf_pair_free_output_t, *phwrm_cfa_vf_pair_free_output_t; - -/************************* - * hwrm_cfa_vf_pair_info * - *************************/ - - -/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */ - -typedef struct hwrm_cfa_vf_pair_info_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint16_t flags; + /* tunnel is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1) + /* num_vlan is 2 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1 + /* no tags */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE (UINT32_C(0x0) << 1) + /* 1 tag */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE (UINT32_C(0x1) << 1) + /* 2 tags */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO (UINT32_C(0x2) << 1) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO + /* Enumeration denoting the Flow Type. */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3 + /* L2 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 (UINT32_C(0x0) << 3) + /* IPV4 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 (UINT32_C(0x1) << 3) + /* IPV6 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 (UINT32_C(0x2) << 3) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * when set to 1, indicates TX flow offload for function specified + * in src_fid and the dst_fid should be set to invalid value. To + * indicate a VM to VM flow, both of the path_tx and path_rx flags + * need to be set. For virtio vSwitch offload case, the src_fid and + * dst_fid is set to the same fid value. For the SRIOV vSwitch + * offload case, the src_fid and dst_fid must be set to the same VF + * FID belong to the children VFs of the same PF to indicate VM to + * VM flow. */ - uint16_t cmpl_ring; + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x40) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * when set to 1, indicates RX flow offload for function specified + * in dst_fid and the src_fid should be set to invalid value. */ - uint16_t seq_id; + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x80) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan + * header is required and the VXLAN VNI value is stored in the first + * 24 bits of the dmac field. This flag is only valid when the flow + * direction is RX. */ - uint16_t target_id; + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI UINT32_C(0x100) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci + * field. */ - uint64_t resp_addr; - uint32_t flags; - /* If this flag is set, lookup by name else lookup by index. */ - #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) - /* vf pair table index. */ - uint16_t vf_pair_index; - uint8_t unused_0[2]; - /* VF Pair name (32 byte string). */ - char vf_pair_name[32]; -} hwrm_cfa_vf_pair_info_input_t, *phwrm_cfa_vf_pair_info_input_t; - -/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */ - -typedef struct hwrm_cfa_vf_pair_info_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* vf pair table index. */ - uint16_t next_vf_pair_index; - /* vf pair member a's vf_fid. */ - uint16_t vf_a_fid; - /* vf pair member a's Linux logical VF number. */ - uint16_t vf_a_index; - /* vf pair member b's vf_fid. */ - uint16_t vf_b_fid; - /* vf pair member a's Linux logical VF number. */ - uint16_t vf_b_index; - /* vf pair state. */ - uint8_t pair_state; - /* Pair has been allocated */ - #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) - /* Both pair members are active */ - #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) - #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE - uint8_t unused_0[5]; - /* VF Pair name (32 byte string). */ - char pair_name[32]; - uint8_t unused_1[7]; + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN UINT32_C(0x200) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * Tx Flow: vf fid. + * Rx Flow: pf fid. */ - uint8_t valid; -} hwrm_cfa_vf_pair_info_output_t, *phwrm_cfa_vf_pair_info_output_t; - -/*********************** - * hwrm_cfa_pair_alloc * - ***********************/ - - -/* hwrm_cfa_pair_alloc_input (size:576b/72B) */ - -typedef struct hwrm_cfa_pair_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint16_t src_fid; + /* Tunnel handle valid when tunnel flag is set. */ + uint32_t tunnel_handle; + uint16_t action_flags; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ - uint16_t cmpl_ring; + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD UINT32_C(0x1) + /* recycle is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE UINT32_C(0x2) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Setting of this flag indicates drop action. If this flag is not + * set, then it should be considered accept action. */ - uint16_t seq_id; + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP UINT32_C(0x4) + /* meter is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER UINT32_C(0x8) + /* tunnel is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL UINT32_C(0x10) + /* nat_src is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC UINT32_C(0x20) + /* nat_dest is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST UINT32_C(0x40) + /* nat_ipv4_address is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS UINT32_C(0x80) + /* l2_header_rewrite is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE UINT32_C(0x100) + /* ttl_decrement is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT UINT32_C(0x200) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * If set to 1 and flow direction is TX, it indicates decap of L2 + * header and encap of tunnel header. If set to 1 and flow direction + * is RX, it indicates decap of tunnel header and encap L2 header. + * The type of tunnel is specified in the tunnel_type field. */ - uint16_t target_id; + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP UINT32_C(0x400) + /* If set to 1, flow aging is enabled for this flow. */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED UINT32_C(0x800) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If set to 1 an attempt will be made to try to offload this flow + * to the most optimal flow table resource. If set to 0, the flow + * will be placed to the default flow table resource. */ - uint64_t resp_addr; + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT UINT32_C(0x1000) /* - * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, - * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). - */ - uint16_t pair_mode; - /* - * Pair between VF on local host with PF or VF on specified host. - * (deprecated) - */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0) - /* - * Pair between REP on local host with PF or VF on specified host. - * (deprecated) - */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1) - /* - * Pair between REP on local host with REP on specified host. - * (deprecated) - */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2) - /* Pair for the proxy interface. (deprecated) */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY UINT32_C(0x3) - /* Pair for the PF interface. (deprecated) */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) - /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5) - /* - * Modify existing rep2fn pairs paired with same PF and move pairs - * to new PF. (deprecated) + * If set to 1 there will be no attempt to allocate an on-chip try + * to offload this flow. If set to 0, which will keep compatibility + * with the older drivers, will cause the FW to attempt to allocate + * an on-chip flow counter for the newly created flow. This will + * keep the existing behavior with EM flows which always had an + * associated flow counter. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6) + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC UINT32_C(0x2000) /* - * Truflow pair between REP on local host with PF or VF on specified - * host. + * Tx Flow: pf or vf fid. + * Rx Flow: vf fid. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7) - #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_a_id; - /* Logical Host (0xff-local host). */ - uint8_t host_b_id; - /* Logical PF (0xff-PF for command channel). */ - uint8_t pf_b_id; - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_b_id; - /* Loopback port (0xff-internal loopback), valid for mode-3. */ - uint8_t port_id; - /* Priority used for encap of loopback packets valid for mode-3. */ - uint8_t pri; - /* New PF for rep2fn modify, valid for mode 5. */ - uint16_t new_pf_fid; - uint32_t enables; + uint16_t dst_fid; + /* VLAN tpid, valid when push_vlan flag is set. */ + uint16_t l2_rewrite_vlan_tpid; + /* VLAN tci, valid when push_vlan flag is set. */ + uint16_t l2_rewrite_vlan_tci; + /* Meter id, valid when meter flag is set. */ + uint16_t act_meter_id; + /* Flow with the same l2 context tcam key. */ + uint16_t ref_flow_handle; + /* This value sets the match value for the ethertype. */ + uint16_t ethertype; + /* valid when num tags is 1 or 2. */ + uint16_t outer_vlan_tci; + /* This value sets the match value for the Destination MAC address. */ + uint16_t dmac[3]; + /* valid when num tags is 2. */ + uint16_t inner_vlan_tci; + /* This value sets the match value for the Source MAC address. */ + uint16_t smac[3]; + /* The bit length of destination IP address mask. */ + uint8_t ip_dst_mask_len; + /* The bit length of source IP address mask. */ + uint8_t ip_src_mask_len; + /* The value of destination IPv4/IPv6 address. */ + uint32_t ip_dst[4]; + /* The source IPv4/IPv6 address. */ + uint32_t ip_src[4]; /* - * This bit must be '1' for the q_ab field to be - * configured. + * The value of source port. + * Applies to UDP and TCP traffic. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1) + uint16_t l4_src_port; /* - * This bit must be '1' for the q_ba field to be - * configured. + * The value of source port mask. + * Applies to UDP and TCP traffic. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2) + uint16_t l4_src_port_mask; /* - * This bit must be '1' for the fc_ab field to be - * configured. + * The value of destination port. + * Applies to UDP and TCP traffic. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4) + uint16_t l4_dst_port; /* - * This bit must be '1' for the fc_ba field to be - * configured. + * The value of destination port mask. + * Applies to UDP and TCP traffic. */ - #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8) - /* VF Pair name (32 byte string). */ - char pair_name[32]; + uint16_t l4_dst_port_mask; /* - * The q_ab value specifies the logical index of the TX/RX CoS - * queue to be assigned for traffic in the A to B direction of - * the interface pair. The default value is 0. + * NAT IPv4/6 address based on address type flag. + * 0 values are ignored. */ - uint8_t q_ab; + uint32_t nat_ip_address[4]; + /* L2 header re-write Destination MAC address. */ + uint16_t l2_rewrite_dmac[3]; /* - * The q_ba value specifies the logical index of the TX/RX CoS - * queue to be assigned for traffic in the B to A direction of - * the interface pair. The default value is 1. + * The NAT source/destination port based on direction flag. + * Applies to UDP and TCP traffic. + * 0 values are ignored. */ - uint8_t q_ba; + uint16_t nat_port; + /* L2 header re-write Source MAC address. */ + uint16_t l2_rewrite_smac[3]; + /* The value of ip protocol. */ + uint8_t ip_proto; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) /* - * Specifies whether RX ring flow control is disabled (0) or enabled - * (1) in the A to B direction. The default value is 0, meaning that - * packets will be dropped when the B-side RX rings are full. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - uint8_t fc_ab; + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) /* - * Specifies whether RX ring flow control is disabled (0) or enabled - * (1) in the B to A direction. The default value is 1, meaning that - * the RX CoS queue will be flow controlled when the A-side RX rings - * are full. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - uint8_t fc_ba; - uint8_t unused_1[4]; -} hwrm_cfa_pair_alloc_input_t, *phwrm_cfa_pair_alloc_input_t; + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + /* Any tunneled traffic */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL +} hwrm_cfa_flow_alloc_input_t, *phwrm_cfa_flow_alloc_input_t; -/* hwrm_cfa_pair_alloc_output (size:192b/24B) */ +/* hwrm_cfa_flow_alloc_output (size:256b/32B) */ -typedef struct hwrm_cfa_pair_alloc_output { +typedef struct hwrm_cfa_flow_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -45641,15 +48692,44 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Only valid for modes 1 and 2. */ - uint16_t rx_cfa_code_a; - /* Only valid for modes 1 and 2. */ - uint16_t tx_cfa_action_a; - /* Only valid for mode 2. */ - uint16_t rx_cfa_code_b; - /* Only valid for mode 2. */ - uint16_t tx_cfa_action_b; - uint8_t unused_0[7]; + /* Flow record index. */ + uint16_t flow_handle; + uint8_t unused_0[2]; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; + uint32_t flow_counter_id; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -45659,16 +48739,44 @@ * written last. */ uint8_t valid; -} hwrm_cfa_pair_alloc_output_t, *phwrm_cfa_pair_alloc_output_t; +} hwrm_cfa_flow_alloc_output_t, *phwrm_cfa_flow_alloc_output_t; + +/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ + +typedef struct hwrm_cfa_flow_alloc_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* No more L2 Context TCAM */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1) + /* No more action records */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2) + /* No more flow counters */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3) + /* No more wild-card TCAM */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4) + /* Hash collision in exact match tables */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5) + /* Key is already installed */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6) + /* Flow Context DB is out of resource */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7) + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB + uint8_t unused_0[7]; +} hwrm_cfa_flow_alloc_cmd_err_t, *phwrm_cfa_flow_alloc_cmd_err_t; /********************** - * hwrm_cfa_pair_free * + * hwrm_cfa_flow_free * **********************/ -/* hwrm_cfa_pair_free_input (size:448b/56B) */ +/* hwrm_cfa_flow_free_input (size:256b/32B) */ -typedef struct hwrm_cfa_pair_free_input { +typedef struct hwrm_cfa_flow_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -45697,55 +48805,18 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* VF Pair name (32 byte string). */ - char pair_name[32]; - /* Logical PF (0xff-PF for command channel). */ - uint8_t pf_b_id; - uint8_t unused_0[3]; - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_id; - /* - * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, - * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). - */ - uint16_t pair_mode; - /* - * Pair between VF on local host with PF or VF on specified host. - * (deprecated) - */ - #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0) - /* - * Pair between REP on local host with PF or VF on specified host. - * (deprecated) - */ - #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1) - /* - * Pair between REP on local host with REP on specified host. - * (deprecated) - */ - #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2) - /* Pair for the proxy interface. (deprecated) */ - #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3) - /* Pair for the PF interface. (deprecated) */ - #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) - /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */ - #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5) - /* - * Modify existing rep2fn pairs paired with same PF and move pairs - * to new PF. (deprecated) - */ - #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6) - /* - * Truflow pair between REP on local host with PF or VF on - * specified host. - */ - #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7) - #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW -} hwrm_cfa_pair_free_input_t, *phwrm_cfa_pair_free_input_t; + /* Flow record index. */ + uint16_t flow_handle; + uint16_t unused_0; + /* Flow counter id to be freed. */ + uint32_t flow_counter_id; + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; +} hwrm_cfa_flow_free_input_t, *phwrm_cfa_flow_free_input_t; -/* hwrm_cfa_pair_free_output (size:128b/16B) */ +/* hwrm_cfa_flow_free_output (size:256b/32B) */ -typedef struct hwrm_cfa_pair_free_output { +typedef struct hwrm_cfa_flow_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -45754,6 +48825,10 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* packet is 64 b */ + uint64_t packet; + /* byte is 64 b */ + uint64_t byte; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -45764,147 +48839,235 @@ * written last. */ uint8_t valid; -} hwrm_cfa_pair_free_output_t, *phwrm_cfa_pair_free_output_t; - -/********************** - * hwrm_cfa_pair_info * - **********************/ - +} hwrm_cfa_flow_free_output_t, *phwrm_cfa_flow_free_output_t; -/* hwrm_cfa_pair_info_input (size:448b/56B) */ +/* hwrm_cfa_flow_action_data (size:960b/120B) */ -typedef struct hwrm_cfa_pair_info_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; +typedef struct hwrm_cfa_flow_action_data { + uint16_t action_flags; + /* Setting of this flag indicates accept action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD UINT32_C(0x1) + /* Setting of this flag indicates recycle action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE UINT32_C(0x2) + /* Setting of this flag indicates drop action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP UINT32_C(0x4) + /* Setting of this flag indicates meter action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER UINT32_C(0x8) + /* Setting of this flag indicates tunnel action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL UINT32_C(0x10) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * If set to 1 and flow direction is TX, it indicates decap of L2 + * header and encap of tunnel header. If set to 1 and flow direction + * is RX, it indicates decap of tunnel header and encap L2 header. */ - uint16_t seq_id; + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP UINT32_C(0x20) + /* Setting of this flag indicates ttl decrement action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT UINT32_C(0x40) + /* If set to 1, flow aging is enabled for this flow. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED UINT32_C(0x80) + /* Setting of this flag indicates encap action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP UINT32_C(0x100) + /* Setting of this flag indicates decap action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP UINT32_C(0x200) + /* Meter id. */ + uint16_t act_meter_id; + /* VNIC id. */ + uint16_t vnic_id; + /* vport number. */ + uint16_t vport_id; + /* The NAT source/destination. */ + uint16_t nat_port; + uint16_t unused_0[3]; + /* NAT IPv4/IPv6 address. */ + uint32_t nat_ip_address[4]; + /* Encapsulation Type. */ + uint8_t encap_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6) + /* VLAN */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - uint16_t target_id; + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - uint64_t resp_addr; - uint32_t flags; - /* If this flag is set, lookup by name else lookup by index. */ - #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) - /* If this flag is set, lookup by PF id and VF id. */ - #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2) - /* Pair table index. */ - uint16_t pair_index; - /* Pair pf index. */ - uint8_t pair_pfid; - /* Pair vf index. */ - uint8_t pair_vfid; - /* Pair name (32 byte string). */ - char pair_name[32]; -} hwrm_cfa_pair_info_input_t, *phwrm_cfa_pair_info_input_t; + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE UINT32_C(0x10) + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE + uint8_t unused[7]; + /* This value is encap data for the associated encap type. */ + uint32_t encap_data[20]; +} hwrm_cfa_flow_action_data_t, *phwrm_cfa_flow_action_data_t; -/* hwrm_cfa_pair_info_output (size:576b/72B) */ +/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */ -typedef struct hwrm_cfa_pair_info_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Pair table index. */ - uint16_t next_pair_index; - /* Pair member a's fid. */ - uint16_t a_fid; - /* Logical host number. */ - uint8_t host_a_index; - /* Logical PF number. */ - uint8_t pf_a_index; - /* Pair member a's Linux logical VF number. */ - uint16_t vf_a_index; - /* Rx CFA code. */ - uint16_t rx_cfa_code_a; - /* Tx CFA action. */ - uint16_t tx_cfa_action_a; - /* Pair member b's fid. */ - uint16_t b_fid; - /* Logical host number. */ - uint8_t host_b_index; - /* Logical PF number. */ - uint8_t pf_b_index; - /* Pair member a's Linux logical VF number. */ - uint16_t vf_b_index; - /* Rx CFA code. */ - uint16_t rx_cfa_code_b; - /* Tx CFA action. */ - uint16_t tx_cfa_action_b; - /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */ - uint8_t pair_mode; +typedef struct hwrm_cfa_flow_tunnel_hdr_data { + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) /* - * Pair between VF on local host with PF or VF on specified host. - * (deprecated) + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0) + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) /* - * Pair between REP on local host with PF or VF on specified host. - * (deprecated) + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1) + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + /* Any tunneled traffic */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused[3]; /* - * Pair between REP on local host with REP on specified host. - * (deprecated) + * Tunnel identifier. + * Virtual Network Identifier (VNI). */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2) - /* Pair for the proxy interface. (deprecated) */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3) - /* Pair for the PF interface. (deprecated) */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR - /* Pair state. */ - uint8_t pair_state; - /* Pair has been allocated */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) - /* Both pair members are active */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE - /* Pair name (32 byte string). */ - char pair_name[32]; + uint32_t tunnel_id; +} hwrm_cfa_flow_tunnel_hdr_data_t, *phwrm_cfa_flow_tunnel_hdr_data_t; + +/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */ + +typedef struct hwrm_cfa_flow_l4_key_data { + /* The value of source port. */ + uint16_t l4_src_port; + /* The value of destination port. */ + uint16_t l4_dst_port; + uint32_t unused; +} hwrm_cfa_flow_l4_key_data_t, *phwrm_cfa_flow_l4_key_data_t; + +/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */ + +typedef struct hwrm_cfa_flow_l3_key_data { + /* The value of ip protocol. */ + uint8_t ip_protocol; uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. - */ - uint8_t valid; -} hwrm_cfa_pair_info_output_t, *phwrm_cfa_pair_info_output_t; + /* The value of destination IPv4/IPv6 address. */ + uint32_t ip_dst[4]; + /* The source IPv4/IPv6 address. */ + uint32_t ip_src[4]; + /* NAT IPv4/IPv6 address. */ + uint32_t nat_ip_address[4]; + uint64_t unused; +} hwrm_cfa_flow_l3_key_data_t, *phwrm_cfa_flow_l3_key_data_t; + +/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */ + +typedef struct hwrm_cfa_flow_l2_key_data { + /* Destination MAC address. */ + uint16_t dmac[3]; + uint16_t unused_0; + /* Source MAC address. */ + uint16_t smac[3]; + uint16_t unused_1; + /* L2 header re-write Destination MAC address. */ + uint16_t l2_rewrite_dmac[3]; + uint16_t unused_2; + /* L2 header re-write Source MAC address. */ + uint16_t l2_rewrite_smac[3]; + /* Ethertype. */ + uint16_t ethertype; + /* Number of VLAN tags. */ + uint16_t num_vlan_tags; + /* VLAN tpid. */ + uint16_t l2_rewrite_vlan_tpid; + /* VLAN tci. */ + uint16_t l2_rewrite_vlan_tci; + uint8_t unused_3[2]; + /* Outer VLAN TPID. */ + uint16_t ovlan_tpid; + /* Outer VLAN TCI. */ + uint16_t ovlan_tci; + /* Inner VLAN TPID. */ + uint16_t ivlan_tpid; + /* Inner VLAN TCI. */ + uint16_t ivlan_tci; + uint8_t unused[8]; +} hwrm_cfa_flow_l2_key_data_t, *phwrm_cfa_flow_l2_key_data_t; + +/* hwrm_cfa_flow_key_data (size:4160b/520B) */ + +typedef struct hwrm_cfa_flow_key_data { + /* Flow associated tunnel L2 header key info. */ + uint32_t t_l2_key_data[14]; + /* Flow associated tunnel L2 header mask info. */ + uint32_t t_l2_key_mask[14]; + /* Flow associated tunnel L3 header key info. */ + uint32_t t_l3_key_data[16]; + /* Flow associated tunnel L3 header mask info. */ + uint32_t t_l3_key_mask[16]; + /* Flow associated tunnel L4 header key info. */ + uint64_t t_l4_key_data; + /* Flow associated tunnel L4 header mask info. */ + uint64_t t_l4_key_mask; + /* Flow associated tunnel header info. */ + uint64_t tunnel_hdr; + /* Flow associated L2 header key info. */ + uint32_t l2_key_data[14]; + /* Flow associated L2 header mask info. */ + uint32_t l2_key_mask[14]; + /* Flow associated L3 header key info. */ + uint32_t l3_key_data[16]; + /* Flow associated L3 header mask info. */ + uint32_t l3_key_mask[16]; + /* Flow associated L4 header key info. */ + uint64_t l4_key_data; + /* Flow associated L4 header mask info. */ + uint64_t l4_key_mask; +} hwrm_cfa_flow_key_data_t, *phwrm_cfa_flow_key_data_t; /********************** - * hwrm_cfa_vfr_alloc * + * hwrm_cfa_flow_info * **********************/ -/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ +/* hwrm_cfa_flow_info_input (size:256b/32B) */ -typedef struct hwrm_cfa_vfr_alloc_input { +typedef struct hwrm_cfa_flow_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -45933,21 +49096,37 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_id; - /* - * This field is reserved for the future use. - * It shall be set to 0. - */ - uint16_t reserved; - uint8_t unused_0[4]; - /* VF Representor name (32 byte string). */ - char vfr_name[32]; -} hwrm_cfa_vfr_alloc_input_t, *phwrm_cfa_vfr_alloc_input_t; + /* Flow record index. */ + uint16_t flow_handle; + /* Max flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK UINT32_C(0xfff) + /* CNP flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT UINT32_C(0x1000) + /* RoCEv1 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT UINT32_C(0x2000) + /* NIC flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_TX UINT32_C(0x3000) + /* RoCEv2 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT UINT32_C(0x4000) + /* Direction rx = 1 */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX UINT32_C(0x8000) + /* CNP flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT_RX UINT32_C(0x9000) + /* RoCEv1 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT_RX UINT32_C(0xa000) + /* NIC flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_RX UINT32_C(0xb000) + /* RoCEv2 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX UINT32_C(0xc000) + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_LAST HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX + uint8_t unused_0[6]; + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; +} hwrm_cfa_flow_info_input_t, *phwrm_cfa_flow_info_input_t; -/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ +/* hwrm_cfa_flow_info_output (size:5632b/704B) */ -typedef struct hwrm_cfa_vfr_alloc_output { +typedef struct hwrm_cfa_flow_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -45956,11 +49135,39 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Rx CFA code. */ - uint16_t rx_cfa_code; - /* Tx CFA action. */ - uint16_t tx_cfa_action; - uint8_t unused_0[3]; + uint8_t flags; + /* When set to 1, indicates the configuration is the TX flow. */ + #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1) + /* When set to 1, indicates the configuration is the RX flow. */ + #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2) + /* profile is 8 b */ + uint8_t profile; + /* src_fid is 16 b */ + uint16_t src_fid; + /* dst_fid is 16 b */ + uint16_t dst_fid; + /* l2_ctxt_id is 16 b */ + uint16_t l2_ctxt_id; + /* em_info is 64 b */ + uint64_t em_info; + /* tcam_info is 64 b */ + uint64_t tcam_info; + /* vfp_tcam_info is 64 b */ + uint64_t vfp_tcam_info; + /* ar_id is 16 b */ + uint16_t ar_id; + /* flow_handle is 16 b */ + uint16_t flow_handle; + /* tunnel_handle is 32 b */ + uint32_t tunnel_handle; + /* The flow aging timer for the flow, the unit is 100 milliseconds */ + uint16_t flow_timer; + uint8_t unused_0[6]; + /* Flow associated L2, L3 and L4 headers info. */ + uint32_t flow_key_data[130]; + /* Flow associated action record info. */ + uint32_t flow_action_info[30]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -45970,16 +49177,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_vfr_alloc_output_t, *phwrm_cfa_vfr_alloc_output_t; +} hwrm_cfa_flow_info_output_t, *phwrm_cfa_flow_info_output_t; -/********************* - * hwrm_cfa_vfr_free * - *********************/ +/*********************** + * hwrm_cfa_flow_flush * + ***********************/ -/* hwrm_cfa_vfr_free_input (size:448b/56B) */ +/* hwrm_cfa_flow_flush_input (size:256b/32B) */ -typedef struct hwrm_cfa_vfr_free_input { +typedef struct hwrm_cfa_flow_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46008,21 +49215,86 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* VF Representor name (32 byte string). */ - char vfr_name[32]; - /* Logical VF number (range: 0 -> MAX_VFS -1). */ - uint16_t vf_id; + /* flags is 32 b */ + uint32_t flags; /* - * This field is reserved for the future use. - * It shall be set to 0. + * Set to 1 to indicate the page size, page layers, and + * flow_handle_table_dma_addr fields are valid. The flow flush + * operation should only flush the flows from the flow table + * specified. This flag is set to 0 by older driver. For older + * firmware, setting this flag has no effect. */ - uint16_t reserved; - uint8_t unused_0[4]; -} hwrm_cfa_vfr_free_input_t, *phwrm_cfa_vfr_free_input_t; + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID UINT32_C(0x1) + /* + * Set to 1 to indicate flow flush operation to cleanup all the + * flows, meters, CFA context memory tables etc. This flag is set to + * 0 by older driver. For older firmware, setting this flag has no + * effect. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL UINT32_C(0x2) + /* + * Set to 1 to indicate flow flush operation to cleanup all the + * flows by the caller. This flag is set to 0 by older driver. For + * older firmware, setting this flag has no effect. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT UINT32_C(0x4) + /* + * Set to 1 to indicate the flow counter IDs are included in the + * flow table. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC UINT32_C(0x8000000) + /* + * This specifies the size of flow handle entries provided by the + * driver in the flow table specified below. Only two flow handle + * size enums are defined. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK UINT32_C(0xc0000000) + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT 30 + /* The flow handle is 16bit */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT (UINT32_C(0x0) << 30) + /* The flow handle is 64bit */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT (UINT32_C(0x1) << 30) + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT + /* Specify page size of the flow table memory. */ + uint8_t page_size; + /* The page size is 4K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* The page size is 8K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* The page size is 64K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* The page size is 256K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* The page size is 1M */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* The page size is 2M */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* The page size is 4M */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* The page size is 1G */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G + /* FLow table memory indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 + /* number of flows in the flow table */ + uint16_t num_flows; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; +} hwrm_cfa_flow_flush_input_t, *phwrm_cfa_flow_flush_input_t; -/* hwrm_cfa_vfr_free_output (size:128b/16B) */ +/* hwrm_cfa_flow_flush_output (size:128b/16B) */ -typedef struct hwrm_cfa_vfr_free_output { +typedef struct hwrm_cfa_flow_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46041,16 +49313,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_vfr_free_output_t, *phwrm_cfa_vfr_free_output_t; +} hwrm_cfa_flow_flush_output_t, *phwrm_cfa_flow_flush_output_t; -/*************************************** - * hwrm_cfa_redirect_query_tunnel_type * - ***************************************/ +/*********************** + * hwrm_cfa_flow_stats * + ***********************/ -/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */ +/* hwrm_cfa_flow_stats_input (size:640b/80B) */ -typedef struct hwrm_cfa_redirect_query_tunnel_type_input { +typedef struct hwrm_cfa_flow_stats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46079,14 +49351,94 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The source function id. */ - uint16_t src_fid; - uint8_t unused_0[6]; -} hwrm_cfa_redirect_query_tunnel_type_input_t, *phwrm_cfa_redirect_query_tunnel_type_input_t; + /* Number of valid flows in this command. */ + uint16_t num_flows; + /* + * Flow handle. + * For a listing of applicable flow_handle_0 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ + uint16_t flow_handle_0; + /* + * Flow handle. + * For a listing of applicable flow_handle_1 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ + uint16_t flow_handle_1; + /* + * Flow handle. + * For a listing of applicable flow_handle_2 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ + uint16_t flow_handle_2; + /* + * Flow handle. + * For a listing of applicable flow_handle_3 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ + uint16_t flow_handle_3; + /* + * Flow handle. + * For a listing of applicable flow_handle_4 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ + uint16_t flow_handle_4; + /* + * Flow handle. + * For a listing of applicable flow_handle_5 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ + uint16_t flow_handle_5; + /* + * Flow handle. + * For a listing of applicable flow_handle_6 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ + uint16_t flow_handle_6; + /* + * Flow handle. + * For a listing of applicable flow_handle_7 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ + uint16_t flow_handle_7; + /* + * Flow handle. + * For a listing of applicable flow_handle_8 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ + uint16_t flow_handle_8; + /* + * Flow handle. + * For a listing of applicable flow_handle_9 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ + uint16_t flow_handle_9; + uint8_t unused_0[2]; + /* Flow ID of a flow. */ + uint32_t flow_id_0; + /* Flow ID of a flow. */ + uint32_t flow_id_1; + /* Flow ID of a flow. */ + uint32_t flow_id_2; + /* Flow ID of a flow. */ + uint32_t flow_id_3; + /* Flow ID of a flow. */ + uint32_t flow_id_4; + /* Flow ID of a flow. */ + uint32_t flow_id_5; + /* Flow ID of a flow. */ + uint32_t flow_id_6; + /* Flow ID of a flow. */ + uint32_t flow_id_7; + /* Flow ID of a flow. */ + uint32_t flow_id_8; + /* Flow ID of a flow. */ + uint32_t flow_id_9; +} hwrm_cfa_flow_stats_input_t, *phwrm_cfa_flow_stats_input_t; -/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */ +/* hwrm_cfa_flow_stats_output (size:1408b/176B) */ -typedef struct hwrm_cfa_redirect_query_tunnel_type_output { +typedef struct hwrm_cfa_flow_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46095,45 +49447,56 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Tunnel Mask. */ - uint32_t tunnel_mask; - /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL UINT32_C(0x1) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN UINT32_C(0x2) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE UINT32_C(0x4) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE UINT32_C(0x8) - /* IP in IP */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP UINT32_C(0x10) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE UINT32_C(0x20) - /* Multi-Protocol Label Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS UINT32_C(0x40) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT UINT32_C(0x80) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE UINT32_C(0x100) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 UINT32_C(0x200) - /* - * Enhance Generic Routing Encapsulation (GRE version 1) inside IP - * datagram payload - */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 UINT32_C(0x400) - /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL UINT32_C(0x800) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE UINT32_C(0x1000) + /* packet_0 is 64 b */ + uint64_t packet_0; + /* packet_1 is 64 b */ + uint64_t packet_1; + /* packet_2 is 64 b */ + uint64_t packet_2; + /* packet_3 is 64 b */ + uint64_t packet_3; + /* packet_4 is 64 b */ + uint64_t packet_4; + /* packet_5 is 64 b */ + uint64_t packet_5; + /* packet_6 is 64 b */ + uint64_t packet_6; + /* packet_7 is 64 b */ + uint64_t packet_7; + /* packet_8 is 64 b */ + uint64_t packet_8; + /* packet_9 is 64 b */ + uint64_t packet_9; + /* byte_0 is 64 b */ + uint64_t byte_0; + /* byte_1 is 64 b */ + uint64_t byte_1; + /* byte_2 is 64 b */ + uint64_t byte_2; + /* byte_3 is 64 b */ + uint64_t byte_3; + /* byte_4 is 64 b */ + uint64_t byte_4; + /* byte_5 is 64 b */ + uint64_t byte_5; + /* byte_6 is 64 b */ + uint64_t byte_6; + /* byte_7 is 64 b */ + uint64_t byte_7; + /* byte_8 is 64 b */ + uint64_t byte_8; + /* byte_9 is 64 b */ + uint64_t byte_9; /* - * IPV6 over virtual eXtensible Local Area Network with GPE header - * (IPV6oVXLANGPE) + * If a flow has been hit, the bit representing the flow will be 1. + * Likewise, if a flow has not, the bit representing the flow + * will be 0. Mapping will match flow numbers where bitX is for flowX + * (ex: bit 0 is flow0). This only applies for NIC flows. Upon + * reading of the flow, the bit will be cleared for the flow and only + * set again when traffic is received by the flow. */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 UINT32_C(0x2000) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE UINT32_C(0x4000) - uint8_t unused_0[3]; + uint16_t flow_hits; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -46143,16 +49506,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_redirect_query_tunnel_type_output_t, *phwrm_cfa_redirect_query_tunnel_type_output_t; - -/************************* - * hwrm_cfa_ctx_mem_rgtr * - *************************/ - +} hwrm_cfa_flow_stats_output_t, *phwrm_cfa_flow_stats_output_t; -/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */ +/*********************************** + * hwrm_cfa_flow_aging_timer_reset * + ***********************************/ -typedef struct hwrm_cfa_ctx_mem_rgtr_input { + +/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */ + +typedef struct hwrm_cfa_flow_aging_timer_reset_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46181,46 +49544,21 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t flags; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* Flow record index. */ + uint16_t flow_handle; + uint8_t unused_0[2]; /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * New flow timer value for the flow specified in the ext_flow_handle. + * The flow timer unit is 100ms. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 256KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 1MB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 1GB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G - uint32_t unused_0; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; -} hwrm_cfa_ctx_mem_rgtr_input_t, *phwrm_cfa_ctx_mem_rgtr_input_t; + uint32_t flow_timer; + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; +} hwrm_cfa_flow_aging_timer_reset_input_t, *phwrm_cfa_flow_aging_timer_reset_input_t; -/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */ +/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */ -typedef struct hwrm_cfa_ctx_mem_rgtr_output { +typedef struct hwrm_cfa_flow_aging_timer_reset_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46229,12 +49567,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Id/Handle to the recently register context memory. This handle is - * passed to the CFA feature. - */ - uint16_t ctx_id; - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -46244,16 +49577,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_ctx_mem_rgtr_output_t, *phwrm_cfa_ctx_mem_rgtr_output_t; +} hwrm_cfa_flow_aging_timer_reset_output_t, *phwrm_cfa_flow_aging_timer_reset_output_t; /*************************** - * hwrm_cfa_ctx_mem_unrgtr * + * hwrm_cfa_flow_aging_cfg * ***************************/ -/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */ +/* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */ -typedef struct hwrm_cfa_ctx_mem_unrgtr_input { +typedef struct hwrm_cfa_flow_aging_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46282,17 +49615,109 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* The bit field to enable per flow aging configuration. */ + uint16_t enables; /* - * Id/Handle to the recently register context memory. This handle is - * passed to the CFA feature. + * This bit must be '1' for the tcp flow timer field to be + * configured */ - uint16_t ctx_id; - uint8_t unused_0[6]; -} hwrm_cfa_ctx_mem_unrgtr_input_t, *phwrm_cfa_ctx_mem_unrgtr_input_t; + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER UINT32_C(0x1) + /* + * This bit must be '1' for the tcp finish timer field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER UINT32_C(0x2) + /* + * This bit must be '1' for the udp flow timer field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER UINT32_C(0x4) + /* + * This bit must be '1' for the eem dma interval field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL UINT32_C(0x8) + /* + * This bit must be '1' for the eem notice interval field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL UINT32_C(0x10) + /* + * This bit must be '1' for the eem context memory maximum entries + * field to be configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES UINT32_C(0x20) + /* + * This bit must be '1' for the eem context memory ID field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID UINT32_C(0x40) + /* + * This bit must be '1' for the eem context memory type field to be + * configured + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE UINT32_C(0x80) + uint8_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX + /* + * Enumeration denoting the enable, disable eem flow aging + * configuration. + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE (UINT32_C(0x0) << 1) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE (UINT32_C(0x1) << 1) + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE + uint8_t unused_0; + /* + * The flow aging timer for all TCP flows, the unit is 100 + * milliseconds. + */ + uint32_t tcp_flow_timer; + /* + * The TCP finished timer for all TCP flows, the unit is 100 + * milliseconds. + */ + uint32_t tcp_fin_timer; + /* + * The flow aging timer for all UDP flows, the unit is 100 + * milliseconds. + */ + uint32_t udp_flow_timer; + /* + * The interval to dma eem ejection data to host memory, the unit is + * milliseconds. + */ + uint16_t eem_dma_interval; + /* + * The interval to notify driver to read the eem ejection data, the + * unit is milliseconds. + */ + uint16_t eem_notice_interval; + /* The maximum entries number in the eem context memory. */ + uint32_t eem_ctx_max_entries; + /* The context memory ID for eem flow aging. */ + uint16_t eem_ctx_id; + uint16_t eem_ctx_mem_type; + /* + * The content of context memory is eem ejection data, the size of + * each entry is 4 bytes. + */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA UINT32_C(0x0) + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA + uint8_t unused_1[4]; +} hwrm_cfa_flow_aging_cfg_input_t, *phwrm_cfa_flow_aging_cfg_input_t; -/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */ +/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */ -typedef struct hwrm_cfa_ctx_mem_unrgtr_output { +typedef struct hwrm_cfa_flow_aging_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46311,16 +49736,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_ctx_mem_unrgtr_output_t, *phwrm_cfa_ctx_mem_unrgtr_output_t; +} hwrm_cfa_flow_aging_cfg_output_t, *phwrm_cfa_flow_aging_cfg_output_t; -/************************* - * hwrm_cfa_ctx_mem_qctx * - *************************/ +/**************************** + * hwrm_cfa_flow_aging_qcfg * + ****************************/ -/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */ +/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */ -typedef struct hwrm_cfa_ctx_mem_qctx_input { +typedef struct hwrm_cfa_flow_aging_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46350,16 +49775,23 @@ */ uint64_t resp_addr; /* - * Id/Handle to the recently register context memory. This handle is - * passed to the CFA feature. + * The direction for the flow aging configuration, 1 is rx path, 2 is + * tx path. */ - uint16_t ctx_id; - uint8_t unused_0[6]; -} hwrm_cfa_ctx_mem_qctx_input_t, *phwrm_cfa_ctx_mem_qctx_input_t; + uint8_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX + uint8_t unused_0[7]; +} hwrm_cfa_flow_aging_qcfg_input_t, *phwrm_cfa_flow_aging_qcfg_input_t; -/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */ +/* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */ -typedef struct hwrm_cfa_ctx_mem_qctx_output { +typedef struct hwrm_cfa_flow_aging_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46368,42 +49800,38 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint16_t flags; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * The current flow aging timer for all TCP flows, the unit is 100 + * millisecond. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 256KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 1MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 1GB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G - uint8_t unused_0[4]; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; - uint8_t unused_1[7]; + uint32_t tcp_flow_timer; + /* + * The current TCP finished timer for all TCP flows, the unit is 100 + * millisecond. + */ + uint32_t tcp_fin_timer; + /* + * The current flow aging timer for all UDP flows, the unit is 100 + * millisecond. + */ + uint32_t udp_flow_timer; + /* + * The interval to dma eem ejection data to host memory, the unit is + * milliseconds. + */ + uint16_t eem_dma_interval; + /* + * The interval to notify driver to read the eem ejection data, the + * unit is milliseconds. + */ + uint16_t eem_notice_interval; + /* The maximum entries number in the eem context memory. */ + uint32_t eem_ctx_max_entries; + /* The context memory ID for eem flow aging. */ + uint16_t eem_ctx_id; + /* The context memory type for eem flow aging. */ + uint16_t eem_ctx_mem_type; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -46413,16 +49841,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_ctx_mem_qctx_output_t, *phwrm_cfa_ctx_mem_qctx_output_t; +} hwrm_cfa_flow_aging_qcfg_output_t, *phwrm_cfa_flow_aging_qcfg_output_t; -/************************** - * hwrm_cfa_ctx_mem_qcaps * - **************************/ +/***************************** + * hwrm_cfa_flow_aging_qcaps * + *****************************/ -/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */ +/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */ -typedef struct hwrm_cfa_ctx_mem_qcaps_input { +typedef struct hwrm_cfa_flow_aging_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46451,11 +49879,24 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_cfa_ctx_mem_qcaps_input_t, *phwrm_cfa_ctx_mem_qcaps_input_t; + /* + * The direction for the flow aging configuration, 1 is rx path, 2 is + * tx path. + */ + uint8_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX + uint8_t unused_0[7]; +} hwrm_cfa_flow_aging_qcaps_input_t, *phwrm_cfa_flow_aging_qcaps_input_t; -/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */ +/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */ -typedef struct hwrm_cfa_ctx_mem_qcaps_output { +typedef struct hwrm_cfa_flow_aging_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46465,11 +49906,23 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Indicates the maximum number of context memory which can be - * registered. + * The maximum flow aging timer for all TCP flows, the unit is 100 + * millisecond. */ - uint16_t max_entries; - uint8_t unused_0[5]; + uint32_t max_tcp_flow_timer; + /* + * The maximum TCP finished timer for all TCP flows, the unit is 100 + * millisecond. + */ + uint32_t max_tcp_fin_timer; + /* + * The maximum flow aging timer for all UDP flows, the unit is 100 + * millisecond. + */ + uint32_t max_udp_flow_timer; + /* The maximum aging flows that HW can support. */ + uint32_t max_aging_flows; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -46479,16 +49932,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_ctx_mem_qcaps_output_t, *phwrm_cfa_ctx_mem_qcaps_output_t; +} hwrm_cfa_flow_aging_qcaps_output_t, *phwrm_cfa_flow_aging_qcaps_output_t; -/************************** - * hwrm_cfa_counter_qcaps * - **************************/ +/********************************** + * hwrm_cfa_tcp_flag_process_qcfg * + **********************************/ -/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */ +/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */ -typedef struct hwrm_cfa_counter_qcaps_input { +typedef struct hwrm_cfa_tcp_flag_process_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46517,11 +49970,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_cfa_counter_qcaps_input_t, *phwrm_cfa_counter_qcaps_input_t; +} hwrm_cfa_tcp_flag_process_qcfg_input_t, *phwrm_cfa_tcp_flag_process_qcfg_input_t; -/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */ +/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */ -typedef struct hwrm_cfa_counter_qcaps_output { +typedef struct hwrm_cfa_tcp_flag_process_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46530,81 +49983,21 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* Enumeration denoting the supported CFA counter format. */ - #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT UINT32_C(0x1) - /* CFA counter types are not supported. */ - #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE UINT32_C(0x0) - /* 64-bit packet counters followed by 64-bit byte counters format. */ - #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT UINT32_C(0x1) - #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT - uint32_t unused_0; - /* - * Minimum guaranteed number of flow counters supported for this - * function, in RX direction. - */ - uint32_t min_rx_fc; - /* - * Maximum non-guaranteed number of flow counters supported for this - * function, in RX direction. - */ - uint32_t max_rx_fc; - /* - * Minimum guaranteed number of flow counters supported for this - * function, in TX direction. - */ - uint32_t min_tx_fc; - /* - * Maximum non-guaranteed number of flow counters supported for this - * function, in TX direction. - */ - uint32_t max_tx_fc; - /* - * Minimum guaranteed number of extension flow counters supported for - * this function, in RX direction. - */ - uint32_t min_rx_efc; - /* - * Maximum non-guaranteed number of extension flow counters supported - * for this function, in RX direction. - */ - uint32_t max_rx_efc; - /* - * Minimum guaranteed number of extension flow counters supported for - * this function, in TX direction. - */ - uint32_t min_tx_efc; - /* - * Maximum non-guaranteed number of extension flow counters supported - * for this function, in TX direction. - */ - uint32_t max_tx_efc; - /* - * Minimum guaranteed number of meter drop counters supported for - * this function, in RX direction. - */ - uint32_t min_rx_mdc; - /* - * Maximum non-guaranteed number of meter drop counters supported for - * this function, in RX direction. - */ - uint32_t max_rx_mdc; - /* - * Minimum guaranteed number of meter drop counters supported for this - * function, in TX direction. - */ - uint32_t min_tx_mdc; + /* The port 0 RX mirror action record ID. */ + uint16_t rx_ar_id_port0; + /* The port 1 RX mirror action record ID. */ + uint16_t rx_ar_id_port1; /* - * Maximum non-guaranteed number of meter drop counters supported for - * this function, in TX direction. + * The port 0 RX action record ID for TX TCP flag packets from + * loopback path. */ - uint32_t max_tx_mdc; + uint16_t tx_ar_id_port0; /* - * Maximum guaranteed number of flow counters which can be used during - * flow alloc. + * The port 1 RX action record ID for TX TCP flag packets from + * loopback path. */ - uint32_t max_flow_alloc_fc; - uint8_t unused_1[3]; + uint16_t tx_ar_id_port1; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -46614,16 +50007,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_counter_qcaps_output_t, *phwrm_cfa_counter_qcaps_output_t; +} hwrm_cfa_tcp_flag_process_qcfg_output_t, *phwrm_cfa_tcp_flag_process_qcfg_output_t; -/************************ - * hwrm_cfa_counter_cfg * - ************************/ +/************************** + * hwrm_cfa_vf_pair_alloc * + **************************/ -/* hwrm_cfa_counter_cfg_input (size:256b/32B) */ +/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */ -typedef struct hwrm_cfa_counter_cfg_input { +typedef struct hwrm_cfa_vf_pair_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46652,51 +50045,18 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t flags; - /* Enumeration denoting the configuration mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE UINT32_C(0x1) - /* Disable the configuration mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE UINT32_C(0x0) - /* Enable the configuration mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE UINT32_C(0x1) - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x2) - /* Tx path. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 1) - /* Rx path. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 1) - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX - /* Enumeration denoting the data transfer mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK UINT32_C(0xc) - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2 - /* Push mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH (UINT32_C(0x0) << 2) - /* Pull mode. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL (UINT32_C(0x1) << 2) - /* Pull on async update. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC (UINT32_C(0x2) << 2) - #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC - uint16_t counter_type; - /* Flow counters. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0) - /* Extended flow counters. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1) - /* Meter drop counters. */ - #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2) - #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC - /* Ctx memory handle to be used for the counter. */ - uint16_t ctx_id; - /* Counter update cadence hint (only in Push mode). */ - uint16_t update_tmr_ms; - /* Total number of entries. */ - uint32_t num_entries; - uint32_t unused_0; -} hwrm_cfa_counter_cfg_input_t, *phwrm_cfa_counter_cfg_input_t; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_a_id; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_b_id; + uint8_t unused_0[4]; + /* VF Pair name (32 byte string). */ + char pair_name[32]; +} hwrm_cfa_vf_pair_alloc_input_t, *phwrm_cfa_vf_pair_alloc_input_t; -/* hwrm_cfa_counter_cfg_output (size:128b/16B) */ +/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */ -typedef struct hwrm_cfa_counter_cfg_output { +typedef struct hwrm_cfa_vf_pair_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46715,16 +50075,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_counter_cfg_output_t, *phwrm_cfa_counter_cfg_output_t; +} hwrm_cfa_vf_pair_alloc_output_t, *phwrm_cfa_vf_pair_alloc_output_t; /************************* - * hwrm_cfa_counter_qcfg * + * hwrm_cfa_vf_pair_free * *************************/ -/* hwrm_cfa_counter_qcfg_input (size:192b/24B) */ +/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */ -typedef struct hwrm_cfa_counter_qcfg_input { +typedef struct hwrm_cfa_vf_pair_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46753,31 +50113,13 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* Tx path. */ - #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* Rx path. */ - #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_RX - /* Enumeration denoting the data transfer mode. */ - #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK UINT32_C(0x6) - #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 1 - /* Push mode. */ - #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH (UINT32_C(0x0) << 1) - /* Pull mode. */ - #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL (UINT32_C(0x1) << 1) - /* Pull on async update. */ - #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC (UINT32_C(0x2) << 1) - #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC - uint16_t counter_type; - uint32_t unused_0; -} hwrm_cfa_counter_qcfg_input_t, *phwrm_cfa_counter_qcfg_input_t; + /* VF Pair name (32 byte string). */ + char pair_name[32]; +} hwrm_cfa_vf_pair_free_input_t, *phwrm_cfa_vf_pair_free_input_t; -/* hwrm_cfa_counter_qcfg_output (size:192b/24B) */ +/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_counter_qcfg_output { +typedef struct hwrm_cfa_vf_pair_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46786,9 +50128,6 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint16_t ctx_id; - uint16_t update_tmr_ms; - uint32_t num_entries; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -46799,16 +50138,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_counter_qcfg_output_t, *phwrm_cfa_counter_qcfg_output_t; +} hwrm_cfa_vf_pair_free_output_t, *phwrm_cfa_vf_pair_free_output_t; -/*************************** - * hwrm_cfa_counter_qstats * - ***************************/ +/************************* + * hwrm_cfa_vf_pair_info * + *************************/ -/* hwrm_cfa_counter_qstats_input (size:320b/40B) */ +/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */ -typedef struct hwrm_cfa_counter_qstats_input { +typedef struct hwrm_cfa_vf_pair_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46837,27 +50176,19 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1) - /* Tx path. */ - #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* Rx path. */ - #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX - uint16_t counter_type; - uint16_t input_flow_ctx_id; - uint16_t num_entries; - uint16_t delta_time_ms; - uint16_t meter_instance_id; - uint16_t mdc_ctx_id; + uint32_t flags; + /* If this flag is set, lookup by name else lookup by index. */ + #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) + /* vf pair table index. */ + uint16_t vf_pair_index; uint8_t unused_0[2]; - uint64_t expected_count; -} hwrm_cfa_counter_qstats_input_t, *phwrm_cfa_counter_qstats_input_t; + /* VF Pair name (32 byte string). */ + char vf_pair_name[32]; +} hwrm_cfa_vf_pair_info_input_t, *phwrm_cfa_vf_pair_info_input_t; -/* hwrm_cfa_counter_qstats_output (size:128b/16B) */ +/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */ -typedef struct hwrm_cfa_counter_qstats_output { +typedef struct hwrm_cfa_vf_pair_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -46866,7 +50197,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* vf pair table index. */ + uint16_t next_vf_pair_index; + /* vf pair member a's vf_fid. */ + uint16_t vf_a_fid; + /* vf pair member a's Linux logical VF number. */ + uint16_t vf_a_index; + /* vf pair member b's vf_fid. */ + uint16_t vf_b_fid; + /* vf pair member a's Linux logical VF number. */ + uint16_t vf_b_index; + /* vf pair state. */ + uint8_t pair_state; + /* Pair has been allocated */ + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) + /* Both pair members are active */ + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) + #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE + uint8_t unused_0[5]; + /* VF Pair name (32 byte string). */ + char pair_name[32]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -46876,16 +50227,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_counter_qstats_output_t, *phwrm_cfa_counter_qstats_output_t; +} hwrm_cfa_vf_pair_info_output_t, *phwrm_cfa_vf_pair_info_output_t; -/********************** - * hwrm_cfa_eem_qcaps * - **********************/ +/*********************** + * hwrm_cfa_pair_alloc * + ***********************/ -/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ +/* hwrm_cfa_pair_alloc_input (size:576b/72B) */ -typedef struct hwrm_cfa_eem_qcaps_input { +typedef struct hwrm_cfa_pair_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -46914,111 +50265,128 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; /* - * When set to 1, indicates the configuration will apply to TX flows - * which are to be offloaded. - * Note if this bit is set then the path_rx bit can't be set. + * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, + * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). */ - #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x1) + uint16_t pair_mode; /* - * When set to 1, indicates the configuration will apply to RX flows - * which are to be offloaded. - * Note if this bit is set then the path_tx bit can't be set. + * Pair between VF on local host with PF or VF on specified host. + * (deprecated) */ - #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x2) - /* When set to 1, all offloaded flows will be sent to EEM. */ - #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4) - uint32_t unused_0; -} hwrm_cfa_eem_qcaps_input_t, *phwrm_cfa_eem_qcaps_input_t; - -/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ - -typedef struct hwrm_cfa_eem_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t flags; + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0) /* - * When set to 1, indicates the configuration will apply to TX flows - * which are to be offloaded. - * Note if this bit is set then the path_rx bit can't be set. + * Pair between REP on local host with PF or VF on specified host. + * (deprecated) */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1) + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1) /* - * When set to 1, indicates the configuration will apply to RX flows - * which are to be offloaded. - * Note if this bit is set then the path_tx bit can't be set. + * Pair between REP on local host with REP on specified host. + * (deprecated) */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2) + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2) + /* Pair for the proxy interface. (deprecated) */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY UINT32_C(0x3) + /* Pair for the PF interface. (deprecated) */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) + /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */ + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5) /* - * When set to 1, indicates the FW supports the Centralized - * Memory Model. The concept designates one entity for the - * memory allocation while all others ‘subscribe’ to it. + * Modify existing rep2fn pairs paired with same PF and move pairs + * to new PF. (deprecated) */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x4) + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6) /* - * When set to 1, indicates the FW supports the Detached - * Centralized Memory Model. The memory is allocated and managed - * as a separate entity. All PFs and VFs will be granted direct - * or semi-direct access to the allocated memory while none of - * which can interfere with the management of the memory. + * Truflow pair between REP on local host with PF or VF on specified + * host. */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x8) - uint32_t unused_0; - uint32_t supported; + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7) + #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_a_id; + /* Logical Host (0xff-local host). */ + uint8_t host_b_id; + /* Logical PF (0xff-PF for command channel). */ + uint8_t pf_b_id; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_b_id; + /* Loopback port (0xff-internal loopback), valid for mode-3. */ + uint8_t port_id; + /* Priority used for encap of loopback packets valid for mode-3. */ + uint8_t pri; + /* New PF for rep2fn modify, valid for mode 5. */ + uint16_t new_pf_fid; + uint32_t enables; /* - * If set to 1, then EEM KEY0 table is supported using crc32 hash. - * If set to 0, EEM KEY0 table is not supported. + * This bit must be '1' for the q_ab field to be + * configured. */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE UINT32_C(0x1) + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1) /* - * If set to 1, then EEM KEY1 table is supported using lookup3 hash. - * If set to 0, EEM KEY1 table is not supported. + * This bit must be '1' for the q_ba field to be + * configured. */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE UINT32_C(0x2) + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2) /* - * If set to 1, then EEM External Record table is supported. - * If set to 0, EEM External Record table is not supported. - * (This table includes action record, EFC pointers, encap pointers) + * This bit must be '1' for the fc_ab field to be + * configured. */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE UINT32_C(0x4) + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4) /* - * If set to 1, then EEM External Flow Counters table is supported. - * If set to 0, EEM External Flow Counters table is not supported. + * This bit must be '1' for the fc_ba field to be + * configured. */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE UINT32_C(0x8) + #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8) + /* VF Pair name (32 byte string). */ + char pair_name[32]; /* - * If set to 1, then FID table used for implicit flow flush is - * supported. - * If set to 0, then FID table used for implicit flow flush is - * not supported. + * The q_ab value specifies the logical index of the TX/RX CoS + * queue to be assigned for traffic in the A to B direction of + * the interface pair. The default value is 0. */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE UINT32_C(0x10) + uint8_t q_ab; /* - * The maximum number of entries supported by EEM. When configuring - * the host memory, the number of numbers of entries that can - * supported are: - * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M - * entries. - * Any value that are not these values, the FW will round down to the - * closest support number of entries. + * The q_ba value specifies the logical index of the TX/RX CoS + * queue to be assigned for traffic in the B to A direction of + * the interface pair. The default value is 1. */ - uint32_t max_entries_supported; - /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */ - uint16_t key_entry_size; - /* The entry size in bytes of each entry in the EEM RECORD tables. */ - uint16_t record_entry_size; - /* The entry size in bytes of each entry in the EEM EFC tables. */ - uint16_t efc_entry_size; - /* The FID size in bytes of each entry in the EEM FID tables. */ - uint16_t fid_entry_size; - uint8_t unused_1[7]; + uint8_t q_ba; + /* + * Specifies whether RX ring flow control is disabled (0) or enabled + * (1) in the A to B direction. The default value is 0, meaning that + * packets will be dropped when the B-side RX rings are full. + */ + uint8_t fc_ab; + /* + * Specifies whether RX ring flow control is disabled (0) or enabled + * (1) in the B to A direction. The default value is 1, meaning that + * the RX CoS queue will be flow controlled when the A-side RX rings + * are full. + */ + uint8_t fc_ba; + uint8_t unused_1[4]; +} hwrm_cfa_pair_alloc_input_t, *phwrm_cfa_pair_alloc_input_t; + +/* hwrm_cfa_pair_alloc_output (size:192b/24B) */ + +typedef struct hwrm_cfa_pair_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Only valid for modes 1 and 2. */ + uint16_t rx_cfa_code_a; + /* Only valid for modes 1 and 2. */ + uint16_t tx_cfa_action_a; + /* Only valid for mode 2. */ + uint16_t rx_cfa_code_b; + /* Only valid for mode 2. */ + uint16_t tx_cfa_action_b; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -47028,16 +50396,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_eem_qcaps_output_t, *phwrm_cfa_eem_qcaps_output_t; +} hwrm_cfa_pair_alloc_output_t, *phwrm_cfa_pair_alloc_output_t; -/******************** - * hwrm_cfa_eem_cfg * - ********************/ +/********************** + * hwrm_cfa_pair_free * + **********************/ -/* hwrm_cfa_eem_cfg_input (size:384b/48B) */ +/* hwrm_cfa_pair_free_input (size:448b/56B) */ -typedef struct hwrm_cfa_eem_cfg_input { +typedef struct hwrm_cfa_pair_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47066,54 +50434,55 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + /* VF Pair name (32 byte string). */ + char pair_name[32]; + /* Logical PF (0xff-PF for command channel). */ + uint8_t pf_b_id; + uint8_t unused_0[3]; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; /* - * When set to 1, indicates the configuration will apply to TX flows - * which are to be offloaded. - * Note if this bit is set then the path_rx bit can't be set. + * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, + * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1) + uint16_t pair_mode; /* - * When set to 1, indicates the configuration will apply to RX flows - * which are to be offloaded. - * Note if this bit is set then the path_tx bit can't be set. + * Pair between VF on local host with PF or VF on specified host. + * (deprecated) */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) - /* When set to 1, all offloaded flows will be sent to EEM. */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4) - /* When set to 1, secondary, 0 means primary. */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF UINT32_C(0x8) + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0) /* - * Group_id which used by Firmware to identify memory pools belonging - * to certain group. + * Pair between REP on local host with PF or VF on specified host. + * (deprecated) */ - uint16_t group_id; - uint16_t unused_0; + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1) /* - * Configured EEM with the given number of entries. All the EEM tables - * KEY0, KEY1, RECORD, EFC all have the same number of entries and all - * tables will be configured using this value. Current minimum value - * is 32k. Current maximum value is 128M. + * Pair between REP on local host with REP on specified host. + * (deprecated) */ - uint32_t num_entries; - uint32_t unused_1; - /* Configured EEM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EEM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EEM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - uint16_t unused_2; - uint32_t unused_3; -} hwrm_cfa_eem_cfg_input_t, *phwrm_cfa_eem_cfg_input_t; + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2) + /* Pair for the proxy interface. (deprecated) */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3) + /* Pair for the PF interface. (deprecated) */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) + /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5) + /* + * Modify existing rep2fn pairs paired with same PF and move pairs + * to new PF. (deprecated) + */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6) + /* + * Truflow pair between REP on local host with PF or VF on + * specified host. + */ + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7) + #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW +} hwrm_cfa_pair_free_input_t, *phwrm_cfa_pair_free_input_t; -/* hwrm_cfa_eem_cfg_output (size:128b/16B) */ +/* hwrm_cfa_pair_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_eem_cfg_output { +typedef struct hwrm_cfa_pair_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47132,16 +50501,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_eem_cfg_output_t, *phwrm_cfa_eem_cfg_output_t; +} hwrm_cfa_pair_free_output_t, *phwrm_cfa_pair_free_output_t; -/********************* - * hwrm_cfa_eem_qcfg * - *********************/ +/********************** + * hwrm_cfa_pair_info * + **********************/ -/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ +/* hwrm_cfa_pair_info_input (size:448b/56B) */ -typedef struct hwrm_cfa_eem_qcfg_input { +typedef struct hwrm_cfa_pair_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47171,16 +50540,23 @@ */ uint64_t resp_addr; uint32_t flags; - /* When set to 1, indicates the configuration is the TX flow. */ - #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* When set to 1, indicates the configuration is the RX flow. */ - #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) - uint32_t unused_0; -} hwrm_cfa_eem_qcfg_input_t, *phwrm_cfa_eem_qcfg_input_t; + /* If this flag is set, lookup by name else lookup by index. */ + #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) + /* If this flag is set, lookup by PF id and VF id. */ + #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2) + /* Pair table index. */ + uint16_t pair_index; + /* Pair pf index. */ + uint8_t pair_pfid; + /* Pair vf index. */ + uint8_t pair_vfid; + /* Pair name (32 byte string). */ + char pair_name[32]; +} hwrm_cfa_pair_info_input_t, *phwrm_cfa_pair_info_input_t; -/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ +/* hwrm_cfa_pair_info_output (size:576b/72B) */ -typedef struct hwrm_cfa_eem_qcfg_output { +typedef struct hwrm_cfa_pair_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47189,26 +50565,64 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* When set to 1, indicates the configuration is the TX flow. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* When set to 1, indicates the configuration is the RX flow. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2) - /* When set to 1, all offloaded flows will be sent to EEM. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4) - /* The number of entries the FW has configured for EEM. */ - uint32_t num_entries; - /* Configured EEM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EEM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EEM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - uint8_t unused_2[5]; + /* Pair table index. */ + uint16_t next_pair_index; + /* Pair member a's fid. */ + uint16_t a_fid; + /* Logical host number. */ + uint8_t host_a_index; + /* Logical PF number. */ + uint8_t pf_a_index; + /* Pair member a's Linux logical VF number. */ + uint16_t vf_a_index; + /* Rx CFA code. */ + uint16_t rx_cfa_code_a; + /* Tx CFA action. */ + uint16_t tx_cfa_action_a; + /* Pair member b's fid. */ + uint16_t b_fid; + /* Logical host number. */ + uint8_t host_b_index; + /* Logical PF number. */ + uint8_t pf_b_index; + /* Pair member a's Linux logical VF number. */ + uint16_t vf_b_index; + /* Rx CFA code. */ + uint16_t rx_cfa_code_b; + /* Tx CFA action. */ + uint16_t tx_cfa_action_b; + /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */ + uint8_t pair_mode; + /* + * Pair between VF on local host with PF or VF on specified host. + * (deprecated) + */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0) + /* + * Pair between REP on local host with PF or VF on specified host. + * (deprecated) + */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1) + /* + * Pair between REP on local host with REP on specified host. + * (deprecated) + */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2) + /* Pair for the proxy interface. (deprecated) */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3) + /* Pair for the PF interface. (deprecated) */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR + /* Pair state. */ + uint8_t pair_state; + /* Pair has been allocated */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) + /* Both pair members are active */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE + /* Pair name (32 byte string). */ + char pair_name[32]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -47218,16 +50632,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_eem_qcfg_output_t, *phwrm_cfa_eem_qcfg_output_t; +} hwrm_cfa_pair_info_output_t, *phwrm_cfa_pair_info_output_t; -/******************* - * hwrm_cfa_eem_op * - *******************/ +/********************** + * hwrm_cfa_vfr_alloc * + **********************/ -/* hwrm_cfa_eem_op_input (size:192b/24B) */ +/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ -typedef struct hwrm_cfa_eem_op_input { +typedef struct hwrm_cfa_vfr_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47256,49 +50670,21 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * When set to 1, indicates the host memory which is passed will be - * used for the TX flow offload function specified in fid. - * Note if this bit is set then the path_rx bit can't be set. - */ - #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* - * When set to 1, indicates the host memory which is passed will be - * used for the RX flow offload function specified in fid. - * Note if this bit is set then the path_tx bit can't be set. - */ - #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2) - uint16_t unused_0; - /* The number of EEM key table entries to be configured. */ - uint16_t op; - /* This value is reserved and should not be used. */ - #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0) + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; /* - * To properly stop EEM and ensure there are no DMA's, the caller - * must disable EEM for the given PF, using this call. This will - * safely disable EEM and ensure that all DMA'ed to the - * keys/records/efc have been completed. + * This field is reserved for the future use. + * It shall be set to 0. */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1) - /* - * Once the EEM host memory has been configured, EEM options have - * been configured. Then the caller should enable EEM for the given - * PF. Note once this call has been made, then the EEM mechanism - * will be active and DMA's will occur as packets are processed. - */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2) - /* - * Clear EEM settings for the given PF so that the register values - * are reset back to there initial state. - */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3) - #define HWRM_CFA_EEM_OP_INPUT_OP_LAST HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP -} hwrm_cfa_eem_op_input_t, *phwrm_cfa_eem_op_input_t; + uint16_t reserved; + uint8_t unused_0[4]; + /* VF Representor name (32 byte string). */ + char vfr_name[32]; +} hwrm_cfa_vfr_alloc_input_t, *phwrm_cfa_vfr_alloc_input_t; -/* hwrm_cfa_eem_op_output (size:128b/16B) */ +/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ -typedef struct hwrm_cfa_eem_op_output { +typedef struct hwrm_cfa_vfr_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47307,7 +50693,11 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Rx CFA code. */ + uint16_t rx_cfa_code; + /* Tx CFA action. */ + uint16_t tx_cfa_action; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -47317,16 +50707,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_eem_op_output_t, *phwrm_cfa_eem_op_output_t; +} hwrm_cfa_vfr_alloc_output_t, *phwrm_cfa_vfr_alloc_output_t; -/******************************** - * hwrm_cfa_adv_flow_mgnt_qcaps * - ********************************/ +/********************* + * hwrm_cfa_vfr_free * + *********************/ -/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ +/* hwrm_cfa_vfr_free_input (size:448b/56B) */ -typedef struct hwrm_cfa_adv_flow_mgnt_qcaps_input { +typedef struct hwrm_cfa_vfr_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47355,12 +50745,21 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t unused_0[4]; -} hwrm_cfa_adv_flow_mgnt_qcaps_input_t, *phwrm_cfa_adv_flow_mgnt_qcaps_input_t; + /* VF Representor name (32 byte string). */ + char vfr_name[32]; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint16_t reserved; + uint8_t unused_0[4]; +} hwrm_cfa_vfr_free_input_t, *phwrm_cfa_vfr_free_input_t; -/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ +/* hwrm_cfa_vfr_free_output (size:128b/16B) */ -typedef struct hwrm_cfa_adv_flow_mgnt_qcaps_output { +typedef struct hwrm_cfa_vfr_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47369,137 +50768,210 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * Value of 1 to indicate firmware support 16-bit flow handle. - * Value of 0 to indicate firmware not support 16-bit flow handle. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED UINT32_C(0x1) - /* - * Value of 1 to indicate firmware support 64-bit flow handle. - * Value of 0 to indicate firmware not support 64-bit flow handle. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED UINT32_C(0x2) - /* - * Value of 1 to indicate firmware support flow batch delete - * operation through HWRM_CFA_FLOW_FLUSH command. - * Value of 0 to indicate that the firmware does not support flow - * batch delete operation. (deprecated) - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED UINT32_C(0x4) - /* - * Value of 1 to indicate that the firmware support flow reset all - * operation through HWRM_CFA_FLOW_FLUSH command. - * Value of 0 indicates firmware does not support flow reset all - * operation. (deprecated) - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED UINT32_C(0x8) - /* - * Value of 1 to indicate that firmware supports use of FID as - * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands. - * Value of 0 indicates firmware does not support use of FID as - * dest_id. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED UINT32_C(0x10) - /* - * Value of 1 to indicate that firmware supports TX EEM flows. - * Value of 0 indicates firmware does not support TX EEM flows. - * (deprecated) - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED UINT32_C(0x20) - /* - * Value of 1 to indicate that firmware supports RX EEM flows. - * Value of 0 indicates firmware does not support RX EEM flows. - * (deprecated) - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED UINT32_C(0x40) + uint8_t unused_0[7]; /* - * Value of 1 to indicate that firmware supports the dynamic - * allocation of an on-chip flow counter which can be used for EEM - * flows. Value of 0 indicates firmware does not support the dynamic - * allocation of an on-chip flow counter. - * (deprecated) + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED UINT32_C(0x80) + uint8_t valid; +} hwrm_cfa_vfr_free_output_t, *phwrm_cfa_vfr_free_output_t; + +/*************************************** + * hwrm_cfa_redirect_query_tunnel_type * + ***************************************/ + + +/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */ + +typedef struct hwrm_cfa_redirect_query_tunnel_type_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. - * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED UINT32_C(0x100) + uint16_t cmpl_ring; /* - * Value of 1 to indicate that firmware supports untagged matching - * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 - * indicates firmware does not support untagged matching. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED UINT32_C(0x200) + uint16_t seq_id; /* - * Value of 1 to indicate that firmware supports XDP filter. Value - * of 0 indicates firmware does not support XDP filter. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED UINT32_C(0x400) + uint16_t target_id; /* - * Value of 1 to indicate that the firmware support L2 header source - * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. - * Value of 0 indicates firmware does not support L2 header source - * fields matching. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED UINT32_C(0x800) + uint64_t resp_addr; + /* The source function id. */ + uint16_t src_fid; + uint8_t unused_0[6]; +} hwrm_cfa_redirect_query_tunnel_type_input_t, *phwrm_cfa_redirect_query_tunnel_type_input_t; + +/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */ + +typedef struct hwrm_cfa_redirect_query_tunnel_type_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Tunnel Mask. */ + uint32_t tunnel_mask; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL UINT32_C(0x1) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN UINT32_C(0x2) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE UINT32_C(0x4) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE UINT32_C(0x8) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP UINT32_C(0x10) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE UINT32_C(0x20) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS UINT32_C(0x40) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT UINT32_C(0x80) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE UINT32_C(0x100) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 UINT32_C(0x200) /* - * If set to 1, firmware is capable of supporting ARP ethertype as - * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the - * RX direction. By default, this flag should be 0 for older version - * of firmware. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED UINT32_C(0x1000) + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 UINT32_C(0x400) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL UINT32_C(0x800) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE UINT32_C(0x1000) /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC - * command. Value of 0 indicates firmware does not support - * rfs_ring_tbl_idx in dst_id field. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED UINT32_C(0x2000) + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 UINT32_C(0x2000) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE UINT32_C(0x4000) + uint8_t unused_0[3]; /* - * If set to 1, firmware is capable of supporting IPv4/IPv6 as - * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX - * direction. By default, this flag should be 0 for older version - * of firmware. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED UINT32_C(0x4000) + uint8_t valid; +} hwrm_cfa_redirect_query_tunnel_type_output_t, *phwrm_cfa_redirect_query_tunnel_type_output_t; + +/************************* + * hwrm_cfa_ctx_mem_rgtr * + *************************/ + + +/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */ + +typedef struct hwrm_cfa_ctx_mem_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When this bit is '1', it indicates that core firmware is - * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX - * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE UINT32_C(0x8000) + uint16_t cmpl_ring; /* - * If set to 1, firmware is capable of supporting L2/ROCE as - * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command. - * By default, this flag should be 0 for older version of firmware. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED UINT32_C(0x10000) + uint16_t seq_id; /* - * If set to 1, firmware is capable of HW LAG. This bit is only - * advertised if the calling function is a PAXC function. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED UINT32_C(0x20000) + uint16_t target_id; /* - * If set to 1, firmware is capable installing ntuple rules without - * additional classification on the L2 Context. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED UINT32_C(0x40000) + uint64_t resp_addr; + uint16_t flags; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) /* - * If set to 1, firmware is capable returning stats for nic flows - * in cfa_flow_stats command where flow_handle value 0xF000. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NIC_FLOW_STATS_SUPPORTED UINT32_C(0x80000) + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 256KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 1MB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 1GB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G + uint32_t unused_0; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; +} hwrm_cfa_ctx_mem_rgtr_input_t, *phwrm_cfa_ctx_mem_rgtr_input_t; + +/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */ + +typedef struct hwrm_cfa_ctx_mem_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * If set to 1, firmware is capable of supporting these additional - * ip_protoccols: ICMP, ICMPV6, RSVD for ntuple rules. By default, - * this flag should be 0 for older version of firmware. + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED UINT32_C(0x100000) - uint8_t unused_0[3]; + uint16_t ctx_id; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -47509,16 +50981,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_adv_flow_mgnt_qcaps_output_t, *phwrm_cfa_adv_flow_mgnt_qcaps_output_t; +} hwrm_cfa_ctx_mem_rgtr_output_t, *phwrm_cfa_ctx_mem_rgtr_output_t; -/****************** - * hwrm_cfa_tflib * - ******************/ +/*************************** + * hwrm_cfa_ctx_mem_unrgtr * + ***************************/ -/* hwrm_cfa_tflib_input (size:1024b/128B) */ +/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */ -typedef struct hwrm_cfa_tflib_input { +typedef struct hwrm_cfa_ctx_mem_unrgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47547,19 +51019,17 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; - /* unused. */ - uint8_t unused0[4]; - /* TFLIB request data. */ - uint32_t tf_req[26]; -} hwrm_cfa_tflib_input_t, *phwrm_cfa_tflib_input_t; + /* + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. + */ + uint16_t ctx_id; + uint8_t unused_0[6]; +} hwrm_cfa_ctx_mem_unrgtr_input_t, *phwrm_cfa_ctx_mem_unrgtr_input_t; -/* hwrm_cfa_tflib_output (size:5632b/704B) */ +/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */ -typedef struct hwrm_cfa_tflib_output { +typedef struct hwrm_cfa_ctx_mem_unrgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47568,16 +51038,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; - /* TFLIB response code */ - uint32_t tf_resp_code; - /* TFLIB response data. */ - uint32_t tf_resp[170]; - /* unused. */ - uint8_t unused1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -47587,16 +51048,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_tflib_output_t, *phwrm_cfa_tflib_output_t; +} hwrm_cfa_ctx_mem_unrgtr_output_t, *phwrm_cfa_ctx_mem_unrgtr_output_t; -/********************************** - * hwrm_cfa_lag_group_member_rgtr * - **********************************/ +/************************* + * hwrm_cfa_ctx_mem_qctx * + *************************/ -/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */ +/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */ -typedef struct hwrm_cfa_lag_group_member_rgtr_input { +typedef struct hwrm_cfa_ctx_mem_qctx_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47625,39 +51086,17 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t mode; - /* - * Transmit only on the active port. Automatically failover - * to backup port. - */ - #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP UINT32_C(0x1) - /* - * Transmit based on packet header ntuple hash. Packet with only - * layer 2 headers will hash using the destination MAC, source MAC - * and Ethertype fields. Packets with layer 3 (IP) headers will - * hash using the destination MAC, source MAC, IP protocol/next - * header, source IP address and destination IP address. Packets - * with layer 4 (TCP/UDP) headers will hash using the destination - * MAC, source MAC, IP protocol/next header, source IP address, - * destination IP address, source port and destination port fields. - */ - #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR UINT32_C(0x2) - /* Transmit packets on all specified ports. */ - #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST UINT32_C(0x3) - #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST /* - * Supports up to 5 ports. bit0 = port 0, bit1 = port 1, - * bit2 = port 2, bit3 = port 4, bit4 = loopback port + * Id/Handle to the recently register context memory. This handle is + * passed to the CFA feature. */ - uint8_t port_bitmap; - /* Specify the active port when active-backup mode is specified */ - uint8_t active_port; - uint8_t unused_0[5]; -} hwrm_cfa_lag_group_member_rgtr_input_t, *phwrm_cfa_lag_group_member_rgtr_input_t; + uint16_t ctx_id; + uint8_t unused_0[6]; +} hwrm_cfa_ctx_mem_qctx_input_t, *phwrm_cfa_ctx_mem_qctx_input_t; -/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */ +/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */ -typedef struct hwrm_cfa_lag_group_member_rgtr_output { +typedef struct hwrm_cfa_ctx_mem_qctx_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47666,9 +51105,42 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* lag group ID configured for the function */ - uint16_t lag_id; - uint8_t unused_0[5]; + uint16_t flags; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 256KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 1MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 1GB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G + uint8_t unused_0[4]; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -47678,16 +51150,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_lag_group_member_rgtr_output_t, *phwrm_cfa_lag_group_member_rgtr_output_t; +} hwrm_cfa_ctx_mem_qctx_output_t, *phwrm_cfa_ctx_mem_qctx_output_t; -/************************************ - * hwrm_cfa_lag_group_member_unrgtr * - ************************************/ +/************************** + * hwrm_cfa_ctx_mem_qcaps * + **************************/ -/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */ +/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */ -typedef struct hwrm_cfa_lag_group_member_unrgtr_input { +typedef struct hwrm_cfa_ctx_mem_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47716,14 +51188,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* lag group ID configured for the function */ - uint16_t lag_id; - uint8_t unused_0[6]; -} hwrm_cfa_lag_group_member_unrgtr_input_t, *phwrm_cfa_lag_group_member_unrgtr_input_t; +} hwrm_cfa_ctx_mem_qcaps_input_t, *phwrm_cfa_ctx_mem_qcaps_input_t; -/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */ +/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */ -typedef struct hwrm_cfa_lag_group_member_unrgtr_output { +typedef struct hwrm_cfa_ctx_mem_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -47732,7 +51201,12 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * Indicates the maximum number of context memory which can be + * registered. + */ + uint16_t max_entries; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -47742,16 +51216,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_lag_group_member_unrgtr_output_t, *phwrm_cfa_lag_group_member_unrgtr_output_t; +} hwrm_cfa_ctx_mem_qcaps_output_t, *phwrm_cfa_ctx_mem_qcaps_output_t; -/***************************** - * hwrm_cfa_tls_filter_alloc * - *****************************/ +/************************** + * hwrm_cfa_counter_qcaps * + **************************/ -/* hwrm_cfa_tls_filter_alloc_input (size:704b/88B) */ +/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */ -typedef struct hwrm_cfa_tls_filter_alloc_input { +typedef struct hwrm_cfa_counter_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -47780,184 +51254,94 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t unused_0; - uint32_t enables; - /* - * This bit must be '1' for the l2_filter_id field to be - * configured. - */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) - /* - * This bit must be '1' for the ethertype field to be - * configured. - */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2) - /* - * This bit must be '1' for the ipaddr_type field to be - * configured. - */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x4) - /* - * This bit must be '1' for the src_ipaddr field to be - * configured. - */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x8) - /* - * This bit must be '1' for the dst_ipaddr field to be - * configured. - */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x10) - /* - * This bit must be '1' for the ip_protocol field to be - * configured. - */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x20) - /* - * This bit must be '1' for the src_port field to be - * configured. - */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x40) - /* - * This bit must be '1' for the dst_port field to be - * configured. - */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x80) - /* - * This bit must be '1' for the kid field to be - * configured. - */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_KID UINT32_C(0x100) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x200) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x400) +} hwrm_cfa_counter_qcaps_input_t, *phwrm_cfa_counter_qcaps_input_t; + +/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */ + +typedef struct hwrm_cfa_counter_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* Enumeration denoting the supported CFA counter format. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT UINT32_C(0x1) + /* CFA counter types are not supported. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE UINT32_C(0x0) + /* 64-bit packet counters followed by 64-bit byte counters format. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT UINT32_C(0x1) + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT + uint32_t unused_0; /* - * This value identifies a set of CFA data structures used for an L2 - * context. + * Minimum guaranteed number of flow counters supported for this + * function, in RX direction. */ - uint64_t l2_filter_id; - uint8_t unused_1[6]; - /* This value indicates the ethertype in the Ethernet header. */ - uint16_t ethertype; + uint32_t min_rx_fc; /* - * This value indicates the type of IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. + * Maximum non-guaranteed number of flow counters supported for this + * function, in RX direction. */ - uint8_t ip_addr_type; - /* invalid */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) - /* IPv4 */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) - /* IPv6 */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + uint32_t max_rx_fc; /* - * The value of protocol filed in IP header. - * Applies to UDP and TCP traffic. - * 6 - TCP - * 17 - UDP + * Minimum guaranteed number of flow counters supported for this + * function, in TX direction. */ - uint8_t ip_protocol; - /* invalid */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) - /* TCP */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) - /* UDP */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP + uint32_t min_tx_fc; /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. + * Maximum non-guaranteed number of flow counters supported for this + * function, in TX direction. */ - uint16_t dst_id; + uint32_t max_tx_fc; /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. + * Minimum guaranteed number of extension flow counters supported for + * this function, in RX direction. */ - uint16_t mirror_vnic_id; - uint8_t unused_2[2]; + uint32_t min_rx_efc; /* - * The value of source IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * Maximum non-guaranteed number of extension flow counters supported + * for this function, in RX direction. */ - uint32_t src_ipaddr[4]; + uint32_t max_rx_efc; /* - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * Minimum guaranteed number of extension flow counters supported for + * this function, in TX direction. */ - uint32_t dst_ipaddr[4]; + uint32_t min_tx_efc; /* - * The value of source port to be used in filtering. - * Applies to UDP and TCP traffic. + * Maximum non-guaranteed number of extension flow counters supported + * for this function, in TX direction. */ - uint16_t src_port; + uint32_t max_tx_efc; /* - * The value of destination port to be used in filtering. - * Applies to UDP and TCP traffic. + * Minimum guaranteed number of meter drop counters supported for + * this function, in RX direction. */ - uint16_t dst_port; + uint32_t min_rx_mdc; /* - * The Key Context Identifier (KID) for use with KTLS. - * KID is limited to 20-bits. + * Maximum non-guaranteed number of meter drop counters supported for + * this function, in RX direction. */ - uint32_t kid; -} hwrm_cfa_tls_filter_alloc_input_t, *phwrm_cfa_tls_filter_alloc_input_t; - -/* hwrm_cfa_tls_filter_alloc_output (size:192b/24B) */ - -typedef struct hwrm_cfa_tls_filter_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint64_t tls_filter_id; + uint32_t max_rx_mdc; /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. + * Minimum guaranteed number of meter drop counters supported for this + * function, in TX direction. */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) - #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) + uint32_t min_tx_mdc; /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. + * Maximum non-guaranteed number of meter drop counters supported for + * this function, in TX direction. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) + uint32_t max_tx_mdc; /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. + * Maximum guaranteed number of flow counters which can be used during + * flow alloc. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) - #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) - #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX - uint8_t unused_0[3]; + uint32_t max_flow_alloc_fc; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -47967,16 +51351,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_tls_filter_alloc_output_t, *phwrm_cfa_tls_filter_alloc_output_t; +} hwrm_cfa_counter_qcaps_output_t, *phwrm_cfa_counter_qcaps_output_t; -/**************************** - * hwrm_cfa_tls_filter_free * - ****************************/ +/************************ + * hwrm_cfa_counter_cfg * + ************************/ -/* hwrm_cfa_tls_filter_free_input (size:192b/24B) */ +/* hwrm_cfa_counter_cfg_input (size:256b/32B) */ -typedef struct hwrm_cfa_tls_filter_free_input { +typedef struct hwrm_cfa_counter_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48005,13 +51389,51 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint64_t tls_filter_id; -} hwrm_cfa_tls_filter_free_input_t, *phwrm_cfa_tls_filter_free_input_t; + uint16_t flags; + /* Enumeration denoting the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE UINT32_C(0x1) + /* Disable the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE UINT32_C(0x0) + /* Enable the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE UINT32_C(0x1) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x2) + /* Tx path. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 1) + /* Rx path. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 1) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX + /* Enumeration denoting the data transfer mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK UINT32_C(0xc) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2 + /* Push mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH (UINT32_C(0x0) << 2) + /* Pull mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL (UINT32_C(0x1) << 2) + /* Pull on async update. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC (UINT32_C(0x2) << 2) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC + uint16_t counter_type; + /* Flow counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0) + /* Extended flow counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1) + /* Meter drop counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2) + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC + /* Ctx memory handle to be used for the counter. */ + uint16_t ctx_id; + /* Counter update cadence hint (only in Push mode). */ + uint16_t update_tmr_ms; + /* Total number of entries. */ + uint32_t num_entries; + uint32_t unused_0; +} hwrm_cfa_counter_cfg_input_t, *phwrm_cfa_counter_cfg_input_t; -/* hwrm_cfa_tls_filter_free_output (size:128b/16B) */ +/* hwrm_cfa_counter_cfg_output (size:128b/16B) */ -typedef struct hwrm_cfa_tls_filter_free_output { +typedef struct hwrm_cfa_counter_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48030,16 +51452,16 @@ * written last. */ uint8_t valid; -} hwrm_cfa_tls_filter_free_output_t, *phwrm_cfa_tls_filter_free_output_t; +} hwrm_cfa_counter_cfg_output_t, *phwrm_cfa_counter_cfg_output_t; -/*********** - * hwrm_tf * - ***********/ +/************************* + * hwrm_cfa_counter_qcfg * + *************************/ -/* hwrm_tf_input (size:1024b/128B) */ +/* hwrm_cfa_counter_qcfg_input (size:192b/24B) */ -typedef struct hwrm_tf_input { +typedef struct hwrm_cfa_counter_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48068,19 +51490,31 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* TF message type. */ - uint16_t type; - /* TF message subtype. */ - uint16_t subtype; - /* unused. */ - uint8_t unused0[4]; - /* TF request data. */ - uint32_t req[26]; -} hwrm_tf_input_t, *phwrm_tf_input_t; + uint16_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* Tx path. */ + #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* Rx path. */ + #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_RX + /* Enumeration denoting the data transfer mode. */ + #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK UINT32_C(0x6) + #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 1 + /* Push mode. */ + #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH (UINT32_C(0x0) << 1) + /* Pull mode. */ + #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL (UINT32_C(0x1) << 1) + /* Pull on async update. */ + #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC (UINT32_C(0x2) << 1) + #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC + uint16_t counter_type; + uint32_t unused_0; +} hwrm_cfa_counter_qcfg_input_t, *phwrm_cfa_counter_qcfg_input_t; -/* hwrm_tf_output (size:5632b/704B) */ +/* hwrm_cfa_counter_qcfg_output (size:192b/24B) */ -typedef struct hwrm_tf_output { +typedef struct hwrm_cfa_counter_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48089,35 +51523,29 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* TF message type. */ - uint16_t type; - /* TF message subtype. */ - uint16_t subtype; - /* TF response code */ - uint32_t resp_code; - /* TF response data. */ - uint32_t resp[170]; - /* unused. */ - uint8_t unused1[7]; + uint16_t ctx_id; + uint16_t update_tmr_ms; + uint32_t num_entries; + uint8_t unused_0[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tf_output_t, *phwrm_tf_output_t; +} hwrm_cfa_counter_qcfg_output_t, *phwrm_cfa_counter_qcfg_output_t; -/*********************** - * hwrm_tf_version_get * - ***********************/ +/*************************** + * hwrm_cfa_counter_qstats * + ***************************/ -/* hwrm_tf_version_get_input (size:128b/16B) */ +/* hwrm_cfa_counter_qstats_input (size:320b/40B) */ -typedef struct hwrm_tf_version_get_input { +typedef struct hwrm_cfa_counter_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48146,11 +51574,27 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_tf_version_get_input_t, *phwrm_tf_version_get_input_t; + uint16_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1) + /* Tx path. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* Rx path. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX + uint16_t counter_type; + uint16_t input_flow_ctx_id; + uint16_t num_entries; + uint16_t delta_time_ms; + uint16_t meter_instance_id; + uint16_t mdc_ctx_id; + uint8_t unused_0[2]; + uint64_t expected_count; +} hwrm_cfa_counter_qstats_input_t, *phwrm_cfa_counter_qstats_input_t; -/* hwrm_tf_version_get_output (size:256b/32B) */ +/* hwrm_cfa_counter_qstats_output (size:128b/16B) */ -typedef struct hwrm_tf_version_get_output { +typedef struct hwrm_cfa_counter_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48159,21 +51603,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Version Major number. */ - uint8_t major; - /* Version Minor number. */ - uint8_t minor; - /* Version Update number. */ - uint8_t update; - /* unused. */ - uint8_t unused0[5]; - /* - * This field is used to indicate device's capabilities and - * configurations. - */ - uint64_t dev_caps_cfg; - /* unused. */ - uint8_t unused1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -48183,16 +51613,16 @@ * written last. */ uint8_t valid; -} hwrm_tf_version_get_output_t, *phwrm_tf_version_get_output_t; +} hwrm_cfa_counter_qstats_output_t, *phwrm_cfa_counter_qstats_output_t; -/************************ - * hwrm_tf_session_open * - ************************/ +/********************** + * hwrm_cfa_eem_qcaps * + **********************/ -/* hwrm_tf_session_open_input (size:640b/80B) */ +/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ -typedef struct hwrm_tf_session_open_input { +typedef struct hwrm_cfa_eem_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48221,13 +51651,27 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Name of the session. */ - uint8_t session_name[64]; -} hwrm_tf_session_open_input_t, *phwrm_tf_session_open_input_t; + uint32_t flags; + /* + * When set to 1, indicates the configuration will apply to TX flows + * which are to be offloaded. + * Note if this bit is set then the path_rx bit can't be set. + */ + #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x1) + /* + * When set to 1, indicates the configuration will apply to RX flows + * which are to be offloaded. + * Note if this bit is set then the path_tx bit can't be set. + */ + #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x2) + /* When set to 1, all offloaded flows will be sent to EEM. */ + #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4) + uint32_t unused_0; +} hwrm_cfa_eem_qcaps_input_t, *phwrm_cfa_eem_qcaps_input_t; -/* hwrm_tf_session_open_output (size:192b/24B) */ +/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ -typedef struct hwrm_tf_session_open_output { +typedef struct hwrm_cfa_eem_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48236,37 +51680,82 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + uint32_t flags; /* - * Unique session identifier for the session created by the - * firmware. + * When set to 1, indicates the configuration will apply to TX flows + * which are to be offloaded. + * Note if this bit is set then the path_rx bit can't be set. */ - uint32_t fw_session_id; + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1) /* - * Unique session client identifier for the first client on - * the newly created session. + * When set to 1, indicates the configuration will apply to RX flows + * which are to be offloaded. + * Note if this bit is set then the path_tx bit can't be set. */ - uint32_t fw_session_client_id; - /* This field is used to return the status of fw session to host. */ - uint32_t flags; + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2) /* - * Indicates if the shared session has been created. Shared session - * should be the first session created ever. Its fw_rm_client_id - * should be 1. The AFM session's fw_rm_client_id is 0. + * When set to 1, indicates the FW supports the Centralized + * Memory Model. The concept designates one entity for the + * memory allocation while all others 'subscribe' to it. */ - #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION UINT32_C(0x1) + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x4) /* - * If this bit set to 0, then it indicates the shared session - * has been created by another session. + * When set to 1, indicates the FW supports the Detached + * Centralized Memory Model. The memory is allocated and managed + * as a separate entity. All PFs and VFs will be granted direct + * or semi-direct access to the allocated memory while none of + * which can interfere with the management of the memory. */ - #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR UINT32_C(0x0) + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x8) + uint32_t unused_0; + uint32_t supported; /* - * If this bit is set to 1, then it indicates the shared session - * is created by this session. + * If set to 1, then EEM KEY0 table is supported using crc32 hash. + * If set to 0, EEM KEY0 table is not supported. */ - #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR UINT32_C(0x1) - #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_LAST HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR - /* unused. */ - uint8_t unused1[3]; + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE UINT32_C(0x1) + /* + * If set to 1, then EEM KEY1 table is supported using lookup3 hash. + * If set to 0, EEM KEY1 table is not supported. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE UINT32_C(0x2) + /* + * If set to 1, then EEM External Record table is supported. + * If set to 0, EEM External Record table is not supported. + * (This table includes action record, EFC pointers, encap pointers) + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE UINT32_C(0x4) + /* + * If set to 1, then EEM External Flow Counters table is supported. + * If set to 0, EEM External Flow Counters table is not supported. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE UINT32_C(0x8) + /* + * If set to 1, then FID table used for implicit flow flush is + * supported. + * If set to 0, then FID table used for implicit flow flush is + * not supported. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE UINT32_C(0x10) + /* + * The maximum number of entries supported by EEM. When configuring + * the host memory, the number of numbers of entries that can + * supported are: + * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M + * entries. + * Any value that are not these values, the FW will round down to the + * closest support number of entries. + */ + uint32_t max_entries_supported; + /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */ + uint16_t key_entry_size; + /* The entry size in bytes of each entry in the EEM RECORD tables. */ + uint16_t record_entry_size; + /* The entry size in bytes of each entry in the EEM EFC tables. */ + uint16_t efc_entry_size; + /* The FID size in bytes of each entry in the EEM FID tables. */ + uint16_t fid_entry_size; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -48276,16 +51765,16 @@ * written last. */ uint8_t valid; -} hwrm_tf_session_open_output_t, *phwrm_tf_session_open_output_t; +} hwrm_cfa_eem_qcaps_output_t, *phwrm_cfa_eem_qcaps_output_t; -/************************** - * hwrm_tf_session_attach * - **************************/ +/******************** + * hwrm_cfa_eem_cfg * + ********************/ -/* hwrm_tf_session_attach_input (size:704b/88B) */ +/* hwrm_cfa_eem_cfg_input (size:384b/48B) */ -typedef struct hwrm_tf_session_attach_input { +typedef struct hwrm_cfa_eem_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48314,26 +51803,54 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t flags; /* - * Unique session identifier for the session that the attach - * request want to attach to. This value originates from the - * shared session memory that the attach request opened by - * way of the 'attach name' that was passed in to the core - * attach API. - * The fw_session_id of the attach session includes PCIe bus - * info to distinguish the PF and session info to identify - * the associated TruFlow session. + * When set to 1, indicates the configuration will apply to TX flows + * which are to be offloaded. + * Note if this bit is set then the path_rx bit can't be set. */ - uint32_t attach_fw_session_id; - /* unused. */ - uint32_t unused0; - /* Name of the session it self. */ - uint8_t session_name[64]; -} hwrm_tf_session_attach_input_t, *phwrm_tf_session_attach_input_t; + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1) + /* + * When set to 1, indicates the configuration will apply to RX flows + * which are to be offloaded. + * Note if this bit is set then the path_tx bit can't be set. + */ + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) + /* When set to 1, all offloaded flows will be sent to EEM. */ + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4) + /* When set to 1, secondary, 0 means primary. */ + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF UINT32_C(0x8) + /* + * Group_id which used by Firmware to identify memory pools belonging + * to certain group. + */ + uint16_t group_id; + uint16_t unused_0; + /* + * Configured EEM with the given number of entries. All the EEM tables + * KEY0, KEY1, RECORD, EFC all have the same number of entries and all + * tables will be configured using this value. Current minimum value + * is 32k. Current maximum value is 128M. + */ + uint32_t num_entries; + uint32_t unused_1; + /* Configured EEM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EEM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EEM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + uint16_t unused_2; + uint32_t unused_3; +} hwrm_cfa_eem_cfg_input_t, *phwrm_cfa_eem_cfg_input_t; -/* hwrm_tf_session_attach_output (size:128b/16B) */ +/* hwrm_cfa_eem_cfg_output (size:128b/16B) */ -typedef struct hwrm_tf_session_attach_output { +typedef struct hwrm_cfa_eem_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48342,16 +51859,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Unique session identifier for the session created by the - * firmware. It includes PCIe bus info to distinguish the PF - * and session info to identify the associated TruFlow - * session. This fw_session_id is unique to the attach - * request. - */ - uint32_t fw_session_id; - /* unused. */ - uint8_t unused0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -48361,16 +51869,16 @@ * written last. */ uint8_t valid; -} hwrm_tf_session_attach_output_t, *phwrm_tf_session_attach_output_t; +} hwrm_cfa_eem_cfg_output_t, *phwrm_cfa_eem_cfg_output_t; -/**************************** - * hwrm_tf_session_register * - ****************************/ +/********************* + * hwrm_cfa_eem_qcfg * + *********************/ -/* hwrm_tf_session_register_input (size:704b/88B) */ +/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ -typedef struct hwrm_tf_session_register_input { +typedef struct hwrm_cfa_eem_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48399,24 +51907,17 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Unique session identifier for the session that the - * register request want to create a new client on. This - * value originates from the first open request. - * The fw_session_id of the attach session includes PCIe bus - * info to distinguish the PF and session info to identify - * the associated TruFlow session. - */ - uint32_t fw_session_id; - /* unused. */ - uint32_t unused0; - /* Name of the session client. */ - uint8_t session_client_name[64]; -} hwrm_tf_session_register_input_t, *phwrm_tf_session_register_input_t; + uint32_t flags; + /* When set to 1, indicates the configuration is the TX flow. */ + #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1) + /* When set to 1, indicates the configuration is the RX flow. */ + #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) + uint32_t unused_0; +} hwrm_cfa_eem_qcfg_input_t, *phwrm_cfa_eem_qcfg_input_t; -/* hwrm_tf_session_register_output (size:128b/16B) */ +/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ -typedef struct hwrm_tf_session_register_output { +typedef struct hwrm_cfa_eem_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48425,14 +51926,26 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Unique session client identifier for the session created - * by the firmware. It includes the session the client it - * attached to and session client info. - */ - uint32_t fw_session_client_id; - /* unused. */ - uint8_t unused0[3]; + uint32_t flags; + /* When set to 1, indicates the configuration is the TX flow. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1) + /* When set to 1, indicates the configuration is the RX flow. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2) + /* When set to 1, all offloaded flows will be sent to EEM. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4) + /* The number of entries the FW has configured for EEM. */ + uint32_t num_entries; + /* Configured EEM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EEM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EEM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + uint8_t unused_2[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -48442,16 +51955,16 @@ * written last. */ uint8_t valid; -} hwrm_tf_session_register_output_t, *phwrm_tf_session_register_output_t; +} hwrm_cfa_eem_qcfg_output_t, *phwrm_cfa_eem_qcfg_output_t; -/****************************** - * hwrm_tf_session_unregister * - ******************************/ +/******************* + * hwrm_cfa_eem_op * + *******************/ -/* hwrm_tf_session_unregister_input (size:192b/24B) */ +/* hwrm_cfa_eem_op_input (size:192b/24B) */ -typedef struct hwrm_tf_session_unregister_input { +typedef struct hwrm_cfa_eem_op_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48480,21 +51993,49 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t flags; /* - * Unique session identifier for the session that the - * unregister request want to close a session client on. + * When set to 1, indicates the host memory which is passed will be + * used for the TX flow offload function specified in fid. + * Note if this bit is set then the path_rx bit can't be set. */ - uint32_t fw_session_id; + #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1) /* - * Unique session client identifier for the session that the - * unregister request want to close. + * When set to 1, indicates the host memory which is passed will be + * used for the RX flow offload function specified in fid. + * Note if this bit is set then the path_tx bit can't be set. */ - uint32_t fw_session_client_id; -} hwrm_tf_session_unregister_input_t, *phwrm_tf_session_unregister_input_t; + #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2) + uint16_t unused_0; + /* The number of EEM key table entries to be configured. */ + uint16_t op; + /* This value is reserved and should not be used. */ + #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0) + /* + * To properly stop EEM and ensure there are no DMA's, the caller + * must disable EEM for the given PF, using this call. This will + * safely disable EEM and ensure that all DMA'ed to the + * keys/records/efc have been completed. + */ + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1) + /* + * Once the EEM host memory has been configured, EEM options have + * been configured. Then the caller should enable EEM for the given + * PF. Note once this call has been made, then the EEM mechanism + * will be active and DMA's will occur as packets are processed. + */ + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2) + /* + * Clear EEM settings for the given PF so that the register values + * are reset back to there initial state. + */ + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3) + #define HWRM_CFA_EEM_OP_INPUT_OP_LAST HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP +} hwrm_cfa_eem_op_input_t, *phwrm_cfa_eem_op_input_t; -/* hwrm_tf_session_unregister_output (size:128b/16B) */ +/* hwrm_cfa_eem_op_output (size:128b/16B) */ -typedef struct hwrm_tf_session_unregister_output { +typedef struct hwrm_cfa_eem_op_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48503,8 +52044,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -48514,16 +52054,16 @@ * written last. */ uint8_t valid; -} hwrm_tf_session_unregister_output_t, *phwrm_tf_session_unregister_output_t; +} hwrm_cfa_eem_op_output_t, *phwrm_cfa_eem_op_output_t; -/************************* - * hwrm_tf_session_close * - *************************/ +/******************************** + * hwrm_cfa_adv_flow_mgnt_qcaps * + ********************************/ -/* hwrm_tf_session_close_input (size:192b/24B) */ +/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ -typedef struct hwrm_tf_session_close_input { +typedef struct hwrm_cfa_adv_flow_mgnt_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48552,15 +52092,12 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* unused. */ - uint8_t unused0[4]; -} hwrm_tf_session_close_input_t, *phwrm_tf_session_close_input_t; + uint32_t unused_0[4]; +} hwrm_cfa_adv_flow_mgnt_qcaps_input_t, *phwrm_cfa_adv_flow_mgnt_qcaps_input_t; -/* hwrm_tf_session_close_output (size:128b/16B) */ +/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ -typedef struct hwrm_tf_session_close_output { +typedef struct hwrm_cfa_adv_flow_mgnt_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48569,134 +52106,162 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; + uint32_t flags; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * Value of 1 to indicate firmware support 16-bit flow handle. + * Value of 0 to indicate firmware not support 16-bit flow handle. */ - uint8_t valid; -} hwrm_tf_session_close_output_t, *phwrm_tf_session_close_output_t; - -/************************ - * hwrm_tf_session_qcfg * - ************************/ - - -/* hwrm_tf_session_qcfg_input (size:192b/24B) */ - -typedef struct hwrm_tf_session_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED UINT32_C(0x1) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Value of 1 to indicate firmware support 64-bit flow handle. + * Value of 0 to indicate firmware not support 64-bit flow handle. */ - uint16_t cmpl_ring; + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED UINT32_C(0x2) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Value of 1 to indicate firmware support flow batch delete + * operation through HWRM_CFA_FLOW_FLUSH command. + * Value of 0 to indicate that the firmware does not support flow + * batch delete operation. (deprecated) */ - uint16_t seq_id; + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED UINT32_C(0x4) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Value of 1 to indicate that the firmware support flow reset all + * operation through HWRM_CFA_FLOW_FLUSH command. + * Value of 0 indicates firmware does not support flow reset all + * operation. (deprecated) */ - uint16_t target_id; + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED UINT32_C(0x8) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Value of 1 to indicate that firmware supports use of FID as + * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands. + * Value of 0 indicates firmware does not support use of FID as + * dest_id. */ - uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* unused. */ - uint8_t unused0[4]; -} hwrm_tf_session_qcfg_input_t, *phwrm_tf_session_qcfg_input_t; - -/* hwrm_tf_session_qcfg_output (size:128b/16B) */ - -typedef struct hwrm_tf_session_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* RX action control settings flags. */ - uint8_t rx_act_flags; + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED UINT32_C(0x10) /* - * A value of 1 in this field indicates that Global Flow ID - * reporting into cfa_code and cfa_metadata is enabled. + * Value of 1 to indicate that firmware supports TX EEM flows. + * Value of 0 indicates firmware does not support TX EEM flows. + * (deprecated) */ - #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN UINT32_C(0x1) + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED UINT32_C(0x20) /* - * A value of 1 in this field indicates that both inner and outer - * are stripped and inner tag is passed. - * Enabled. + * Value of 1 to indicate that firmware supports RX EEM flows. + * Value of 0 indicates firmware does not support RX EEM flows. + * (deprecated) */ - #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH UINT32_C(0x2) + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED UINT32_C(0x40) /* - * A value of 1 in this field indicates that the re-use of - * existing tunnel L2 header SMAC is enabled for - * Non-tunnel L2, L2-L3 and IP-IP tunnel. + * Value of 1 to indicate that firmware supports the dynamic + * allocation of an on-chip flow counter which can be used for EEM + * flows. Value of 0 indicates firmware does not support the dynamic + * allocation of an on-chip flow counter. + * (deprecated) */ - #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 UINT32_C(0x4) - /* TX Action control settings flags. */ - uint8_t tx_act_flags; - /* Disabled. */ - #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN UINT32_C(0x1) + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED UINT32_C(0x80) /* - * When set to 1 any GRE tunnels will include the - * optional Key field. + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. + * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. */ - #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K UINT32_C(0x2) + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED UINT32_C(0x100) /* - * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC) - * field of the outer header is inherited from the inner header - * (if present) or the fixed value as taken from the encap - * record. + * Value of 1 to indicate that firmware supports untagged matching + * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 + * indicates firmware does not support untagged matching. */ - #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH UINT32_C(0x4) + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED UINT32_C(0x200) /* - * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS) - * field of the outer header is inherited from the inner header - * (if present) or the fixed value as taken from the encap record. + * Value of 1 to indicate that firmware supports XDP filter. Value + * of 0 indicates firmware does not support XDP filter. */ - #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH UINT32_C(0x8) - /* unused. */ - uint8_t unused0[5]; + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED UINT32_C(0x400) + /* + * Value of 1 to indicate that the firmware support L2 header source + * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. + * Value of 0 indicates firmware does not support L2 header source + * fields matching. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED UINT32_C(0x800) + /* + * If set to 1, firmware is capable of supporting ARP ethertype as + * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the + * RX direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED UINT32_C(0x1000) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC + * command. Value of 0 indicates firmware does not support + * rfs_ring_tbl_idx in dst_id field. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED UINT32_C(0x2000) + /* + * If set to 1, firmware is capable of supporting IPv4/IPv6 as + * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX + * direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED UINT32_C(0x4000) + /* + * When this bit is '1', it indicates that core firmware is + * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX + * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE UINT32_C(0x8000) + /* + * If set to 1, firmware is capable of supporting L2/ROCE as + * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command. + * By default, this flag should be 0 for older version of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED UINT32_C(0x10000) + /* + * If set to 1, firmware is capable of HW LAG. This bit is only + * advertised if the calling function is a PAXC function. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED UINT32_C(0x20000) + /* + * If set to 1, firmware is capable installing ntuple rules without + * additional classification on the L2 Context. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED UINT32_C(0x40000) + /* + * If set to 1, firmware is capable returning stats for nic flows + * in cfa_flow_stats command where flow_handle value 0xF000. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NIC_FLOW_STATS_SUPPORTED UINT32_C(0x80000) + /* + * If set to 1, firmware is capable of supporting these additional + * ip_protocols: ICMP, ICMPV6, RSVD for ntuple rules. By default, + * this flag should be 0 for older version of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED UINT32_C(0x100000) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx (new offset) in HWRM_CFA_NTUPLE_ALLOC command. + * Value of 0 indicates ring tbl idx should be passed using dst_id. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED UINT32_C(0x200000) + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tf_session_qcfg_output_t, *phwrm_tf_session_qcfg_output_t; +} hwrm_cfa_adv_flow_mgnt_qcaps_output_t, *phwrm_cfa_adv_flow_mgnt_qcaps_output_t; -/****************************** - * hwrm_tf_session_resc_qcaps * - ******************************/ +/****************** + * hwrm_cfa_tflib * + ******************/ -/* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */ +/* hwrm_cfa_tflib_input (size:1024b/128B) */ -typedef struct hwrm_tf_session_resc_qcaps_input { +typedef struct hwrm_cfa_tflib_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48725,36 +52290,19 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX - /* - * Defines the size of the provided qcaps_addr array - * buffer. The size should be set to the Resource Manager - * provided max number of qcaps entries which is device - * specific. Resource Manager gets the max size from HCAPI - * RM. - */ - uint16_t qcaps_size; - /* - * This is the DMA address for the qcaps output data array - * buffer. Array is of tf_rm_resc_req_entry type and is - * device specific. - */ - uint64_t qcaps_addr; -} hwrm_tf_session_resc_qcaps_input_t, *phwrm_tf_session_resc_qcaps_input_t; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* unused. */ + uint8_t unused0[4]; + /* TFLIB request data. */ + uint32_t tf_req[26]; +} hwrm_cfa_tflib_input_t, *phwrm_cfa_tflib_input_t; -/* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */ +/* hwrm_cfa_tflib_output (size:5632b/704B) */ -typedef struct hwrm_tf_session_resc_qcaps_output { +typedef struct hwrm_cfa_tflib_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48763,33 +52311,14 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Control flags. */ - uint32_t flags; - /* Session reservation strategy. */ - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK UINT32_C(0x3) - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT 0 - /* Static partitioning. */ - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC UINT32_C(0x0) - /* Strategy 1. */ - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 UINT32_C(0x1) - /* Strategy 2. */ - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 UINT32_C(0x2) - /* Strategy 3. */ - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 UINT32_C(0x3) - #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 - /* - * Size of the returned qcaps_addr data array buffer. The - * value cannot exceed the size defined by the input msg, - * qcaps_size. - */ - uint16_t size; - /* - * SRAM profile number that sets the partition of SRAM memory - * between TF and AFM within the 4 internal memory banks (Thor). - */ - uint8_t sram_profile; - /* unused. */ - uint8_t unused0; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* TFLIB response code */ + uint32_t tf_resp_code; + /* TFLIB response data. */ + uint32_t tf_resp[170]; /* unused. */ uint8_t unused1[7]; /* @@ -48801,16 +52330,16 @@ * written last. */ uint8_t valid; -} hwrm_tf_session_resc_qcaps_output_t, *phwrm_tf_session_resc_qcaps_output_t; +} hwrm_cfa_tflib_output_t, *phwrm_cfa_tflib_output_t; -/****************************** - * hwrm_tf_session_resc_alloc * - ******************************/ +/********************************** + * hwrm_cfa_lag_group_member_rgtr * + **********************************/ -/* hwrm_tf_session_resc_alloc_input (size:320b/40B) */ +/* hwrm_cfa_lag_group_member_rgtr_input (size:192b/24B) */ -typedef struct hwrm_tf_session_resc_alloc_input { +typedef struct hwrm_cfa_lag_group_member_rgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48839,42 +52368,39 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX + uint8_t mode; /* - * Defines the array size of the provided req_addr and - * resv_addr array buffers. Should be set to the number of - * request entries. + * Transmit only on the active port. Automatically failover + * to backup port. */ - uint16_t req_size; + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP UINT32_C(0x1) /* - * This is the DMA address for the request input data array - * buffer. Array is of tf_rm_resc_req_entry type. Size of the - * array buffer is provided by the 'req_size' field in this - * message. + * Transmit based on packet header ntuple hash. Packet with only + * layer 2 headers will hash using the destination MAC, source MAC + * and Ethertype fields. Packets with layer 3 (IP) headers will + * hash using the destination MAC, source MAC, IP protocol/next + * header, source IP address and destination IP address. Packets + * with layer 4 (TCP/UDP) headers will hash using the destination + * MAC, source MAC, IP protocol/next header, source IP address, + * destination IP address, source port and destination port fields. */ - uint64_t req_addr; + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR UINT32_C(0x2) + /* Transmit packets on all specified ports. */ + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST UINT32_C(0x3) + #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_LAST HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST /* - * This is the DMA address for the resc output data array - * buffer. Array is of tf_rm_resc_entry type. Size of the array - * buffer is provided by the 'req_size' field in this - * message. + * Supports up to 5 ports. bit0 = port 0, bit1 = port 1, + * bit2 = port 2, bit3 = port 4, bit4 = loopback port */ - uint64_t resc_addr; -} hwrm_tf_session_resc_alloc_input_t, *phwrm_tf_session_resc_alloc_input_t; + uint8_t port_bitmap; + /* Specify the active port when active-backup mode is specified */ + uint8_t active_port; + uint8_t unused_0[5]; +} hwrm_cfa_lag_group_member_rgtr_input_t, *phwrm_cfa_lag_group_member_rgtr_input_t; -/* hwrm_tf_session_resc_alloc_output (size:128b/16B) */ +/* hwrm_cfa_lag_group_member_rgtr_output (size:128b/16B) */ -typedef struct hwrm_tf_session_resc_alloc_output { +typedef struct hwrm_cfa_lag_group_member_rgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48883,15 +52409,9 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Size of the returned tf_rm_resc_entry data array. The value - * cannot exceed the req_size defined by the input msg. The data - * array is returned using the resv_addr specified DMA - * address also provided by the input msg. - */ - uint16_t size; - /* unused. */ - uint8_t unused0[5]; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -48901,16 +52421,16 @@ * written last. */ uint8_t valid; -} hwrm_tf_session_resc_alloc_output_t, *phwrm_tf_session_resc_alloc_output_t; +} hwrm_cfa_lag_group_member_rgtr_output_t, *phwrm_cfa_lag_group_member_rgtr_output_t; -/***************************** - * hwrm_tf_session_resc_free * - *****************************/ +/************************************ + * hwrm_cfa_lag_group_member_unrgtr * + ************************************/ -/* hwrm_tf_session_resc_free_input (size:256b/32B) */ +/* hwrm_cfa_lag_group_member_unrgtr_input (size:192b/24B) */ -typedef struct hwrm_tf_session_resc_free_input { +typedef struct hwrm_cfa_lag_group_member_unrgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -48939,34 +52459,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX - /* - * Defines the size, in bytes, of the provided free_addr - * buffer. - */ - uint16_t free_size; - /* - * This is the DMA address for the free input data array - * buffer. Array is of tf_rm_resc_entry type. Size of the - * buffer is provided by the 'free_size' field of this - * message. - */ - uint64_t free_addr; -} hwrm_tf_session_resc_free_input_t, *phwrm_tf_session_resc_free_input_t; + /* lag group ID configured for the function */ + uint16_t lag_id; + uint8_t unused_0[6]; +} hwrm_cfa_lag_group_member_unrgtr_input_t, *phwrm_cfa_lag_group_member_unrgtr_input_t; -/* hwrm_tf_session_resc_free_output (size:128b/16B) */ +/* hwrm_cfa_lag_group_member_unrgtr_output (size:128b/16B) */ -typedef struct hwrm_tf_session_resc_free_output { +typedef struct hwrm_cfa_lag_group_member_unrgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -48975,8 +52475,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -48986,16 +52485,16 @@ * written last. */ uint8_t valid; -} hwrm_tf_session_resc_free_output_t, *phwrm_tf_session_resc_free_output_t; +} hwrm_cfa_lag_group_member_unrgtr_output_t, *phwrm_cfa_lag_group_member_unrgtr_output_t; -/****************************** - * hwrm_tf_session_resc_flush * - ******************************/ +/***************************** + * hwrm_cfa_tls_filter_alloc * + *****************************/ -/* hwrm_tf_session_resc_flush_input (size:256b/32B) */ +/* hwrm_cfa_tls_filter_alloc_input (size:768b/96B) */ -typedef struct hwrm_tf_session_resc_flush_input { +typedef struct hwrm_cfa_tls_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49024,34 +52523,149 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX + uint32_t unused_0; + uint32_t enables; /* - * Defines the size, in bytes, of the provided flush_addr - * buffer. + * This bit must be '1' for the l2_filter_id field to be + * configured. */ - uint16_t flush_size; + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) /* - * This is the DMA address for the flush input data array - * buffer. Array of tf_rm_resc_entry type. Size of the - * buffer is provided by the 'flush_size' field in this - * message. + * This bit must be '1' for the ethertype field to be + * configured. */ - uint64_t flush_addr; -} hwrm_tf_session_resc_flush_input_t, *phwrm_tf_session_resc_flush_input_t; + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2) + /* + * This bit must be '1' for the ipaddr_type field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x4) + /* + * This bit must be '1' for the src_ipaddr field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x8) + /* + * This bit must be '1' for the dst_ipaddr field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x10) + /* + * This bit must be '1' for the ip_protocol field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x20) + /* + * This bit must be '1' for the src_port field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x40) + /* + * This bit must be '1' for the dst_port field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x80) + /* + * This bit must be '1' for the kid field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_KID UINT32_C(0x100) + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x200) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x400) + /* + * This bit must be '1' for the quic_dst_connect_id field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_QUIC_DST_CONNECT_ID UINT32_C(0x800) + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + uint8_t unused_1[6]; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; + /* + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + /* + * The value of protocol field in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP + */ + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. + */ + uint16_t dst_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint16_t mirror_vnic_id; + uint8_t unused_2[2]; + /* + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t src_ipaddr[4]; + /* + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t dst_ipaddr[4]; + /* + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t src_port; + /* + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t dst_port; + /* + * The Key Context Identifier (KID) for use with KTLS or QUIC. + * KID is limited to 20-bits. + */ + uint32_t kid; + /* The Destination Connection ID of QUIC. */ + uint64_t quic_dst_connect_id; +} hwrm_cfa_tls_filter_alloc_input_t, *phwrm_cfa_tls_filter_alloc_input_t; -/* hwrm_tf_session_resc_flush_output (size:128b/16B) */ +/* hwrm_cfa_tls_filter_alloc_output (size:192b/24B) */ -typedef struct hwrm_tf_session_resc_flush_output { +typedef struct hwrm_cfa_tls_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49060,8 +52674,40 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; + /* This value is an opaque id into CFA data structures. */ + uint64_t tls_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff) + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30) + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31) + #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -49071,16 +52717,16 @@ * written last. */ uint8_t valid; -} hwrm_tf_session_resc_flush_output_t, *phwrm_tf_session_resc_flush_output_t; +} hwrm_cfa_tls_filter_alloc_output_t, *phwrm_cfa_tls_filter_alloc_output_t; -/***************************** - * hwrm_tf_session_resc_info * - *****************************/ +/**************************** + * hwrm_cfa_tls_filter_free * + ****************************/ -/* hwrm_tf_session_resc_info_input (size:320b/40B) */ +/* hwrm_cfa_tls_filter_free_input (size:192b/24B) */ -typedef struct hwrm_tf_session_resc_info_input { +typedef struct hwrm_cfa_tls_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49109,42 +52755,13 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX - /* - * Defines the array size of the provided req_addr and - * resv_addr array buffers. Should be set to the number of - * request entries. - */ - uint16_t req_size; - /* - * This is the DMA address for the request input data array - * buffer. Array is of tf_rm_resc_req_entry type. Size of the - * array buffer is provided by the 'req_size' field in this - * message. - */ - uint64_t req_addr; - /* - * This is the DMA address for the resc output data array - * buffer. Array is of tf_rm_resc_entry type. Size of the array - * buffer is provided by the 'req_size' field in this - * message. - */ - uint64_t resc_addr; -} hwrm_tf_session_resc_info_input_t, *phwrm_tf_session_resc_info_input_t; + /* This value is an opaque id into CFA data structures. */ + uint64_t tls_filter_id; +} hwrm_cfa_tls_filter_free_input_t, *phwrm_cfa_tls_filter_free_input_t; -/* hwrm_tf_session_resc_info_output (size:128b/16B) */ +/* hwrm_cfa_tls_filter_free_output (size:128b/16B) */ -typedef struct hwrm_tf_session_resc_info_output { +typedef struct hwrm_cfa_tls_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49153,15 +52770,7 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Size of the returned tf_rm_resc_entry data array. The value - * cannot exceed the req_size defined by the input msg. The data - * array is returned using the resv_addr specified DMA - * address also provided by the input msg. - */ - uint16_t size; - /* unused. */ - uint8_t unused0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -49171,40 +52780,16 @@ * written last. */ uint8_t valid; -} hwrm_tf_session_resc_info_output_t, *phwrm_tf_session_resc_info_output_t; - -/* TruFlow RM capability of a resource. */ -/* tf_rm_resc_req_entry (size:64b/8B) */ - -typedef struct tf_rm_resc_req_entry { - /* Type of the resource, defined globally in HCAPI RM. */ - uint32_t type; - /* Minimum value. */ - uint16_t min; - /* Maximum value. */ - uint16_t max; -} tf_rm_resc_req_entry_t, *ptf_rm_resc_req_entry_t; - -/* TruFlow RM reservation information. */ -/* tf_rm_resc_entry (size:64b/8B) */ - -typedef struct tf_rm_resc_entry { - /* Type of the resource, defined globally in HCAPI RM. */ - uint32_t type; - /* Start offset. */ - uint16_t start; - /* Number of resources. */ - uint16_t stride; -} tf_rm_resc_entry_t, *ptf_rm_resc_entry_t; +} hwrm_cfa_tls_filter_free_output_t, *phwrm_cfa_tls_filter_free_output_t; -/************************ - * hwrm_tf_tbl_type_get * - ************************/ +/***************************** + * hwrm_cfa_release_afm_func * + *****************************/ -/* hwrm_tf_tbl_type_get_input (size:256b/32B) */ +/* hwrm_cfa_release_afm_func_input (size:256b/32B) */ -typedef struct hwrm_tf_tbl_type_get_input { +typedef struct hwrm_cfa_release_afm_func_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49233,36 +52818,37 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX - /* - * When set use the special access register access to clear - * the table entry on read. - */ - #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2) - /* unused. */ - uint8_t unused0[2]; + /* Function identifier, may be of type efid, rfid or dfid. */ + uint16_t fid; + /* Representor function identifier. */ + uint16_t rfid; + /* Fid type. */ + uint8_t type; + /* Endpoint fid. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_EFID UINT32_C(0x1) + /* Representor fid. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_RFID UINT32_C(0x2) + /* Redirect fid. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_DFID UINT32_C(0x3) + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_LAST HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_DFID + uint8_t unused_0[3]; /* - * Type of the resource, defined globally in the - * hwrm_tf_resc_type enum. + * Flags used to control AFMs actions when releasing the function. + * Only used when type is dfid. */ - uint32_t type; - /* Index of the type to retrieve. */ - uint32_t index; -} hwrm_tf_tbl_type_get_input_t, *phwrm_tf_tbl_type_get_input_t; + uint32_t flags; + /* Remove broadcast. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_BC_REM UINT32_C(0x1) + /* Remove multicast. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_MC_REM UINT32_C(0x2) + /* Remove promiscuous. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_PROMISC_REM UINT32_C(0x4) + uint32_t unused_1; +} hwrm_cfa_release_afm_func_input_t, *phwrm_cfa_release_afm_func_input_t; -/* hwrm_tf_tbl_type_get_output (size:2240b/280B) */ +/* hwrm_cfa_release_afm_func_output (size:128b/16B) */ -typedef struct hwrm_tf_tbl_type_get_output { +typedef struct hwrm_cfa_release_afm_func_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49271,35 +52857,26 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Response code. */ - uint32_t resp_code; - /* Response size. */ - uint16_t size; - /* unused */ - uint16_t unused0; - /* Response data. */ - uint8_t data[256]; - /* unused */ - uint8_t unused1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tf_tbl_type_get_output_t, *phwrm_tf_tbl_type_get_output_t; +} hwrm_cfa_release_afm_func_output_t, *phwrm_cfa_release_afm_func_output_t; -/************************ - * hwrm_tf_tbl_type_set * - ************************/ +/*********** + * hwrm_tf * + ***********/ -/* hwrm_tf_tbl_type_set_input (size:1024b/128B) */ +/* hwrm_tf_input (size:1024b/128B) */ -typedef struct hwrm_tf_tbl_type_set_input { +typedef struct hwrm_tf_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49328,39 +52905,19 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX - /* Indicate table data is being sent via DMA. */ - #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* TF message type. */ + uint16_t type; + /* TF message subtype. */ + uint16_t subtype; /* unused. */ - uint8_t unused0[2]; - /* - * Type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ - uint32_t type; - /* Index of the type to retrieve. */ - uint32_t index; - /* Size of the data to set. */ - uint16_t size; - /* unused */ - uint8_t unused1[6]; - /* Data to be set. */ - uint8_t data[88]; -} hwrm_tf_tbl_type_set_input_t, *phwrm_tf_tbl_type_set_input_t; + uint8_t unused0[4]; + /* TF request data. */ + uint32_t req[26]; +} hwrm_tf_input_t, *phwrm_tf_input_t; -/* hwrm_tf_tbl_type_set_output (size:128b/16B) */ +/* hwrm_tf_output (size:5632b/704B) */ -typedef struct hwrm_tf_tbl_type_set_output { +typedef struct hwrm_tf_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49369,27 +52926,35 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* TF message type. */ + uint16_t type; + /* TF message subtype. */ + uint16_t subtype; + /* TF response code */ + uint32_t resp_code; + /* TF response data. */ + uint32_t resp[170]; /* unused. */ - uint8_t unused0[7]; + uint8_t unused1[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} hwrm_tf_tbl_type_set_output_t, *phwrm_tf_tbl_type_set_output_t; +} hwrm_tf_output_t, *phwrm_tf_output_t; -/************************** - * hwrm_tf_ctxt_mem_alloc * - **************************/ +/*********************** + * hwrm_tf_version_get * + ***********************/ -/* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */ +/* hwrm_tf_version_get_input (size:128b/16B) */ -typedef struct hwrm_tf_ctxt_mem_alloc_input { +typedef struct hwrm_tf_version_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49418,15 +52983,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Size in KB of memory to be allocated. */ - uint32_t mem_size; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; -} hwrm_tf_ctxt_mem_alloc_input_t, *phwrm_tf_ctxt_mem_alloc_input_t; +} hwrm_tf_version_get_input_t, *phwrm_tf_version_get_input_t; -/* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */ +/* hwrm_tf_version_get_output (size:256b/32B) */ -typedef struct hwrm_tf_ctxt_mem_alloc_output { +typedef struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49435,68 +52996,40 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; - /* Size of memory allocated. */ - uint32_t mem_size; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* Version Major number. */ + uint8_t major; + /* Version Minor number. */ + uint8_t minor; + /* Version Update number. */ + uint8_t update; + /* unused. */ + uint8_t unused0[5]; /* - * PBL pointer points to PDE table with each entry pointing - * to PTE tables. - */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 128KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5) - /* 256KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 512KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7) - /* 1MB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 8MB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb) - /* 1GB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G + * This field is used to indicate device's capabilities and + * configurations. + */ + uint64_t dev_caps_cfg; /* unused. */ - uint8_t unused0; + uint8_t unused1[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tf_ctxt_mem_alloc_output_t, *phwrm_tf_ctxt_mem_alloc_output_t; +} hwrm_tf_version_get_output_t, *phwrm_tf_version_get_output_t; -/************************* - * hwrm_tf_ctxt_mem_free * - *************************/ +/************************ + * hwrm_tf_session_open * + ************************/ -/* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */ +/* hwrm_tf_session_open_input (size:640b/80B) */ -typedef struct hwrm_tf_ctxt_mem_free_input { +typedef struct hwrm_tf_session_open_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49525,58 +53058,13 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* - * PBL pointer points to PDE table with each entry pointing - * to PTE tables. - */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 128KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5) - /* 256KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 512KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7) - /* 1MB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 8MB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb) - /* 1GB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G - /* unused. */ - uint8_t unused0[2]; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; - /* Size of memory allocated. */ - uint32_t mem_size; - /* unused. */ - uint8_t unused1[4]; -} hwrm_tf_ctxt_mem_free_input_t, *phwrm_tf_ctxt_mem_free_input_t; + /* Name of the session. */ + uint8_t session_name[64]; +} hwrm_tf_session_open_input_t, *phwrm_tf_session_open_input_t; -/* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */ +/* hwrm_tf_session_open_output (size:192b/24B) */ -typedef struct hwrm_tf_ctxt_mem_free_output { +typedef struct hwrm_tf_session_open_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49585,27 +53073,56 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* + * Unique session identifier for the session created by the + * firmware. + */ + uint32_t fw_session_id; + /* + * Unique session client identifier for the first client on + * the newly created session. + */ + uint32_t fw_session_client_id; + /* This field is used to return the status of fw session to host. */ + uint32_t flags; + /* + * Indicates if the shared session has been created. Shared session + * should be the first session created ever. Its fw_rm_client_id + * should be 1. The AFM session's fw_rm_client_id is 0. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION UINT32_C(0x1) + /* + * If this bit set to 0, then it indicates the shared session + * has been created by another session. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR UINT32_C(0x0) + /* + * If this bit is set to 1, then it indicates the shared session + * is created by this session. + */ + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR UINT32_C(0x1) + #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_LAST HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR /* unused. */ - uint8_t unused0[7]; + uint8_t unused1[3]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tf_ctxt_mem_free_output_t, *phwrm_tf_ctxt_mem_free_output_t; +} hwrm_tf_session_open_output_t, *phwrm_tf_session_open_output_t; -/************************* - * hwrm_tf_ctxt_mem_rgtr * - *************************/ +/**************************** + * hwrm_tf_session_register * + ****************************/ -/* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */ +/* hwrm_tf_session_register_input (size:704b/88B) */ -typedef struct hwrm_tf_ctxt_mem_rgtr_input { +typedef struct hwrm_tf_session_register_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49634,54 +53151,24 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Control flags. */ - uint16_t flags; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) /* - * PBL pointer points to PDE table with each entry pointing - * to PTE tables. + * Unique session identifier for the session that the + * register request want to create a new client on. This + * value originates from the first open request. + * The fw_session_id of the attach session includes PCIe bus + * info to distinguish the PF and session info to identify + * the associated TruFlow session. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 128KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5) - /* 256KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 512KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7) - /* 1MB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 8MB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb) - /* 1GB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; -} hwrm_tf_ctxt_mem_rgtr_input_t, *phwrm_tf_ctxt_mem_rgtr_input_t; + /* unused. */ + uint32_t unused0; + /* Name of the session client. */ + uint8_t session_client_name[64]; +} hwrm_tf_session_register_input_t, *phwrm_tf_session_register_input_t; -/* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */ +/* hwrm_tf_session_register_output (size:128b/16B) */ -typedef struct hwrm_tf_ctxt_mem_rgtr_output { +typedef struct hwrm_tf_session_register_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49691,31 +53178,32 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Id/Handle to the recently register context memory. This - * handle is passed to the TF session. + * Unique session client identifier for the session created + * by the firmware. It includes the session the client it + * attached to and session client info. */ - uint16_t ctx_id; + uint32_t fw_session_client_id; /* unused. */ - uint8_t unused0[5]; + uint8_t unused0[3]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tf_ctxt_mem_rgtr_output_t, *phwrm_tf_ctxt_mem_rgtr_output_t; +} hwrm_tf_session_register_output_t, *phwrm_tf_session_register_output_t; -/*************************** - * hwrm_tf_ctxt_mem_unrgtr * - ***************************/ +/****************************** + * hwrm_tf_session_unregister * + ******************************/ -/* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */ +/* hwrm_tf_session_unregister_input (size:192b/24B) */ -typedef struct hwrm_tf_ctxt_mem_unrgtr_input { +typedef struct hwrm_tf_session_unregister_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49745,19 +53233,20 @@ */ uint64_t resp_addr; /* - * Id/Handle to the recently register context memory. This - * handle is passed to the TF session. + * Unique session identifier for the session that the + * unregister request want to close a session client on. */ - uint16_t ctx_id; - /* unused. */ - uint8_t unused0[2]; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; -} hwrm_tf_ctxt_mem_unrgtr_input_t, *phwrm_tf_ctxt_mem_unrgtr_input_t; + /* + * Unique session client identifier for the session that the + * unregister request want to close. + */ + uint32_t fw_session_client_id; +} hwrm_tf_session_unregister_input_t, *phwrm_tf_session_unregister_input_t; -/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */ +/* hwrm_tf_session_unregister_output (size:128b/16B) */ -typedef struct hwrm_tf_ctxt_mem_unrgtr_output { +typedef struct hwrm_tf_session_unregister_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49769,24 +53258,24 @@ /* unused. */ uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tf_ctxt_mem_unrgtr_output_t, *phwrm_tf_ctxt_mem_unrgtr_output_t; +} hwrm_tf_session_unregister_output_t, *phwrm_tf_session_unregister_output_t; -/************************ - * hwrm_tf_ext_em_qcaps * - ************************/ +/************************* + * hwrm_tf_session_close * + *************************/ -/* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */ +/* hwrm_tf_session_close_input (size:192b/24B) */ -typedef struct hwrm_tf_ext_em_qcaps_input { +typedef struct hwrm_tf_session_close_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49815,24 +53304,15 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Control flags. */ - uint32_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX - /* When set to 1, all offloaded flows will be sent to EXT EM. */ - #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x2) /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; -} hwrm_tf_ext_em_qcaps_input_t, *phwrm_tf_ext_em_qcaps_input_t; + /* unused. */ + uint8_t unused0[4]; +} hwrm_tf_session_close_input_t, *phwrm_tf_session_close_input_t; -/* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */ +/* hwrm_tf_session_close_output (size:128b/16B) */ -typedef struct hwrm_tf_ext_em_qcaps_output { +typedef struct hwrm_tf_session_close_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -49841,119 +53321,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * When set to 1, indicates the FW supports the Centralized - * Memory Model. The concept designates one entity for the - * memory allocation while all others ‘subscribe’ to it. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x1) - /* - * When set to 1, indicates the FW supports the Detached - * Centralized Memory Model. The memory is allocated and managed - * as a separate entity. All PFs and VFs will be granted direct - * or semi-direct access to the allocated memory while none of - * which can interfere with the management of the memory. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x2) - /* When set to 1, indicates FW support for host based EEM memory. */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED UINT32_C(0x4) - /* When set to 1, indicates FW support for on-chip based EEM memory. */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED UINT32_C(0x8) - /* unused. */ - uint32_t unused0; - /* Support flags. */ - uint32_t supported; - /* - * If set to 1, then EXT EM KEY0 table is supported using - * crc32 hash. - * If set to 0, EXT EM KEY0 table is not supported. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE UINT32_C(0x1) - /* - * If set to 1, then EXT EM KEY1 table is supported using - * lookup3 hash. - * If set to 0, EXT EM KEY1 table is not supported. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE UINT32_C(0x2) - /* - * If set to 1, then EXT EM External Record table is supported. - * If set to 0, EXT EM External Record table is not - * supported. (This table includes action record, EFC - * pointers, encap pointers) - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE UINT32_C(0x4) - /* - * If set to 1, then EXT EM External Flow Counters table is - * supported. - * If set to 0, EXT EM External Flow Counters table is not - * supported. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE UINT32_C(0x8) - /* - * If set to 1, then FID table used for implicit flow flush - * is supported. - * If set to 0, then FID table used for implicit flow flush - * is not supported. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE UINT32_C(0x10) - /* - * If set to 1, then table scopes are supported. - * If set to 0, then table scopes are not supported. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES UINT32_C(0x20) - /* - * The maximum number of entries supported by EXT EM. When - * configuring the host memory the number of numbers of - * entries that can supported are - - * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, - * 128M entries. - * Any value that are not these values, the FW will round - * down to the closest support number of entries. - */ - uint32_t max_entries_supported; - /* - * The entry size in bytes of each entry in the EXT EM - * KEY0/KEY1 tables. - */ - uint16_t key_entry_size; - /* - * The entry size in bytes of each entry in the EXT EM RECORD - * tables. - */ - uint16_t record_entry_size; - /* The entry size in bytes of each entry in the EXT EM EFC tables. */ - uint16_t efc_entry_size; - /* The FID size in bytes of each entry in the EXT EM FID tables. */ - uint16_t fid_entry_size; - /* Maximum number of ctxt mem allocations allowed. */ - uint32_t max_ctxt_mem_allocs; - /* - * Maximum number of static buckets that can be assigned to lookup - * table scopes. - */ - uint32_t max_static_buckets; /* unused. */ - uint8_t unused1[7]; + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tf_ext_em_qcaps_output_t, *phwrm_tf_ext_em_qcaps_output_t; +} hwrm_tf_session_close_output_t, *phwrm_tf_session_close_output_t; -/********************* - * hwrm_tf_ext_em_op * - *********************/ +/************************ + * hwrm_tf_session_qcfg * + ************************/ -/* hwrm_tf_ext_em_op_input (size:256b/32B) */ +/* hwrm_tf_session_qcfg_input (size:192b/24B) */ -typedef struct hwrm_tf_ext_em_op_input { +typedef struct hwrm_tf_session_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49982,54 +53370,15 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX - /* unused. */ - uint16_t unused0; - /* The number of EXT EM key table entries to be configured. */ - uint16_t op; - /* This value is reserved and should not be used. */ - #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0) - /* - * To properly stop EXT EM and ensure there are no DMA's, - * the caller must disable EXT EM for the given PF, using - * this call. This will safely disable EXT EM and ensure - * that all DMA'ed to the keys/records/efc have been - * completed. - */ - #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1) - /* - * Once the EXT EM host memory has been configured, EXT EM - * options have been configured. Then the caller should - * enable EXT EM for the given PF. Note once this call has - * been made, then the EXT EM mechanism will be active and - * DMA's will occur as packets are processed. - */ - #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2) - /* - * Clear EXT EM settings for the given PF so that the - * register values are reset back to their initial state. - */ - #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3) - #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP - /* unused. */ - uint16_t unused1; /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* unused. */ - uint32_t unused2; -} hwrm_tf_ext_em_op_input_t, *phwrm_tf_ext_em_op_input_t; + uint8_t unused0[4]; +} hwrm_tf_session_qcfg_input_t, *phwrm_tf_session_qcfg_input_t; -/* hwrm_tf_ext_em_op_output (size:128b/16B) */ +/* hwrm_tf_session_qcfg_output (size:128b/16B) */ -typedef struct hwrm_tf_ext_em_op_output { +typedef struct hwrm_tf_session_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50038,27 +53387,68 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* RX action control settings flags. */ + uint8_t rx_act_flags; + /* + * A value of 1 in this field indicates that Global Flow ID + * reporting into cfa_code and cfa_metadata is enabled. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN UINT32_C(0x1) + /* + * A value of 1 in this field indicates that both inner and outer + * are stripped and inner tag is passed. + * Enabled. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH UINT32_C(0x2) + /* + * A value of 1 in this field indicates that the re-use of + * existing tunnel L2 header SMAC is enabled for + * Non-tunnel L2, L2-L3 and IP-IP tunnel. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 UINT32_C(0x4) + /* TX Action control settings flags. */ + uint8_t tx_act_flags; + /* Disabled. */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN UINT32_C(0x1) + /* + * When set to 1 any GRE tunnels will include the + * optional Key field. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K UINT32_C(0x2) + /* + * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC) + * field of the outer header is inherited from the inner header + * (if present) or the fixed value as taken from the encap + * record. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH UINT32_C(0x4) + /* + * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS) + * field of the outer header is inherited from the inner header + * (if present) or the fixed value as taken from the encap record. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH UINT32_C(0x8) /* unused. */ - uint8_t unused0[7]; + uint8_t unused0[5]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tf_ext_em_op_output_t, *phwrm_tf_ext_em_op_output_t; +} hwrm_tf_session_qcfg_output_t, *phwrm_tf_session_qcfg_output_t; -/********************** - * hwrm_tf_ext_em_cfg * - **********************/ +/****************************** + * hwrm_tf_session_resc_qcaps * + ******************************/ -/* hwrm_tf_ext_em_cfg_input (size:512b/64B) */ +/* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */ -typedef struct hwrm_tf_ext_em_cfg_input { +typedef struct hwrm_tf_session_resc_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50087,139 +53477,36 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; /* Control flags. */ - uint32_t flags; + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX - /* When set to 1, all offloaded flows will be sent to EXT EM. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x2) - /* When set to 1, secondary, 0 means primary. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF UINT32_C(0x4) - /* - * Group_id which used by Firmware to identify memory pools belonging - * to certain group. - */ - uint16_t group_id; - /* - * Dynamically reconfigure EEM pending cache every 1/10th of second. - * If set to 0 it will disable the EEM HW flush of the pending cache. - */ - uint8_t flush_interval; - /* unused. */ - uint8_t unused0; - /* - * Configured EXT EM with the given number of entries. All - * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the - * same number of entries and all tables will be configured - * using this value. Current minimum value is 32k. Current - * maximum value is 128M. - */ - uint32_t num_entries; - uint32_t enables; - /* - * This bit must be '1' for the group_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID UINT32_C(0x1) - /* - * This bit must be '1' for the flush_interval field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL UINT32_C(0x2) - /* - * This bit must be '1' for the num_entries field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES UINT32_C(0x4) - /* - * This bit must be '1' for the key0_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID UINT32_C(0x8) - /* - * This bit must be '1' for the key1_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID UINT32_C(0x10) - /* - * This bit must be '1' for the record_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID UINT32_C(0x20) - /* - * This bit must be '1' for the efc_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID UINT32_C(0x40) - /* - * This bit must be '1' for the fid_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID UINT32_C(0x80) - /* - * This bit must be '1' for the action_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID UINT32_C(0x100) - /* - * This bit must be '1' for the action_tbl_scope field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE UINT32_C(0x200) - /* - * This bit must be '1' for the lkup_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID UINT32_C(0x400) - /* - * This bit must be '1' for the lkup_tbl_scope field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE UINT32_C(0x800) + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX /* - * This bit must be '1' for the lkup_static_buckets field to be - * configured. + * Defines the size of the provided qcaps_addr array + * buffer. The size should be set to the Resource Manager + * provided max number of qcaps entries which is device + * specific. Resource Manager gets the max size from HCAPI + * RM. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS UINT32_C(0x1000) - /* Configured EXT EM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EXT EM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EXT EM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - /* Context id of action table scope. */ - uint16_t action_ctx_id; - /* Table scope id used for action record entries. */ - uint16_t action_tbl_scope; - /* Context id of lookup table scope. */ - uint16_t lkup_ctx_id; - /* Table scope id used for EM lookup entries. */ - uint16_t lkup_tbl_scope; - /* unused. */ - uint16_t unused1; + uint16_t qcaps_size; /* - * Number of 32B static buckets to be allocated at the beginning - * of table scope. + * This is the DMA address for the qcaps output data array + * buffer. Array is of tf_rm_resc_req_entry type and is + * device specific. */ - uint32_t lkup_static_buckets; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* unused. */ - uint32_t unused2; -} hwrm_tf_ext_em_cfg_input_t, *phwrm_tf_ext_em_cfg_input_t; + uint64_t qcaps_addr; +} hwrm_tf_session_resc_qcaps_input_t, *phwrm_tf_session_resc_qcaps_input_t; -/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */ +/* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */ -typedef struct hwrm_tf_ext_em_cfg_output { +typedef struct hwrm_tf_session_resc_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50228,27 +53515,54 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Control flags. */ + uint32_t flags; + /* Session reservation strategy. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK UINT32_C(0x3) + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT 0 + /* Static partitioning. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC UINT32_C(0x0) + /* Strategy 1. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 UINT32_C(0x1) + /* Strategy 2. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 UINT32_C(0x2) + /* Strategy 3. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 UINT32_C(0x3) + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 + /* + * Size of the returned qcaps_addr data array buffer. The + * value cannot exceed the size defined by the input msg, + * qcaps_size. + */ + uint16_t size; + /* + * SRAM profile number that sets the partition of SRAM memory + * between TF and AFM within the 4 internal memory banks (Thor). + */ + uint8_t sram_profile; /* unused. */ - uint8_t unused0[7]; + uint8_t unused0; + /* unused. */ + uint8_t unused1[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tf_ext_em_cfg_output_t, *phwrm_tf_ext_em_cfg_output_t; +} hwrm_tf_session_resc_qcaps_output_t, *phwrm_tf_session_resc_qcaps_output_t; -/*********************** - * hwrm_tf_ext_em_qcfg * - ***********************/ +/****************************** + * hwrm_tf_session_resc_alloc * + ******************************/ -/* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */ +/* hwrm_tf_session_resc_alloc_input (size:320b/40B) */ -typedef struct hwrm_tf_ext_em_qcfg_input { +typedef struct hwrm_tf_session_resc_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50277,181 +53591,42 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Control flags. */ - uint32_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; -} hwrm_tf_ext_em_qcfg_input_t, *phwrm_tf_ext_em_qcfg_input_t; - -/* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */ - -typedef struct hwrm_tf_ext_em_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; /* Control flags. */ - uint32_t flags; + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX - /* When set to 1, all offloaded flows will be sent to EXT EM. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x2) - /* The number of entries the FW has configured for EXT EM. */ - uint32_t num_entries; - /* Configured EXT EM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EXT EM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EXT EM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - /* unused. */ - uint16_t unused0; - uint32_t supported; - /* This bit must be '1' for the group_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID UINT32_C(0x1) - /* This bit must be '1' for the flush_interval field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL UINT32_C(0x2) - /* This bit must be '1' for the num_entries field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES UINT32_C(0x4) - /* This bit must be '1' for the key0_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID UINT32_C(0x8) - /* This bit must be '1' for the key1_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID UINT32_C(0x10) - /* This bit must be '1' for the record_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID UINT32_C(0x20) - /* This bit must be '1' for the efc_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID UINT32_C(0x40) - /* This bit must be '1' for the fid_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID UINT32_C(0x80) - /* This bit must be '1' for the action_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID UINT32_C(0x100) - /* This bit must be '1' for the action_tbl_scope field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE UINT32_C(0x200) - /* This bit must be '1' for the lkup_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID UINT32_C(0x400) - /* This bit must be '1' for the lkup_tbl_scope field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE UINT32_C(0x800) - /* This bit must be '1' for the lkup_static_buckets field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS UINT32_C(0x1000) - /* - * Group id is used by firmware to identify memory pools belonging - * to certain group. - */ - uint16_t group_id; - /* EEM pending cache flush interval in 1/10th of second. */ - uint8_t flush_interval; - /* unused. */ - uint8_t unused1; - /* Context id of action table scope. */ - uint16_t action_ctx_id; - /* Table scope id used for action record entries. */ - uint16_t action_tbl_scope; - /* Context id of lookup table scope. */ - uint16_t lkup_ctx_id; - /* Table scope id used for EM lookup entries. */ - uint16_t lkup_tbl_scope; - /* - * Number of 32B static buckets to be allocated at the beginning - * of table scope. - */ - uint32_t lkup_static_buckets; - /* unused. */ - uint8_t unused2[7]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; -} hwrm_tf_ext_em_qcfg_output_t, *phwrm_tf_ext_em_qcfg_output_t; - -/********************* - * hwrm_tf_em_insert * - *********************/ - - -/* hwrm_tf_em_insert_input (size:832b/104B) */ - -typedef struct hwrm_tf_em_insert_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. */ - uint16_t seq_id; + uint16_t req_size; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This is the DMA address for the request input data array + * buffer. Array is of tf_rm_resc_req_entry type. Size of the + * array buffer is provided by the 'req_size' field in this + * message. */ - uint16_t target_id; + uint64_t req_addr; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This is the DMA address for the resc output data array + * buffer. Array is of tf_rm_resc_entry type. Size of the array + * buffer is provided by the 'req_size' field in this + * message. */ - uint64_t resp_addr; - /* Firmware Session Id. */ - uint32_t fw_session_id; - /* Control Flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX - /* Reported match strength. */ - uint16_t strength; - /* Index to action. */ - uint32_t action_ptr; - /* Index of EM record. */ - uint32_t em_record_idx; - /* EM Key value. */ - uint64_t em_key[8]; - /* Number of bits in em_key. */ - uint16_t em_key_bitlen; - /* unused. */ - uint16_t unused0[3]; -} hwrm_tf_em_insert_input_t, *phwrm_tf_em_insert_input_t; + uint64_t resc_addr; +} hwrm_tf_session_resc_alloc_input_t, *phwrm_tf_session_resc_alloc_input_t; -/* hwrm_tf_em_insert_output (size:128b/16B) */ +/* hwrm_tf_session_resc_alloc_output (size:128b/16B) */ -typedef struct hwrm_tf_em_insert_output { +typedef struct hwrm_tf_session_resc_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50460,24 +53635,34 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* EM record pointer index. */ - uint16_t rptr_index; - /* EM record offset 0~3. */ - uint8_t rptr_entry; - /* Number of word entries consumed by the key. */ - uint8_t num_of_entries; + /* + * Size of the returned tf_rm_resc_entry data array. The value + * cannot exceed the req_size defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; /* unused. */ - uint32_t unused0; -} hwrm_tf_em_insert_output_t, *phwrm_tf_em_insert_output_t; + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} hwrm_tf_session_resc_alloc_output_t, *phwrm_tf_session_resc_alloc_output_t; -/************************** - * hwrm_tf_em_hash_insert * - **************************/ +/****************************** + * hwrm_tf_session_resc_flush * + ******************************/ -/* hwrm_tf_em_hash_insert_input (size:1024b/128B) */ +/* hwrm_tf_session_resc_flush_input (size:256b/32B) */ -typedef struct hwrm_tf_em_hash_insert_input { +typedef struct hwrm_tf_session_resc_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50506,34 +53691,34 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware Session Id. */ + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; - /* Control Flags. */ + /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX - /* Number of bits in the EM record. */ - uint16_t em_record_size_bits; - /* CRC32 hash of key. */ - uint32_t key0_hash; - /* Lookup3 hash of key. */ - uint32_t key1_hash; - /* Index of EM record. */ - uint32_t em_record_idx; - /* Unused. */ - uint32_t unused0; - /* EM record. */ - uint64_t em_record[11]; -} hwrm_tf_em_hash_insert_input_t, *phwrm_tf_em_hash_insert_input_t; + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided flush_addr + * buffer. + */ + uint16_t flush_size; + /* + * This is the DMA address for the flush input data array + * buffer. Array of tf_rm_resc_entry type. Size of the + * buffer is provided by the 'flush_size' field in this + * message. + */ + uint64_t flush_addr; +} hwrm_tf_session_resc_flush_input_t, *phwrm_tf_session_resc_flush_input_t; -/* hwrm_tf_em_hash_insert_output (size:128b/16B) */ +/* hwrm_tf_session_resc_flush_output (size:128b/16B) */ -typedef struct hwrm_tf_em_hash_insert_output { +typedef struct hwrm_tf_session_resc_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50542,24 +53727,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* EM record pointer index. */ - uint16_t rptr_index; - /* EM record offset 0~3. */ - uint8_t rptr_entry; - /* Number of word entries consumed by the key. */ - uint8_t num_of_entries; /* unused. */ - uint32_t unused0; -} hwrm_tf_em_hash_insert_output_t, *phwrm_tf_em_hash_insert_output_t; + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} hwrm_tf_session_resc_flush_output_t, *phwrm_tf_session_resc_flush_output_t; -/********************* - * hwrm_tf_em_delete * - *********************/ +/***************************** + * hwrm_tf_session_resc_info * + *****************************/ -/* hwrm_tf_em_delete_input (size:832b/104B) */ +/* hwrm_tf_session_resc_info_input (size:320b/40B) */ -typedef struct hwrm_tf_em_delete_input { +typedef struct hwrm_tf_session_resc_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50588,32 +53776,42 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Session Id. */ + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX - /* Unused0 */ - uint16_t unused0; - /* EM internal flow handle. */ - uint64_t flow_handle; - /* EM Key value */ - uint64_t em_key[8]; - /* Number of bits in em_key. */ - uint16_t em_key_bitlen; - /* unused. */ - uint16_t unused1[3]; -} hwrm_tf_em_delete_input_t, *phwrm_tf_em_delete_input_t; + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX + /* + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. + */ + uint16_t req_size; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tf_rm_resc_req_entry type. Size of the + * array buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tf_rm_resc_entry type. Size of the array + * buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t resc_addr; +} hwrm_tf_session_resc_info_input_t, *phwrm_tf_session_resc_info_input_t; -/* hwrm_tf_em_delete_output (size:128b/16B) */ +/* hwrm_tf_session_resc_info_output (size:128b/16B) */ -typedef struct hwrm_tf_em_delete_output { +typedef struct hwrm_tf_session_resc_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50622,20 +53820,58 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Original stack allocation index. */ - uint16_t em_index; + /* + * Size of the returned tf_rm_resc_entry data array. The value + * cannot exceed the req_size defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; /* unused. */ - uint16_t unused0[3]; -} hwrm_tf_em_delete_output_t, *phwrm_tf_em_delete_output_t; + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} hwrm_tf_session_resc_info_output_t, *phwrm_tf_session_resc_info_output_t; -/******************* - * hwrm_tf_em_move * - *******************/ +/* TruFlow RM capability of a resource. */ +/* tf_rm_resc_req_entry (size:64b/8B) */ + +typedef struct tf_rm_resc_req_entry { + /* Type of the resource, defined globally in HCAPI RM. */ + uint32_t type; + /* Minimum value. */ + uint16_t min; + /* Maximum value. */ + uint16_t max; +} tf_rm_resc_req_entry_t, *ptf_rm_resc_req_entry_t; +/* TruFlow RM reservation information. */ +/* tf_rm_resc_entry (size:64b/8B) */ -/* hwrm_tf_em_move_input (size:320b/40B) */ +typedef struct tf_rm_resc_entry { + /* Type of the resource, defined globally in HCAPI RM. */ + uint32_t type; + /* Start offset. */ + uint16_t start; + /* Number of resources. */ + uint16_t stride; +} tf_rm_resc_entry_t, *ptf_rm_resc_entry_t; -typedef struct hwrm_tf_em_move_input { +/************************** + * hwrm_tf_tbl_type_alloc * + **************************/ + + +/* hwrm_tf_tbl_type_alloc_input (size:192b/24B) */ + +typedef struct hwrm_tf_tbl_type_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50664,30 +53900,39 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Session Id. */ + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_LAST HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX - /* Number of EM entry blocks */ - uint16_t num_blocks; - /* New index for entry */ - uint32_t new_index; - /* Unused */ - uint32_t unused0; - /* EM internal flow handle. */ - uint64_t flow_handle; -} hwrm_tf_em_move_input_t, *phwrm_tf_em_move_input_t; + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_TX + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_LAST HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* + * This field is blktype specific. For any of the UPAR types it is + * set to a non-zero value in case of a re-alloc, specifies a + * tunnel-type of dynamic UPAR tunnel. + */ + uint8_t type; +} hwrm_tf_tbl_type_alloc_input_t, *phwrm_tf_tbl_type_alloc_input_t; -/* hwrm_tf_em_move_output (size:128b/16B) */ +/* hwrm_tf_tbl_type_alloc_output (size:128b/16B) */ -typedef struct hwrm_tf_em_move_output { +typedef struct hwrm_tf_tbl_type_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50696,20 +53941,34 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Index of old entry. */ - uint16_t em_index; - /* unused. */ - uint16_t unused0[3]; -} hwrm_tf_em_move_output_t, *phwrm_tf_em_move_output_t; + /* Response code. */ + uint32_t resp_code; + /* + * Table entry allocated by the firmware using the + * parameters above. + */ + uint16_t idx_tbl_id; + /* unused */ + uint8_t unused0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} hwrm_tf_tbl_type_alloc_output_t, *phwrm_tf_tbl_type_alloc_output_t; -/******************** - * hwrm_tf_tcam_set * - ********************/ +/************************ + * hwrm_tf_tbl_type_get * + ************************/ -/* hwrm_tf_tcam_set_input (size:1024b/128B) */ +/* hwrm_tf_tbl_type_get_input (size:256b/32B) */ -typedef struct hwrm_tf_tcam_set_input { +typedef struct hwrm_tf_tbl_type_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50741,49 +54000,44 @@ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ - uint32_t flags; + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX /* - * Indicate device data is being sent via DMA, the device - * data is packing does not change. + * When set use the special access register access to clear + * the table entry on read. */ - #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2) + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_LAST HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* unused. */ + uint8_t unused0; /* - * TCAM type of the resource, defined globally in the + * Type of the resource, defined globally in the * hwrm_tf_resc_type enum. */ uint32_t type; - /* Index of TCAM entry. */ - uint16_t idx; - /* Number of bytes in the TCAM key. */ - uint8_t key_size; - /* Number of bytes in the TCAM result. */ - uint8_t result_size; - /* - * Offset from which the mask bytes start in the device data - * array, key offset is always 0. - */ - uint8_t mask_offset; - /* Offset from which the result bytes start in the device data array. */ - uint8_t result_offset; - /* unused. */ - uint8_t unused0[6]; - /* - * TCAM key located at offset 0, mask located at mask_offset - * and result at result_offset for the device. - */ - uint8_t dev_data[88]; -} hwrm_tf_tcam_set_input_t, *phwrm_tf_tcam_set_input_t; + /* Index of the type to retrieve. */ + uint32_t index; +} hwrm_tf_tbl_type_get_input_t, *phwrm_tf_tbl_type_get_input_t; -/* hwrm_tf_tcam_set_output (size:128b/16B) */ +/* hwrm_tf_tbl_type_get_output (size:2240b/280B) */ -typedef struct hwrm_tf_tcam_set_output { +typedef struct hwrm_tf_tbl_type_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50792,27 +54046,35 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[256]; + /* unused */ + uint8_t unused1[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tf_tcam_set_output_t, *phwrm_tf_tcam_set_output_t; +} hwrm_tf_tbl_type_get_output_t, *phwrm_tf_tbl_type_get_output_t; -/******************** - * hwrm_tf_tcam_get * - ********************/ +/************************ + * hwrm_tf_tbl_type_set * + ************************/ -/* hwrm_tf_tcam_get_input (size:256b/32B) */ +/* hwrm_tf_tbl_type_set_input (size:1024b/128B) */ -typedef struct hwrm_tf_tcam_get_input { +typedef struct hwrm_tf_tbl_type_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50844,28 +54106,47 @@ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ - uint32_t flags; + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX + /* Indicate table data is being sent via DMA. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_LAST HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* unused. */ + uint8_t unused0; /* - * TCAM type of the resource, defined globally in the + * Type of the resource, defined globally in the * hwrm_tf_resc_type enum. */ uint32_t type; - /* Index of a TCAM entry. */ - uint16_t idx; - /* unused. */ - uint16_t unused0; -} hwrm_tf_tcam_get_input_t, *phwrm_tf_tcam_get_input_t; + /* Index of the type to retrieve. */ + uint32_t index; + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[88]; +} hwrm_tf_tbl_type_set_input_t, *phwrm_tf_tbl_type_set_input_t; -/* hwrm_tf_tcam_get_output (size:2368b/296B) */ +/* hwrm_tf_tbl_type_set_output (size:128b/16B) */ -typedef struct hwrm_tf_tcam_get_output { +typedef struct hwrm_tf_tbl_type_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50874,42 +54155,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of bytes in the TCAM key. */ - uint8_t key_size; - /* Number of bytes in the TCAM entry. */ - uint8_t result_size; - /* Offset from which the mask bytes start in the device data array. */ - uint8_t mask_offset; - /* Offset from which the result bytes start in the device data array. */ - uint8_t result_offset; - /* unused. */ - uint8_t unused0[4]; - /* - * TCAM key located at offset 0, mask located at mask_offset - * and result at result_offset for the device. - */ - uint8_t dev_data[272]; /* unused. */ - uint8_t unused1[7]; + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tf_tcam_get_output_t, *phwrm_tf_tcam_get_output_t; +} hwrm_tf_tbl_type_set_output_t, *phwrm_tf_tbl_type_set_output_t; -/********************* - * hwrm_tf_tcam_move * - *********************/ +/************************* + * hwrm_tf_tbl_type_free * + *************************/ -/* hwrm_tf_tcam_move_input (size:1024b/128B) */ +/* hwrm_tf_tbl_type_free_input (size:256b/32B) */ -typedef struct hwrm_tf_tcam_move_input { +typedef struct hwrm_tf_tbl_type_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -50941,30 +54207,39 @@ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ - uint32_t flags; + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX + #define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_LAST HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_TX + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_LAST HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* Unused */ + uint8_t unused0; /* - * TCAM type of the resource, defined globally in the - * hwrm_tf_resc_type enum. + * Table entry to be freed by the firmware using the parameters + * above. */ - uint32_t type; - /* Number of TCAM index pairs to be swapped for the device. */ - uint16_t count; - /* unused. */ - uint16_t unused0; - /* TCAM index pairs to be swapped for the device. */ - uint16_t idx_pairs[48]; -} hwrm_tf_tcam_move_input_t, *phwrm_tf_tcam_move_input_t; + uint16_t idx_tbl_id; + /* Unused */ + uint8_t unused1[6]; +} hwrm_tf_tbl_type_free_input_t, *phwrm_tf_tbl_type_free_input_t; -/* hwrm_tf_tcam_move_output (size:128b/16B) */ +/* hwrm_tf_tbl_type_free_output (size:128b/16B) */ -typedef struct hwrm_tf_tcam_move_output { +typedef struct hwrm_tf_tbl_type_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50973,27 +54248,29 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; + /* Response code. */ + uint32_t resp_code; + /* unused */ + uint8_t unused0[3]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tf_tcam_move_output_t, *phwrm_tf_tcam_move_output_t; +} hwrm_tf_tbl_type_free_output_t, *phwrm_tf_tbl_type_free_output_t; /********************* - * hwrm_tf_tcam_free * + * hwrm_tf_em_insert * *********************/ -/* hwrm_tf_tcam_free_input (size:1024b/128B) */ +/* hwrm_tf_em_insert_input (size:832b/104B) */ -typedef struct hwrm_tf_tcam_free_input { +typedef struct hwrm_tf_em_insert_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51022,33 +54299,34 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + /* Firmware Session Id. */ uint32_t fw_session_id; - /* Control flags. */ - uint32_t flags; + /* Control Flags. */ + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX - /* - * TCAM type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ - uint32_t type; - /* Number of TCAM index to be deleted for the device. */ - uint16_t count; + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX + /* Reported match strength. */ + uint16_t strength; + /* Index to action. */ + uint32_t action_ptr; + /* Index of EM record. */ + uint32_t em_record_idx; + /* EM Key value. */ + uint64_t em_key[8]; + /* Number of bits in em_key. */ + uint16_t em_key_bitlen; /* unused. */ - uint16_t unused0; - /* TCAM index list to be deleted for the device. */ - uint16_t idx_list[48]; -} hwrm_tf_tcam_free_input_t, *phwrm_tf_tcam_free_input_t; + uint16_t unused0[3]; +} hwrm_tf_em_insert_input_t, *phwrm_tf_em_insert_input_t; -/* hwrm_tf_tcam_free_output (size:128b/16B) */ +/* hwrm_tf_em_insert_output (size:128b/16B) */ -typedef struct hwrm_tf_tcam_free_output { +typedef struct hwrm_tf_em_insert_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51057,27 +54335,33 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* EM record pointer index. */ + uint16_t rptr_index; + /* EM record offset 0~3. */ + uint8_t rptr_entry; + /* Number of word entries consumed by the key. */ + uint8_t num_of_entries; /* unused. */ - uint8_t unused0[7]; + uint8_t unused0[3]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tf_tcam_free_output_t, *phwrm_tf_tcam_free_output_t; +} hwrm_tf_em_insert_output_t, *phwrm_tf_em_insert_output_t; /************************** - * hwrm_tf_global_cfg_set * + * hwrm_tf_em_hash_insert * **************************/ -/* hwrm_tf_global_cfg_set_input (size:448b/56B) */ +/* hwrm_tf_em_hash_insert_input (size:1024b/128B) */ -typedef struct hwrm_tf_global_cfg_set_input { +typedef struct hwrm_tf_em_hash_insert_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51106,34 +54390,36 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + /* Firmware Session Id. */ uint32_t fw_session_id; - /* Control flags. */ - uint32_t flags; + /* Control Flags. */ + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX - /* Global Cfg type */ - uint32_t type; - /* Offset of the type */ - uint32_t offset; - /* Size of the data to set in bytes */ - uint16_t size; - /* unused. */ - uint8_t unused0[6]; - /* Data to set */ - uint8_t data[8]; - /* Mask of data to set, 0 indicates no mask */ - uint8_t mask[8]; -} hwrm_tf_global_cfg_set_input_t, *phwrm_tf_global_cfg_set_input_t; + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX + /* Indicates table data is being sent via DMA. */ + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DMA UINT32_C(0x2) + /* Number of bits in the EM record. */ + uint16_t em_record_size_bits; + /* CRC32 hash of key. */ + uint32_t key0_hash; + /* Lookup3 hash of key. */ + uint32_t key1_hash; + /* Index of EM record. */ + uint32_t em_record_idx; + /* Unused. */ + uint32_t unused0; + /* EM record. */ + uint64_t em_record[11]; +} hwrm_tf_em_hash_insert_input_t, *phwrm_tf_em_hash_insert_input_t; -/* hwrm_tf_global_cfg_set_output (size:128b/16B) */ +/* hwrm_tf_em_hash_insert_output (size:128b/16B) */ -typedef struct hwrm_tf_global_cfg_set_output { +typedef struct hwrm_tf_em_hash_insert_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51142,27 +54428,33 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* EM record pointer index. */ + uint16_t rptr_index; + /* EM record offset 0~3. */ + uint8_t rptr_entry; + /* Number of word entries consumed by the key. */ + uint8_t num_of_entries; /* unused. */ - uint8_t unused0[7]; + uint8_t unused0[3]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tf_global_cfg_set_output_t, *phwrm_tf_global_cfg_set_output_t; +} hwrm_tf_em_hash_insert_output_t, *phwrm_tf_em_hash_insert_output_t; -/************************** - * hwrm_tf_global_cfg_get * - **************************/ +/********************* + * hwrm_tf_em_delete * + *********************/ -/* hwrm_tf_global_cfg_get_input (size:320b/40B) */ +/* hwrm_tf_em_delete_input (size:832b/104B) */ -typedef struct hwrm_tf_global_cfg_get_input { +typedef struct hwrm_tf_em_delete_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51191,30 +54483,32 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + /* Session Id. */ uint32_t fw_session_id; /* Control flags. */ - uint32_t flags; + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX - /* Global Cfg type */ - uint32_t type; - /* Offset of the type */ - uint32_t offset; - /* Size of the data to set in bytes */ - uint16_t size; + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX + /* Unused0 */ + uint16_t unused0; + /* EM internal flow handle. */ + uint64_t flow_handle; + /* EM Key value */ + uint64_t em_key[8]; + /* Number of bits in em_key. */ + uint16_t em_key_bitlen; /* unused. */ - uint8_t unused0[6]; -} hwrm_tf_global_cfg_get_input_t, *phwrm_tf_global_cfg_get_input_t; + uint16_t unused1[3]; +} hwrm_tf_em_delete_input_t, *phwrm_tf_em_delete_input_t; -/* hwrm_tf_global_cfg_get_output (size:256b/32B) */ +/* hwrm_tf_em_delete_output (size:128b/16B) */ -typedef struct hwrm_tf_global_cfg_get_output { +typedef struct hwrm_tf_em_delete_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51223,22 +54517,29 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Size of the data read in bytes */ - uint16_t size; + /* Original stack allocation index. */ + uint16_t em_index; /* unused. */ - uint8_t unused0[6]; - /* Data to set */ - uint8_t data[16]; -} hwrm_tf_global_cfg_get_output_t, *phwrm_tf_global_cfg_get_output_t; + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} hwrm_tf_em_delete_output_t, *phwrm_tf_em_delete_output_t; -/********************** - * hwrm_tf_if_tbl_get * - **********************/ +/******************* + * hwrm_tf_em_move * + *******************/ -/* hwrm_tf_if_tbl_get_input (size:256b/32B) */ +/* hwrm_tf_em_move_input (size:320b/40B) */ -typedef struct hwrm_tf_if_tbl_get_input { +typedef struct hwrm_tf_em_move_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51267,31 +54568,30 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + /* Session Id. */ uint32_t fw_session_id; /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX - /* Size of the data to set. */ - uint16_t size; - /* - * Type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ - uint32_t type; - /* Index of the type to retrieve. */ - uint32_t index; -} hwrm_tf_if_tbl_get_input_t, *phwrm_tf_if_tbl_get_input_t; + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_LAST HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX + /* Number of EM entry blocks */ + uint16_t num_blocks; + /* New index for entry */ + uint32_t new_index; + /* Unused */ + uint32_t unused0; + /* EM internal flow handle. */ + uint64_t flow_handle; +} hwrm_tf_em_move_input_t, *phwrm_tf_em_move_input_t; -/* hwrm_tf_if_tbl_get_output (size:1216b/152B) */ +/* hwrm_tf_em_move_output (size:128b/16B) */ -typedef struct hwrm_tf_if_tbl_get_output { +typedef struct hwrm_tf_em_move_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51300,16 +54600,10 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Response code. */ - uint32_t resp_code; - /* Response size. */ - uint16_t size; - /* unused */ - uint16_t unused0; - /* Response data. */ - uint8_t data[128]; - /* unused */ - uint8_t unused1[7]; + /* Index of old entry. */ + uint16_t em_index; + /* unused. */ + uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -51319,16 +54613,16 @@ * is written last. */ uint8_t valid; -} hwrm_tf_if_tbl_get_output_t, *phwrm_tf_if_tbl_get_output_t; +} hwrm_tf_em_move_output_t, *phwrm_tf_em_move_output_t; -/*************************** - * hwrm_tf_if_tbl_type_set * - ***************************/ +/******************** + * hwrm_tf_tcam_set * + ********************/ -/* hwrm_tf_if_tbl_set_input (size:1024b/128B) */ +/* hwrm_tf_tcam_set_input (size:1024b/128B) */ -typedef struct hwrm_tf_if_tbl_set_input { +typedef struct hwrm_tf_tcam_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51360,34 +54654,49 @@ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ - uint16_t flags; + uint32_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX - /* unused. */ - uint8_t unused0[2]; + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX /* - * Type of the resource, defined globally in the + * Indicate device data is being sent via DMA, the device + * data is packing does not change. + */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * TCAM type of the resource, defined globally in the * hwrm_tf_resc_type enum. */ uint32_t type; - /* Index of the type to set. */ - uint32_t index; - /* Size of the data to set. */ - uint16_t size; - /* unused */ - uint8_t unused1[6]; - /* Data to be set. */ - uint8_t data[88]; -} hwrm_tf_if_tbl_set_input_t, *phwrm_tf_if_tbl_set_input_t; + /* Index of TCAM entry. */ + uint16_t idx; + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM result. */ + uint8_t result_size; + /* + * Offset from which the mask bytes start in the device data + * array, key offset is always 0. + */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[6]; + /* + * TCAM key located at offset 0, mask located at mask_offset + * and result at result_offset for the device. + */ + uint8_t dev_data[88]; +} hwrm_tf_tcam_set_input_t, *phwrm_tf_tcam_set_input_t; -/* hwrm_tf_if_tbl_set_output (size:128b/16B) */ +/* hwrm_tf_tcam_set_output (size:128b/16B) */ -typedef struct hwrm_tf_if_tbl_set_output { +typedef struct hwrm_tf_tcam_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51399,24 +54708,24 @@ /* unused. */ uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} hwrm_tf_if_tbl_set_output_t, *phwrm_tf_if_tbl_set_output_t; +} hwrm_tf_tcam_set_output_t, *phwrm_tf_tcam_set_output_t; -/***************************** - * hwrm_tf_tbl_type_bulk_get * - *****************************/ +/******************** + * hwrm_tf_tcam_get * + ********************/ -/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */ +/* hwrm_tf_tcam_get_input (size:256b/32B) */ -typedef struct hwrm_tf_tbl_type_bulk_get_input { +typedef struct hwrm_tf_tcam_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51448,39 +54757,28 @@ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ - uint16_t flags; + uint32_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX - /* - * When set use the special access register access to clear - * the table entries on read. - */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2) - /* unused. */ - uint8_t unused0[2]; + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX /* - * Type of the resource, defined globally in the + * TCAM type of the resource, defined globally in the * hwrm_tf_resc_type enum. */ uint32_t type; - /* Starting index of the type to retrieve. */ - uint32_t start_index; - /* Number of entries to retrieve. */ - uint32_t num_entries; - /* Number of entries to retrieve. */ - uint32_t unused1; - /* Host memory where data will be stored. */ - uint64_t host_addr; -} hwrm_tf_tbl_type_bulk_get_input_t, *phwrm_tf_tbl_type_bulk_get_input_t; + /* Index of a TCAM entry. */ + uint16_t idx; + /* unused. */ + uint16_t unused0; +} hwrm_tf_tcam_get_input_t, *phwrm_tf_tcam_get_input_t; -/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */ +/* hwrm_tf_tcam_get_output (size:2368b/296B) */ -typedef struct hwrm_tf_tbl_type_bulk_get_output { +typedef struct hwrm_tf_tcam_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51489,31 +54787,42 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Response code. */ - uint32_t resp_code; - /* Response size. */ - uint16_t size; - /* unused */ - uint8_t unused0; + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM entry. */ + uint8_t result_size; + /* Offset from which the mask bytes start in the device data array. */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[4]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * TCAM key located at offset 0, mask located at mask_offset + * and result at result_offset for the device. + */ + uint8_t dev_data[272]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} hwrm_tf_tbl_type_bulk_get_output_t, *phwrm_tf_tbl_type_bulk_get_output_t; +} hwrm_tf_tcam_get_output_t, *phwrm_tf_tcam_get_output_t; -/*********************************** - * hwrm_tf_session_hotup_state_set * - ***********************************/ +/********************* + * hwrm_tf_tcam_move * + *********************/ -/* hwrm_tf_session_hotup_state_set_input (size:192b/24B) */ +/* hwrm_tf_tcam_move_input (size:1024b/128B) */ -typedef struct hwrm_tf_session_hotup_state_set_input { +typedef struct hwrm_tf_tcam_move_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51544,22 +54853,31 @@ uint64_t resp_addr; /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; - /* Shared session state. */ - uint16_t state; /* Control flags. */ - uint16_t flags; + uint32_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX -} hwrm_tf_session_hotup_state_set_input_t, *phwrm_tf_session_hotup_state_set_input_t; + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of TCAM index pairs to be swapped for the device. */ + uint16_t count; + /* unused. */ + uint16_t unused0; + /* TCAM index pairs to be swapped for the device. */ + uint16_t idx_pairs[48]; +} hwrm_tf_tcam_move_input_t, *phwrm_tf_tcam_move_input_t; -/* hwrm_tf_session_hotup_state_set_output (size:128b/16B) */ +/* hwrm_tf_tcam_move_output (size:128b/16B) */ -typedef struct hwrm_tf_session_hotup_state_set_output { +typedef struct hwrm_tf_tcam_move_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51571,24 +54889,24 @@ /* unused. */ uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} hwrm_tf_session_hotup_state_set_output_t, *phwrm_tf_session_hotup_state_set_output_t; +} hwrm_tf_tcam_move_output_t, *phwrm_tf_tcam_move_output_t; -/*********************************** - * hwrm_tf_session_hotup_state_get * - ***********************************/ +/********************* + * hwrm_tf_tcam_free * + *********************/ -/* hwrm_tf_session_hotup_state_get_input (size:192b/24B) */ +/* hwrm_tf_tcam_free_input (size:1024b/128B) */ -typedef struct hwrm_tf_session_hotup_state_get_input { +typedef struct hwrm_tf_tcam_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51620,21 +54938,30 @@ /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; /* Control flags. */ - uint16_t flags; + uint32_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of TCAM index to be deleted for the device. */ + uint16_t count; /* unused. */ - uint8_t unused0[2]; -} hwrm_tf_session_hotup_state_get_input_t, *phwrm_tf_session_hotup_state_get_input_t; + uint16_t unused0; + /* TCAM index list to be deleted for the device. */ + uint16_t idx_list[48]; +} hwrm_tf_tcam_free_input_t, *phwrm_tf_tcam_free_input_t; -/* hwrm_tf_session_hotup_state_get_output (size:128b/16B) */ +/* hwrm_tf_tcam_free_output (size:128b/16B) */ -typedef struct hwrm_tf_session_hotup_state_get_output { +typedef struct hwrm_tf_tcam_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51643,35 +54970,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Shared session HA state. */ - uint16_t state; - /* Shared session HA reference count. */ - uint16_t ref_cnt; /* unused. */ - uint8_t unused0[3]; + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} hwrm_tf_session_hotup_state_get_output_t, *phwrm_tf_session_hotup_state_get_output_t; +} hwrm_tf_tcam_free_output_t, *phwrm_tf_tcam_free_output_t; -/**************************** - * hwrm_tfc_tbl_scope_qcaps * - ****************************/ +/************************** + * hwrm_tf_global_cfg_set * + **************************/ -/* - * TruFlow command to check if firmware is capable of - * supporting table scopes. - */ -/* hwrm_tfc_tbl_scope_qcaps_input (size:128b/16B) */ +/* hwrm_tf_global_cfg_set_input (size:448b/56B) */ -typedef struct hwrm_tfc_tbl_scope_qcaps_input { +typedef struct hwrm_tf_global_cfg_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51700,11 +55019,36 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_tfc_tbl_scope_qcaps_input_t, *phwrm_tfc_tbl_scope_qcaps_input_t; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX + /* Indicate device data is being sent via DMA. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* Global Cfg type */ + uint32_t type; + /* Offset of the type */ + uint32_t offset; + /* Size of the data to set in bytes */ + uint16_t size; + /* unused. */ + uint8_t unused0[6]; + /* Data to set */ + uint8_t data[8]; + /* Mask of data to set, 0 indicates no mask */ + uint8_t mask[8]; +} hwrm_tf_global_cfg_set_input_t, *phwrm_tf_global_cfg_set_input_t; -/* hwrm_tfc_tbl_scope_qcaps_output (size:192b/24B) */ +/* hwrm_tf_global_cfg_set_output (size:128b/16B) */ -typedef struct hwrm_tfc_tbl_scope_qcaps_output { +typedef struct hwrm_tf_global_cfg_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51713,53 +55057,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * The maximum number of lookup records that a table scope can support. - * This field is only valid if tbl_scope_capable is not zero. - */ - uint32_t max_lkup_rec_cnt; - /* - * The maximum number of action records that a table scope can support. - * This field is only valid if tbl_scope_capable is not zero. - */ - uint32_t max_act_rec_cnt; - /* Not zero if firmware capable of table scopes. */ - uint8_t tbl_scope_capable; - /* - * log2 of the number of lookup static buckets that a table scope can - * support. This field is only valid if tbl_scope_capable is not zero. - */ - uint8_t max_lkup_static_buckets_exp; /* unused. */ - uint8_t unused0[5]; + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} hwrm_tfc_tbl_scope_qcaps_output_t, *phwrm_tfc_tbl_scope_qcaps_output_t; +} hwrm_tf_global_cfg_set_output_t, *phwrm_tf_global_cfg_set_output_t; -/******************************* - * hwrm_tfc_tbl_scope_id_alloc * - *******************************/ +/************************** + * hwrm_tf_global_cfg_get * + **************************/ -/* - * TruFlow command to allocate a table scope ID and create the pools. - * - * There is no corresponding free command since a table scope - * ID will automatically be freed once the last FID is removed. - * That is, when the hwrm_tfc_tbl_scope_fid_rem command returns - * a fid_cnt of 0 that also means that the table scope ID has - * been freed. - */ -/* hwrm_tfc_tbl_scope_id_alloc_input (size:192b/24B) */ +/* hwrm_tf_global_cfg_get_input (size:320b/40B) */ -typedef struct hwrm_tfc_tbl_scope_id_alloc_input { +typedef struct hwrm_tf_global_cfg_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51788,31 +55106,30 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The maximum number of pools for this table scope. */ - uint16_t max_pools; - /* Non-zero if this table scope is shared. */ - uint8_t shared; - /* - * The size of the lookup pools per direction expressed as - * log2(max_records/max_pools). That is, size=2^exp. - * - * Array is indexed by enum cfa_dir. - */ - uint8_t lkup_pool_sz_exp[2]; - /* - * The size of the action pools per direction expressed as - * log2(max_records/max_pools). That is, size=2^exp. - * - * Array is indexed by enum cfa_dir. - */ - uint8_t act_pool_sz_exp[2]; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX + /* Global Cfg type */ + uint32_t type; + /* Offset of the type */ + uint32_t offset; + /* Size of the data to set in bytes */ + uint16_t size; /* unused. */ - uint8_t unused0; -} hwrm_tfc_tbl_scope_id_alloc_input_t, *phwrm_tfc_tbl_scope_id_alloc_input_t; + uint8_t unused0[6]; +} hwrm_tf_global_cfg_get_input_t, *phwrm_tf_global_cfg_get_input_t; -/* hwrm_tfc_tbl_scope_id_alloc_output (size:128b/16B) */ +/* hwrm_tf_global_cfg_get_output (size:2240b/280B) */ -typedef struct hwrm_tfc_tbl_scope_id_alloc_output { +typedef struct hwrm_tf_global_cfg_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51821,35 +55138,33 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The table scope ID that was allocated. */ - uint8_t tsid; - /* - * Non-zero if this is the first FID associated with this table scope - * ID. - */ - uint8_t first; + /* Size of the data read in bytes */ + uint16_t size; /* unused. */ - uint8_t unused0[5]; + uint8_t unused0[6]; + /* Data to set */ + uint8_t data[256]; + /* unused. */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tfc_tbl_scope_id_alloc_output_t, *phwrm_tfc_tbl_scope_id_alloc_output_t; +} hwrm_tf_global_cfg_get_output_t, *phwrm_tf_global_cfg_get_output_t; -/***************************** - * hwrm_tfc_tbl_scope_config * - *****************************/ +/********************** + * hwrm_tf_if_tbl_get * + **********************/ -/* TruFlow command to configure the table scope memory. */ -/* hwrm_tfc_tbl_scope_config_input (size:704b/88B) */ +/* hwrm_tf_if_tbl_get_input (size:256b/32B) */ -typedef struct hwrm_tfc_tbl_scope_config_input { +typedef struct hwrm_tf_if_tbl_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51878,59 +55193,31 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX + /* Size of the data to set. */ + uint16_t size; /* - * The base addresses for lookup memory. - * Array is indexed by enum cfa_dir. - */ - uint64_t lkup_base_addr[2]; - /* - * The base addresses for action memory. - * Array is indexed by enum cfa_dir. - */ - uint64_t act_base_addr[2]; - /* - * The number of minimum sized lkup records per direction. - * In this usage, records are the minimum lookup memory - * allocation unit in a table scope. This value is the total - * memory required for buckets and entries. - * - * Array is indexed by enum cfa_dir. - */ - uint64_t lkup_rec_cnt; - /* - * The number of minimum sized action records per direction. - * Similar to the lkup_rec_cnt, records are the minimum - * action memory allocation unit in a table scope. - * - * Array is indexed by enum cfa_dir. - */ - uint64_t act_rec_cnt; - /* - * The number of static lookup buckets in the table scope. - * Array is indexed by enum cfa_dir. - */ - uint64_t lkup_static_bucket_cnt; - /* The page size of the table scope. */ - uint32_t pbl_page_sz; - /* - * The PBL level for lookup memory. - * Array is indexed by enum cfa_dir. - */ - uint8_t lkup_pbl_level[2]; - /* - * The PBL level for action memory. - * Array is indexed by enum cfa_dir. + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. */ - uint8_t act_pbl_level[2]; - /* The table scope ID. */ - uint8_t tsid; - /* unused. */ - uint8_t unused0[7]; -} hwrm_tfc_tbl_scope_config_input_t, *phwrm_tfc_tbl_scope_config_input_t; + uint32_t type; + /* Index of the type to retrieve. */ + uint32_t index; +} hwrm_tf_if_tbl_get_input_t, *phwrm_tf_if_tbl_get_input_t; -/* hwrm_tfc_tbl_scope_config_output (size:128b/16B) */ +/* hwrm_tf_if_tbl_get_output (size:1216b/152B) */ -typedef struct hwrm_tfc_tbl_scope_config_output { +typedef struct hwrm_tf_if_tbl_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -51939,8 +55226,16 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[128]; + /* unused */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -51950,17 +55245,16 @@ * is written last. */ uint8_t valid; -} hwrm_tfc_tbl_scope_config_output_t, *phwrm_tfc_tbl_scope_config_output_t; +} hwrm_tf_if_tbl_get_output_t, *phwrm_tf_if_tbl_get_output_t; -/******************************* - * hwrm_tfc_tbl_scope_deconfig * - *******************************/ +/*************************** + * hwrm_tf_if_tbl_type_set * + ***************************/ -/* TruFlow command to deconfigure the table scope memory. */ -/* hwrm_tfc_tbl_scope_deconfig_input (size:192b/24B) */ +/* hwrm_tf_if_tbl_set_input (size:1024b/128B) */ -typedef struct hwrm_tfc_tbl_scope_deconfig_input { +typedef struct hwrm_tf_if_tbl_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -51989,15 +55283,37 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The table scope ID. */ - uint8_t tsid; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX /* unused. */ - uint8_t unused0[7]; -} hwrm_tfc_tbl_scope_deconfig_input_t, *phwrm_tfc_tbl_scope_deconfig_input_t; + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to set. */ + uint32_t index; + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[88]; +} hwrm_tf_if_tbl_set_input_t, *phwrm_tf_if_tbl_set_input_t; -/* hwrm_tfc_tbl_scope_deconfig_output (size:128b/16B) */ +/* hwrm_tf_if_tbl_set_output (size:128b/16B) */ -typedef struct hwrm_tfc_tbl_scope_deconfig_output { +typedef struct hwrm_tf_if_tbl_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52017,17 +55333,16 @@ * is written last. */ uint8_t valid; -} hwrm_tfc_tbl_scope_deconfig_output_t, *phwrm_tfc_tbl_scope_deconfig_output_t; +} hwrm_tf_if_tbl_set_output_t, *phwrm_tf_if_tbl_set_output_t; -/****************************** - * hwrm_tfc_tbl_scope_fid_add * - ******************************/ +/***************************** + * hwrm_tf_tbl_type_bulk_get * + *****************************/ -/* TruFlow command to add a FID to a table scope. */ -/* hwrm_tfc_tbl_scope_fid_add_input (size:192b/24B) */ +/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */ -typedef struct hwrm_tfc_tbl_scope_fid_add_input { +typedef struct hwrm_tf_tbl_type_bulk_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52056,15 +55371,42 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The table scope ID. */ - uint8_t tsid; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entries on read. + */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2) /* unused. */ - uint8_t unused0[7]; -} hwrm_tfc_tbl_scope_fid_add_input_t, *phwrm_tfc_tbl_scope_fid_add_input_t; + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Starting index of the type to retrieve. */ + uint32_t start_index; + /* Number of entries to retrieve. */ + uint32_t num_entries; + /* Number of entries to retrieve. */ + uint32_t unused1; + /* Host memory where data will be stored. */ + uint64_t host_addr; +} hwrm_tf_tbl_type_bulk_get_input_t, *phwrm_tf_tbl_type_bulk_get_input_t; -/* hwrm_tfc_tbl_scope_fid_add_output (size:128b/16B) */ +/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */ -typedef struct hwrm_tfc_tbl_scope_fid_add_output { +typedef struct hwrm_tf_tbl_type_bulk_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52073,10 +55415,12 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The number of FIDs currently in the table scope ID. */ - uint8_t fid_cnt; - /* unused. */ - uint8_t unused0[6]; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint8_t unused0; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -52086,17 +55430,16 @@ * is written last. */ uint8_t valid; -} hwrm_tfc_tbl_scope_fid_add_output_t, *phwrm_tfc_tbl_scope_fid_add_output_t; +} hwrm_tf_tbl_type_bulk_get_output_t, *phwrm_tf_tbl_type_bulk_get_output_t; -/****************************** - * hwrm_tfc_tbl_scope_fid_rem * - ******************************/ +/*********************************** + * hwrm_tf_session_hotup_state_set * + ***********************************/ -/* TruFlow command to remove a FID from a table scope. */ -/* hwrm_tfc_tbl_scope_fid_rem_input (size:192b/24B) */ +/* hwrm_tf_session_hotup_state_set_input (size:192b/24B) */ -typedef struct hwrm_tfc_tbl_scope_fid_rem_input { +typedef struct hwrm_tf_session_hotup_state_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52125,15 +55468,24 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The table scope ID. */ - uint8_t tsid; - /* unused. */ - uint8_t unused0[7]; -} hwrm_tfc_tbl_scope_fid_rem_input_t, *phwrm_tfc_tbl_scope_fid_rem_input_t; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Shared session state. */ + uint16_t state; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX +} hwrm_tf_session_hotup_state_set_input_t, *phwrm_tf_session_hotup_state_set_input_t; -/* hwrm_tfc_tbl_scope_fid_rem_output (size:128b/16B) */ +/* hwrm_tf_session_hotup_state_set_output (size:128b/16B) */ -typedef struct hwrm_tfc_tbl_scope_fid_rem_output { +typedef struct hwrm_tf_session_hotup_state_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52142,10 +55494,8 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The number of FIDs remaining in the table scope ID. */ - uint16_t fid_cnt; /* unused. */ - uint8_t unused0[5]; + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -52155,16 +55505,16 @@ * is written last. */ uint8_t valid; -} hwrm_tfc_tbl_scope_fid_rem_output_t, *phwrm_tfc_tbl_scope_fid_rem_output_t; +} hwrm_tf_session_hotup_state_set_output_t, *phwrm_tf_session_hotup_state_set_output_t; -/********************************* - * hwrm_tfc_tbl_scope_pool_alloc * - *********************************/ +/*********************************** + * hwrm_tf_session_hotup_state_get * + ***********************************/ -/* hwrm_tfc_tbl_scope_pool_alloc_input (size:192b/24B) */ +/* hwrm_tf_session_hotup_state_get_input (size:192b/24B) */ -typedef struct hwrm_tfc_tbl_scope_pool_alloc_input { +typedef struct hwrm_tf_session_hotup_state_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52193,31 +55543,24 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Table Scope ID */ - uint8_t tsid; - /* Control flags. Direction and type. */ - uint8_t flags; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX - /* Indicates the table type. */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE UINT32_C(0x2) - /* Lookup table */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LOOKUP (UINT32_C(0x0) << 1) - /* Action table */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION (UINT32_C(0x1) << 1) - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LAST HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION - /* Unused */ - uint8_t unused[6]; -} hwrm_tfc_tbl_scope_pool_alloc_input_t, *phwrm_tfc_tbl_scope_pool_alloc_input_t; + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; +} hwrm_tf_session_hotup_state_get_input_t, *phwrm_tf_session_hotup_state_get_input_t; -/* hwrm_tfc_tbl_scope_pool_alloc_output (size:128b/16B) */ +/* hwrm_tf_session_hotup_state_get_output (size:128b/16B) */ -typedef struct hwrm_tfc_tbl_scope_pool_alloc_output { +typedef struct hwrm_tf_session_hotup_state_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52226,31 +55569,31 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Pool ID */ - uint16_t pool_id; - /* Pool size exponent. An exponent of 0 indicates a failure. */ - uint8_t pool_sz_exp; + /* Shared session HA state. */ + uint16_t state; + /* Shared session HA reference count. */ + uint16_t ref_cnt; /* unused. */ - uint8_t unused1[4]; + uint8_t unused0[3]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tfc_tbl_scope_pool_alloc_output_t, *phwrm_tfc_tbl_scope_pool_alloc_output_t; +} hwrm_tf_session_hotup_state_get_output_t, *phwrm_tf_session_hotup_state_get_output_t; -/******************************** - * hwrm_tfc_tbl_scope_pool_free * - ********************************/ +/************************** + * hwrm_tf_resc_usage_set * + **************************/ -/* hwrm_tfc_tbl_scope_pool_free_input (size:192b/24B) */ +/* hwrm_tf_resc_usage_set_input (size:1024b/128B) */ -typedef struct hwrm_tfc_tbl_scope_pool_free_input { +typedef struct hwrm_tf_resc_usage_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52279,33 +55622,48 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Table Scope ID */ - uint8_t tsid; - /* Control flags. Direction and type. */ - uint8_t flags; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_LAST HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX - /* Indicates the table type. */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE UINT32_C(0x2) - /* Lookup table */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LOOKUP (UINT32_C(0x0) << 1) - /* Action table */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION (UINT32_C(0x1) << 1) - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LAST HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION - /* Pool ID */ - uint16_t pool_id; - /* Unused */ - uint8_t unused[4]; -} hwrm_tfc_tbl_scope_pool_free_input_t, *phwrm_tfc_tbl_scope_pool_free_input_t; + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_TX + /* Indicate table data is being sent via DMA. */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* Types of the resource to set their usage state. */ + uint16_t types; + /* WC TCAM Pool */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_WC_TCAM UINT32_C(0x1) + /* EM Internal Memory Pool */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_EM UINT32_C(0x2) + /* Meter Instance */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_METER UINT32_C(0x4) + /* Counter Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_COUNTER UINT32_C(0x8) + /* Action Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACTION UINT32_C(0x10) + /* ACT MODIFY/ENCAP Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACT_MOD_ENCAP UINT32_C(0x20) + /* Source Property SMAC Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_SP_SMAC UINT32_C(0x40) + /* All Resource Types */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ALL UINT32_C(0x80) + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[96]; +} hwrm_tf_resc_usage_set_input_t, *phwrm_tf_resc_usage_set_input_t; -/* hwrm_tfc_tbl_scope_pool_free_output (size:128b/16B) */ +/* hwrm_tf_resc_usage_set_output (size:128b/16B) */ -typedef struct hwrm_tfc_tbl_scope_pool_free_output { +typedef struct hwrm_tf_resc_usage_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52315,33 +55673,26 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* unused. */ - uint8_t unused1[7]; + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tfc_tbl_scope_pool_free_output_t, *phwrm_tfc_tbl_scope_pool_free_output_t; +} hwrm_tf_resc_usage_set_output_t, *phwrm_tf_resc_usage_set_output_t; -/***************************** - * hwrm_tfc_session_id_alloc * - *****************************/ +/**************************** + * hwrm_tf_resc_usage_query * + ****************************/ -/* - * Allocate a TFC session. Requests the firmware to allocate a TFC - * session identifier and associate a forwarding function with the - * session. Though there's not an explicit matching free for a session - * id alloc, dis-associating the last fid from a session id (fid_cnt goes - * to 0), will result in this session id being freed automatically. - */ -/* hwrm_tfc_session_id_alloc_input (size:128b/16B) */ +/* hwrm_tf_resc_usage_query_input (size:256b/32B) */ -typedef struct hwrm_tfc_session_id_alloc_input { +typedef struct hwrm_tf_resc_usage_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52370,11 +55721,44 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_tfc_session_id_alloc_input_t, *phwrm_tfc_session_id_alloc_input_t; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_LAST HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* Types of the resource to retrieve their usage state. */ + uint16_t types; + /* WC TCAM Pool */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_WC_TCAM UINT32_C(0x1) + /* EM Internal Memory Pool */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_EM UINT32_C(0x2) + /* Meter Instance */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_METER UINT32_C(0x4) + /* Counter Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_COUNTER UINT32_C(0x8) + /* Action Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACTION UINT32_C(0x10) + /* ACT MODIFY/ENCAP Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACT_MOD_ENCAP UINT32_C(0x20) + /* Source Property SMAC Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_SP_SMAC UINT32_C(0x40) + /* All Resource Types */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ALL UINT32_C(0x80) + /* unused */ + uint8_t unused1[6]; +} hwrm_tf_resc_usage_query_input_t, *phwrm_tf_resc_usage_query_input_t; -/* hwrm_tfc_session_id_alloc_output (size:128b/16B) */ +/* hwrm_tf_resc_usage_query_output (size:960b/120B) */ -typedef struct hwrm_tfc_session_id_alloc_output { +typedef struct hwrm_tf_resc_usage_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52383,36 +55767,39 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Unique session identifier for the session created by the - * firmware. - */ - uint16_t sid; - /* Unused field */ - uint8_t unused0[5]; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[96]; + /* unused */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tfc_session_id_alloc_output_t, *phwrm_tfc_session_id_alloc_output_t; +} hwrm_tf_resc_usage_query_output_t, *phwrm_tf_resc_usage_query_output_t; /**************************** - * hwrm_tfc_session_fid_add * + * hwrm_tfc_tbl_scope_qcaps * ****************************/ /* - * Associate a TFC session id with a forwarding function. The target_fid - * will be associated with the passed in sid. + * TruFlow command to check if firmware is capable of + * supporting table scopes. */ -/* hwrm_tfc_session_fid_add_input (size:192b/24B) */ +/* hwrm_tfc_tbl_scope_qcaps_input (size:128b/16B) */ -typedef struct hwrm_tfc_session_fid_add_input { +typedef struct hwrm_tfc_tbl_scope_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52441,18 +55828,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Unique session identifier for the session created by the - * firmware. - */ - uint16_t sid; - /* Unused field */ - uint8_t unused0[6]; -} hwrm_tfc_session_fid_add_input_t, *phwrm_tfc_session_fid_add_input_t; +} hwrm_tfc_tbl_scope_qcaps_input_t, *phwrm_tfc_tbl_scope_qcaps_input_t; -/* hwrm_tfc_session_fid_add_output (size:128b/16B) */ +/* hwrm_tfc_tbl_scope_qcaps_output (size:192b/24B) */ -typedef struct hwrm_tfc_session_fid_add_output { +typedef struct hwrm_tfc_tbl_scope_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52461,36 +55841,53 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The number of FIDs that share this session. */ - uint16_t fid_cnt; - /* Unused field */ + /* + * The maximum number of lookup records that a table scope can support. + * This field is only valid if tbl_scope_capable is not zero. + */ + uint32_t max_lkup_rec_cnt; + /* + * The maximum number of action records that a table scope can support. + * This field is only valid if tbl_scope_capable is not zero. + */ + uint32_t max_act_rec_cnt; + /* Not zero if firmware capable of table scopes. */ + uint8_t tbl_scope_capable; + /* + * log2 of the number of lookup static buckets that a table scope can + * support. This field is only valid if tbl_scope_capable is not zero. + */ + uint8_t max_lkup_static_buckets_exp; + /* unused. */ uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tfc_session_fid_add_output_t, *phwrm_tfc_session_fid_add_output_t; +} hwrm_tfc_tbl_scope_qcaps_output_t, *phwrm_tfc_tbl_scope_qcaps_output_t; -/**************************** - * hwrm_tfc_session_fid_rem * - ****************************/ +/******************************* + * hwrm_tfc_tbl_scope_id_alloc * + *******************************/ /* - * Dis-associate a TFC session from the target_fid. - * Though there's not an explicit matching free for a - * session id alloc, dis-associating the last fid from a session id - * (fid_cnt goes to 0), will result in this session id being freed - * automatically. + * TruFlow command to allocate a table scope ID and create the pools. + * + * There is no corresponding free command since a table scope + * ID will automatically be freed once the last FID is removed. + * That is, when the hwrm_tfc_tbl_scope_fid_rem command returns + * a fid_cnt of 0 that also means that the table scope ID has + * been freed. */ -/* hwrm_tfc_session_fid_rem_input (size:192b/24B) */ +/* hwrm_tfc_tbl_scope_id_alloc_input (size:256b/32B) */ -typedef struct hwrm_tfc_session_fid_rem_input { +typedef struct hwrm_tfc_tbl_scope_id_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52520,17 +55917,41 @@ */ uint64_t resp_addr; /* - * Unique session identifier for the session created by the - * firmware. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. */ - uint16_t sid; - /* Unused field */ + uint16_t fid; + /* The maximum number of pools for this table scope. */ + uint16_t max_pools; + /* Non-zero if this table scope is shared. */ + uint8_t shared; + /* + * The size of the lookup pools per direction expressed as + * log2(max_records/max_pools). That is, size=2^exp. + * + * Array is indexed by enum cfa_dir. + */ + uint8_t lkup_pool_sz_exp[2]; + /* + * The size of the action pools per direction expressed as + * log2(max_records/max_pools). That is, size=2^exp. + * + * Array is indexed by enum cfa_dir. + */ + uint8_t act_pool_sz_exp[2]; + /* Application type. 0 (AFM), 1 (TF) */ + uint8_t app_type; + /* unused. */ uint8_t unused0[6]; -} hwrm_tfc_session_fid_rem_input_t, *phwrm_tfc_session_fid_rem_input_t; +} hwrm_tfc_tbl_scope_id_alloc_input_t, *phwrm_tfc_tbl_scope_id_alloc_input_t; -/* hwrm_tfc_session_fid_rem_output (size:128b/16B) */ +/* hwrm_tfc_tbl_scope_id_alloc_output (size:128b/16B) */ -typedef struct hwrm_tfc_session_fid_rem_output { +typedef struct hwrm_tfc_tbl_scope_id_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52539,36 +55960,35 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The number of FIDs that share this session. */ - uint16_t fid_cnt; - /* Unused field */ + /* The table scope ID that was allocated. */ + uint8_t tsid; + /* + * Non-zero if this is the first FID associated with this table scope + * ID. + */ + uint8_t first; + /* unused. */ uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tfc_session_fid_rem_output_t, *phwrm_tfc_session_fid_rem_output_t; +} hwrm_tfc_tbl_scope_id_alloc_output_t, *phwrm_tfc_tbl_scope_id_alloc_output_t; -/************************ - * hwrm_tfc_ident_alloc * - ************************/ +/***************************** + * hwrm_tfc_tbl_scope_config * + *****************************/ -/* - * Allocate a TFC identifier. Requests the firmware to - * allocate a TFC identifier. The session id and track_type are passed - * in. The tracking_id is either the sid or target_fid depends on the - * track_type. The resource subtype is passed in, an id corresponding - * to all these is allocated and returned in the HWRM response. - */ -/* hwrm_tfc_ident_alloc_input (size:192b/24B) */ +/* TruFlow command to configure the table scope memory. */ +/* hwrm_tfc_tbl_scope_config_input (size:704b/88B) */ -typedef struct hwrm_tfc_ident_alloc_input { +typedef struct hwrm_tfc_tbl_scope_config_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52598,40 +56018,58 @@ */ uint64_t resp_addr; /* - * Unique session identifier for the session created by the - * firmware. Will be used to track this identifier. + * The base addresses for lookup memory. + * Array is indexed by enum cfa_dir. */ - uint16_t sid; - /* Control flags. Direction. */ - uint8_t flags; - /* Indicates the flow direction. */ - #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX + uint64_t lkup_base_addr[2]; /* - * CFA resource subtype. For definitions, please see - * cfa_v3/include/cfa_resources.h. + * The base addresses for action memory. + * Array is indexed by enum cfa_dir. */ - uint8_t subtype; - /* Describes the type of tracking tag to be used */ - uint8_t track_type; - /* Invalid track type */ - #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) - /* Tracked by session id */ - #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) - /* Tracked by function id */ - #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) - #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_LAST HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID - /* Unused field */ - uint8_t unused0[3]; -} hwrm_tfc_ident_alloc_input_t, *phwrm_tfc_ident_alloc_input_t; + uint64_t act_base_addr[2]; + /* + * The number of minimum sized lkup records per direction. + * In this usage, records are the minimum lookup memory + * allocation unit in a table scope. This value is the total + * memory required for buckets and entries. + * + * Array is indexed by enum cfa_dir. + */ + uint64_t lkup_rec_cnt; + /* + * The number of minimum sized action records per direction. + * Similar to the lkup_rec_cnt, records are the minimum + * action memory allocation unit in a table scope. + * + * Array is indexed by enum cfa_dir. + */ + uint64_t act_rec_cnt; + /* + * The number of static lookup buckets in the table scope. + * Array is indexed by enum cfa_dir. + */ + uint64_t lkup_static_bucket_cnt; + /* The page size of the table scope. */ + uint32_t pbl_page_sz; + /* + * The PBL level for lookup memory. + * Array is indexed by enum cfa_dir. + */ + uint8_t lkup_pbl_level[2]; + /* + * The PBL level for action memory. + * Array is indexed by enum cfa_dir. + */ + uint8_t act_pbl_level[2]; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} hwrm_tfc_tbl_scope_config_input_t, *phwrm_tfc_tbl_scope_config_input_t; -/* hwrm_tfc_ident_alloc_output (size:128b/16B) */ +/* hwrm_tfc_tbl_scope_config_output (size:128b/16B) */ -typedef struct hwrm_tfc_ident_alloc_output { +typedef struct hwrm_tfc_tbl_scope_config_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52640,38 +56078,28 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Resource identifier allocated by the firmware using - * parameters above. - */ - uint16_t ident_id; - /* Unused field */ - uint8_t unused0[5]; + /* unused. */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tfc_ident_alloc_output_t, *phwrm_tfc_ident_alloc_output_t; +} hwrm_tfc_tbl_scope_config_output_t, *phwrm_tfc_tbl_scope_config_output_t; -/*********************** - * hwrm_tfc_ident_free * - ***********************/ +/******************************* + * hwrm_tfc_tbl_scope_deconfig * + *******************************/ -/* - * Requests the firmware to free a TFC resource identifier. - * A resource subtype and session id are passed in. - * An identifier (previously allocated) corresponding to all these is - * freed, only after various sanity checks are completed. - */ -/* hwrm_tfc_ident_free_input (size:192b/24B) */ +/* TruFlow command to deconfigure the table scope memory. */ +/* hwrm_tfc_tbl_scope_deconfig_input (size:192b/24B) */ -typedef struct hwrm_tfc_ident_free_input { +typedef struct hwrm_tfc_tbl_scope_deconfig_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52700,34 +56128,15 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Unique session identifier for the session created by the - * firmware. Will be used to validate this request. - */ - uint16_t sid; - /* - * CFA resource subtype. For definitions, please see - * cfa_v3/include/cfa_resources.h. - */ - uint8_t subtype; - /* Control flags. Direction. */ - uint8_t flags; - /* Indicates the flow direction. */ - #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX - /* The resource identifier to be freed */ - uint16_t ident_id; - /* Reserved */ - uint8_t unused0[2]; -} hwrm_tfc_ident_free_input_t, *phwrm_tfc_ident_free_input_t; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} hwrm_tfc_tbl_scope_deconfig_input_t, *phwrm_tfc_tbl_scope_deconfig_input_t; -/* hwrm_tfc_ident_free_output (size:128b/16B) */ +/* hwrm_tfc_tbl_scope_deconfig_output (size:128b/16B) */ -typedef struct hwrm_tfc_ident_free_output { +typedef struct hwrm_tfc_tbl_scope_deconfig_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52736,27 +56145,28 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Reserved */ + /* unused. */ uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tfc_ident_free_output_t, *phwrm_tfc_ident_free_output_t; +} hwrm_tfc_tbl_scope_deconfig_output_t, *phwrm_tfc_tbl_scope_deconfig_output_t; -/************************** - * hwrm_tfc_idx_tbl_alloc * - **************************/ +/****************************** + * hwrm_tfc_tbl_scope_fid_add * + ******************************/ -/* hwrm_tfc_idx_tbl_alloc_input (size:192b/24B) */ +/* TruFlow command to add a FID to a table scope. */ +/* hwrm_tfc_tbl_scope_fid_add_input (size:192b/24B) */ -typedef struct hwrm_tfc_idx_tbl_alloc_input { +typedef struct hwrm_tfc_tbl_scope_fid_add_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52786,41 +56196,23 @@ */ uint64_t resp_addr; /* - * Unique session id for the session created by the - * firmware. Will be used to track this index table entry - * only if track type is track_type_sid. - */ - uint16_t sid; - /* Control flags. */ - uint8_t flags; - /* Indicates the flow direction. */ - #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX - /* - * CFA resource subtype. For definitions, please see - * cfa_v3/include/cfa_resources.h. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. */ - uint8_t subtype; - /* Describes the type of tracking id to be used */ - uint8_t track_type; - /* Invalid track type */ - #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) - /* Tracked by session id */ - #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) - /* Tracked by function id */ - #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) - #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_LAST HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID - /* Reserved */ - uint8_t unused0[3]; -} hwrm_tfc_idx_tbl_alloc_input_t, *phwrm_tfc_idx_tbl_alloc_input_t; + uint16_t fid; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[5]; +} hwrm_tfc_tbl_scope_fid_add_input_t, *phwrm_tfc_tbl_scope_fid_add_input_t; -/* hwrm_tfc_idx_tbl_alloc_output (size:128b/16B) */ +/* hwrm_tfc_tbl_scope_fid_add_output (size:128b/16B) */ -typedef struct hwrm_tfc_idx_tbl_alloc_output { +typedef struct hwrm_tfc_tbl_scope_fid_add_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52829,13 +56221,10 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Index table entry allocated by the firmware using the - * parameters above. - */ - uint16_t idx_tbl_id; - /* Reserved */ - uint8_t unused0[5]; + /* The number of FIDs currently in the table scope ID. */ + uint8_t fid_cnt; + /* unused. */ + uint8_t unused0[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -52845,16 +56234,17 @@ * is written last. */ uint8_t valid; -} hwrm_tfc_idx_tbl_alloc_output_t, *phwrm_tfc_idx_tbl_alloc_output_t; +} hwrm_tfc_tbl_scope_fid_add_output_t, *phwrm_tfc_tbl_scope_fid_add_output_t; /****************************** - * hwrm_tfc_idx_tbl_alloc_set * + * hwrm_tfc_tbl_scope_fid_rem * ******************************/ -/* hwrm_tfc_idx_tbl_alloc_set_input (size:1088b/136B) */ +/* TruFlow command to remove a FID from a table scope. */ +/* hwrm_tfc_tbl_scope_fid_rem_input (size:192b/24B) */ -typedef struct hwrm_tfc_idx_tbl_alloc_set_input { +typedef struct hwrm_tfc_tbl_scope_fid_rem_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52884,55 +56274,23 @@ */ uint64_t resp_addr; /* - * Unique session id for the session created by the - * firmware. Will be used to track this index table entry - * only if track type is track_type_sid. - */ - uint16_t sid; - /* Control flags. */ - uint8_t flags; - /* Indicates the flow direction. */ - #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX - /* - * Indicate device data is being sent via DMA, the device - * data packing does not change. - */ - #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2) - /* - * CFA resource subtype. For definitions, please see - * cfa_v3/include/cfa_resources.h. - */ - uint8_t subtype; - /* Describes the type of tracking id to be used */ - uint8_t track_type; - /* Invalid track type */ - #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) - /* Tracked by session id */ - #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) - /* Tracked by function id */ - #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) - #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_LAST HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID - /* Reserved */ - uint8_t unused0; - /* The size of the index table entry in bytes. */ - uint16_t data_size; - /* The location of the dma buffer */ - uint64_t dma_addr; - /* - * Index table data located at offset 0. If dma bit is set, - * then this field contains the DMA buffer pointer. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. */ - uint8_t dev_data[104]; -} hwrm_tfc_idx_tbl_alloc_set_input_t, *phwrm_tfc_idx_tbl_alloc_set_input_t; + uint16_t fid; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[5]; +} hwrm_tfc_tbl_scope_fid_rem_input_t, *phwrm_tfc_tbl_scope_fid_rem_input_t; -/* hwrm_tfc_idx_tbl_alloc_set_output (size:128b/16B) */ +/* hwrm_tfc_tbl_scope_fid_rem_output (size:128b/16B) */ -typedef struct hwrm_tfc_idx_tbl_alloc_set_output { +typedef struct hwrm_tfc_tbl_scope_fid_rem_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52941,12 +56299,9 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Index table entry allocated by the firmware using the - * parameters above. - */ - uint16_t idx_tbl_id; - /* Reserved */ + /* The number of FIDs remaining in the table scope ID. */ + uint16_t fid_cnt; + /* unused. */ uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output @@ -52957,16 +56312,23 @@ * is written last. */ uint8_t valid; -} hwrm_tfc_idx_tbl_alloc_set_output_t, *phwrm_tfc_idx_tbl_alloc_set_output_t; +} hwrm_tfc_tbl_scope_fid_rem_output_t, *phwrm_tfc_tbl_scope_fid_rem_output_t; -/************************ - * hwrm_tfc_idx_tbl_set * - ************************/ +/***************************** + * hwrm_tfc_session_id_alloc * + *****************************/ -/* hwrm_tfc_idx_tbl_set_input (size:1088b/136B) */ +/* + * Allocate a TFC session. Requests the firmware to allocate a TFC + * session identifier and associate a forwarding function with the + * session. Though there's not an explicit matching free for a session + * id alloc, dis-associating the last fid from a session id (fid_cnt goes + * to 0), will result in this session id being freed automatically. + */ +/* hwrm_tfc_session_id_alloc_input (size:192b/24B) */ -typedef struct hwrm_tfc_idx_tbl_set_input { +typedef struct hwrm_tfc_session_id_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -52995,49 +56357,22 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Control flags. */ - uint8_t flags; - /* Indicates the flow direction. */ - #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX - /* - * Indicate device data is being sent via DMA, the device - * data packing does not change. - */ - #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DMA UINT32_C(0x2) /* - * CFA resource subtype. For definitions, please see - * cfa_v3/include/cfa_resources.h. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. */ - uint8_t subtype; - /* - * Session id associated with the firmware. Will be used - * for validation if the track type matches. - */ - uint16_t sid; - /* - * Index table index returned during alloc by the - * firmware. - */ - uint16_t idx_tbl_id; - /* The size of the index table entry in bytes. */ - uint16_t data_size; - /* The location of the dma buffer */ - uint64_t dma_addr; - /* - * Index table data located at offset 0. If dma bit is set, - * then this field contains the DMA buffer pointer. - */ - uint8_t dev_data[104]; -} hwrm_tfc_idx_tbl_set_input_t, *phwrm_tfc_idx_tbl_set_input_t; + uint16_t fid; + /* Unused field */ + uint8_t unused0[6]; +} hwrm_tfc_session_id_alloc_input_t, *phwrm_tfc_session_id_alloc_input_t; -/* hwrm_tfc_idx_tbl_set_output (size:128b/16B) */ +/* hwrm_tfc_session_id_alloc_output (size:128b/16B) */ -typedef struct hwrm_tfc_idx_tbl_set_output { +typedef struct hwrm_tfc_session_id_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53046,27 +56381,36 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; + /* + * Unique session identifier for the session created by the + * firmware. + */ + uint16_t sid; + /* Unused field */ + uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tfc_idx_tbl_set_output_t, *phwrm_tfc_idx_tbl_set_output_t; +} hwrm_tfc_session_id_alloc_output_t, *phwrm_tfc_session_id_alloc_output_t; -/************************ - * hwrm_tfc_idx_tbl_get * - ************************/ +/**************************** + * hwrm_tfc_session_fid_add * + ****************************/ -/* hwrm_tfc_idx_tbl_get_input (size:256b/32B) */ +/* + * Associate a TFC session id with a forwarding function. The target_fid + * will be associated with the passed in sid. + */ +/* hwrm_tfc_session_fid_add_input (size:192b/24B) */ -typedef struct hwrm_tfc_idx_tbl_get_input { +typedef struct hwrm_tfc_session_fid_add_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53095,44 +56439,27 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Control flags. */ - uint8_t flags; - /* Indicates the flow direction. */ - #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX - /* - * When set use the special access register access to clear - * the table entry on read. - */ - #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2) - /* - * CFA resource subtype. For definitions, please see - * cfa_v3/include/cfa_resources.h. - */ - uint8_t subtype; /* - * Session id associated with the firmware. Will be used - * for validation if the track type matches. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. */ - uint16_t sid; + uint16_t fid; /* - * Index table index returned during alloc by the + * Unique session identifier for the session created by the * firmware. */ - uint16_t idx_tbl_id; - /* The size of the index table entry buffer in bytes. */ - uint16_t buffer_size; - /* The location of the response dma buffer */ - uint64_t dma_addr; -} hwrm_tfc_idx_tbl_get_input_t, *phwrm_tfc_idx_tbl_get_input_t; + uint16_t sid; + /* Unused field */ + uint8_t unused0[4]; +} hwrm_tfc_session_fid_add_input_t, *phwrm_tfc_session_fid_add_input_t; -/* hwrm_tfc_idx_tbl_get_output (size:128b/16B) */ +/* hwrm_tfc_session_fid_add_output (size:128b/16B) */ -typedef struct hwrm_tfc_idx_tbl_get_output { +typedef struct hwrm_tfc_session_fid_add_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53141,29 +56468,36 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The size of the index table buffer returned in device size bytes. */ - uint16_t data_size; - /* unused */ - uint8_t unused1[5]; + /* The number of FIDs that share this session. */ + uint16_t fid_cnt; + /* Unused field */ + uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tfc_idx_tbl_get_output_t, *phwrm_tfc_idx_tbl_get_output_t; +} hwrm_tfc_session_fid_add_output_t, *phwrm_tfc_session_fid_add_output_t; -/************************* - * hwrm_tfc_idx_tbl_free * - *************************/ +/**************************** + * hwrm_tfc_session_fid_rem * + ****************************/ -/* hwrm_tfc_idx_tbl_free_input (size:192b/24B) */ +/* + * Dis-associate a TFC session from the target_fid. + * Though there's not an explicit matching free for a + * session id alloc, dis-associating the last fid from a session id + * (fid_cnt goes to 0), will result in this session id being freed + * automatically. + */ +/* hwrm_tfc_session_fid_rem_input (size:192b/24B) */ -typedef struct hwrm_tfc_idx_tbl_free_input { +typedef struct hwrm_tfc_session_fid_rem_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53192,34 +56526,27 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Control flags. */ - uint8_t flags; - /* Indicates the flow direction. */ - #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX /* - * CFA resource subtype. For definitions, please see - * cfa_v3/include/cfa_resources.h. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. */ - uint8_t subtype; + uint16_t fid; /* - * Session id associated with the firmware. Will be used - * for validation if the track type matches. + * Unique session identifier for the session created by the + * firmware. */ uint16_t sid; - /* Index table id to be freed by the firmware. */ - uint16_t idx_tbl_id; - /* Reserved */ - uint8_t unused0[2]; -} hwrm_tfc_idx_tbl_free_input_t, *phwrm_tfc_idx_tbl_free_input_t; + /* Unused field */ + uint8_t unused0[4]; +} hwrm_tfc_session_fid_rem_input_t, *phwrm_tfc_session_fid_rem_input_t; -/* hwrm_tfc_idx_tbl_free_output (size:128b/16B) */ +/* hwrm_tfc_session_fid_rem_output (size:128b/16B) */ -typedef struct hwrm_tfc_idx_tbl_free_output { +typedef struct hwrm_tfc_session_fid_rem_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53228,55 +56555,36 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Reserved */ - uint8_t unused0[7]; + /* The number of FIDs that share this session. */ + uint16_t fid_cnt; + /* Unused field */ + uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tfc_idx_tbl_free_output_t, *phwrm_tfc_idx_tbl_free_output_t; - -/* TruFlow resources request for a global id. */ -/* tfc_global_id_hwrm_req (size:64b/8B) */ - -typedef struct tfc_global_id_hwrm_req { - /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */ - uint16_t rtype; - /* Indicates the flow direction in type of cfa_dir. */ - uint16_t dir; - /* Subtype of the resource type. */ - uint16_t subtype; - /* Number of the type of resources. */ - uint16_t cnt; -} tfc_global_id_hwrm_req_t, *ptfc_global_id_hwrm_req_t; - -/* The reserved resources for the global id. */ -/* tfc_global_id_hwrm_rsp (size:64b/8B) */ - -typedef struct tfc_global_id_hwrm_rsp { - /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */ - uint16_t rtype; - /* Indicates the flow direction in type of cfa_dir. */ - uint16_t dir; - /* Subtype of the resource type. */ - uint16_t subtype; - /* The global id that the resources reserved for. */ - uint16_t id; -} tfc_global_id_hwrm_rsp_t, *ptfc_global_id_hwrm_rsp_t; +} hwrm_tfc_session_fid_rem_output_t, *phwrm_tfc_session_fid_rem_output_t; -/**************************** - * hwrm_tfc_global_id_alloc * - ****************************/ +/************************ + * hwrm_tfc_ident_alloc * + ************************/ -/* hwrm_tfc_global_id_alloc_input (size:320b/40B) */ +/* + * Allocate a TFC identifier. Requests the firmware to + * allocate a TFC identifier. The session id and track_type are passed + * in. The tracking_id is either the sid or target_fid depends on the + * track_type. The resource subtype is passed in, an id corresponding + * to all these is allocated and returned in the HWRM response. + */ +/* hwrm_tfc_ident_alloc_input (size:192b/24B) */ -typedef struct hwrm_tfc_global_id_alloc_input { +typedef struct hwrm_tfc_ident_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53305,37 +56613,50 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint16_t sid; - /* Global domain id. */ - uint16_t global_id; /* - * Defines the array size of the provided req_addr and - * resv_addr array buffers. Should be set to the number of - * request entries. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. */ - uint16_t req_cnt; - /* unused. */ - uint8_t unused0[2]; + uint16_t fid; /* - * This is the DMA address for the request input data array - * buffer. Array is of tfc_global_id_hwrm_req type. Size of the - * array buffer is provided by the 'req_cnt' field in this - * message. + * Unique session identifier for the session created by the + * firmware. Will be used to track this identifier. */ - uint64_t req_addr; + uint16_t sid; + /* Control flags. Direction. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX /* - * This is the DMA address for the resc output data array - * buffer. Array is of tfc_global_id_hwrm_rsp type. Size of the array - * buffer is provided by the 'req_cnt' field in this - * message. + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. */ - uint64_t resc_addr; -} hwrm_tfc_global_id_alloc_input_t, *phwrm_tfc_global_id_alloc_input_t; + uint8_t subtype; + /* Describes the type of tracking tag to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_LAST HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Unused field */ + uint8_t unused0; +} hwrm_tfc_ident_alloc_input_t, *phwrm_tfc_ident_alloc_input_t; -/* hwrm_tfc_global_id_alloc_output (size:128b/16B) */ +/* hwrm_tfc_ident_alloc_output (size:128b/16B) */ -typedef struct hwrm_tfc_global_id_alloc_output { +typedef struct hwrm_tfc_ident_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53345,35 +56666,37 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Size of the returned hwrm_tfc_global_id_req data array. The value - * cannot exceed the req_cnt defined by the input msg. The data - * array is returned using the resv_addr specified DMA - * address also provided by the input msg. + * Resource identifier allocated by the firmware using + * parameters above. */ - uint16_t rsp_cnt; - /* Non-zero if this is the first allocation for the global ID. */ - uint8_t first; - /* unused. */ - uint8_t unused0[4]; + uint16_t ident_id; + /* Unused field */ + uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tfc_global_id_alloc_output_t, *phwrm_tfc_global_id_alloc_output_t; +} hwrm_tfc_ident_alloc_output_t, *phwrm_tfc_ident_alloc_output_t; -/********************* - * hwrm_tfc_tcam_set * - *********************/ +/*********************** + * hwrm_tfc_ident_free * + ***********************/ -/* hwrm_tfc_tcam_set_input (size:1088b/136B) */ +/* + * Requests the firmware to free a TFC resource identifier. + * A resource subtype and session id are passed in. + * An identifier (previously allocated) corresponding to all these is + * freed, only after various sanity checks are completed. + */ +/* hwrm_tfc_ident_free_input (size:192b/24B) */ -typedef struct hwrm_tfc_tcam_set_input { +typedef struct hwrm_tfc_ident_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53403,46 +56726,40 @@ */ uint64_t resp_addr; /* - * Session id associated with the firmware. Will be used - * for validation if the track type matches. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; + /* + * Unique session identifier for the session created by the + * firmware. Will be used to validate this request. */ uint16_t sid; - /* Logical TCAM ID. */ - uint16_t tcam_id; - /* Number of bytes in the TCAM key. */ - uint16_t key_size; - /* Number of bytes in the TCAM result. */ - uint16_t result_size; - /* Control flags. */ - uint8_t flags; - /* Indicates the flow direction. */ - #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_LAST HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX - /* Indicate device data is being sent via DMA. */ - #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) /* - * Subtype of TCAM resource. See + * CFA resource subtype. For definitions, please see * cfa_v3/include/cfa_resources.h. */ uint8_t subtype; - /* unused. */ - uint8_t unused0[6]; - /* The location of the response dma buffer */ - uint64_t dma_addr; - /* - * TCAM key located at offset 0, mask located at mask_offset - * and result at result_offset for the device. - */ - uint8_t dev_data[96]; -} hwrm_tfc_tcam_set_input_t, *phwrm_tfc_tcam_set_input_t; + /* Control flags. Direction. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX + /* The resource identifier to be freed */ + uint16_t ident_id; +} hwrm_tfc_ident_free_input_t, *phwrm_tfc_ident_free_input_t; -/* hwrm_tfc_tcam_set_output (size:128b/16B) */ +/* hwrm_tfc_ident_free_output (size:128b/16B) */ -typedef struct hwrm_tfc_tcam_set_output { +typedef struct hwrm_tfc_ident_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53451,27 +56768,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* unused. */ + /* Reserved */ uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_tfc_tcam_set_output_t, *phwrm_tfc_tcam_set_output_t; +} hwrm_tfc_ident_free_output_t, *phwrm_tfc_ident_free_output_t; -/********************* - * hwrm_tfc_tcam_get * - *********************/ +/************************** + * hwrm_tfc_idx_tbl_alloc * + **************************/ -/* hwrm_tfc_tcam_get_input (size:192b/24B) */ +/* hwrm_tfc_idx_tbl_alloc_input (size:192b/24B) */ -typedef struct hwrm_tfc_tcam_get_input { +typedef struct hwrm_tfc_idx_tbl_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53500,34 +56817,65 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; + /* + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. + */ + uint16_t sid; /* Control flags. */ uint8_t flags; /* Indicates the flow direction. */ - #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_LAST HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX /* - * Subtype of TCAM resource See - * cfa_v3/include/cfa_resources.h. + * This field is blktype specific. + * For blktype CFA - CFA resource subtype. For definitions, + * please see cfa_v3/include/cfa_resources.h. + * For blktype rxp, re_gparse, te_gparse - + * Tunnel Type. A value of zero (or unknown) means alloc. A known + * value (previously allocated dynamic UPAR for tunnel_type) means + * realloc. Will fail if a realloc is for previously allocated FID, */ uint8_t subtype; - /* - * Session id associated with the firmware. Will be used - * for validation if the track type matches. - */ - uint16_t sid; - /* Logical TCAM ID. */ - uint16_t tcam_id; - /* unused. */ - uint8_t unused0[2]; -} hwrm_tfc_tcam_get_input_t, *phwrm_tfc_tcam_get_input_t; + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_LAST HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_LAST HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE +} hwrm_tfc_idx_tbl_alloc_input_t, *phwrm_tfc_idx_tbl_alloc_input_t; -/* hwrm_tfc_tcam_get_output (size:2368b/296B) */ +/* hwrm_tfc_idx_tbl_alloc_output (size:128b/16B) */ -typedef struct hwrm_tfc_tcam_get_output { +typedef struct hwrm_tfc_idx_tbl_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53536,38 +56884,32 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of bytes in the TCAM key. */ - uint16_t key_size; - /* Number of bytes in the TCAM result. */ - uint16_t result_size; - /* unused. */ - uint8_t unused0[4]; /* - * TCAM key located at offset 0, mask located at key_size - * and result at 2 * key_size for the device. + * Index table entry allocated by the firmware using the + * parameters above. */ - uint8_t dev_data[272]; - /* unused. */ - uint8_t unused1[7]; + uint16_t idx_tbl_id; + /* Reserved */ + uint8_t unused0[5]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tfc_tcam_get_output_t, *phwrm_tfc_tcam_get_output_t; +} hwrm_tfc_idx_tbl_alloc_output_t, *phwrm_tfc_idx_tbl_alloc_output_t; -/*********************** - * hwrm_tfc_tcam_alloc * - ***********************/ +/****************************** + * hwrm_tfc_idx_tbl_alloc_set * + ******************************/ -/* hwrm_tfc_tcam_alloc_input (size:256b/32B) */ +/* hwrm_tfc_idx_tbl_alloc_set_input (size:1088b/136B) */ -typedef struct hwrm_tfc_tcam_alloc_input { +typedef struct hwrm_tfc_idx_tbl_alloc_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53596,59 +56938,94 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; + /* + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. + */ + uint16_t sid; /* Control flags. */ uint8_t flags; /* Indicates the flow direction. */ - #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX /* - * Subtype of TCAM resource. See - * cfa_v3/include/cfa_resources.h. + * Indicate device data is being sent via DMA, the device + * data packing does not change. */ - uint8_t subtype; + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2) /* - * Unique session id for the session created by the - * firmware. Will be used to track this index table entry - * only if track type is track_type_sid. + * This field is blktype specific. + * For blktype CFA - CFA resource subtype. For definitions, + * please see cfa_v3/include/cfa_resources.h. + * For blktype rxp, re_gparse, te_gparse - + * Tunnel Type. A value of zero (or unknown) means alloc. A known + * value (previously allocated dynamic UPAR for tunnel_type) means + * realloc. Will fail if a realloc is for previously allocated FID, */ - uint16_t sid; - /* Number of bytes in the TCAM key. */ - uint16_t key_size; - /* Entry priority. */ - uint16_t priority; + uint8_t subtype; /* Describes the type of tracking id to be used */ uint8_t track_type; /* Invalid track type */ - #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) /* Tracked by session id */ - #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) /* Tracked by function id */ - #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) - #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_LAST HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID - /* Unused. */ - uint8_t unused0[7]; -} hwrm_tfc_tcam_alloc_input_t, *phwrm_tfc_tcam_alloc_input_t; - -/* hwrm_tfc_tcam_alloc_output (size:128b/16B) */ - -typedef struct hwrm_tfc_tcam_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_LAST HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_LAST HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* The size of the index table entry in bytes. */ + uint16_t data_size; + /* Reserved */ + uint8_t unused1[6]; + /* The location of the dma buffer */ + uint64_t dma_addr; + /* + * Index table data located at offset 0. If dma bit is set, + * then this field contains the DMA buffer pointer. + */ + uint8_t dev_data[96]; +} hwrm_tfc_idx_tbl_alloc_set_input_t, *phwrm_tfc_idx_tbl_alloc_set_input_t; + +/* hwrm_tfc_idx_tbl_alloc_set_output (size:128b/16B) */ + +typedef struct hwrm_tfc_idx_tbl_alloc_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ uint16_t resp_len; /* * Index table entry allocated by the firmware using the * parameters above. */ - uint16_t idx; + uint16_t idx_tbl_id; /* Reserved */ uint8_t unused0[5]; /* @@ -53660,16 +57037,16 @@ * is written last. */ uint8_t valid; -} hwrm_tfc_tcam_alloc_output_t, *phwrm_tfc_tcam_alloc_output_t; +} hwrm_tfc_idx_tbl_alloc_set_output_t, *phwrm_tfc_idx_tbl_alloc_set_output_t; -/*************************** - * hwrm_tfc_tcam_alloc_set * - ***************************/ +/************************ + * hwrm_tfc_idx_tbl_set * + ************************/ -/* hwrm_tfc_tcam_alloc_set_input (size:1088b/136B) */ +/* hwrm_tfc_idx_tbl_set_input (size:1088b/136B) */ -typedef struct hwrm_tfc_tcam_alloc_set_input { +typedef struct hwrm_tfc_idx_tbl_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53701,54 +57078,68 @@ /* Control flags. */ uint8_t flags; /* Indicates the flow direction. */ - #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_LAST HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX - /* Indicate device data is being sent via DMA. */ - #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX /* - * Subtype of TCAM resource. See + * Indicate device data is being sent via DMA, the device + * data packing does not change. + */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * CFA resource subtype. For definitions, please see * cfa_v3/include/cfa_resources.h. */ uint8_t subtype; /* - * Unique session id for the session created by the - * firmware. Will be used to track this index table entry - * only if track type is track_type_sid. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. */ uint16_t sid; - /* Number of bytes in the TCAM key. */ - uint16_t key_size; - /* The size of the TCAM table entry in bytes. */ - uint16_t result_size; - /* Entry priority. */ - uint16_t priority; - /* Describes the type of tracking id to be used */ - uint8_t track_type; - /* Invalid track type */ - #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) - /* Tracked by session id */ - #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) - /* Tracked by function id */ - #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) - #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_LAST HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID - /* Unused */ - uint8_t unused[5]; - /* The location of the response dma buffer */ + /* + * Index table index returned during alloc by the + * firmware. + */ + uint16_t idx_tbl_id; + /* The size of the index table entry in bytes. */ + uint16_t data_size; + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_LAST HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* unused. */ + uint8_t unused0[5]; + /* The location of the dma buffer */ uint64_t dma_addr; /* - * Index table data located at offset 0. If dma bit is set, + * Index table data located at offset 0. If dma bit is set, * then this field contains the DMA buffer pointer. */ uint8_t dev_data[96]; -} hwrm_tfc_tcam_alloc_set_input_t, *phwrm_tfc_tcam_alloc_set_input_t; +} hwrm_tfc_idx_tbl_set_input_t, *phwrm_tfc_idx_tbl_set_input_t; -/* hwrm_tfc_tcam_alloc_set_output (size:128b/16B) */ +/* hwrm_tfc_idx_tbl_set_output (size:128b/16B) */ -typedef struct hwrm_tfc_tcam_alloc_set_output { +typedef struct hwrm_tfc_idx_tbl_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53757,10 +57148,8 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Logical TCAM ID. */ - uint16_t tcam_id; - /* Reserved */ - uint8_t unused0[5]; + /* unused. */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -53770,16 +57159,16 @@ * is written last. */ uint8_t valid; -} hwrm_tfc_tcam_alloc_set_output_t, *phwrm_tfc_tcam_alloc_set_output_t; +} hwrm_tfc_idx_tbl_set_output_t, *phwrm_tfc_idx_tbl_set_output_t; -/********************** - * hwrm_tfc_tcam_free * - **********************/ +/************************ + * hwrm_tfc_idx_tbl_get * + ************************/ -/* hwrm_tfc_tcam_free_input (size:192b/24B) */ +/* hwrm_tfc_idx_tbl_get_input (size:320b/40B) */ -typedef struct hwrm_tfc_tcam_free_input { +typedef struct hwrm_tfc_idx_tbl_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53811,31 +57200,63 @@ /* Control flags. */ uint8_t flags; /* Indicates the flow direction. */ - #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_LAST HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX /* - * Subtype of TCAM resource. See + * When set use the special access register access to clear + * the table entry on read. + */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2) + /* + * CFA resource subtype. For definitions, please see * cfa_v3/include/cfa_resources.h. */ uint8_t subtype; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Session id associated with the firmware. Will be used * for validation if the track type matches. */ uint16_t sid; - /* Logical TCAM ID. */ - uint16_t tcam_id; - /* Reserved */ - uint8_t unused0[2]; -} hwrm_tfc_tcam_free_input_t, *phwrm_tfc_tcam_free_input_t; + /* + * Index table index returned during alloc by the + * firmware. + */ + uint16_t idx_tbl_id; + /* The size of the index table entry buffer in bytes. */ + uint16_t buffer_size; + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP block type */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_LAST HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* unused. */ + uint8_t unused0[5]; + /* The location of the response dma buffer */ + uint64_t dma_addr; +} hwrm_tfc_idx_tbl_get_input_t, *phwrm_tfc_idx_tbl_get_input_t; -/* hwrm_tfc_tcam_free_output (size:128b/16B) */ +/* hwrm_tfc_idx_tbl_get_output (size:128b/16B) */ -typedef struct hwrm_tfc_tcam_free_output { +typedef struct hwrm_tfc_idx_tbl_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53844,8 +57265,10 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Reserved */ - uint8_t unused0[7]; + /* The size of the index table buffer returned in device size bytes. */ + uint16_t data_size; + /* unused */ + uint8_t unused1[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -53855,16 +57278,16 @@ * is written last. */ uint8_t valid; -} hwrm_tfc_tcam_free_output_t, *phwrm_tfc_tcam_free_output_t; +} hwrm_tfc_idx_tbl_get_output_t, *phwrm_tfc_idx_tbl_get_output_t; -/****************************** - * hwrm_tunnel_dst_port_query * - ******************************/ +/************************* + * hwrm_tfc_idx_tbl_free * + *************************/ -/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ +/* hwrm_tfc_idx_tbl_free_input (size:256b/32B) */ -typedef struct hwrm_tunnel_dst_port_query_input { +typedef struct hwrm_tfc_idx_tbl_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -53893,35 +57316,54 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Custom GRE uses UPAR to parse customized GRE packets */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) - /* Enhanced Common Packet Radio Interface (eCPRI) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) - /* IPv6 Segment Routing (SRv6) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE - uint8_t unused_0[7]; -} hwrm_tunnel_dst_port_query_input_t, *phwrm_tunnel_dst_port_query_input_t; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* Index table id to be freed by the firmware. */ + uint16_t idx_tbl_id; + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP block type */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE parse block type */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE parse block type */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_LAST HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* unused. */ + uint8_t unused0[7]; +} hwrm_tfc_idx_tbl_free_input_t, *phwrm_tfc_idx_tbl_free_input_t; -/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ +/* hwrm_tfc_idx_tbl_free_output (size:128b/16B) */ -typedef struct hwrm_tunnel_dst_port_query_output { +typedef struct hwrm_tfc_idx_tbl_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -53930,66 +57372,55 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This field represents the identifier of L4 destination port - * used for the given tunnel type. This field is valid for - * specific tunnel types that use layer 4 (e.g. UDP) - * transports for tunneling. - */ - uint16_t tunnel_dst_port_id; - /* - * This field represents the value of L4 destination port - * identified by tunnel_dst_port_id. This field is valid for - * specific tunnel types that use layer 4 (e.g. UDP) - * transports for tunneling. - * This field is in network byte order. - * - * A value of 0 means that the destination port is not - * configured. - */ - uint16_t tunnel_dst_port_val; - /* - * This field represents the UPAR usage status. - * Available UPARs on wh+ are UPAR0 and UPAR1 - * Available UPARs on Thor are UPAR0 to UPAR3 - * Available UPARs on Thor2 are UPAR0 to UPAR7 - */ - uint8_t upar_in_use; - /* This bit will be '1' when UPAR0 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR0 UINT32_C(0x1) - /* This bit will be '1' when UPAR1 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR1 UINT32_C(0x2) - /* This bit will be '1' when UPAR2 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR2 UINT32_C(0x4) - /* This bit will be '1' when UPAR3 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR3 UINT32_C(0x8) - /* This bit will be '1' when UPAR4 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR4 UINT32_C(0x10) - /* This bit will be '1' when UPAR5 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR5 UINT32_C(0x20) - /* This bit will be '1' when UPAR6 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR6 UINT32_C(0x40) - /* This bit will be '1' when UPAR7 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7 UINT32_C(0x80) - uint8_t unused_0[2]; + /* Reserved */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tunnel_dst_port_query_output_t, *phwrm_tunnel_dst_port_query_output_t; +} hwrm_tfc_idx_tbl_free_output_t, *phwrm_tfc_idx_tbl_free_output_t; -/****************************** - * hwrm_tunnel_dst_port_alloc * - ******************************/ +/* TruFlow resources request for a global id. */ +/* tfc_global_id_hwrm_req (size:64b/8B) */ +typedef struct tfc_global_id_hwrm_req { + /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */ + uint16_t rtype; + /* Indicates the flow direction in type of cfa_dir. */ + uint16_t dir; + /* Subtype of the resource type. */ + uint16_t subtype; + /* Number of the type of resources. */ + uint16_t cnt; +} tfc_global_id_hwrm_req_t, *ptfc_global_id_hwrm_req_t; -/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ +/* The reserved resources for the global id. */ +/* tfc_global_id_hwrm_rsp (size:64b/8B) */ -typedef struct hwrm_tunnel_dst_port_alloc_input { +typedef struct tfc_global_id_hwrm_rsp { + /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */ + uint16_t rtype; + /* Indicates the flow direction in type of cfa_dir. */ + uint16_t dir; + /* Subtype of the resource type. */ + uint16_t subtype; + /* The global id that the resources reserved for. */ + uint16_t id; +} tfc_global_id_hwrm_rsp_t, *ptfc_global_id_hwrm_rsp_t; + +/**************************** + * hwrm_tfc_global_id_alloc * + ****************************/ + + +/* hwrm_tfc_global_id_alloc_input (size:320b/40B) */ + +typedef struct hwrm_tfc_global_id_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54018,47 +57449,44 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) - /* Enhanced Common Packet Radio Interface (eCPRI) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) - /* IPv6 Segment Routing (SRv6) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE - uint8_t unused_0; /* - * This field represents the value of L4 destination port used - * for the given tunnel type. This field is valid for - * specific tunnel types that use layer 4 (e.g. UDP) - * transports for tunneling. - * - * This field is in network byte order. - * - * A value of 0 shall fail the command. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. */ - uint16_t tunnel_dst_port_val; - uint8_t unused_1[4]; -} hwrm_tunnel_dst_port_alloc_input_t, *phwrm_tunnel_dst_port_alloc_input_t; + uint16_t fid; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint16_t sid; + /* Global domain id. */ + uint16_t global_id; + /* + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. + */ + uint16_t req_cnt; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tfc_global_id_hwrm_req type. Size of the + * array buffer is provided by the 'req_cnt' field in this + * message. + */ + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tfc_global_id_hwrm_rsp type. Size of the array + * buffer is provided by the 'req_cnt' field in this + * message. + */ + uint64_t resc_addr; +} hwrm_tfc_global_id_alloc_input_t, *phwrm_tfc_global_id_alloc_input_t; -/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ +/* hwrm_tfc_global_id_alloc_output (size:128b/16B) */ -typedef struct hwrm_tunnel_dst_port_alloc_output { +typedef struct hwrm_tfc_global_id_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54068,61 +57496,35 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Identifier of a tunnel L4 destination port value. Only applies to tunnel - * types that has l4 destination port parameters. - */ - uint16_t tunnel_dst_port_id; - /* Error information */ - uint8_t error_info; - /* No error */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_SUCCESS UINT32_C(0x0) - /* Tunnel port is already allocated */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED UINT32_C(0x1) - /* Out of resources error */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE UINT32_C(0x2) - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_LAST HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE - /* - * This field represents the UPAR usage status. - * Available UPARs on wh+ are UPAR0 and UPAR1 - * Available UPARs on Thor are UPAR0 to UPAR3 - * Available UPARs on Thor2 are UPAR0 to UPAR7 + * Size of the returned hwrm_tfc_global_id_req data array. The value + * cannot exceed the req_cnt defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. */ - uint8_t upar_in_use; - /* This bit will be '1' when UPAR0 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR0 UINT32_C(0x1) - /* This bit will be '1' when UPAR1 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR1 UINT32_C(0x2) - /* This bit will be '1' when UPAR2 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR2 UINT32_C(0x4) - /* This bit will be '1' when UPAR3 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR3 UINT32_C(0x8) - /* This bit will be '1' when UPAR4 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR4 UINT32_C(0x10) - /* This bit will be '1' when UPAR5 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR5 UINT32_C(0x20) - /* This bit will be '1' when UPAR6 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR6 UINT32_C(0x40) - /* This bit will be '1' when UPAR7 is IN_USE */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR7 UINT32_C(0x80) - uint8_t unused_0[3]; + uint16_t rsp_cnt; + /* Non-zero if this is the first allocation for the global ID. */ + uint8_t first; + /* unused. */ + uint8_t unused0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tunnel_dst_port_alloc_output_t, *phwrm_tunnel_dst_port_alloc_output_t; +} hwrm_tfc_global_id_alloc_output_t, *phwrm_tfc_global_id_alloc_output_t; -/***************************** - * hwrm_tunnel_dst_port_free * - *****************************/ +/********************* + * hwrm_tfc_tcam_set * + *********************/ -/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ +/* hwrm_tfc_tcam_set_input (size:1088b/136B) */ -typedef struct hwrm_tunnel_dst_port_free_input { +typedef struct hwrm_tfc_tcam_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54151,41 +57553,56 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) - /* Enhanced Common Packet Radio Interface (eCPRI) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) - /* IPv6 Segment Routing (SRv6) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) - /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE - uint8_t unused_0; /* - * Identifier of a tunnel L4 destination port value. Only applies to tunnel - * types that has l4 destination port parameters. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. */ - uint16_t tunnel_dst_port_id; - uint8_t unused_1[4]; -} hwrm_tunnel_dst_port_free_input_t, *phwrm_tunnel_dst_port_free_input_t; + uint16_t fid; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* Logical TCAM ID. */ + uint16_t tcam_id; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* Number of bytes in the TCAM result. */ + uint16_t result_size; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_LAST HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX + /* Indicate device data is being sent via DMA. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* unused. */ + uint8_t unused0[4]; + /* The location of the response dma buffer */ + uint64_t dma_addr; + /* + * TCAM key located at offset 0, mask located at mask_offset + * and result at result_offset for the device. + */ + uint8_t dev_data[96]; +} hwrm_tfc_tcam_set_input_t, *phwrm_tfc_tcam_set_input_t; -/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ +/* hwrm_tfc_tcam_set_output (size:128b/16B) */ -typedef struct hwrm_tunnel_dst_port_free_output { +typedef struct hwrm_tfc_tcam_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54194,181 +57611,130 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Error information */ - uint8_t error_info; - /* No error */ - #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_SUCCESS UINT32_C(0x0) - /* Not owner error */ - #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_OWNER UINT32_C(0x1) - /* Not allocated error */ - #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED UINT32_C(0x2) - #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_LAST HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED - uint8_t unused_1[6]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} hwrm_tunnel_dst_port_free_output_t, *phwrm_tunnel_dst_port_free_output_t; +} hwrm_tfc_tcam_set_output_t, *phwrm_tfc_tcam_set_output_t; -/* Periodic statistics context DMA to host. */ -/* ctx_hw_stats (size:1280b/160B) */ +/********************* + * hwrm_tfc_tcam_get * + *********************/ -typedef struct ctx_hw_stats { - /* Number of received unicast packets */ - uint64_t rx_ucast_pkts; - /* Number of received multicast packets */ - uint64_t rx_mcast_pkts; - /* Number of received broadcast packets */ - uint64_t rx_bcast_pkts; - /* Number of discarded packets on receive path */ - uint64_t rx_discard_pkts; - /* Number of packets on receive path with error */ - uint64_t rx_error_pkts; - /* Number of received bytes for unicast traffic */ - uint64_t rx_ucast_bytes; - /* Number of received bytes for multicast traffic */ - uint64_t rx_mcast_bytes; - /* Number of received bytes for broadcast traffic */ - uint64_t rx_bcast_bytes; - /* Number of transmitted unicast packets */ - uint64_t tx_ucast_pkts; - /* Number of transmitted multicast packets */ - uint64_t tx_mcast_pkts; - /* Number of transmitted broadcast packets */ - uint64_t tx_bcast_pkts; - /* Number of packets on transmit path with error */ - uint64_t tx_error_pkts; - /* Number of discarded packets on transmit path */ - uint64_t tx_discard_pkts; - /* Number of transmitted bytes for unicast traffic */ - uint64_t tx_ucast_bytes; - /* Number of transmitted bytes for multicast traffic */ - uint64_t tx_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic */ - uint64_t tx_bcast_bytes; - /* Number of TPA packets */ - uint64_t tpa_pkts; - /* Number of TPA bytes */ - uint64_t tpa_bytes; - /* Number of TPA events */ - uint64_t tpa_events; - /* Number of TPA aborts */ - uint64_t tpa_aborts; -} ctx_hw_stats_t, *pctx_hw_stats_t; - -/* - * Extended periodic statistics context DMA to host. On cards that - * support TPA v2, additional TPA related stats exist and can be retrieved - * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure. - */ -/* ctx_hw_stats_ext (size:1408b/176B) */ - -typedef struct ctx_hw_stats_ext { - /* Number of received unicast packets */ - uint64_t rx_ucast_pkts; - /* Number of received multicast packets */ - uint64_t rx_mcast_pkts; - /* Number of received broadcast packets */ - uint64_t rx_bcast_pkts; - /* Number of discarded packets on receive path */ - uint64_t rx_discard_pkts; - /* Number of packets on receive path with error */ - uint64_t rx_error_pkts; - /* Number of received bytes for unicast traffic */ - uint64_t rx_ucast_bytes; - /* Number of received bytes for multicast traffic */ - uint64_t rx_mcast_bytes; - /* Number of received bytes for broadcast traffic */ - uint64_t rx_bcast_bytes; - /* Number of transmitted unicast packets */ - uint64_t tx_ucast_pkts; - /* Number of transmitted multicast packets */ - uint64_t tx_mcast_pkts; - /* Number of transmitted broadcast packets */ - uint64_t tx_bcast_pkts; - /* Number of packets on transmit path with error */ - uint64_t tx_error_pkts; - /* Number of discarded packets on transmit path */ - uint64_t tx_discard_pkts; - /* Number of transmitted bytes for unicast traffic */ - uint64_t tx_ucast_bytes; - /* Number of transmitted bytes for multicast traffic */ - uint64_t tx_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic */ - uint64_t tx_bcast_bytes; - /* Number of TPA eligible packets */ - uint64_t rx_tpa_eligible_pkt; - /* Number of TPA eligible bytes */ - uint64_t rx_tpa_eligible_bytes; - /* Number of TPA packets */ - uint64_t rx_tpa_pkt; - /* Number of TPA bytes */ - uint64_t rx_tpa_bytes; - /* Number of TPA errors */ - uint64_t rx_tpa_errors; - /* Number of TPA events */ - uint64_t rx_tpa_events; -} ctx_hw_stats_ext_t, *pctx_hw_stats_ext_t; -/* Periodic Engine statistics context DMA to host. */ -/* ctx_eng_stats (size:512b/64B) */ +/* hwrm_tfc_tcam_get_input (size:192b/24B) */ -typedef struct ctx_eng_stats { +typedef struct hwrm_tfc_tcam_get_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Count of data bytes into the Engine. - * This includes any user supplied prefix, - * but does not include any predefined - * prefix data. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint64_t eng_bytes_in; - /* Count of data bytes out of the Engine. */ - uint64_t eng_bytes_out; + uint16_t cmpl_ring; /* - * Count, in 4-byte (dword) units, of bytes - * that are input as auxiliary data. - * This includes the aux_cmd data. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint64_t aux_bytes_in; + uint16_t seq_id; /* - * Count, in 4-byte (dword) units, of bytes - * that are output as auxiliary data. - * This count is the buffer space for aux_data - * output provided in the RQE, not the actual - * aux_data written + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint64_t aux_bytes_out; - /* Count of number of commands executed. */ - uint64_t commands; + uint16_t target_id; /* - * Count of number of error commands. - * These are the commands with a - * non-zero status value. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint64_t error_commands; + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_LAST HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX /* - * Compression/Encryption Engine usage, - * the unit is count of clock cycles + * Subtype of TCAM resource See + * cfa_v3/include/cfa_resources.h. */ - uint64_t cce_engine_usage; + uint8_t subtype; /* - * De-Compression/De-cryption Engine usage, - * the unit is count of clock cycles + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. */ - uint64_t cdd_engine_usage; -} ctx_eng_stats_t, *pctx_eng_stats_t; + uint16_t fid; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* Logical TCAM ID. */ + uint16_t tcam_id; +} hwrm_tfc_tcam_get_input_t, *phwrm_tfc_tcam_get_input_t; + +/* hwrm_tfc_tcam_get_output (size:2368b/296B) */ + +typedef struct hwrm_tfc_tcam_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* Number of bytes in the TCAM result. */ + uint16_t result_size; + /* unused. */ + uint8_t unused0[4]; + /* + * TCAM key located at offset 0, mask located at key_size + * and result at 2 * key_size for the device. + */ + uint8_t dev_data[272]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} hwrm_tfc_tcam_get_output_t, *phwrm_tfc_tcam_get_output_t; /*********************** - * hwrm_stat_ctx_alloc * + * hwrm_tfc_tcam_alloc * ***********************/ -/* hwrm_stat_ctx_alloc_input (size:256b/32B) */ +/* hwrm_tfc_tcam_alloc_input (size:256b/32B) */ -typedef struct hwrm_stat_ctx_alloc_input { +typedef struct hwrm_tfc_tcam_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54397,52 +57763,55 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX /* - * This is the address for statistic block. - * > For new versions of the chip, this address should be 128B - * > aligned. - */ - uint64_t stats_dma_addr; - /* - * The statistic block update period in ms. - * e.g. 250ms, 500ms, 750ms, 1000ms. - * If update_period_ms is 0, then the stats update - * shall be never done and the DMA address shall not be used. - * In this case, the stat block can only be read by - * hwrm_stat_ctx_query command. - * On Ethernet/L2 based devices: - * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0), - * ctx_hw_stats_ext is used for DMA, - * else - * ctx_hw_stats is used for DMA. - */ - uint32_t update_period_ms; - /* - * This field is used to specify statistics context specific - * configuration flags. + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. */ - uint8_t stat_ctx_flags; + uint8_t subtype; /* - * When this bit is set to '1', the statistics context shall be - * allocated for RoCE traffic only. In this case, traffic other - * than offloaded RoCE traffic shall not be included in this - * statistic context. - * When this bit is set to '0', the statistics context shall be - * used for network traffic or engine traffic. + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. */ - #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1) - uint8_t unused_0; + uint16_t fid; /* - * This is the size of the structure (ctx_hw_stats or - * ctx_hw_stats_ext) that the driver has allocated to be used - * for the periodic DMA updates. + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. */ - uint16_t stats_dma_length; -} hwrm_stat_ctx_alloc_input_t, *phwrm_stat_ctx_alloc_input_t; + uint16_t sid; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* Entry priority. */ + uint16_t priority; + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_LAST HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Unused. */ + uint8_t unused0[5]; +} hwrm_tfc_tcam_alloc_input_t, *phwrm_tfc_tcam_alloc_input_t; -/* hwrm_stat_ctx_alloc_output (size:128b/16B) */ +/* hwrm_tfc_tcam_alloc_output (size:128b/16B) */ -typedef struct hwrm_stat_ctx_alloc_output { +typedef struct hwrm_tfc_tcam_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54451,27 +57820,32 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This is the statistics context ID value. */ - uint32_t stat_ctx_id; - uint8_t unused_0[3]; + /* + * Index table entry allocated by the firmware using the + * parameters above. + */ + uint16_t idx; + /* Reserved */ + uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_stat_ctx_alloc_output_t, *phwrm_stat_ctx_alloc_output_t; +} hwrm_tfc_tcam_alloc_output_t, *phwrm_tfc_tcam_alloc_output_t; -/********************** - * hwrm_stat_ctx_free * - **********************/ +/*************************** + * hwrm_tfc_tcam_alloc_set * + ***************************/ -/* hwrm_stat_ctx_free_input (size:192b/24B) */ +/* hwrm_tfc_tcam_alloc_set_input (size:1088b/136B) */ -typedef struct hwrm_stat_ctx_free_input { +typedef struct hwrm_tfc_tcam_alloc_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54500,14 +57874,66 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* ID of the statistics context that is being queried. */ - uint32_t stat_ctx_id; - uint8_t unused_0[4]; -} hwrm_stat_ctx_free_input_t, *phwrm_stat_ctx_free_input_t; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_LAST HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX + /* Indicate device data is being sent via DMA. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; + /* + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. + */ + uint16_t sid; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* The size of the TCAM table entry in bytes. */ + uint16_t result_size; + /* Entry priority. */ + uint16_t priority; + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_LAST HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Unused */ + uint8_t unused[3]; + /* The location of the response dma buffer */ + uint64_t dma_addr; + /* + * Index table data located at offset 0. If dma bit is set, + * then this field contains the DMA buffer pointer. + */ + uint8_t dev_data[96]; +} hwrm_tfc_tcam_alloc_set_input_t, *phwrm_tfc_tcam_alloc_set_input_t; -/* hwrm_stat_ctx_free_output (size:128b/16B) */ +/* hwrm_tfc_tcam_alloc_set_output (size:128b/16B) */ -typedef struct hwrm_stat_ctx_free_output { +typedef struct hwrm_tfc_tcam_alloc_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54516,27 +57942,29 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This is the statistics context ID value. */ - uint32_t stat_ctx_id; - uint8_t unused_0[3]; + /* Logical TCAM ID. */ + uint16_t tcam_id; + /* Reserved */ + uint8_t unused0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_stat_ctx_free_output_t, *phwrm_stat_ctx_free_output_t; +} hwrm_tfc_tcam_alloc_set_output_t, *phwrm_tfc_tcam_alloc_set_output_t; -/*********************** - * hwrm_stat_ctx_query * - ***********************/ +/********************** + * hwrm_tfc_tcam_free * + **********************/ -/* hwrm_stat_ctx_query_input (size:192b/24B) */ +/* hwrm_tfc_tcam_free_input (size:192b/24B) */ -typedef struct hwrm_stat_ctx_query_input { +typedef struct hwrm_tfc_tcam_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54565,21 +57993,41 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* ID of the statistics context that is being queried. */ - uint32_t stat_ctx_id; + /* Control flags. */ uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_LAST HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX /* - * This bit is set to 1 when request is for a counter mask, - * representing the width of each of the stats counters, rather - * than counters themselves. + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. */ - #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) - uint8_t unused_0[3]; -} hwrm_stat_ctx_query_input_t, *phwrm_stat_ctx_query_input_t; + uint8_t subtype; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* Logical TCAM ID. */ + uint16_t tcam_id; +} hwrm_tfc_tcam_free_input_t, *phwrm_tfc_tcam_free_input_t; -/* hwrm_stat_ctx_query_output (size:1408b/176B) */ +/* hwrm_tfc_tcam_free_output (size:128b/16B) */ -typedef struct hwrm_stat_ctx_query_output { +typedef struct hwrm_tfc_tcam_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54588,65 +58036,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of transmitted unicast packets */ - uint64_t tx_ucast_pkts; - /* Number of transmitted multicast packets */ - uint64_t tx_mcast_pkts; - /* Number of transmitted broadcast packets */ - uint64_t tx_bcast_pkts; - /* Number of packets discarded in transmit path */ - uint64_t tx_discard_pkts; - /* Number of packets in transmit path with error */ - uint64_t tx_error_pkts; - /* Number of transmitted bytes for unicast traffic */ - uint64_t tx_ucast_bytes; - /* Number of transmitted bytes for multicast traffic */ - uint64_t tx_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic */ - uint64_t tx_bcast_bytes; - /* Number of received unicast packets */ - uint64_t rx_ucast_pkts; - /* Number of received multicast packets */ - uint64_t rx_mcast_pkts; - /* Number of received broadcast packets */ - uint64_t rx_bcast_pkts; - /* Number of packets discarded in receive path */ - uint64_t rx_discard_pkts; - /* Number of packets in receive path with errors */ - uint64_t rx_error_pkts; - /* Number of received bytes for unicast traffic */ - uint64_t rx_ucast_bytes; - /* Number of received bytes for multicast traffic */ - uint64_t rx_mcast_bytes; - /* Number of received bytes for broadcast traffic */ - uint64_t rx_bcast_bytes; - /* Number of aggregated unicast packets */ - uint64_t rx_agg_pkts; - /* Number of aggregated unicast bytes */ - uint64_t rx_agg_bytes; - /* Number of aggregation events */ - uint64_t rx_agg_events; - /* Number of aborted aggregations */ - uint64_t rx_agg_aborts; - uint8_t unused_0[7]; + /* Reserved */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_stat_ctx_query_output_t, *phwrm_stat_ctx_query_output_t; +} hwrm_tfc_tcam_free_output_t, *phwrm_tfc_tcam_free_output_t; -/*************************** - * hwrm_stat_ext_ctx_query * - ***************************/ +/*********************** + * hwrm_tfc_if_tbl_set * + ***********************/ -/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ +/* hwrm_tfc_if_tbl_set_input (size:960b/120B) */ -typedef struct hwrm_stat_ext_ctx_query_input { +typedef struct hwrm_tfc_if_tbl_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54675,21 +58085,37 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* ID of the extended statistics context that is being queried. */ - uint32_t stat_ctx_id; - uint8_t flags; + /* Session identifier. */ + uint16_t sid; + /* Function identifier. */ + uint16_t fid; /* - * This bit is set to 1 when request is for a counter mask, - * representing the width of each of the stats counters, rather - * than counters themselves. + * Subtype identifying IF table type. See + * cfa_v3/include/cfa_resources.h. */ - #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) - uint8_t unused_0[3]; -} hwrm_stat_ext_ctx_query_input_t, *phwrm_stat_ext_ctx_query_input_t; + uint8_t subtype; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_LAST HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_TX + /* Table entry index. */ + uint16_t index; + /* Size of data in data field. */ + uint8_t data_size; + /* Reserved */ + uint8_t unused0[7]; + /* Table data. */ + uint8_t data[88]; +} hwrm_tfc_if_tbl_set_input_t, *phwrm_tfc_if_tbl_set_input_t; -/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ +/* hwrm_tfc_if_tbl_set_output (size:128b/16B) */ -typedef struct hwrm_stat_ext_ctx_query_output { +typedef struct hwrm_tfc_if_tbl_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54698,69 +58124,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of received unicast packets */ - uint64_t rx_ucast_pkts; - /* Number of received multicast packets */ - uint64_t rx_mcast_pkts; - /* Number of received broadcast packets */ - uint64_t rx_bcast_pkts; - /* Number of discarded packets on receive path */ - uint64_t rx_discard_pkts; - /* Number of packets on receive path with error */ - uint64_t rx_error_pkts; - /* Number of received bytes for unicast traffic */ - uint64_t rx_ucast_bytes; - /* Number of received bytes for multicast traffic */ - uint64_t rx_mcast_bytes; - /* Number of received bytes for broadcast traffic */ - uint64_t rx_bcast_bytes; - /* Number of transmitted unicast packets */ - uint64_t tx_ucast_pkts; - /* Number of transmitted multicast packets */ - uint64_t tx_mcast_pkts; - /* Number of transmitted broadcast packets */ - uint64_t tx_bcast_pkts; - /* Number of packets on transmit path with error */ - uint64_t tx_error_pkts; - /* Number of discarded packets on transmit path */ - uint64_t tx_discard_pkts; - /* Number of transmitted bytes for unicast traffic */ - uint64_t tx_ucast_bytes; - /* Number of transmitted bytes for multicast traffic */ - uint64_t tx_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic */ - uint64_t tx_bcast_bytes; - /* Number of TPA eligible packets */ - uint64_t rx_tpa_eligible_pkt; - /* Number of TPA eligible bytes */ - uint64_t rx_tpa_eligible_bytes; - /* Number of TPA packets */ - uint64_t rx_tpa_pkt; - /* Number of TPA bytes */ - uint64_t rx_tpa_bytes; - /* Number of TPA errors */ - uint64_t rx_tpa_errors; - /* Number of TPA events */ - uint64_t rx_tpa_events; - uint8_t unused_0[7]; + /* Reserved */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_stat_ext_ctx_query_output_t, *phwrm_stat_ext_ctx_query_output_t; +} hwrm_tfc_if_tbl_set_output_t, *phwrm_tfc_if_tbl_set_output_t; -/*************************** - * hwrm_stat_ctx_eng_query * - ***************************/ +/*********************** + * hwrm_tfc_if_tbl_get * + ***********************/ -/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */ +/* hwrm_tfc_if_tbl_get_input (size:256b/32B) */ -typedef struct hwrm_stat_ctx_eng_query_input { +typedef struct hwrm_tfc_if_tbl_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54789,14 +58173,35 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* ID of the statistics context that is being queried. */ - uint32_t stat_ctx_id; - uint8_t unused_0[4]; -} hwrm_stat_ctx_eng_query_input_t, *phwrm_stat_ctx_eng_query_input_t; + /* Session identifier. */ + uint16_t sid; + /* Function identifier. */ + uint16_t fid; + /* + * Subtype identifying IF table type. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_LAST HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_TX + /* Table entry index. */ + uint16_t index; + /* Size of data in data field. */ + uint8_t data_size; + /* Reserved */ + uint8_t unused0[7]; +} hwrm_tfc_if_tbl_get_input_t, *phwrm_tfc_if_tbl_get_input_t; -/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */ +/* hwrm_tfc_if_tbl_get_output (size:960b/120B) */ -typedef struct hwrm_stat_ctx_eng_query_output { +typedef struct hwrm_tfc_if_tbl_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54805,66 +58210,54 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Session identifier. */ + uint16_t sid; + /* Function identifier. */ + uint16_t fid; /* - * Count of data bytes into the Engine. - * This includes any user supplied prefix, - * but does not include any predefined - * prefix data. - */ - uint64_t eng_bytes_in; - /* Count of data bytes out of the Engine. */ - uint64_t eng_bytes_out; - /* - * Count, in 4-byte (dword) units, of bytes - * that are input as auxiliary data. - * This includes the aux_cmd data. - */ - uint64_t aux_bytes_in; - /* - * Count, in 4-byte (dword) units, of bytes - * that are output as auxiliary data. - * This count is the buffer space for aux_data - * output provided in the RQE, not the actual - * aux_data written - */ - uint64_t aux_bytes_out; - /* Count of number of commands executed. */ - uint64_t commands; - /* - * Count of number of error commands. - * These are the commands with a - * non-zero status value. - */ - uint64_t error_commands; - /* - * Compression/Encryption Engine usage, - * the unit is count of clock cycles - */ - uint64_t cce_engine_usage; - /* - * De-Compression/De-cryption Engine usage, - * the unit is count of clock cycles + * Subtype identifying IF table type. See + * cfa_v3/include/cfa_resources.h. */ - uint64_t cdd_engine_usage; - uint8_t unused_0[7]; + uint8_t subtype; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_LAST HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_TX + /* Table entry index. */ + uint16_t index; + /* Size of data in data field. */ + uint8_t data_size; + /* Reserved */ + uint8_t unused0[7]; + /* Table data. */ + uint8_t data[88]; + /* Reserved */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_stat_ctx_eng_query_output_t, *phwrm_stat_ctx_eng_query_output_t; +} hwrm_tfc_if_tbl_get_output_t, *phwrm_tfc_if_tbl_get_output_t; -/*************************** - * hwrm_stat_ctx_clr_stats * - ***************************/ +/********************************* + * hwrm_tfc_tbl_scope_config_get * + *********************************/ -/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ +/* TruFlow command to return whether the table scope is fully configured. */ +/* hwrm_tfc_tbl_scope_config_get_input (size:192b/24B) */ -typedef struct hwrm_stat_ctx_clr_stats_input { +typedef struct hwrm_tfc_tbl_scope_config_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54893,14 +58286,15 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* ID of the statistics context that is being queried. */ - uint32_t stat_ctx_id; - uint8_t unused_0[4]; -} hwrm_stat_ctx_clr_stats_input_t, *phwrm_stat_ctx_clr_stats_input_t; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} hwrm_tfc_tbl_scope_config_get_input_t, *phwrm_tfc_tbl_scope_config_get_input_t; -/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ +/* hwrm_tfc_tbl_scope_config_get_output (size:128b/16B) */ -typedef struct hwrm_stat_ctx_clr_stats_output { +typedef struct hwrm_tfc_tbl_scope_config_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54909,25 +58303,29 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* If set to 1, the table scope is configured. */ + uint8_t configured; + /* unused. */ + uint8_t unused0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_stat_ctx_clr_stats_output_t, *phwrm_stat_ctx_clr_stats_output_t; +} hwrm_tfc_tbl_scope_config_get_output_t, *phwrm_tfc_tbl_scope_config_get_output_t; -/******************** - * hwrm_pcie_qstats * - ********************/ +/***************************** + * hwrm_tfc_resc_usage_query * + *****************************/ -/* hwrm_pcie_qstats_input (size:256b/32B) */ +/* hwrm_tfc_resc_usage_query_input (size:256b/32B) */ -typedef struct hwrm_pcie_qstats_input { +typedef struct hwrm_tfc_resc_usage_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -54956,23 +58354,37 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * The size of PCIe statistics block in bytes. - * Firmware will DMA the PCIe statistics to - * the host with this field size in the response. - */ - uint16_t pcie_stat_size; - uint8_t unused_0[6]; - /* - * This is the host address where - * PCIe statistics will be stored - */ - uint64_t pcie_stat_host_addr; -} hwrm_pcie_qstats_input_t, *phwrm_pcie_qstats_input_t; + /* Session identifier. */ + uint16_t sid; + /* Function identifier. */ + uint16_t fid; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_LAST HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_LAST HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Size of data in data field. */ + uint16_t data_size; + /* unused */ + uint8_t unused1[8]; +} hwrm_tfc_resc_usage_query_input_t, *phwrm_tfc_resc_usage_query_input_t; -/* hwrm_pcie_qstats_output (size:128b/16B) */ +/* hwrm_tfc_resc_usage_query_output (size:960b/120B) */ -typedef struct hwrm_pcie_qstats_output { +typedef struct hwrm_tfc_resc_usage_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -54981,64 +58393,35 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The size of PCIe statistics block in bytes. */ - uint16_t pcie_stat_size; - uint8_t unused_0[5]; + /* Response code. */ + uint32_t resp_code; + /* Size of data in data field. */ + uint16_t data_size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[96]; + /* unused */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_pcie_qstats_output_t, *phwrm_pcie_qstats_output_t; - -/* PCIe Statistics Formats */ -/* pcie_ctx_hw_stats (size:768b/96B) */ - -typedef struct pcie_ctx_hw_stats { - /* Number of physical layer receiver errors */ - uint64_t pcie_pl_signal_integrity; - /* Number of DLLP CRC errors detected by Data Link Layer */ - uint64_t pcie_dl_signal_integrity; - /* - * Number of TLP LCRC and sequence number errors detected - * by Data Link Layer - */ - uint64_t pcie_tl_signal_integrity; - /* Number of times LTSSM entered Recovery state */ - uint64_t pcie_link_integrity; - /* Report number of TLP bits that have been transmitted in Mbps */ - uint64_t pcie_tx_traffic_rate; - /* Report number of TLP bits that have been received in Mbps */ - uint64_t pcie_rx_traffic_rate; - /* Number of DLLP bytes that have been transmitted */ - uint64_t pcie_tx_dllp_statistics; - /* Number of DLLP bytes that have been received */ - uint64_t pcie_rx_dllp_statistics; - /* - * Number of times spent in each phase of gen3 - * equalization - */ - uint64_t pcie_equalization_time; - /* Records the last 16 transitions of the LTSSM */ - uint32_t pcie_ltssm_histogram[4]; - /* - * Record the last 8 reasons on why LTSSM transitioned - * to Recovery - */ - uint64_t pcie_recovery_histogram; -} pcie_ctx_hw_stats_t, *ppcie_ctx_hw_stats_t; +} hwrm_tfc_resc_usage_query_output_t, *phwrm_tfc_resc_usage_query_output_t; -/**************************** - * hwrm_stat_generic_qstats * - ****************************/ +/****************************** + * hwrm_tunnel_dst_port_query * + ******************************/ -/* hwrm_stat_generic_qstats_input (size:256b/32B) */ +/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ -typedef struct hwrm_stat_generic_qstats_input { +typedef struct hwrm_tunnel_dst_port_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55067,32 +58450,64 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) /* - * The size of the generic statistics buffer passed in the - * generic_stat_host_addr in bytes. - * Firmware will not exceed this size when it DMAs the - * statistics structure to the host. The actual DMA size - * will be returned in the response. - */ - uint16_t generic_stat_size; - uint8_t flags; - /* - * The bit should be set to 1 when request is for the counter mask - * representing the width of each of the stats counters, rather - * than counters themselves. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - #define HWRM_STAT_GENERIC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) - uint8_t unused_0[5]; + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) /* - * This is the host address where - * generic statistics will be stored + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - uint64_t generic_stat_host_addr; -} hwrm_stat_generic_qstats_input_t, *phwrm_stat_generic_qstats_input_t; + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Custom GRE uses UPAR to parse customized GRE packets */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) + /* Enhanced Common Packet Radio Interface (eCPRI) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) + /* IPv6 Segment Routing (SRv6) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + /* Generic Routing Encapsulation */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11) + /* ULP Dynamic UPAR tunnel */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12) + /* ULP Dynamic UPAR tunnel reserved 1 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13) + /* ULP Dynamic UPAR tunnel reserved 2 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14) + /* ULP Dynamic UPAR tunnel reserved 3 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15) + /* ULP Dynamic UPAR tunnel reserved 4 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16) + /* ULP Dynamic UPAR tunnel reserved 5 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17) + /* ULP Dynamic UPAR tunnel reserved 6 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18) + /* ULP Dynamic UPAR tunnel reserved 7 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19) + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 + /* + * This field is used to specify the next protocol value defined in the + * corresponding RFC spec for the applicable tunnel type. + */ + uint8_t tunnel_next_proto; + uint8_t unused_0[6]; +} hwrm_tunnel_dst_port_query_input_t, *phwrm_tunnel_dst_port_query_input_t; -/* hwrm_stat_generic_qstats_output (size:128b/16B) */ +/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ -typedef struct hwrm_stat_generic_qstats_output { +typedef struct hwrm_tunnel_dst_port_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55101,125 +58516,78 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The size of Generic Statistics block in bytes. */ - uint16_t generic_stat_size; - uint8_t unused_0[5]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. - */ - uint8_t valid; -} hwrm_stat_generic_qstats_output_t, *phwrm_stat_generic_qstats_output_t; - -/* Generic Statistic Format */ -/* generic_sw_hw_stats (size:1408b/176B) */ - -typedef struct generic_sw_hw_stats { - /* - * This is the number of TLP bytes that have been transmitted for - * the caller PF. - */ - uint64_t pcie_statistics_tx_tlp; - /* - * This is the number of TLP bytes that have been received - * for the caller PF. - */ - uint64_t pcie_statistics_rx_tlp; - /* Posted Header Flow Control credits available for the caller PF. */ - uint64_t pcie_credit_fc_hdr_posted; - /* Non-posted Header Flow Control credits available for the caller PF. */ - uint64_t pcie_credit_fc_hdr_nonposted; - /* Completion Header Flow Control credits available for the caller PF. */ - uint64_t pcie_credit_fc_hdr_cmpl; - /* Posted Data Flow Control credits available for the caller PF. */ - uint64_t pcie_credit_fc_data_posted; - /* Non-Posted Data Flow Control credits available for the caller PF. */ - uint64_t pcie_credit_fc_data_nonposted; - /* Completion Data Flow Control credits available for the caller PF. */ - uint64_t pcie_credit_fc_data_cmpl; - /* - * Available Non-posted credit for target flow control reads or - * config for the caller PF. - */ - uint64_t pcie_credit_fc_tgt_nonposted; - /* - * Available posted data credit for target flow control writes - * for the caller PF. - */ - uint64_t pcie_credit_fc_tgt_data_posted; - /* - * Available posted header credit for target flow control writes - * for the caller PF. - */ - uint64_t pcie_credit_fc_tgt_hdr_posted; - /* Available completion flow control header credits for the caller PF. */ - uint64_t pcie_credit_fc_cmpl_hdr_posted; - /* Available completion flow control data credits. */ - uint64_t pcie_credit_fc_cmpl_data_posted; - /* - * Displays Time information of the longest completon time from any of - * the 4 tags for the caller PF. The unit of time recorded is in - * microseconds. - */ - uint64_t pcie_cmpl_longest; - /* - * Displays Time information of the shortest completon time from any of - * the 4 tags for the caller PF. The unit of time recorded is in - * microseconds. - */ - uint64_t pcie_cmpl_shortest; - /* - * This field containts the total number of CFCQ 'misses' observed for - * all the PF's. - */ - uint64_t cache_miss_count_cfcq; /* - * This field containts the total number of CFCS 'misses' observed for - * all the PF's. + * This field represents the identifier of L4 destination port + * used for the given tunnel type. This field is valid for + * specific tunnel types that use layer 4 (e.g. UDP) + * transports for tunneling. */ - uint64_t cache_miss_count_cfcs; + uint16_t tunnel_dst_port_id; /* - * This field containts the total number of CFCC 'misses' observed for - * all the PF's. + * This field represents the value of L4 destination port + * identified by tunnel_dst_port_id. This field is valid for + * specific tunnel types that use layer 4 (e.g. UDP) + * transports for tunneling. + * This field is in network byte order. + * + * A value of 0 means that the destination port is not + * configured. */ - uint64_t cache_miss_count_cfcc; + uint16_t tunnel_dst_port_val; /* - * This field containts the total number of CFCM 'misses' observed - * for all the PF's. + * This field represents the UPAR usage status. + * Available UPARs on wh+ are UPAR0 and UPAR1 + * Available UPARs on Thor are UPAR0 to UPAR3 + * Available UPARs on Thor2 are UPAR0 to UPAR7 */ - uint64_t cache_miss_count_cfcm; + uint8_t upar_in_use; + /* This bit will be '1' when UPAR0 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR0 UINT32_C(0x1) + /* This bit will be '1' when UPAR1 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR1 UINT32_C(0x2) + /* This bit will be '1' when UPAR2 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR2 UINT32_C(0x4) + /* This bit will be '1' when UPAR3 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR3 UINT32_C(0x8) + /* This bit will be '1' when UPAR4 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR4 UINT32_C(0x10) + /* This bit will be '1' when UPAR5 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR5 UINT32_C(0x20) + /* This bit will be '1' when UPAR6 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR6 UINT32_C(0x40) + /* This bit will be '1' when UPAR7 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7 UINT32_C(0x80) /* - * Total number of Doorbell messages dropped from the DB FIFO. - * This counter is only applicable for devices that support - * the hardware based doorbell drop recovery feature. + * This field is used to convey the status of non udp port based + * tunnel parsing at chip level and at function level. */ - uint64_t hw_db_recov_dbs_dropped; + uint8_t status; + /* This bit will be '1' when tunnel parsing is enabled globally. */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_CHIP_LEVEL UINT32_C(0x1) /* - * Total number of doorbell drops serviced. - * This counter is only applicable for devices that support - * the hardware based doorbell drop recovery feature. + * This bit will be '1' when tunnel parsing is enabled + * on the corresponding function. */ - uint64_t hw_db_recov_drops_serviced; + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_FUNC_LEVEL UINT32_C(0x2) + uint8_t unused_0; /* - * Total number of dropped doorbells recovered. - * This counter is only applicable for devices that support - * the hardware based doorbell drop recovery feature. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint64_t hw_db_recov_dbs_recovered; -} generic_sw_hw_stats_t, *pgeneric_sw_hw_stats_t; + uint8_t valid; +} hwrm_tunnel_dst_port_query_output_t, *phwrm_tunnel_dst_port_query_output_t; -/***************** - * hwrm_fw_reset * - *****************/ +/****************************** + * hwrm_tunnel_dst_port_alloc * + ******************************/ -/* hwrm_fw_reset_input (size:192b/24B) */ +/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ -typedef struct hwrm_fw_reset_input { +typedef struct hwrm_tunnel_dst_port_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55248,81 +58616,78 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Type of embedded processor. */ - uint8_t embedded_proc_type; - /* Boot Processor */ - #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0) - /* Management Processor */ - #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1) - /* Network control processor */ - #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2) - /* RoCE control processor */ - #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3) - /* - * Host (in multi-host environment): This is only valid if requester is IPC. - * Reinit host hardware resources and PCIe. - */ - #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4) + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) /* - * AP processor complex (in multi-host environment). - * Use host_idx to control which core is reset. + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload */ - #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP UINT32_C(0x5) - /* Reset all blocks of the chip (including all processors) */ - #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP UINT32_C(0x6) + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) /* - * Host (in multi-host environment): This is only valid if requester is IPC. - * Reinit host hardware resources. + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) */ - #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT UINT32_C(0x7) + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) /* - * Activate firmware that has been programmed to NVM. The - * activation is done in an impactless manner as part of the scheme - * where hwrm_fw_state_backup precedes the call, and - * hwrm_fw_state_restore follows it. Before this call returns, FW - * status is set to a non-0x8000 value to disambiguate reset pending - * from reset complete. The reset process begins after this call - * returns to ensure this HWRM has completed before reset begins. + * Custom GRE uses UPAR to parse customized GRE packets. This is not + * supported. */ - #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION UINT32_C(0x8) - #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION - /* Type of self reset. */ - uint8_t selfrst_status; - /* No Self Reset */ - #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0) - /* Self Reset as soon as possible to do so safely */ - #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1) - /* Self Reset on PCIe Reset */ - #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2) - /* Self Reset immediately after notification to all clients. */ - #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE UINT32_C(0x3) - #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) + /* Enhanced Common Packet Radio Interface (eCPRI) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) + /* IPv6 Segment Routing (SRv6) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + /* Generic Routing Encapsulation */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11) + /* ULP Dynamic UPAR tunnel */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12) + /* ULP Dynamic UPAR tunnel reserved 1 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13) + /* ULP Dynamic UPAR tunnel reserved 2 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14) + /* ULP Dynamic UPAR tunnel reserved 3 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15) + /* ULP Dynamic UPAR tunnel reserved 4 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16) + /* ULP Dynamic UPAR tunnel reserved 5 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17) + /* ULP Dynamic UPAR tunnel reserved 6 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18) + /* ULP Dynamic UPAR tunnel reserved 7 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19) + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 + /* + * This field is used to specify the next protocol value defined in the + * corresponding RFC spec for the applicable tunnel type. + */ + uint8_t tunnel_next_proto; /* - * Indicate which host is being reset. 0 means first host. - * Only valid when embedded_proc_type is host in multihost - * environment + * This field represents the value of L4 destination port used + * for the given tunnel type. This field is valid for + * specific tunnel types that use layer 4 (e.g. UDP) + * transports for tunneling. + * + * This field is in network byte order. + * + * A value of 0 shall fail the command. */ - uint8_t host_idx; - uint8_t flags; - /* - * When this bit is '1', then the core firmware initiates - * the reset only after graceful shut down of all registered instances. - * If not, the device will continue with the existing firmware. - */ - #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1) - /* - * When this bit is '1', then drivers will be notified that - * that the purpose of the reset was a firmware activation. - * Such notifications are delivered via the RESET_NOTIFY async - * event (reason_code: fw_activation). - */ - #define HWRM_FW_RESET_INPUT_FLAGS_FW_ACTIVATION UINT32_C(0x2) + uint16_t tunnel_dst_port_val; uint8_t unused_0[4]; -} hwrm_fw_reset_input_t, *phwrm_fw_reset_input_t; +} hwrm_tunnel_dst_port_alloc_input_t, *phwrm_tunnel_dst_port_alloc_input_t; -/* hwrm_fw_reset_output (size:128b/16B) */ +/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ -typedef struct hwrm_fw_reset_output { +typedef struct hwrm_tunnel_dst_port_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55331,36 +58696,64 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Type of self reset. */ - uint8_t selfrst_status; - /* No Self Reset */ - #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0) - /* Self Reset as soon as possible to do so safely */ - #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1) - /* Self Reset on PCIe Reset */ - #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2) - /* Self Reset immediately after notification to all clients. */ - #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE UINT32_C(0x3) - #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE - uint8_t unused_0[6]; + /* + * Identifier of a tunnel L4 destination port value. Only applies to + * tunnel types that has l4 destination port parameters. + */ + uint16_t tunnel_dst_port_id; + /* Error information */ + uint8_t error_info; + /* No error */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_SUCCESS UINT32_C(0x0) + /* Tunnel port is already allocated */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED UINT32_C(0x1) + /* Out of resources error */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE UINT32_C(0x2) + /* Tunnel type is already enabled */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ENABLED UINT32_C(0x3) + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_LAST HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ENABLED + /* + * This field represents the UPAR usage status. + * Available UPARs on wh+ are UPAR0 and UPAR1 + * Available UPARs on Thor are UPAR0 to UPAR3 + * Available UPARs on Thor2 are UPAR0 to UPAR7 + */ + uint8_t upar_in_use; + /* This bit will be '1' when UPAR0 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR0 UINT32_C(0x1) + /* This bit will be '1' when UPAR1 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR1 UINT32_C(0x2) + /* This bit will be '1' when UPAR2 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR2 UINT32_C(0x4) + /* This bit will be '1' when UPAR3 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR3 UINT32_C(0x8) + /* This bit will be '1' when UPAR4 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR4 UINT32_C(0x10) + /* This bit will be '1' when UPAR5 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR5 UINT32_C(0x20) + /* This bit will be '1' when UPAR6 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR6 UINT32_C(0x40) + /* This bit will be '1' when UPAR7 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR7 UINT32_C(0x80) + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_reset_output_t, *phwrm_fw_reset_output_t; +} hwrm_tunnel_dst_port_alloc_output_t, *phwrm_tunnel_dst_port_alloc_output_t; -/******************* - * hwrm_fw_qstatus * - *******************/ +/***************************** + * hwrm_tunnel_dst_port_free * + *****************************/ -/* hwrm_fw_qstatus_input (size:192b/24B) */ +/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ -typedef struct hwrm_fw_qstatus_input { +typedef struct hwrm_tunnel_dst_port_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55389,29 +58782,72 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Type of embedded processor. */ - uint8_t embedded_proc_type; - /* Boot Processor */ - #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0) - /* Management Processor */ - #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1) - /* Network control processor */ - #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2) - /* RoCE control processor */ - #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3) - /* Host (in multi-host environment): This is only valid if requester is IPC */ - #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4) - /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */ - #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_AP UINT32_C(0x5) - /* Reset all blocks of the chip (including all processors) */ - #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_CHIP UINT32_C(0x6) - #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_LAST HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_CHIP - uint8_t unused_0[7]; -} hwrm_fw_qstatus_input_t, *phwrm_fw_qstatus_input_t; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* + * Custom GRE uses UPAR to parse customized GRE packets. This is not + * supported. + */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) + /* Enhanced Common Packet Radio Interface (eCPRI) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) + /* IPv6 Segment Routing (SRv6) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) + /* Generic Routing Encapsulation */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11) + /* ULP Dynamic UPAR tunnel */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12) + /* ULP Dynamic UPAR tunnel reserved 1 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13) + /* ULP Dynamic UPAR tunnel reserved 2 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14) + /* ULP Dynamic UPAR tunnel reserved 3 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15) + /* ULP Dynamic UPAR tunnel reserved 4 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16) + /* ULP Dynamic UPAR tunnel reserved 5 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17) + /* ULP Dynamic UPAR tunnel reserved 6 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18) + /* ULP Dynamic UPAR tunnel reserved 7 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19) + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 + /* + * This field is used to specify the next protocol value defined in the + * corresponding RFC spec for the applicable tunnel type. + */ + uint8_t tunnel_next_proto; + /* + * Identifier of a tunnel L4 destination port value. Only applies to + * tunnel types that has l4 destination port parameters. + */ + uint16_t tunnel_dst_port_id; + uint8_t unused_0[4]; +} hwrm_tunnel_dst_port_free_input_t, *phwrm_tunnel_dst_port_free_input_t; -/* hwrm_fw_qstatus_output (size:128b/16B) */ +/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ -typedef struct hwrm_fw_qstatus_output { +typedef struct hwrm_tunnel_dst_port_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55420,51 +58856,181 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Type of self reset. */ - uint8_t selfrst_status; - /* No Self Reset */ - #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0) - /* Self Reset as soon as possible to do so safely */ - #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1) - /* Self Reset on PCIe Reset */ - #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2) - /* NIC power cycle (system cold boot) required */ - #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPOWER UINT32_C(0x3) - #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_LAST HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPOWER - /* - * The action needed to apply any pend nvm option changes. - * If multiple options have been set the highest level - * action is reported. - */ - uint8_t nvm_option_action_status; - /* No Action needed */ - #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE UINT32_C(0x0) - /* Hot reset needed to apply nvm options */ - #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET UINT32_C(0x1) - /* Warm boot needed to apply nvm options */ - #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT UINT32_C(0x2) - /* Cold boot needed to apply nvm options */ - #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT UINT32_C(0x3) - #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_LAST HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT - uint8_t unused_0[5]; + /* Error information */ + uint8_t error_info; + /* No error */ + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_SUCCESS UINT32_C(0x0) + /* Not owner error */ + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_OWNER UINT32_C(0x1) + /* Not allocated error */ + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED UINT32_C(0x2) + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_LAST HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED + uint8_t unused_1[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_qstatus_output_t, *phwrm_fw_qstatus_output_t; +} hwrm_tunnel_dst_port_free_output_t, *phwrm_tunnel_dst_port_free_output_t; -/******************** - * hwrm_fw_set_time * - ********************/ +/* Periodic statistics context DMA to host. */ +/* ctx_hw_stats (size:1280b/160B) */ +typedef struct ctx_hw_stats { + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of discarded packets on receive path */ + uint64_t rx_discard_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; + /* Number of discarded packets on transmit path */ + uint64_t tx_discard_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of TPA packets */ + uint64_t tpa_pkts; + /* Number of TPA bytes */ + uint64_t tpa_bytes; + /* Number of TPA events */ + uint64_t tpa_events; + /* Number of TPA aborts */ + uint64_t tpa_aborts; +} ctx_hw_stats_t, *pctx_hw_stats_t; -/* hwrm_fw_set_time_input (size:256b/32B) */ +/* + * Extended periodic statistics context DMA to host. On cards that + * support TPA v2, additional TPA related stats exist and can be retrieved + * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure. + */ +/* ctx_hw_stats_ext (size:1408b/176B) */ -typedef struct hwrm_fw_set_time_input { +typedef struct ctx_hw_stats_ext { + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of discarded packets on receive path */ + uint64_t rx_discard_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; + /* Number of discarded packets on transmit path */ + uint64_t tx_discard_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of TPA eligible packets */ + uint64_t rx_tpa_eligible_pkt; + /* Number of TPA eligible bytes */ + uint64_t rx_tpa_eligible_bytes; + /* Number of TPA packets */ + uint64_t rx_tpa_pkt; + /* Number of TPA bytes */ + uint64_t rx_tpa_bytes; + /* Number of TPA errors */ + uint64_t rx_tpa_errors; + /* Number of TPA events */ + uint64_t rx_tpa_events; +} ctx_hw_stats_ext_t, *pctx_hw_stats_ext_t; + +/* Periodic Engine statistics context DMA to host. */ +/* ctx_eng_stats (size:512b/64B) */ + +typedef struct ctx_eng_stats { + /* + * Count of data bytes into the Engine. + * This includes any user supplied prefix, + * but does not include any predefined + * prefix data. + */ + uint64_t eng_bytes_in; + /* Count of data bytes out of the Engine. */ + uint64_t eng_bytes_out; + /* + * Count, in 4-byte (dword) units, of bytes + * that are input as auxiliary data. + * This includes the aux_cmd data. + */ + uint64_t aux_bytes_in; + /* + * Count, in 4-byte (dword) units, of bytes + * that are output as auxiliary data. + * This count is the buffer space for aux_data + * output provided in the RQE, not the actual + * aux_data written + */ + uint64_t aux_bytes_out; + /* Count of number of commands executed. */ + uint64_t commands; + /* + * Count of number of error commands. + * These are the commands with a + * non-zero status value. + */ + uint64_t error_commands; + /* + * Compression/Encryption Engine usage, + * the unit is count of clock cycles + */ + uint64_t cce_engine_usage; + /* + * De-Compression/De-cryption Engine usage, + * the unit is count of clock cycles + */ + uint64_t cdd_engine_usage; +} ctx_eng_stats_t, *pctx_eng_stats_t; + +/*********************** + * hwrm_stat_ctx_alloc * + ***********************/ + + +/* hwrm_stat_ctx_alloc_input (size:320b/40B) */ + +typedef struct hwrm_stat_ctx_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55493,37 +59059,63 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Current year */ - uint16_t year; - /* Date/time is not known */ - #define HWRM_FW_SET_TIME_INPUT_YEAR_UNKNOWN UINT32_C(0x0) - #define HWRM_FW_SET_TIME_INPUT_YEAR_LAST HWRM_FW_SET_TIME_INPUT_YEAR_UNKNOWN - /* Current month of year (1-12) */ - uint8_t month; - /* Current day of month (1-31) */ - uint8_t day; - /* Current hour (0-23) */ - uint8_t hour; - /* Current minute (0-59) */ - uint8_t minute; - /* Current second (0-59) */ - uint8_t second; + /* + * This is the address for statistic block. + * > For new versions of the chip, this address should be 128B + * > aligned. + */ + uint64_t stats_dma_addr; + /* + * The statistic block update period in ms. + * e.g. 250ms, 500ms, 750ms, 1000ms. + * If update_period_ms is 0, then the stats update + * shall be never done and the DMA address shall not be used. + * In this case, the stat block can only be read by + * hwrm_stat_ctx_query command. + * On Ethernet/L2 based devices: + * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0), + * ctx_hw_stats_ext is used for DMA, + * else + * ctx_hw_stats is used for DMA. + */ + uint32_t update_period_ms; + /* + * This field is used to specify statistics context specific + * configuration flags. + */ + uint8_t stat_ctx_flags; + /* + * When this bit is set to '1', the statistics context shall be + * allocated for RoCE traffic only. In this case, traffic other + * than offloaded RoCE traffic shall not be included in this + * statistic context. + * When this bit is set to '0', the statistics context shall be + * used for network traffic or engine traffic. + */ + #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1) uint8_t unused_0; - /* Current millisecond (0-999) */ - uint16_t millisecond; - /* Minutes east of UTC, 0xffff if TZ is not known */ - int16_t zone; - /* Time zone is Coordinated Universal Time (UTC) */ - #define HWRM_FW_SET_TIME_INPUT_ZONE_UTC 0 - /* Time zone is not known */ - #define HWRM_FW_SET_TIME_INPUT_ZONE_UNKNOWN 65535 - #define HWRM_FW_SET_TIME_INPUT_ZONE_LAST HWRM_FW_SET_TIME_INPUT_ZONE_UNKNOWN - uint8_t unused_1[4]; -} hwrm_fw_set_time_input_t, *phwrm_fw_set_time_input_t; + /* + * This is the size of the structure (ctx_hw_stats or + * ctx_hw_stats_ext) that the driver has allocated to be used + * for the periodic DMA updates. + */ + uint16_t stats_dma_length; + uint16_t flags; + /* This stats context uses the steering tag specified in the command. */ + #define HWRM_STAT_CTX_ALLOC_INPUT_FLAGS_STEERING_TAG_VALID UINT32_C(0x1) + /* + * Steering tag to use for memory transactions from the periodic DMA + * updates. 'steering_tag_valid' should be set and 'steering_tag' + * should be specified, when the 'steering_tag_supported' bit is set + * under the 'flags_ext2' field of the hwrm_func_qcaps_output. + */ + uint16_t steering_tag; + uint32_t unused_1; +} hwrm_stat_ctx_alloc_input_t, *phwrm_stat_ctx_alloc_input_t; -/* hwrm_fw_set_time_output (size:128b/16B) */ +/* hwrm_stat_ctx_alloc_output (size:128b/16B) */ -typedef struct hwrm_fw_set_time_output { +typedef struct hwrm_stat_ctx_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55532,25 +59124,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* This is the statistics context ID value. */ + uint32_t stat_ctx_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_set_time_output_t, *phwrm_fw_set_time_output_t; +} hwrm_stat_ctx_alloc_output_t, *phwrm_stat_ctx_alloc_output_t; -/******************** - * hwrm_fw_get_time * - ********************/ +/********************** + * hwrm_stat_ctx_free * + **********************/ -/* hwrm_fw_get_time_input (size:128b/16B) */ +/* hwrm_stat_ctx_free_input (size:192b/24B) */ -typedef struct hwrm_fw_get_time_input { +typedef struct hwrm_stat_ctx_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -55579,11 +59173,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_fw_get_time_input_t, *phwrm_fw_get_time_input_t; + /* ID of the statistics context that is being queried. */ + uint32_t stat_ctx_id; + uint8_t unused_0[4]; +} hwrm_stat_ctx_free_input_t, *phwrm_stat_ctx_free_input_t; -/* hwrm_fw_get_time_output (size:192b/24B) */ +/* hwrm_stat_ctx_free_output (size:128b/16B) */ -typedef struct hwrm_fw_get_time_output { +typedef struct hwrm_stat_ctx_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -55592,500 +59189,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Current year */ - uint16_t year; - /* Date/time is not known */ - #define HWRM_FW_GET_TIME_OUTPUT_YEAR_UNKNOWN UINT32_C(0x0) - #define HWRM_FW_GET_TIME_OUTPUT_YEAR_LAST HWRM_FW_GET_TIME_OUTPUT_YEAR_UNKNOWN - /* Current month of year (1-12) */ - uint8_t month; - /* Current day of month (1-31) */ - uint8_t day; - /* Current hour (0-23) */ - uint8_t hour; - /* Current minute (0-59) */ - uint8_t minute; - /* Current second (0-59) */ - uint8_t second; - uint8_t unused_0; - /* Current millisecond (0-999) */ - uint16_t millisecond; - /* Minutes east of UTC, 0xffff if TZ is not known */ - int16_t zone; - /* Time zone is Coordinated Universal Time (UTC) */ - #define HWRM_FW_GET_TIME_OUTPUT_ZONE_UTC 0 - /* Time zone is not known */ - #define HWRM_FW_GET_TIME_OUTPUT_ZONE_UNKNOWN 65535 - #define HWRM_FW_GET_TIME_OUTPUT_ZONE_LAST HWRM_FW_GET_TIME_OUTPUT_ZONE_UNKNOWN - uint8_t unused_1[3]; + /* This is the statistics context ID value. */ + uint32_t stat_ctx_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_get_time_output_t, *phwrm_fw_get_time_output_t; +} hwrm_stat_ctx_free_output_t, *phwrm_stat_ctx_free_output_t; -/* hwrm_struct_hdr (size:128b/16B) */ +/*********************** + * hwrm_stat_ctx_query * + ***********************/ -typedef struct hwrm_struct_hdr { - /* This value indicates the structured data ID. */ - uint16_t struct_id; - /* LLDP configuration structured data ID. */ - #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_CFG UINT32_C(0x41b) - /* DCBX ETS configuration structured data ID. */ - #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_ETS UINT32_C(0x41d) - /* DCBX PFC configuration structured data ID. */ - #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_PFC UINT32_C(0x41f) - /* DCBX APP configuration structured data ID. */ - #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_APP UINT32_C(0x421) - /* DCBX state configuration structured data ID for all DCBX features. */ - #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE UINT32_C(0x422) - /* LLDP generic structured data ID. This is used with GET_STRUCTURED_DATA only. */ - #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_GENERIC UINT32_C(0x424) - /* LLDP device structured data ID. This is used with GET_STRUCTURED_DATA only. */ - #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_DEVICE UINT32_C(0x426) - /* Power Backup info */ - #define HWRM_STRUCT_HDR_STRUCT_ID_POWER_BKUP UINT32_C(0x427) - /* reserved for AFM usage. */ - #define HWRM_STRUCT_HDR_STRUCT_ID_AFM_OPAQUE UINT32_C(0x1) - /* Port description. */ - #define HWRM_STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION UINT32_C(0xa) - /* RSSv2 Configuration. */ - #define HWRM_STRUCT_HDR_STRUCT_ID_RSS_V2 UINT32_C(0x64) - /* MSI-X vectors per VF table. */ - #define HWRM_STRUCT_HDR_STRUCT_ID_MSIX_PER_VF UINT32_C(0xc8) - #define HWRM_STRUCT_HDR_STRUCT_ID_LAST HWRM_STRUCT_HDR_STRUCT_ID_MSIX_PER_VF - /* This value indicates the length of structured data. */ - uint16_t len; - /* This value indicates the version of structured data. */ - uint8_t version; - /* This value indicates the number of structured data elements. */ - uint8_t count; - /* This value indicates the subtype. */ - uint16_t subtype; - /* - * This value indicates the count of 64-bit values that point to the next header. - * A value of 0 means that this is the last element. The value is a count of 64-bit - * words from the beginning of the current header. - */ - uint16_t next_offset; - /* This value indicates this is the last element */ - #define HWRM_STRUCT_HDR_NEXT_OFFSET_LAST UINT32_C(0x0) - uint8_t unused_0[6]; -} hwrm_struct_hdr_t, *phwrm_struct_hdr_t; - -/* hwrm_struct_data_dcbx_ets (size:256b/32B) */ - -typedef struct hwrm_struct_data_dcbx_ets { - /* - * This field indicates if this configuration is ETS recommendation or ETS configuration. - * A value 1 means it is ETS configuration, A value of 2 means it is a ETS recommendation. - */ - uint8_t destination; - /* ETS configuration */ - #define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_CONFIGURATION UINT32_C(0x1) - /* ETS recommendation */ - #define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION UINT32_C(0x2) - #define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_LAST HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION - /* This value indicates maximum ETS TCs supported. */ - uint8_t max_tcs; - /* unused. */ - uint16_t unused1; - /* ETS priority 0 to TC map. */ - uint8_t pri0_to_tc_map; - /* ETS priority 1 to TC map. */ - uint8_t pri1_to_tc_map; - /* ETS priority 2 to TC map. */ - uint8_t pri2_to_tc_map; - /* ETS priority 3 to TC map. */ - uint8_t pri3_to_tc_map; - /* ETS priority 4 to TC map. */ - uint8_t pri4_to_tc_map; - /* ETS priority 5 to TC map. */ - uint8_t pri5_to_tc_map; - /* ETS priority 6 to TC map. */ - uint8_t pri6_to_tc_map; - /* ETS priority 7 to TC map. */ - uint8_t pri7_to_tc_map; - /* ETS TC 0 to bandwidth map. */ - uint8_t tc0_to_bw_map; - /* ETS TC 1 to bandwidth map. */ - uint8_t tc1_to_bw_map; - /* ETS TC 2 to bandwidth map. */ - uint8_t tc2_to_bw_map; - /* ETS TC 3 to bandwidth map. */ - uint8_t tc3_to_bw_map; - /* ETS TC 4 to bandwidth map. */ - uint8_t tc4_to_bw_map; - /* ETS TC 5 to bandwidth map. */ - uint8_t tc5_to_bw_map; - /* ETS TC 6 to bandwidth map. */ - uint8_t tc6_to_bw_map; - /* ETS TC 7 to bandwidth map. */ - uint8_t tc7_to_bw_map; - /* ETS TC 0 to TSA map. */ - uint8_t tc0_to_tsa_map; - /* strict priority */ - #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_SP UINT32_C(0x0) - /* credit based shaper */ - #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_CBS UINT32_C(0x1) - /* ETS */ - #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_ETS UINT32_C(0x2) - /* vendor specific */ - #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC UINT32_C(0xff) - #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_LAST HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC - /* ETS TC 1 to TSA map. */ - uint8_t tc1_to_tsa_map; - /* ETS TC 2 to TSA map. */ - uint8_t tc2_to_tsa_map; - /* ETS TC 3 to TSA map. */ - uint8_t tc3_to_tsa_map; - /* ETS TC 4 to TSA map. */ - uint8_t tc4_to_tsa_map; - /* ETS TC 5 to TSA map. */ - uint8_t tc5_to_tsa_map; - /* ETS TC 6 to TSA map. */ - uint8_t tc6_to_tsa_map; - /* ETS TC 7 to TSA map. */ - uint8_t tc7_to_tsa_map; - uint8_t unused_0[4]; -} hwrm_struct_data_dcbx_ets_t, *phwrm_struct_data_dcbx_ets_t; - -/* hwrm_struct_data_dcbx_pfc (size:64b/8B) */ - -typedef struct hwrm_struct_data_dcbx_pfc { - /* - * This field indicates PFC priority bit map. A value of '0' indicates PFC - * is disabled. A value of '1' indicates PFC is enabled on that priority. - */ - uint8_t pfc_priority_bitmap; - /* - * This field indicates max PFC TCs supported. Each PFC TC will map to - * a lossless CoS queue. - */ - uint8_t max_pfc_tcs; - /* - * This field indicates if MACSec bypass capability is enabled. A value - * of '1' indicates MBC is enabled. A value of '0' indicates MBC is disabled. - */ - uint8_t mbc; - uint8_t unused_0[5]; -} hwrm_struct_data_dcbx_pfc_t, *phwrm_struct_data_dcbx_pfc_t; - -/* hwrm_struct_data_dcbx_app (size:64b/8B) */ - -typedef struct hwrm_struct_data_dcbx_app { - /* - * This field indicates the protocol identifier. This should be specified - * in big endian format. - */ - uint16_t protocol_id; - /* - * This field indicates the protocol selector. The valid values are - * mentioned below. - */ - uint8_t protocol_selector; - /* ether type */ - #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE UINT32_C(0x1) - /* TCP port */ - #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT UINT32_C(0x2) - /* UDP port */ - #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT UINT32_C(0x3) - /* TCP & UDP port */ - #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT UINT32_C(0x4) - #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT - /* This field indicates application priority. */ - uint8_t priority; - /* This field indicates this entry is valid. */ - uint8_t valid; - uint8_t unused_0[3]; -} hwrm_struct_data_dcbx_app_t, *phwrm_struct_data_dcbx_app_t; - -/* hwrm_struct_data_dcbx_feature_state (size:64b/8B) */ - -typedef struct hwrm_struct_data_dcbx_feature_state { - /* DCBX mode - IEEE or CEE. This is read only field. */ - uint8_t dcbx_mode; - /* DCBX disabled mode. */ - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_DISABLED UINT32_C(0x0) - /* DCBX IEEE mode. */ - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_IEEE UINT32_C(0x1) - /* DCBX CEE mode. */ - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE UINT32_C(0x2) - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_LAST HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE - /* ETS TLV state. */ - uint8_t ets_state; - /* PFC TLV state. */ - uint8_t pfc_state; - /* App TLV state. */ - uint8_t app_state; - /* Feature enable bit position. */ - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ENABLE_BIT_POS UINT32_C(0x7) - /* Feature willing bit position. */ - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_WILLING_BIT_POS UINT32_C(0x6) - /* Feature advertise bit position. */ - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS UINT32_C(0x5) - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_LAST HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS - /* unused. */ - uint8_t unused[3]; - /* This field is used to reset the DCBX configuration to factory defaults. */ - uint8_t resets; - /* reset ETS configuration. */ - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS UINT32_C(0x1) - /* reset PFC configuration. */ - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_PFC UINT32_C(0x2) - /* reset application configuration. */ - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_APP UINT32_C(0x4) - /* reset DCBX state configuration. */ - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE UINT32_C(0x8) - #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_LAST HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE -} hwrm_struct_data_dcbx_feature_state_t, *phwrm_struct_data_dcbx_feature_state_t; - -/* hwrm_struct_data_lldp (size:64b/8B) */ - -typedef struct hwrm_struct_data_lldp { - /* Port admin state */ - uint8_t admin_state; - /* Disable both Tx and Rx */ - #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_DISABLE UINT32_C(0x0) - /* Enable Tx only */ - #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_TX UINT32_C(0x1) - /* Enable Rx only */ - #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_RX UINT32_C(0x2) - /* Enable both Tx and Rx */ - #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE UINT32_C(0x3) - #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_LAST HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE - /* Port description TLV transmit state (enable(1)/disable(0)). */ - uint8_t port_description_state; - /* Disable */ - #define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_DISABLE UINT32_C(0x0) - /* Enable. */ - #define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE UINT32_C(0x1) - #define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_LAST HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE - /* System name TLV transmit state (enable(1)/disable(0)). */ - uint8_t system_name_state; - /* Disable */ - #define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_DISABLE UINT32_C(0x0) - /* Enable. */ - #define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE UINT32_C(0x1) - #define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_LAST HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE - /* System description TLV transmit state (enable(1)/disable(0)). */ - uint8_t system_desc_state; - /* Disable */ - #define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_DISABLE UINT32_C(0x0) - /* Enable. */ - #define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE UINT32_C(0x1) - #define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_LAST HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE - /* System capabilities TLV transmit state (enable(1)/disable(0)). */ - uint8_t system_cap_state; - /* Disable */ - #define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_DISABLE UINT32_C(0x0) - /* Enable. */ - #define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE UINT32_C(0x1) - #define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_LAST HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE - /* Management address TLV transmit state (enable(1)/disable(0)). */ - uint8_t mgmt_addr_state; - /* Disable */ - #define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_DISABLE UINT32_C(0x0) - /* Enable. */ - #define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE UINT32_C(0x1) - #define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_LAST HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE - /* Async event notification state (enable(1)/disable(0)). */ - uint8_t async_event_notification_state; - /* Disable */ - #define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_DISABLE UINT32_C(0x0) - /* Enable. */ - #define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE UINT32_C(0x1) - #define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_LAST HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE - uint8_t unused_0; -} hwrm_struct_data_lldp_t, *phwrm_struct_data_lldp_t; - -/* hwrm_struct_data_lldp_generic (size:2112b/264B) */ - -typedef struct hwrm_struct_data_lldp_generic { - /* TLV type. */ - uint8_t tlv_type; - /* Chassis ID TLV */ - #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_CHASSIS UINT32_C(0x1) - /* Port ID TLV */ - #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT UINT32_C(0x2) - /* System name TLV */ - #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_NAME UINT32_C(0x3) - /* System description TLV */ - #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_DESCRIPTION UINT32_C(0x4) - /* Port name TLV */ - #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_NAME UINT32_C(0x5) - /* Port description TLV */ - #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION UINT32_C(0x6) - #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_LAST HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION - /* TLV sub-type. */ - uint8_t subtype; - /* Length. */ - uint8_t length; - /* unused. */ - uint8_t unused1[5]; - /* TLV value. */ - uint32_t tlv_value[64]; -} hwrm_struct_data_lldp_generic_t, *phwrm_struct_data_lldp_generic_t; - -/* hwrm_struct_data_lldp_device (size:1472b/184B) */ - -typedef struct hwrm_struct_data_lldp_device { - /* Time to Live. */ - uint16_t ttl; - /* Management address length. */ - uint8_t mgmt_addr_len; - /* Management address type. */ - uint8_t mgmt_addr_type; - uint8_t unused_3[4]; - /* Management address. */ - uint32_t mgmt_addr[8]; - /* System capabilities. */ - uint32_t system_caps; - /* Interface number type. */ - uint8_t intf_num_type; - /* Management address OID length. */ - uint8_t mgmt_addr_oid_length; - uint8_t unused_4[2]; - /* Interface number. */ - uint32_t intf_num; - uint8_t unused_5[4]; - /* Management address OID. */ - uint32_t mgmt_addr_oid[32]; -} hwrm_struct_data_lldp_device_t, *phwrm_struct_data_lldp_device_t; - -/* hwrm_struct_data_port_description (size:64b/8B) */ - -typedef struct hwrm_struct_data_port_description { - /* - * Port #. Port number starts at 0 and anything greater than number of ports - * minus 1 is an error. - */ - uint8_t port_id; - uint8_t unused_0[7]; -} hwrm_struct_data_port_description_t, *phwrm_struct_data_port_description_t; - -/* hwrm_struct_data_rss_v2 (size:128b/16B) */ - -typedef struct hwrm_struct_data_rss_v2 { - uint16_t flags; - /* When this bit is '1', the hash type and hash key are included. */ - #define HWRM_STRUCT_DATA_RSS_V2_FLAGS_HASH_VALID UINT32_C(0x1) - /* RSS Context index. */ - uint16_t rss_ctx_id; - /* Number ring group IDs. */ - uint16_t num_ring_groups; - uint16_t hash_type; - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv4 - * packets. - */ - #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV4 UINT32_C(0x1) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of TCP/IPv4 packets. - */ - #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of UDP/IPv4 packets. - */ - #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 - * packets. - */ - #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV6 UINT32_C(0x8) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of TCP/IPv6 packets. - */ - #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of UDP/IPv6 packets. - */ - #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) - /* Hash key. This field is optional. */ - uint64_t hash_key_ring_group_ids; -} hwrm_struct_data_rss_v2_t, *phwrm_struct_data_rss_v2_t; - -/* hwrm_struct_data_power_information (size:192b/24B) */ - -typedef struct hwrm_struct_data_power_information { - /* Backup power information version */ - uint32_t bkup_power_info_ver; - /* Platform backup power count */ - uint32_t platform_bkup_power_count; - /* Load in milli Watt */ - uint32_t load_milli_watt; - /* Backup time in milli seconds */ - uint32_t bkup_time_milli_seconds; - /* Backup power status */ - uint32_t bkup_power_status; - /* Backup power charge time */ - uint32_t bkup_power_charge_time; -} hwrm_struct_data_power_information_t, *phwrm_struct_data_power_information_t; - -/* hwrm_struct_data_msix_per_vf (size:320b/40B) */ - -typedef struct hwrm_struct_data_msix_per_vf { - /* PF ID */ - uint16_t pf_id; - /* Number of rows in table. */ - uint16_t count; - uint32_t unused_0; - /* Starting VF for row 0 */ - uint16_t start_vf_0; - /* MSI-X vectors per VF for row 0 */ - uint16_t msix_0; - /* Starting VF for row 1 */ - uint16_t start_vf_1; - /* MSI-X vectors per VF for row 1 */ - uint16_t msix_1; - /* Starting VF for row 2 */ - uint16_t start_vf_2; - /* MSI-X vectors per VF for row 2 */ - uint16_t msix_2; - /* Starting VF for row 3 */ - uint16_t start_vf_3; - /* MSI-X vectors per VF for row 3 */ - uint16_t msix_3; - /* Starting VF for row 4 */ - uint16_t start_vf_4; - /* MSI-X vectors per VF for row 4 */ - uint16_t msix_4; - /* Starting VF for row 5 */ - uint16_t start_vf_5; - /* MSI-X vectors per VF for row 5 */ - uint16_t msix_5; - /* Starting VF for row 6 */ - uint16_t start_vf_6; - /* MSI-X vectors per VF for row 6 */ - uint16_t msix_6; - /* Starting VF for row 7 */ - uint16_t start_vf_7; - /* MSI-X vectors per VF for row 7 */ - uint16_t msix_7; -} hwrm_struct_data_msix_per_vf_t, *phwrm_struct_data_msix_per_vf_t; - -/******************************* - * hwrm_fw_set_structured_data * - *******************************/ +/* hwrm_stat_ctx_query_input (size:192b/24B) */ -/* hwrm_fw_set_structured_data_input (size:256b/32B) */ - -typedef struct hwrm_fw_set_structured_data_input { +typedef struct hwrm_stat_ctx_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56114,24 +59238,21 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* ID of the statistics context that is being queried. */ + uint32_t stat_ctx_id; + uint8_t flags; /* - * This is the host address where - * structured data will be copied from - */ - uint64_t src_data_addr; - /* size of data in bytes */ - uint16_t data_len; - /* - * a count of the number of Structured Data Headers in the data - * pointed by src_data_addr. + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. */ - uint8_t hdr_cnt; - uint8_t unused_0[5]; -} hwrm_fw_set_structured_data_input_t, *phwrm_fw_set_structured_data_input_t; + #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + uint8_t unused_0[3]; +} hwrm_stat_ctx_query_input_t, *phwrm_stat_ctx_query_input_t; -/* hwrm_fw_set_structured_data_output (size:128b/16B) */ +/* hwrm_stat_ctx_query_output (size:1408b/176B) */ -typedef struct hwrm_fw_set_structured_data_output { +typedef struct hwrm_stat_ctx_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56140,45 +59261,65 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of packets discarded in transmit path */ + uint64_t tx_discard_pkts; + /* Number of packets in transmit path with error */ + uint64_t tx_error_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of packets discarded in receive path */ + uint64_t rx_discard_pkts; + /* Number of packets in receive path with errors */ + uint64_t rx_error_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of aggregated unicast packets */ + uint64_t rx_agg_pkts; + /* Number of aggregated unicast bytes */ + uint64_t rx_agg_bytes; + /* Number of aggregation events */ + uint64_t rx_agg_events; + /* Number of aborted aggregations */ + uint64_t rx_agg_aborts; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_set_structured_data_output_t, *phwrm_fw_set_structured_data_output_t; - -/* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ - -typedef struct hwrm_fw_set_structured_data_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* count_of_headers is incorrect */ - #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT UINT32_C(0x1) - /* data improperly formatted */ - #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT UINT32_C(0x2) - /* unknown structure ID(s) */ - #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3) - #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID - uint8_t unused_0[7]; -} hwrm_fw_set_structured_data_cmd_err_t, *phwrm_fw_set_structured_data_cmd_err_t; +} hwrm_stat_ctx_query_output_t, *phwrm_stat_ctx_query_output_t; -/******************************* - * hwrm_fw_get_structured_data * - *******************************/ +/*************************** + * hwrm_stat_ext_ctx_query * + ***************************/ -/* hwrm_fw_get_structured_data_input (size:256b/32B) */ +/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ -typedef struct hwrm_fw_get_structured_data_input { +typedef struct hwrm_stat_ext_ctx_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56207,49 +59348,21 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* ID of the extended statistics context that is being queried. */ + uint32_t stat_ctx_id; + uint8_t flags; /* - * This is the host address where - * structured data will be copied to + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. */ - uint64_t dest_data_addr; - /* size of data in bytes */ - uint16_t data_len; - /* - * Structure_id is the id of the structure data requesting and count is a - * requested number of instances of this data requested. The actual number - * will be returned in count_of_headers - */ - uint16_t structure_id; - /* - * Subtype is an optional field used to specify additional information of the data - * being retrieved. For example, if data can be categorized as "live" vs "saved" - * then this field can be used to provide an indication of "saved" vs "live" data. - * Not all structured data supports subtypes and if they are supported then the - * structured data will specify the valid values. If structured data is requested - * that supports subtypes but no subtype is given then it is implementation specific - * what will be returned. Some structure data can support a subtype of "All" which - * would cause a list of structures to be returned for all supported subtypes. "All" - * is only used on the hwrm_get_structured_data command. - */ - uint16_t subtype; - #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_UNUSED UINT32_C(0x0) - #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_ALL UINT32_C(0xffff) - #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_ADMIN UINT32_C(0x100) - #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_PEER UINT32_C(0x101) - #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_OPERATIONAL UINT32_C(0x102) - #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_ADMIN UINT32_C(0x200) - #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_PEER UINT32_C(0x201) - #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_OPERATIONAL UINT32_C(0x202) - #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_HOST_OPERATIONAL UINT32_C(0x300) - #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_LAST HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_HOST_OPERATIONAL - /* Number of elements. This allows support of arrayed data */ - uint8_t count; - uint8_t unused_0; -} hwrm_fw_get_structured_data_input_t, *phwrm_fw_get_structured_data_input_t; + #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + uint8_t unused_0[3]; +} hwrm_stat_ext_ctx_query_input_t, *phwrm_stat_ext_ctx_query_input_t; -/* hwrm_fw_get_structured_data_output (size:128b/16B) */ +/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ -typedef struct hwrm_fw_get_structured_data_output { +typedef struct hwrm_stat_ext_ctx_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56258,46 +59371,69 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * a count of the number of Structured Data Headers in the data - * pointed by dest_data_addr. - */ - uint8_t hdr_cnt; - uint8_t unused_0[6]; + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of discarded packets on receive path */ + uint64_t rx_discard_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; + /* Number of discarded packets on transmit path */ + uint64_t tx_discard_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of TPA eligible packets */ + uint64_t rx_tpa_eligible_pkt; + /* Number of TPA eligible bytes */ + uint64_t rx_tpa_eligible_bytes; + /* Number of TPA packets */ + uint64_t rx_tpa_pkt; + /* Number of TPA bytes */ + uint64_t rx_tpa_bytes; + /* Number of TPA errors */ + uint64_t rx_tpa_errors; + /* Number of TPA events */ + uint64_t rx_tpa_events; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_get_structured_data_output_t, *phwrm_fw_get_structured_data_output_t; - -/* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ - -typedef struct hwrm_fw_get_structured_data_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* unknown structure ID(s) */ - #define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3) - #define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID - uint8_t unused_0[7]; -} hwrm_fw_get_structured_data_cmd_err_t, *phwrm_fw_get_structured_data_cmd_err_t; +} hwrm_stat_ext_ctx_query_output_t, *phwrm_stat_ext_ctx_query_output_t; -/******************* - * hwrm_fw_ipc_msg * - *******************/ +/*************************** + * hwrm_stat_ctx_eng_query * + ***************************/ -/* hwrm_fw_ipc_msg_input (size:320b/40B) */ +/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */ -typedef struct hwrm_fw_ipc_msg_input { +typedef struct hwrm_stat_ctx_eng_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56326,58 +59462,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the command_id field to be - * configured. - */ - #define HWRM_FW_IPC_MSG_INPUT_ENABLES_COMMAND_ID UINT32_C(0x1) - /* - * This bit must be '1' for the src_processor field to be - * configured. - */ - #define HWRM_FW_IPC_MSG_INPUT_ENABLES_SRC_PROCESSOR UINT32_C(0x2) - /* - * This bit must be '1' for the data_offset field to be - * configured. - */ - #define HWRM_FW_IPC_MSG_INPUT_ENABLES_DATA_OFFSET UINT32_C(0x4) - /* - * This bit must be '1' for the length field to be - * configured. - */ - #define HWRM_FW_IPC_MSG_INPUT_ENABLES_LENGTH UINT32_C(0x8) - /* Command ID */ - uint16_t command_id; - /* RoCE LAG message */ - #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_LAG UINT32_C(0x1) - /* Query information on PF mapping for x86 and MAIA. */ - #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_MHB_HOST UINT32_C(0x2) - #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_LAST HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_MHB_HOST - /* Source processor for this command. */ - uint8_t src_processor; - /* Chimp processor */ - #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_CFW UINT32_C(0x1) - /* BONO processor */ - #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_BONO UINT32_C(0x2) - /* APE processor */ - #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_APE UINT32_C(0x3) - /* KONG processor */ - #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_KONG UINT32_C(0x4) - #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_LAST HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_KONG - uint8_t unused_0; - /* Offset of the data in the source processor memory. */ - uint32_t data_offset; - /* Length of the data in source processor. */ - uint16_t length; - uint8_t unused_1[2]; - /* This is for storing FW opaque data. */ - uint64_t opaque; -} hwrm_fw_ipc_msg_input_t, *phwrm_fw_ipc_msg_input_t; + /* ID of the statistics context that is being queried. */ + uint32_t stat_ctx_id; + uint8_t unused_0[4]; +} hwrm_stat_ctx_eng_query_input_t, *phwrm_stat_ctx_eng_query_input_t; -/* hwrm_fw_ipc_msg_output (size:256b/32B) */ +/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */ -typedef struct hwrm_fw_ipc_msg_output { +typedef struct hwrm_stat_ctx_eng_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56386,28 +59478,66 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t msg_data_1; - uint32_t msg_data_2; - uint64_t reserved64; - uint8_t reserved48[7]; + /* + * Count of data bytes into the Engine. + * This includes any user supplied prefix, + * but does not include any predefined + * prefix data. + */ + uint64_t eng_bytes_in; + /* Count of data bytes out of the Engine. */ + uint64_t eng_bytes_out; + /* + * Count, in 4-byte (dword) units, of bytes + * that are input as auxiliary data. + * This includes the aux_cmd data. + */ + uint64_t aux_bytes_in; + /* + * Count, in 4-byte (dword) units, of bytes + * that are output as auxiliary data. + * This count is the buffer space for aux_data + * output provided in the RQE, not the actual + * aux_data written + */ + uint64_t aux_bytes_out; + /* Count of number of commands executed. */ + uint64_t commands; + /* + * Count of number of error commands. + * These are the commands with a + * non-zero status value. + */ + uint64_t error_commands; + /* + * Compression/Encryption Engine usage, + * the unit is count of clock cycles + */ + uint64_t cce_engine_usage; + /* + * De-Compression/De-cryption Engine usage, + * the unit is count of clock cycles + */ + uint64_t cdd_engine_usage; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_ipc_msg_output_t, *phwrm_fw_ipc_msg_output_t; +} hwrm_stat_ctx_eng_query_output_t, *phwrm_stat_ctx_eng_query_output_t; -/*********************** - * hwrm_fw_ipc_mailbox * - ***********************/ +/*************************** + * hwrm_stat_ctx_clr_stats * + ***************************/ -/* hwrm_fw_ipc_mailbox_input (size:256b/32B) */ +/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ -typedef struct hwrm_fw_ipc_mailbox_input { +typedef struct hwrm_stat_ctx_clr_stats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56436,23 +59566,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; - /* unused is 8 b */ - uint8_t unused; - /* asynchronous event to hosts. */ - uint8_t event_id; - /* PORT ID */ - uint8_t port_id; - /* event data1 of asynchronous event */ - uint32_t event_data1; - /* event data2 of asynchronous event */ - uint32_t event_data2; + /* ID of the statistics context that is being queried. */ + uint32_t stat_ctx_id; uint8_t unused_0[4]; -} hwrm_fw_ipc_mailbox_input_t, *phwrm_fw_ipc_mailbox_input_t; +} hwrm_stat_ctx_clr_stats_input_t, *phwrm_stat_ctx_clr_stats_input_t; -/* hwrm_fw_ipc_mailbox_output (size:128b/16B) */ +/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ -typedef struct hwrm_fw_ipc_mailbox_output { +typedef struct hwrm_stat_ctx_clr_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56464,38 +59585,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_ipc_mailbox_output_t, *phwrm_fw_ipc_mailbox_output_t; - -/* hwrm_fw_ipc_mailbox_cmd_err (size:64b/8B) */ - -typedef struct hwrm_fw_ipc_mailbox_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* invalid event */ - #define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID UINT32_C(0x3) - #define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_LAST HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID - uint8_t unused_0[7]; -} hwrm_fw_ipc_mailbox_cmd_err_t, *phwrm_fw_ipc_mailbox_cmd_err_t; +} hwrm_stat_ctx_clr_stats_output_t, *phwrm_stat_ctx_clr_stats_output_t; -/******************* - * hwrm_fw_ecn_cfg * - *******************/ +/******************** + * hwrm_pcie_qstats * + ********************/ -/* hwrm_fw_ecn_cfg_input (size:192b/24B) */ +/* hwrm_pcie_qstats_input (size:256b/32B) */ -typedef struct hwrm_fw_ecn_cfg_input { +typedef struct hwrm_pcie_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56524,25 +59629,23 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t flags; /* - * When this bit is '1', Explicit Congestion Notification (ECN) is - * enabled device-wide. When ECN is enabled on a multi-host system, - * it is enabled for all hosts. This setting takes effect - * immediately. When ECN is enabled, the firmware activates - * additional receive Class of Service (CoS) queues that are enabled - * for ECN marking and steers ECN-capable packets to those queues. - * This setting is not saved persistently. To enable ECN - * persistently, set NVM option 173, ENABLE_ECN. - * Setting this bit to '0' disables ECN immediately. + * The size of PCIe statistics block in bytes. + * Firmware will DMA the PCIe statistics to + * the host with this field size in the response. */ - #define HWRM_FW_ECN_CFG_INPUT_FLAGS_ENABLE_ECN UINT32_C(0x1) + uint16_t pcie_stat_size; uint8_t unused_0[6]; -} hwrm_fw_ecn_cfg_input_t, *phwrm_fw_ecn_cfg_input_t; + /* + * This is the host address where + * PCIe statistics will be stored + */ + uint64_t pcie_stat_host_addr; +} hwrm_pcie_qstats_input_t, *phwrm_pcie_qstats_input_t; -/* hwrm_fw_ecn_cfg_output (size:128b/16B) */ +/* hwrm_pcie_qstats_output (size:128b/16B) */ -typedef struct hwrm_fw_ecn_cfg_output { +typedef struct hwrm_pcie_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56551,25 +59654,64 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* The size of PCIe statistics block in bytes. */ + uint16_t pcie_stat_size; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_ecn_cfg_output_t, *phwrm_fw_ecn_cfg_output_t; +} hwrm_pcie_qstats_output_t, *phwrm_pcie_qstats_output_t; -/******************** - * hwrm_fw_ecn_qcfg * - ********************/ +/* PCIe Statistics Formats */ +/* pcie_ctx_hw_stats (size:768b/96B) */ + +typedef struct pcie_ctx_hw_stats { + /* Number of physical layer receiver errors */ + uint64_t pcie_pl_signal_integrity; + /* Number of DLLP CRC errors detected by Data Link Layer */ + uint64_t pcie_dl_signal_integrity; + /* + * Number of TLP LCRC and sequence number errors detected + * by Data Link Layer + */ + uint64_t pcie_tl_signal_integrity; + /* Number of times LTSSM entered Recovery state */ + uint64_t pcie_link_integrity; + /* Report number of TLP bits that have been transmitted in Mbps */ + uint64_t pcie_tx_traffic_rate; + /* Report number of TLP bits that have been received in Mbps */ + uint64_t pcie_rx_traffic_rate; + /* Number of DLLP bytes that have been transmitted */ + uint64_t pcie_tx_dllp_statistics; + /* Number of DLLP bytes that have been received */ + uint64_t pcie_rx_dllp_statistics; + /* + * Number of times spent in each phase of gen3 + * equalization + */ + uint64_t pcie_equalization_time; + /* Records the last 16 transitions of the LTSSM */ + uint32_t pcie_ltssm_histogram[4]; + /* + * Record the last 8 reasons on why LTSSM transitioned + * to Recovery + */ + uint64_t pcie_recovery_histogram; +} pcie_ctx_hw_stats_t, *ppcie_ctx_hw_stats_t; + +/**************************** + * hwrm_stat_generic_qstats * + ****************************/ -/* hwrm_fw_ecn_qcfg_input (size:128b/16B) */ +/* hwrm_stat_generic_qstats_input (size:256b/32B) */ -typedef struct hwrm_fw_ecn_qcfg_input { +typedef struct hwrm_stat_generic_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56598,11 +59740,32 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_fw_ecn_qcfg_input_t, *phwrm_fw_ecn_qcfg_input_t; + /* + * The size of the generic statistics buffer passed in the + * generic_stat_host_addr in bytes. + * Firmware will not exceed this size when it DMAs the + * statistics structure to the host. The actual DMA size + * will be returned in the response. + */ + uint16_t generic_stat_size; + uint8_t flags; + /* + * The bit should be set to 1 when request is for the counter mask + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_STAT_GENERIC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + uint8_t unused_0[5]; + /* + * This is the host address where + * generic statistics will be stored + */ + uint64_t generic_stat_host_addr; +} hwrm_stat_generic_qstats_input_t, *phwrm_stat_generic_qstats_input_t; -/* hwrm_fw_ecn_qcfg_output (size:128b/16B) */ +/* hwrm_stat_generic_qstats_output (size:128b/16B) */ -typedef struct hwrm_fw_ecn_qcfg_output { +typedef struct hwrm_stat_generic_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56611,28 +59774,131 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint16_t flags; - /* When this bit is '1', ECN is enabled device-wide. */ - #define HWRM_FW_ECN_QCFG_OUTPUT_FLAGS_ENABLE_ECN UINT32_C(0x1) + /* The size of Generic Statistics block in bytes. */ + uint16_t generic_stat_size; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_fw_ecn_qcfg_output_t, *phwrm_fw_ecn_qcfg_output_t; +} hwrm_stat_generic_qstats_output_t, *phwrm_stat_generic_qstats_output_t; -/************************ - * hwrm_fw_health_check * - ************************/ +/* Generic Statistic Format */ +/* generic_sw_hw_stats (size:1472b/184B) */ + +typedef struct generic_sw_hw_stats { + /* + * This is the number of TLP bytes that have been transmitted for + * the caller PF. + */ + uint64_t pcie_statistics_tx_tlp; + /* + * This is the number of TLP bytes that have been received + * for the caller PF. + */ + uint64_t pcie_statistics_rx_tlp; + /* Posted Header Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_hdr_posted; + /* Non-posted Header Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_hdr_nonposted; + /* Completion Header Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_hdr_cmpl; + /* Posted Data Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_data_posted; + /* Non-Posted Data Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_data_nonposted; + /* Completion Data Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_data_cmpl; + /* + * Available Non-posted credit for target flow control reads or + * config for the caller PF. + */ + uint64_t pcie_credit_fc_tgt_nonposted; + /* + * Available posted data credit for target flow control writes + * for the caller PF. + */ + uint64_t pcie_credit_fc_tgt_data_posted; + /* + * Available posted header credit for target flow control writes + * for the caller PF. + */ + uint64_t pcie_credit_fc_tgt_hdr_posted; + /* Available completion flow control header credits for the caller PF. */ + uint64_t pcie_credit_fc_cmpl_hdr_posted; + /* Available completion flow control data credits. */ + uint64_t pcie_credit_fc_cmpl_data_posted; + /* + * Displays Time information of the longest completion time from any of + * the 4 tags for the caller PF. The unit of time recorded is in + * microseconds. + */ + uint64_t pcie_cmpl_longest; + /* + * Displays Time information of the shortest completion time from any + * of the 4 tags for the caller PF. The unit of time recorded is in + * microseconds. + */ + uint64_t pcie_cmpl_shortest; + /* + * This field contains the total number of CFCQ 'misses' observed for + * all the PF's. + */ + uint64_t cache_miss_count_cfcq; + /* + * This field contains the total number of CFCS 'misses' observed for + * all the PF's. + */ + uint64_t cache_miss_count_cfcs; + /* + * This field contains the total number of CFCC 'misses' observed for + * all the PF's. + */ + uint64_t cache_miss_count_cfcc; + /* + * This field contains the total number of CFCM 'misses' observed + * for all the PF's. + */ + uint64_t cache_miss_count_cfcm; + /* + * Total number of Doorbell messages dropped from the DB FIFO. + * This counter is only applicable for devices that support + * the hardware based doorbell drop recovery feature. + */ + uint64_t hw_db_recov_dbs_dropped; + /* + * Total number of doorbell drops serviced. + * This counter is only applicable for devices that support + * the hardware based doorbell drop recovery feature. + */ + uint64_t hw_db_recov_drops_serviced; + /* + * Total number of dropped doorbells recovered. + * This counter is only applicable for devices that support + * the hardware based doorbell drop recovery feature. + */ + uint64_t hw_db_recov_dbs_recovered; + /* + * Total number of out of order doorbell messages dropped. + * This counter is only applicable for devices that support + * the hardware based doorbell drop recovery feature. + */ + uint64_t hw_db_recov_oo_drop_count; +} generic_sw_hw_stats_t, *pgeneric_sw_hw_stats_t; +/***************************** + * hwrm_stat_db_error_qstats * + *****************************/ -/* hwrm_fw_health_check_input (size:128b/16B) */ -typedef struct hwrm_fw_health_check_input { +/* hwrm_stat_db_error_qstats_input (size:128b/16B) */ + +typedef struct hwrm_stat_db_error_qstats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56661,11 +59927,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_fw_health_check_input_t, *phwrm_fw_health_check_input_t; +} hwrm_stat_db_error_qstats_input_t, *phwrm_stat_db_error_qstats_input_t; -/* hwrm_fw_health_check_output (size:128b/16B) */ +/* hwrm_stat_db_error_qstats_output (size:320b/40B) */ -typedef struct hwrm_fw_health_check_output { +typedef struct hwrm_stat_db_error_qstats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56674,93 +59940,58 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t fw_status; /* - * This bit is '0' if the primary SBI was used this boot, - * or '1' if the secondary SBI was used. + * Specifies count of doorbells dropped due to RoCE SQs or L2 + * Tx Rings being in invalid state. */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SBI_BOOTED UINT32_C(0x1) + uint32_t tx_db_drop_invalid_qp_state; /* - * This bit is '0' if the primary and secondary SBI images - * match, or '1' if they do not match. + * Specifies count of doorbells dropped due to RoCE RQs/SRQs or + * L2 Rx Rings being used in invalid state. */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SBI_MISMATCH UINT32_C(0x2) + uint32_t rx_db_drop_invalid_rq_state; /* - * This bit is '0' if the primary SRT was used this boot, - * or '1' if the secondary SRT was used. + * Specifies count of doorbells dropped for any doorbell type + * due to formatting errors such as illegal doorbell message + * type, index out of range etc. */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT_BOOTED UINT32_C(0x4) + uint32_t tx_db_drop_format_error; /* - * This bit is '0' if the primary and secondary SRT images - * match, or '1' if they do not match. - */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT_MISMATCH UINT32_C(0x8) - /* - * This bit is '0' if the primary CRT (or second stage SRT) - * was used this boot, or '1' if the secondary CRT (or - * second stage SRT) was used. - */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT_BOOTED UINT32_C(0x10) - /* - * This bit is '0' if the primary and secondary CRT images - * (or second stage SRT images) match, or '1' if they do not - * match. - */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT_MISMATCH UINT32_C(0x20) - /* - * This bit is '0' if the second stage RT image is a CRT, - * or '1' if the second stage RT image is an SRT. - */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SECOND_RT UINT32_C(0x40) - /* - * This bit is '0' if the image was loaded from flash, - * or '1' if the image was fastbooted. - */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_FASTBOOTED UINT32_C(0x80) - /* - * This bit is '0' if the primary dir_hdr was used to locate - * the firmware, or '1' if the secondary dir_hdr was used. - */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_DIR_HDR_BOOTED UINT32_C(0x100) - /* - * This bit is '0' if the primary and secondary dir_hdr match, - * or '1' if they do not match. - */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_DIR_HDR_MISMATCH UINT32_C(0x200) - /* - * This bit is '0' if the Master Boot Record is in good condition, - * or '1' if it is corrupted. + * Specifies count of express mode doorbells dropped for any + * doorbell type due to error conditions such as DPI check, + * context load error etc. */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_MBR_CORRUPT UINT32_C(0x400) + uint32_t express_db_dropped_misc_error; /* - * This bit is '0' if the configuration is in good condition, - * or '1' if it is corrupted. + * Specifies count of express mode doorbells dropped due to + * RoCE SQ overflow. */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CFG_MISMATCH UINT32_C(0x800) + uint32_t express_db_dropped_sq_overflow; /* - * This bit is '0' if both FRU entries match, - * or '1' if they do not match. + * Specifies count of express mode doorbells dropped due to + * RoCE RQ overflow. */ - #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_FRU_MISMATCH UINT32_C(0x1000) - uint8_t unused_0[3]; + uint32_t express_db_dropped_rq_overflow; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_fw_health_check_output_t, *phwrm_fw_health_check_output_t; +} hwrm_stat_db_error_qstats_output_t, *phwrm_stat_db_error_qstats_output_t; -/*************************** - * hwrm_fw_livepatch_query * - ***************************/ +/***************** + * hwrm_fw_reset * + *****************/ -/* hwrm_fw_livepatch_query_input (size:192b/24B) */ +/* hwrm_fw_reset_input (size:192b/24B) */ -typedef struct hwrm_fw_livepatch_query_input { +typedef struct hwrm_fw_reset_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -56789,132 +60020,82 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware target to which to apply the livepatch query */ - uint8_t fw_target; - /* Common firmware livepatch query. */ - #define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_COMMON_FW UINT32_C(0x1) - /* Secure firmware livepatch query. */ - #define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_SECURE_FW UINT32_C(0x2) - #define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_LAST HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_SECURE_FW - uint8_t unused_0[7]; -} hwrm_fw_livepatch_query_input_t, *phwrm_fw_livepatch_query_input_t; - -/* hwrm_fw_livepatch_query_output (size:640b/80B) */ - -typedef struct hwrm_fw_livepatch_query_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * This field represents the patch version string of the NVM installed - * livepatch. (ASCII chars with NULL at the end). - */ - char install_ver[32]; - /* - * This field represents the patch version string of the active - * livepatch. (ASCII chars with NULL at the end). - */ - char active_ver[32]; - uint16_t status_flags; - /* This bit is '1' if a livepatch image is installed to NVM. */ - #define HWRM_FW_LIVEPATCH_QUERY_OUTPUT_STATUS_FLAGS_INSTALL UINT32_C(0x1) - /* This bit is '1' if firmware livepatch is active. */ - #define HWRM_FW_LIVEPATCH_QUERY_OUTPUT_STATUS_FLAGS_ACTIVE UINT32_C(0x2) - uint8_t unused_0[5]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} hwrm_fw_livepatch_query_output_t, *phwrm_fw_livepatch_query_output_t; - -/********************* - * hwrm_fw_livepatch * - *********************/ - - -/* hwrm_fw_livepatch_input (size:256b/32B) */ - -typedef struct hwrm_fw_livepatch_input { - /* The HWRM command request type. */ - uint16_t req_type; + /* Type of embedded processor. */ + uint8_t embedded_proc_type; + /* Boot Processor */ + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0) + /* Management Processor */ + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1) + /* Network control processor */ + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2) + /* RoCE control processor */ + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Host (in multi-host environment): This is only valid if requester + * is IPC. Reinit host hardware resources and PCIe. */ - uint16_t cmpl_ring; + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * AP processor complex (in multi-host environment). + * Use host_idx to control which core is reset. */ - uint16_t seq_id; + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP UINT32_C(0x5) + /* Reset all blocks of the chip (including all processors) */ + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP UINT32_C(0x6) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Host (in multi-host environment): This is only valid if requester + * is IPC. Reinit host hardware resources. */ - uint16_t target_id; + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT UINT32_C(0x7) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * Activate firmware that has been programmed to NVM. The + * activation is done in an impactless manner as part of the scheme + * where hwrm_fw_state_backup precedes the call, and + * hwrm_fw_state_restore follows it. Before this call returns, FW + * status is set to a non-0x8000 value to disambiguate reset pending + * from reset complete. The reset process begins after this call + * returns to ensure this HWRM has completed before reset begins. */ - uint64_t resp_addr; - /* Livepatch operation */ - uint8_t opcode; + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION UINT32_C(0x8) + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION + /* Type of self reset. */ + uint8_t selfrst_status; + /* No Self Reset */ + #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0) + /* Self Reset as soon as possible to do so safely */ + #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1) + /* Self Reset on PCIe Reset */ + #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2) + /* Self Reset immediately after notification to all clients. */ + #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE UINT32_C(0x3) + #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE /* - * Activate a livepatch that is NVM installed or via direct load - * from host memory. Activate will authenticate a signed patch, - * verify the patch version for compatibility and apply the - * livepatch to existing firmware at run-time. + * Indicate which host is being reset. 0 means first host. + * Only valid when embedded_proc_type is host in multihost + * environment */ - #define HWRM_FW_LIVEPATCH_INPUT_OPCODE_ACTIVATE UINT32_C(0x1) + uint8_t host_idx; + uint8_t flags; /* - * Deactivate a livepatch and restore to the original firmware - * operation state. + * When this bit is '1', then the core firmware initiates + * the reset only after graceful shut down of all registered + * instances. If not, the device will continue with the existing + * firmware. */ - #define HWRM_FW_LIVEPATCH_INPUT_OPCODE_DEACTIVATE UINT32_C(0x2) - #define HWRM_FW_LIVEPATCH_INPUT_OPCODE_LAST HWRM_FW_LIVEPATCH_INPUT_OPCODE_DEACTIVATE - /* Firmware target to which to apply the livepatch operation. */ - uint8_t fw_target; - /* Common firmware livepatch. */ - #define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_COMMON_FW UINT32_C(0x1) - /* Secure firmware livepatch. */ - #define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_SECURE_FW UINT32_C(0x2) - #define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_LAST HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_SECURE_FW - /* Load method for livepatch. */ - uint8_t loadtype; - /* Load a livepatch currently installed on NVM. */ - #define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_NVM_INSTALL UINT32_C(0x1) + #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1) /* - * Load a livepatch directly from host memory. The livepatch image - * is available at host_addr. + * When this bit is '1', then drivers will be notified that + * that the purpose of the reset was a firmware activation. + * Such notifications are delivered via the RESET_NOTIFY async + * event (reason_code: fw_activation). */ - #define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_MEMORY_DIRECT UINT32_C(0x2) - #define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_LAST HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_MEMORY_DIRECT - /* Reserved for future use. */ - uint8_t flags; - /* Length of livepatch image for memory direct loading, in bytes. */ - uint32_t patch_len; - /* 64-bit Host address of livepatch image for memory direct loading. */ - uint64_t host_addr; -} hwrm_fw_livepatch_input_t, *phwrm_fw_livepatch_input_t; + #define HWRM_FW_RESET_INPUT_FLAGS_FW_ACTIVATION UINT32_C(0x2) + uint8_t unused_0[4]; +} hwrm_fw_reset_input_t, *phwrm_fw_reset_input_t; -/* hwrm_fw_livepatch_output (size:128b/16B) */ +/* hwrm_fw_reset_output (size:128b/16B) */ -typedef struct hwrm_fw_livepatch_output { +typedef struct hwrm_fw_reset_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -56923,60 +60104,36 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Type of self reset. */ + uint8_t selfrst_status; + /* No Self Reset */ + #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0) + /* Self Reset as soon as possible to do so safely */ + #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1) + /* Self Reset on PCIe Reset */ + #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2) + /* Self Reset immediately after notification to all clients. */ + #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE UINT32_C(0x3) + #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_livepatch_output_t, *phwrm_fw_livepatch_output_t; - -/* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ - -typedef struct hwrm_fw_livepatch_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error. */ - #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* Opcode invalid. */ - #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE UINT32_C(0x1) - /* Firmware target invalid. */ - #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET UINT32_C(0x2) - /* Livepatch operation not supported. */ - #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED UINT32_C(0x3) - /* Livepatch image is not installed in NVRAM. */ - #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED UINT32_C(0x4) - /* Deactivate failed. Firmware is not currently patched. */ - #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED UINT32_C(0x5) - /* Authentication of a signed livepatch failed. */ - #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL UINT32_C(0x6) - /* Livepatch header check failed. Patch incompatible. */ - #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER UINT32_C(0x7) - /* Livepatch size incompatible. */ - #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE UINT32_C(0x8) - /* - * Activate failed. Firmware has already been patched. Deactivate - * existing livepatch before proceeding. - */ - #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED UINT32_C(0x9) - #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_LAST HWRM_FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED - uint8_t unused_0[7]; -} hwrm_fw_livepatch_cmd_err_t, *phwrm_fw_livepatch_cmd_err_t; +} hwrm_fw_reset_output_t, *phwrm_fw_reset_output_t; -/**************** - * hwrm_fw_sync * - ****************/ +/******************* + * hwrm_fw_qstatus * + *******************/ -/* hwrm_fw_sync_input (size:192b/24B) */ +/* hwrm_fw_qstatus_input (size:192b/24B) */ -typedef struct hwrm_fw_sync_input { +typedef struct hwrm_fw_qstatus_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57005,66 +60162,35 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t sync_action; - /* - * If action is '1' (sync) and this bit is set, the SBI - * images will be synchronized, copying from the instance - * used for boot to the other instance, if they currently - * do not match. - */ - #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SBI UINT32_C(0x1) - /* - * If action is '1' (sync) and this bit is set, the SRT - * images will be synchronized, copying from the instance - * used for boot to the other instance, if they currently - * do not match. - */ - #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SRT UINT32_C(0x2) - /* - * If action is '1' (sync) and this bit is set, the CRT - * images will be synchronized (or second stage SRT if that - * is used in place of CRT), copying from the instance - * used for boot to the other instance, if they currently - * do not match. - */ - #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CRT UINT32_C(0x4) - /* - * If action is '1' (sync) and this bit is set, the dir_hdr - * partition will be synchronized, copying from the instance - * used for boot to the other instance, if they currently - * do not match. - */ - #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_DIR_HDR UINT32_C(0x8) - /* - * If action is '1' (sync) and this bit is set, the MBR - * will be erased and reprogrammed with valid content. - */ - #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_WRITE_MBR UINT32_C(0x10) - /* - * If action is '1' (sync) and this bit is set, the - * configuration will be resynced or repaired as needed. - */ - #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CFG UINT32_C(0x20) + /* Type of embedded processor. */ + uint8_t embedded_proc_type; + /* Boot Processor */ + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0) + /* Management Processor */ + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1) + /* Network control processor */ + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2) + /* RoCE control processor */ + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3) /* - * If action is '1' (sync) and this bit is set, the - * FRU in NVM file will be synchronized, copying the active - * FRU to the backup FRU. + * Host (in multi-host environment): This is only valid if requester + * is IPC */ - #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_FRU UINT32_C(0x40) + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4) /* - * A value of '1' instructs the firmware to perform an image - * synchronization of the firmware types denoted by the - * sync_sbi, sync_srt, sync_crt bits. A value of '0' just - * requests the status for the previously requested sync - * operation. + * AP processor complex (in multi-host environment). Use host_idx to + * control which core is reset */ - #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_ACTION UINT32_C(0x80000000) - uint8_t unused_0[4]; -} hwrm_fw_sync_input_t, *phwrm_fw_sync_input_t; + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_AP UINT32_C(0x5) + /* Reset all blocks of the chip (including all processors) */ + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_CHIP UINT32_C(0x6) + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_LAST HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_CHIP + uint8_t unused_0[7]; +} hwrm_fw_qstatus_input_t, *phwrm_fw_qstatus_input_t; -/* hwrm_fw_sync_output (size:128b/16B) */ +/* hwrm_fw_qstatus_output (size:128b/16B) */ -typedef struct hwrm_fw_sync_output { +typedef struct hwrm_fw_qstatus_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57073,55 +60199,51 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t sync_status; - /* This bit field indicates the error if 'sync_err' bit is set. */ - #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_MASK UINT32_C(0xff) - #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_SFT 0 - /* Success, no error */ - #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0) - /* - * A previously requested synchronization command is still - * in progress. - */ - #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_IN_PROGRESS UINT32_C(0x1) - /* An NVRAM operation has timed out. */ - #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_TIMEOUT UINT32_C(0x2) - /* General NVRAM error code. */ - #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_GENERAL UINT32_C(0x3) - #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_LAST HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_GENERAL - /* - * This bit is '1' if the syncronization request has completed - * with an error; the 'err_code' field can be used to obtain - * information about error type. - */ - #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_SYNC_ERR UINT32_C(0x40000000) + /* Type of self reset. */ + uint8_t selfrst_status; + /* No Self Reset */ + #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0) + /* Self Reset as soon as possible to do so safely */ + #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1) + /* Self Reset on PCIe Reset */ + #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2) + /* NIC power cycle (system cold boot) required */ + #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPOWER UINT32_C(0x3) + #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_LAST HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPOWER /* - * This bit is '0' if the previously requested synchronization - * command is still in progress, or '1' if the previously - * requested sync command has completed. If '1', the 'sync_err' - * field will indicate if it completed successfully or with - * an error. + * The action needed to apply any pend nvm option changes. + * If multiple options have been set the highest level + * action is reported. */ - #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_SYNC_COMPLETE UINT32_C(0x80000000) - uint8_t unused_0[3]; + uint8_t nvm_option_action_status; + /* No Action needed */ + #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE UINT32_C(0x0) + /* Hot reset needed to apply nvm options */ + #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET UINT32_C(0x1) + /* Warm boot needed to apply nvm options */ + #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT UINT32_C(0x2) + /* Cold boot needed to apply nvm options */ + #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT UINT32_C(0x3) + #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_LAST HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_sync_output_t, *phwrm_fw_sync_output_t; +} hwrm_fw_qstatus_output_t, *phwrm_fw_qstatus_output_t; -/*********************** - * hwrm_fw_state_qcaps * - ***********************/ +/******************** + * hwrm_fw_set_time * + ********************/ -/* hwrm_fw_state_qcaps_input (size:128b/16B) */ +/* hwrm_fw_set_time_input (size:256b/32B) */ -typedef struct hwrm_fw_state_qcaps_input { +typedef struct hwrm_fw_set_time_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57150,11 +60272,37 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_fw_state_qcaps_input_t, *phwrm_fw_state_qcaps_input_t; + /* Current year */ + uint16_t year; + /* Date/time is not known */ + #define HWRM_FW_SET_TIME_INPUT_YEAR_UNKNOWN UINT32_C(0x0) + #define HWRM_FW_SET_TIME_INPUT_YEAR_LAST HWRM_FW_SET_TIME_INPUT_YEAR_UNKNOWN + /* Current month of year (1-12) */ + uint8_t month; + /* Current day of month (1-31) */ + uint8_t day; + /* Current hour (0-23) */ + uint8_t hour; + /* Current minute (0-59) */ + uint8_t minute; + /* Current second (0-59) */ + uint8_t second; + uint8_t unused_0; + /* Current millisecond (0-999) */ + uint16_t millisecond; + /* Minutes east of UTC, 0xffff if TZ is not known */ + int16_t zone; + /* Time zone is Coordinated Universal Time (UTC) */ + #define HWRM_FW_SET_TIME_INPUT_ZONE_UTC 0 + /* Time zone is not known */ + #define HWRM_FW_SET_TIME_INPUT_ZONE_UNKNOWN 65535 + #define HWRM_FW_SET_TIME_INPUT_ZONE_LAST HWRM_FW_SET_TIME_INPUT_ZONE_UNKNOWN + uint8_t unused_1[4]; +} hwrm_fw_set_time_input_t, *phwrm_fw_set_time_input_t; -/* hwrm_fw_state_qcaps_output (size:256b/32B) */ +/* hwrm_fw_set_time_output (size:128b/16B) */ -typedef struct hwrm_fw_state_qcaps_output { +typedef struct hwrm_fw_set_time_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57163,66 +60311,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This field indicates the size in bytes required by host backup - * memory. Host software should allocate memory according to this - * size requirement and pass the allocated memory to the - * HWRM_FW_STATE_BACKUP and HWRM_FW_STATE_RESTORE commands in the form - * of PBL data as specified in those commands. - */ - uint32_t backup_memory; - /* - * This field indicates the max time in milliseconds that firmware - * waits for quiesce to complete. Firmware indicates successful - * quiesce completion if the quiesce operation completes within this - * timeout. If firmware is still waiting for the quiesce operation - * to complete when this timeout is reached, firmware stops waiting - * (without canceling any quiesce action such as pausing or - * clearing meter profiles) and indicates a timeout status result - * via NQE completion notification. This timeout value may also be - * used by the driver to know the max time to wait for any NQE - * notification response to the HWRM_FW_STATE_QUIESCE command. After - * a timeout, the driver may elect to invoke HWRM_FW_STATE_QUIESCE - * again to keep trying or to invoke HWRM_FW_STATE_UNQUIESCE to - * revert the operation. Since there is no identifier correlating - * each HWRM_FW_STATE_QUIESCE command with its NQE response, it is - * important for the driver to wait for the NQE response before - * issuing a subsequent HWRM_FW_STATE_QUIESCE command. - */ - uint32_t quiesce_timeout; - /* - * This field indicates time in milliseconds that the driver should - * wait after return from HWRM_FW_RESET to begin polling the device - * for status 0x8000. - */ - uint32_t fw_status_blackout; - /* - * This field indicates a max time for firmware to poll for status - * 0x8000 before assuming a reset failure occurred. This time does - * not include fw_status_blackout time which would immediately precede - * this wait. - */ - uint32_t fw_status_max_wait; - uint8_t unused_0[4]; - uint8_t unused_1[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_state_qcaps_output_t, *phwrm_fw_state_qcaps_output_t; +} hwrm_fw_set_time_output_t, *phwrm_fw_set_time_output_t; -/************************* - * hwrm_fw_state_quiesce * - *************************/ +/******************** + * hwrm_fw_get_time * + ********************/ -/* hwrm_fw_state_quiesce_input (size:192b/24B) */ +/* hwrm_fw_get_time_input (size:128b/16B) */ -typedef struct hwrm_fw_state_quiesce_input { +typedef struct hwrm_fw_get_time_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57251,27 +60358,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; - /* - * Setting this bit to '1', indicates impactless firmware update - * is in a recovery mode where hardware is in an error state and - * where recovery is desired with reasonably minimal impact to - * connected clients. The quiesce operation may require separate - * steps to handle quiescing when hardware is in a hung or locked - * state. For example, quiesce via draining may not be possible - * depending on the type of error. This flag's state would be kept - * in firmware if recovery-specific steps are also needed for the - * HWRM_FW_STATE_BACKUP. Note this option is available only for - * specific recovery scenarios and may not be operational across - * all controllers. - */ - #define HWRM_FW_STATE_QUIESCE_INPUT_FLAGS_ERROR_RECOVERY UINT32_C(0x1) - uint8_t unused_0[7]; -} hwrm_fw_state_quiesce_input_t, *phwrm_fw_state_quiesce_input_t; +} hwrm_fw_get_time_input_t, *phwrm_fw_get_time_input_t; -/* hwrm_fw_state_quiesce_output (size:192b/24B) */ +/* hwrm_fw_get_time_output (size:192b/24B) */ -typedef struct hwrm_fw_state_quiesce_output { +typedef struct hwrm_fw_get_time_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57280,33 +60371,512 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t quiesce_status; + /* Current year */ + uint16_t year; + /* Date/time is not known */ + #define HWRM_FW_GET_TIME_OUTPUT_YEAR_UNKNOWN UINT32_C(0x0) + #define HWRM_FW_GET_TIME_OUTPUT_YEAR_LAST HWRM_FW_GET_TIME_OUTPUT_YEAR_UNKNOWN + /* Current month of year (1-12) */ + uint8_t month; + /* Current day of month (1-31) */ + uint8_t day; + /* Current hour (0-23) */ + uint8_t hour; + /* Current minute (0-59) */ + uint8_t minute; + /* Current second (0-59) */ + uint8_t second; + uint8_t unused_0; + /* Current millisecond (0-999) */ + uint16_t millisecond; + /* Minutes east of UTC, 0xffff if TZ is not known */ + int16_t zone; + /* Time zone is Coordinated Universal Time (UTC) */ + #define HWRM_FW_GET_TIME_OUTPUT_ZONE_UTC 0 + /* Time zone is not known */ + #define HWRM_FW_GET_TIME_OUTPUT_ZONE_UNKNOWN 65535 + #define HWRM_FW_GET_TIME_OUTPUT_ZONE_LAST HWRM_FW_GET_TIME_OUTPUT_ZONE_UNKNOWN + uint8_t unused_1[3]; /* - * This bit is '1' if the quiesce request has been successfully - * initiated. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_FW_STATE_QUIESCE_OUTPUT_QUIESCE_STATUS_INITIATED UINT32_C(0x80000000) + uint8_t valid; +} hwrm_fw_get_time_output_t, *phwrm_fw_get_time_output_t; + +/* hwrm_struct_hdr (size:128b/16B) */ + +typedef struct hwrm_struct_hdr { + /* This value indicates the structured data ID. */ + uint16_t struct_id; + /* LLDP configuration structured data ID. */ + #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_CFG UINT32_C(0x41b) + /* DCBX ETS configuration structured data ID. */ + #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_ETS UINT32_C(0x41d) + /* DCBX PFC configuration structured data ID. */ + #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_PFC UINT32_C(0x41f) + /* DCBX APP configuration structured data ID. */ + #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_APP UINT32_C(0x421) + /* DCBX state configuration structured data ID for all DCBX features. */ + #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE UINT32_C(0x422) + /* + * LLDP generic structured data ID. This is used with + * GET_STRUCTURED_DATA only. + */ + #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_GENERIC UINT32_C(0x424) + /* + * LLDP device structured data ID. This is used with + * GET_STRUCTURED_DATA only. + */ + #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_DEVICE UINT32_C(0x426) + /* Power Backup info */ + #define HWRM_STRUCT_HDR_STRUCT_ID_POWER_BKUP UINT32_C(0x427) + /* reserved for AFM usage. */ + #define HWRM_STRUCT_HDR_STRUCT_ID_AFM_OPAQUE UINT32_C(0x1) + /* Port description. */ + #define HWRM_STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION UINT32_C(0xa) + /* RSSv2 Configuration. */ + #define HWRM_STRUCT_HDR_STRUCT_ID_RSS_V2 UINT32_C(0x64) + /* MSI-X vectors per VF table. */ + #define HWRM_STRUCT_HDR_STRUCT_ID_MSIX_PER_VF UINT32_C(0xc8) + #define HWRM_STRUCT_HDR_STRUCT_ID_LAST HWRM_STRUCT_HDR_STRUCT_ID_MSIX_PER_VF + /* This value indicates the length of structured data. */ + uint16_t len; + /* This value indicates the version of structured data. */ + uint8_t version; + /* This value indicates the number of structured data elements. */ + uint8_t count; + /* This value indicates the subtype. */ + uint16_t subtype; + /* + * This value indicates the count of 64-bit values that point to the next + * header. A value of 0 means that this is the last element. The value is + * a count of 64-bit words from the beginning of the current header. + */ + uint16_t next_offset; + /* This value indicates this is the last element */ + #define HWRM_STRUCT_HDR_NEXT_OFFSET_LAST UINT32_C(0x0) + uint8_t unused_0[6]; +} hwrm_struct_hdr_t, *phwrm_struct_hdr_t; + +/* hwrm_struct_data_dcbx_ets (size:256b/32B) */ + +typedef struct hwrm_struct_data_dcbx_ets { + /* + * This field indicates if this configuration is ETS recommendation or + * ETS configuration. A value 1 means it is ETS configuration, A value of + * 2 means it is a ETS recommendation. + */ + uint8_t destination; + /* ETS configuration */ + #define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_CONFIGURATION UINT32_C(0x1) + /* ETS recommendation */ + #define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION UINT32_C(0x2) + #define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_LAST HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION + /* This value indicates maximum ETS TCs supported. */ + uint8_t max_tcs; + /* unused. */ + uint16_t unused1; + /* ETS priority 0 to TC map. */ + uint8_t pri0_to_tc_map; + /* ETS priority 1 to TC map. */ + uint8_t pri1_to_tc_map; + /* ETS priority 2 to TC map. */ + uint8_t pri2_to_tc_map; + /* ETS priority 3 to TC map. */ + uint8_t pri3_to_tc_map; + /* ETS priority 4 to TC map. */ + uint8_t pri4_to_tc_map; + /* ETS priority 5 to TC map. */ + uint8_t pri5_to_tc_map; + /* ETS priority 6 to TC map. */ + uint8_t pri6_to_tc_map; + /* ETS priority 7 to TC map. */ + uint8_t pri7_to_tc_map; + /* ETS TC 0 to bandwidth map. */ + uint8_t tc0_to_bw_map; + /* ETS TC 1 to bandwidth map. */ + uint8_t tc1_to_bw_map; + /* ETS TC 2 to bandwidth map. */ + uint8_t tc2_to_bw_map; + /* ETS TC 3 to bandwidth map. */ + uint8_t tc3_to_bw_map; + /* ETS TC 4 to bandwidth map. */ + uint8_t tc4_to_bw_map; + /* ETS TC 5 to bandwidth map. */ + uint8_t tc5_to_bw_map; + /* ETS TC 6 to bandwidth map. */ + uint8_t tc6_to_bw_map; + /* ETS TC 7 to bandwidth map. */ + uint8_t tc7_to_bw_map; + /* ETS TC 0 to TSA map. */ + uint8_t tc0_to_tsa_map; + /* strict priority */ + #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_SP UINT32_C(0x0) + /* credit based shaper */ + #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_CBS UINT32_C(0x1) + /* ETS */ + #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_ETS UINT32_C(0x2) + /* vendor specific */ + #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC UINT32_C(0xff) + #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_LAST HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC + /* ETS TC 1 to TSA map. */ + uint8_t tc1_to_tsa_map; + /* ETS TC 2 to TSA map. */ + uint8_t tc2_to_tsa_map; + /* ETS TC 3 to TSA map. */ + uint8_t tc3_to_tsa_map; + /* ETS TC 4 to TSA map. */ + uint8_t tc4_to_tsa_map; + /* ETS TC 5 to TSA map. */ + uint8_t tc5_to_tsa_map; + /* ETS TC 6 to TSA map. */ + uint8_t tc6_to_tsa_map; + /* ETS TC 7 to TSA map. */ + uint8_t tc7_to_tsa_map; uint8_t unused_0[4]; - uint8_t unused_1[7]; +} hwrm_struct_data_dcbx_ets_t, *phwrm_struct_data_dcbx_ets_t; + +/* hwrm_struct_data_dcbx_pfc (size:64b/8B) */ + +typedef struct hwrm_struct_data_dcbx_pfc { /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' to - * indicate that the output has been completely written. When - * writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * This field indicates PFC priority bit map. A value of '0' indicates + * PFC is disabled. A value of '1' indicates PFC is enabled on that + * priority. + */ + uint8_t pfc_priority_bitmap; + /* + * This field indicates max PFC TCs supported. Each PFC TC will map to + * a lossless CoS queue. + */ + uint8_t max_pfc_tcs; + /* + * This field indicates if MACSec bypass capability is enabled. A value + * of '1' indicates MBC is enabled. A value of '0' indicates MBC is + * disabled. + */ + uint8_t mbc; + uint8_t unused_0[5]; +} hwrm_struct_data_dcbx_pfc_t, *phwrm_struct_data_dcbx_pfc_t; + +/* hwrm_struct_data_dcbx_app (size:64b/8B) */ + +typedef struct hwrm_struct_data_dcbx_app { + /* + * This field indicates the protocol identifier. This should be specified + * in big endian format. */ + uint16_t protocol_id; + /* + * This field indicates the protocol selector. The valid values are + * mentioned below. + */ + uint8_t protocol_selector; + /* ether type */ + #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE UINT32_C(0x1) + /* TCP port */ + #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT UINT32_C(0x2) + /* UDP port */ + #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT UINT32_C(0x3) + /* TCP & UDP port */ + #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT UINT32_C(0x4) + #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT + /* This field indicates application priority. */ + uint8_t priority; + /* This field indicates this entry is valid. */ uint8_t valid; -} hwrm_fw_state_quiesce_output_t, *phwrm_fw_state_quiesce_output_t; + uint8_t unused_0[3]; +} hwrm_struct_data_dcbx_app_t, *phwrm_struct_data_dcbx_app_t; -/*************************** - * hwrm_fw_state_unquiesce * - ***************************/ +/* hwrm_struct_data_dcbx_feature_state (size:64b/8B) */ + +typedef struct hwrm_struct_data_dcbx_feature_state { + /* DCBX mode - IEEE or CEE. This is read only field. */ + uint8_t dcbx_mode; + /* DCBX disabled mode. */ + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_DISABLED UINT32_C(0x0) + /* DCBX IEEE mode. */ + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_IEEE UINT32_C(0x1) + /* DCBX CEE mode. */ + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE UINT32_C(0x2) + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_LAST HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE + /* ETS TLV state. */ + uint8_t ets_state; + /* PFC TLV state. */ + uint8_t pfc_state; + /* App TLV state. */ + uint8_t app_state; + /* Feature enable bit position. */ + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ENABLE_BIT_POS UINT32_C(0x7) + /* Feature willing bit position. */ + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_WILLING_BIT_POS UINT32_C(0x6) + /* Feature advertise bit position. */ + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS UINT32_C(0x5) + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_LAST HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS + /* unused. */ + uint8_t unused[3]; + /* + * This field is used to reset the DCBX configuration to factory + * defaults. + */ + uint8_t resets; + /* reset ETS configuration. */ + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS UINT32_C(0x1) + /* reset PFC configuration. */ + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_PFC UINT32_C(0x2) + /* reset application configuration. */ + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_APP UINT32_C(0x4) + /* reset DCBX state configuration. */ + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE UINT32_C(0x8) + #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_LAST HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE +} hwrm_struct_data_dcbx_feature_state_t, *phwrm_struct_data_dcbx_feature_state_t; +/* hwrm_struct_data_lldp (size:64b/8B) */ -/* hwrm_fw_state_unquiesce_input (size:128b/16B) */ +typedef struct hwrm_struct_data_lldp { + /* Port admin state */ + uint8_t admin_state; + /* Disable both Tx and Rx */ + #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_DISABLE UINT32_C(0x0) + /* Enable Tx only */ + #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_TX UINT32_C(0x1) + /* Enable Rx only */ + #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_RX UINT32_C(0x2) + /* Enable both Tx and Rx */ + #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE UINT32_C(0x3) + #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_LAST HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE + /* Port description TLV transmit state (enable(1)/disable(0)). */ + uint8_t port_description_state; + /* Disable */ + #define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_DISABLE UINT32_C(0x0) + /* Enable. */ + #define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE UINT32_C(0x1) + #define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_LAST HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE + /* System name TLV transmit state (enable(1)/disable(0)). */ + uint8_t system_name_state; + /* Disable */ + #define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_DISABLE UINT32_C(0x0) + /* Enable. */ + #define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE UINT32_C(0x1) + #define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_LAST HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE + /* System description TLV transmit state (enable(1)/disable(0)). */ + uint8_t system_desc_state; + /* Disable */ + #define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_DISABLE UINT32_C(0x0) + /* Enable. */ + #define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE UINT32_C(0x1) + #define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_LAST HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE + /* System capabilities TLV transmit state (enable(1)/disable(0)). */ + uint8_t system_cap_state; + /* Disable */ + #define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_DISABLE UINT32_C(0x0) + /* Enable. */ + #define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE UINT32_C(0x1) + #define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_LAST HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE + /* Management address TLV transmit state (enable(1)/disable(0)). */ + uint8_t mgmt_addr_state; + /* Disable */ + #define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_DISABLE UINT32_C(0x0) + /* Enable. */ + #define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE UINT32_C(0x1) + #define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_LAST HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE + /* Async event notification state (enable(1)/disable(0)). */ + uint8_t async_event_notification_state; + /* Disable */ + #define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_DISABLE UINT32_C(0x0) + /* Enable. */ + #define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE UINT32_C(0x1) + #define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_LAST HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE + uint8_t unused_0; +} hwrm_struct_data_lldp_t, *phwrm_struct_data_lldp_t; -typedef struct hwrm_fw_state_unquiesce_input { +/* hwrm_struct_data_lldp_generic (size:2112b/264B) */ + +typedef struct hwrm_struct_data_lldp_generic { + /* TLV type. */ + uint8_t tlv_type; + /* Chassis ID TLV */ + #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_CHASSIS UINT32_C(0x1) + /* Port ID TLV */ + #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT UINT32_C(0x2) + /* System name TLV */ + #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_NAME UINT32_C(0x3) + /* System description TLV */ + #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_DESCRIPTION UINT32_C(0x4) + /* Port name TLV */ + #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_NAME UINT32_C(0x5) + /* Port description TLV */ + #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION UINT32_C(0x6) + #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_LAST HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION + /* TLV sub-type. */ + uint8_t subtype; + /* Length. */ + uint8_t length; + /* unused. */ + uint8_t unused1[5]; + /* TLV value. */ + uint32_t tlv_value[64]; +} hwrm_struct_data_lldp_generic_t, *phwrm_struct_data_lldp_generic_t; + +/* hwrm_struct_data_lldp_device (size:1472b/184B) */ + +typedef struct hwrm_struct_data_lldp_device { + /* Time to Live. */ + uint16_t ttl; + /* Management address length. */ + uint8_t mgmt_addr_len; + /* Management address type. */ + uint8_t mgmt_addr_type; + uint8_t unused_3[4]; + /* Management address. */ + uint32_t mgmt_addr[8]; + /* System capabilities. */ + uint32_t system_caps; + /* Interface number type. */ + uint8_t intf_num_type; + /* Management address OID length. */ + uint8_t mgmt_addr_oid_length; + uint8_t unused_4[2]; + /* Interface number. */ + uint32_t intf_num; + uint8_t unused_5[4]; + /* Management address OID. */ + uint32_t mgmt_addr_oid[32]; +} hwrm_struct_data_lldp_device_t, *phwrm_struct_data_lldp_device_t; + +/* hwrm_struct_data_port_description (size:64b/8B) */ + +typedef struct hwrm_struct_data_port_description { + /* + * Port #. Port number starts at 0 and anything greater than number of + * ports minus 1 is an error. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} hwrm_struct_data_port_description_t, *phwrm_struct_data_port_description_t; + +/* hwrm_struct_data_rss_v2 (size:128b/16B) */ + +typedef struct hwrm_struct_data_rss_v2 { + uint16_t flags; + /* When this bit is '1', the hash type and hash key are included. */ + #define HWRM_STRUCT_DATA_RSS_V2_FLAGS_HASH_VALID UINT32_C(0x1) + /* RSS Context index. */ + uint16_t rss_ctx_id; + /* Number ring group IDs. */ + uint16_t num_ring_groups; + uint16_t hash_type; + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. + */ + #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV4 UINT32_C(0x1) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. + */ + #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. + */ + #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + /* + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. + */ + #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV6 UINT32_C(0x8) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. + */ + #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. + */ + #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + /* Hash key. This field is optional. */ + uint64_t hash_key_ring_group_ids; +} hwrm_struct_data_rss_v2_t, *phwrm_struct_data_rss_v2_t; + +/* hwrm_struct_data_power_information (size:192b/24B) */ + +typedef struct hwrm_struct_data_power_information { + /* Backup power information version */ + uint32_t bkup_power_info_ver; + /* Platform backup power count */ + uint32_t platform_bkup_power_count; + /* Load in milliwatts */ + uint32_t load_milli_watt; + /* Backup time in milliseconds */ + uint32_t bkup_time_milli_seconds; + /* Backup power status */ + uint32_t bkup_power_status; + /* Backup power charge time */ + uint32_t bkup_power_charge_time; +} hwrm_struct_data_power_information_t, *phwrm_struct_data_power_information_t; + +/* hwrm_struct_data_msix_per_vf (size:320b/40B) */ + +typedef struct hwrm_struct_data_msix_per_vf { + /* PF ID */ + uint16_t pf_id; + /* Number of rows in table. */ + uint16_t count; + uint32_t unused_0; + /* Starting VF for row 0 */ + uint16_t start_vf_0; + /* MSI-X vectors per VF for row 0 */ + uint16_t msix_0; + /* Starting VF for row 1 */ + uint16_t start_vf_1; + /* MSI-X vectors per VF for row 1 */ + uint16_t msix_1; + /* Starting VF for row 2 */ + uint16_t start_vf_2; + /* MSI-X vectors per VF for row 2 */ + uint16_t msix_2; + /* Starting VF for row 3 */ + uint16_t start_vf_3; + /* MSI-X vectors per VF for row 3 */ + uint16_t msix_3; + /* Starting VF for row 4 */ + uint16_t start_vf_4; + /* MSI-X vectors per VF for row 4 */ + uint16_t msix_4; + /* Starting VF for row 5 */ + uint16_t start_vf_5; + /* MSI-X vectors per VF for row 5 */ + uint16_t msix_5; + /* Starting VF for row 6 */ + uint16_t start_vf_6; + /* MSI-X vectors per VF for row 6 */ + uint16_t msix_6; + /* Starting VF for row 7 */ + uint16_t start_vf_7; + /* MSI-X vectors per VF for row 7 */ + uint16_t msix_7; +} hwrm_struct_data_msix_per_vf_t, *phwrm_struct_data_msix_per_vf_t; + +/******************************* + * hwrm_fw_set_structured_data * + *******************************/ + + +/* hwrm_fw_set_structured_data_input (size:256b/32B) */ + +typedef struct hwrm_fw_set_structured_data_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57335,11 +60905,24 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_fw_state_unquiesce_input_t, *phwrm_fw_state_unquiesce_input_t; - -/* hwrm_fw_state_unquiesce_output (size:192b/24B) */ + /* + * This is the host address where + * structured data will be copied from + */ + uint64_t src_data_addr; + /* size of data in bytes */ + uint16_t data_len; + /* + * a count of the number of Structured Data Headers in the data + * pointed by src_data_addr. + */ + uint8_t hdr_cnt; + uint8_t unused_0[5]; +} hwrm_fw_set_structured_data_input_t, *phwrm_fw_set_structured_data_input_t; -typedef struct hwrm_fw_state_unquiesce_output { +/* hwrm_fw_set_structured_data_output (size:128b/16B) */ + +typedef struct hwrm_fw_set_structured_data_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57348,29 +60931,45 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t unquiesce_status; - /* This bit is '1' if the unquiesce request has fully completed. */ - #define HWRM_FW_STATE_UNQUIESCE_OUTPUT_UNQUIESCE_STATUS_COMPLETE UINT32_C(0x80000000) - uint8_t unused_0[4]; - uint8_t unused_1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_state_unquiesce_output_t, *phwrm_fw_state_unquiesce_output_t; +} hwrm_fw_set_structured_data_output_t, *phwrm_fw_set_structured_data_output_t; -/************************ - * hwrm_fw_state_backup * - ************************/ +/* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ + +typedef struct hwrm_fw_set_structured_data_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* count_of_headers is incorrect */ + #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT UINT32_C(0x1) + /* data improperly formatted */ + #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT UINT32_C(0x2) + /* unknown structure ID(s) */ + #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3) + #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID + uint8_t unused_0[7]; +} hwrm_fw_set_structured_data_cmd_err_t, *phwrm_fw_set_structured_data_cmd_err_t; + +/******************************* + * hwrm_fw_get_structured_data * + *******************************/ -/* hwrm_fw_state_backup_input (size:256b/32B) */ +/* hwrm_fw_get_structured_data_input (size:256b/32B) */ -typedef struct hwrm_fw_state_backup_input { +typedef struct hwrm_fw_get_structured_data_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57399,45 +60998,51 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* State backup page size and level. */ - uint8_t backup_pg_size_backup_lvl; - /* State backup PBL indirect levels. */ - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_MASK UINT32_C(0xf) - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_1 UINT32_C(0x1) /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * This is the host address where + * structured data will be copied to */ - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_2 UINT32_C(0x2) - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LAST HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_2 - /* State backup page size. */ - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_LAST HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_1G - uint8_t unused_0[7]; - /* State backup page directory. */ - uint64_t backup_page_dir; -} hwrm_fw_state_backup_input_t, *phwrm_fw_state_backup_input_t; + uint64_t dest_data_addr; + /* size of data in bytes */ + uint16_t data_len; + /* + * Structure_id is the id of the structure data requesting and count is + * a requested number of instances of this data requested. The actual + * number will be returned in count_of_headers + */ + uint16_t structure_id; + /* + * Subtype is an optional field used to specify additional information + * of the data being retrieved. For example, if data can be categorized + * as "live" vs "saved" then this field can be used to provide an + * indication of "saved" vs "live" data. Not all structured data + * supports subtypes and if they are supported then the structured data + * will specify the valid values. If structured data is requested that + * supports subtypes but no subtype is given then it is implementation + * specific what will be returned. Some structure data can support a + * subtype of "All" which would cause a list of structures to be + * returned for all supported subtypes. "All" is only used on the + * hwrm_get_structured_data command. + */ + uint16_t subtype; + #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_UNUSED UINT32_C(0x0) + #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_ALL UINT32_C(0xffff) + #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_ADMIN UINT32_C(0x100) + #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_PEER UINT32_C(0x101) + #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_OPERATIONAL UINT32_C(0x102) + #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_ADMIN UINT32_C(0x200) + #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_PEER UINT32_C(0x201) + #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_OPERATIONAL UINT32_C(0x202) + #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_HOST_OPERATIONAL UINT32_C(0x300) + #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_LAST HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_HOST_OPERATIONAL + /* Number of elements. This allows support of arrayed data */ + uint8_t count; + uint8_t unused_0; +} hwrm_fw_get_structured_data_input_t, *phwrm_fw_get_structured_data_input_t; -/* hwrm_fw_state_backup_output (size:192b/24B) */ +/* hwrm_fw_get_structured_data_output (size:128b/16B) */ -typedef struct hwrm_fw_state_backup_output { +typedef struct hwrm_fw_get_structured_data_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57446,52 +61051,46 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t backup_status; - /* - * This bit field provides additional information if the error if - * error_code in the common HWRM header is set. - */ - #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_MASK UINT32_C(0xff) - #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_SFT 0 - /* Success, no error */ - #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0) - /* Data or control plane detected as non-quiesced */ - #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_QUIESCE_ERROR UINT32_C(0x1) - /* General backup error */ - #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_GENERAL UINT32_C(0x3) - #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_LAST HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_GENERAL /* - * This bit is '0' if the backout was done in a way that firmware - * may continue running normally after the backup, for example if - * the host elects to skip the subsequent reset and restore for any - * reason. A value of '1' indicates the act of backing up has left - * the firmware/device in a state where subsequent reset is - * required, for example of probing state of a queue leaves changes - * state in a way that is detectable by users. + * a count of the number of Structured Data Headers in the data + * pointed by dest_data_addr. */ - #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_RESET_REQUIRED UINT32_C(0x40000000) - /* This bit is '1' if the backup request has fully completed. */ - #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_COMPLETE UINT32_C(0x80000000) - uint8_t unused_0[4]; - uint8_t unused_1[7]; + uint8_t hdr_cnt; + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_state_backup_output_t, *phwrm_fw_state_backup_output_t; +} hwrm_fw_get_structured_data_output_t, *phwrm_fw_get_structured_data_output_t; -/************************* - * hwrm_fw_state_restore * - *************************/ +/* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ +typedef struct hwrm_fw_get_structured_data_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* unknown structure ID(s) */ + #define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3) + #define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID + uint8_t unused_0[7]; +} hwrm_fw_get_structured_data_cmd_err_t, *phwrm_fw_get_structured_data_cmd_err_t; -/* hwrm_fw_state_restore_input (size:256b/32B) */ +/******************* + * hwrm_fw_ipc_msg * + *******************/ -typedef struct hwrm_fw_state_restore_input { + +/* hwrm_fw_ipc_msg_input (size:320b/40B) */ + +typedef struct hwrm_fw_ipc_msg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57520,45 +61119,60 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* State restore page size and level. */ - uint8_t restore_pg_size_restore_lvl; - /* State restore PBL indirect levels. */ - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_MASK UINT32_C(0xf) - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_1 UINT32_C(0x1) + uint32_t enables; /* - * PBL pointer points to PDE table with each entry pointing to PTE - * tables. + * This bit must be '1' for the command_id field to be + * configured. */ - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_2 UINT32_C(0x2) - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LAST HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_2 - /* State restore page size. */ - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_MASK UINT32_C(0xf0) - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_SFT 4 - /* 4KB. */ - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_LAST HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_1G - uint8_t unused_0[7]; - /* State restore page directory. */ - uint64_t restore_page_dir; -} hwrm_fw_state_restore_input_t, *phwrm_fw_state_restore_input_t; + #define HWRM_FW_IPC_MSG_INPUT_ENABLES_COMMAND_ID UINT32_C(0x1) + /* + * This bit must be '1' for the src_processor field to be + * configured. + */ + #define HWRM_FW_IPC_MSG_INPUT_ENABLES_SRC_PROCESSOR UINT32_C(0x2) + /* + * This bit must be '1' for the data_offset field to be + * configured. + */ + #define HWRM_FW_IPC_MSG_INPUT_ENABLES_DATA_OFFSET UINT32_C(0x4) + /* + * This bit must be '1' for the length field to be + * configured. + */ + #define HWRM_FW_IPC_MSG_INPUT_ENABLES_LENGTH UINT32_C(0x8) + /* Command ID */ + uint16_t command_id; + /* RoCE LAG message */ + #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_LAG UINT32_C(0x1) + /* Query information on PF mapping for x86 and MAIA. */ + #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_MHB_HOST UINT32_C(0x2) + /* RoCE driver version details to be sent to chimp */ + #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_DRVR_VERSION UINT32_C(0x3) + #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_LAST HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_DRVR_VERSION + /* Source processor for this command. */ + uint8_t src_processor; + /* Chimp processor */ + #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_CFW UINT32_C(0x1) + /* BONO processor */ + #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_BONO UINT32_C(0x2) + /* APE processor */ + #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_APE UINT32_C(0x3) + /* KONG processor */ + #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_KONG UINT32_C(0x4) + #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_LAST HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_KONG + uint8_t unused_0; + /* Offset of the data in the source processor memory. */ + uint32_t data_offset; + /* Length of the data in source processor. */ + uint16_t length; + uint8_t unused_1[2]; + /* This is for storing FW opaque data. */ + uint64_t opaque; +} hwrm_fw_ipc_msg_input_t, *phwrm_fw_ipc_msg_input_t; -/* hwrm_fw_state_restore_output (size:128b/16B) */ +/* hwrm_fw_ipc_msg_output (size:256b/32B) */ -typedef struct hwrm_fw_state_restore_output { +typedef struct hwrm_fw_ipc_msg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57567,50 +61181,28 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t restore_status; - /* - * This bit field provides additional information if the error if - * error_code in the common HWRM header is set. - */ - #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_MASK UINT32_C(0xff) - #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_SFT 0 - /* Success, no error */ - #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0) - /* General restore error */ - #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_GENERAL UINT32_C(0x1) - /* Format parse error */ - #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_FORMAT_PARSE UINT32_C(0x2) - /* Integrity check error */ - #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_INTEGRITY_CHECK UINT32_C(0x3) - #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_LAST HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_INTEGRITY_CHECK - /* - * If a failure occurs (complete is 0), restore attempts to - * completely roll back any state applied so that the failure - * results in no state change. This flag indicates whether that - * rollback completed successfully and thoroughly. - */ - #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_FAILURE_ROLLBACK_COMPLETED UINT32_C(0x40000000) - /* This bit is '1' if the restore request has fully completed. */ - #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_COMPLETE UINT32_C(0x80000000) - uint8_t unused_0[3]; + uint32_t msg_data_1; + uint32_t msg_data_2; + uint64_t reserved64; + uint8_t reserved48[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_state_restore_output_t, *phwrm_fw_state_restore_output_t; +} hwrm_fw_ipc_msg_output_t, *phwrm_fw_ipc_msg_output_t; -/********************** - * hwrm_fw_secure_cfg * - **********************/ +/*********************** + * hwrm_fw_ipc_mailbox * + ***********************/ -/* hwrm_fw_secure_cfg_input (size:256b/32B) */ +/* hwrm_fw_ipc_mailbox_input (size:256b/32B) */ -typedef struct hwrm_fw_secure_cfg_input { +typedef struct hwrm_fw_ipc_mailbox_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57639,78 +61231,23 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Specify the type of security option. */ - uint8_t enable; - /* Fields for the nvm lock mode are valid. */ - #define HWRM_FW_SECURE_CFG_INPUT_ENABLE_NVRAM UINT32_C(0x1) - /* Fields for the grc access control are valid. */ - #define HWRM_FW_SECURE_CFG_INPUT_ENABLE_GRC UINT32_C(0x2) - /* Fields for the uart access control are valid. */ - #define HWRM_FW_SECURE_CFG_INPUT_ENABLE_UART UINT32_C(0x3) - #define HWRM_FW_SECURE_CFG_INPUT_ENABLE_LAST HWRM_FW_SECURE_CFG_INPUT_ENABLE_UART - /* - * This bit field indicates the type of the configuration to be - * updated. - */ - uint8_t config_mode; - /* When this bit is '1', persistent config would be updated. */ - #define HWRM_FW_SECURE_CFG_INPUT_CONFIG_MODE_PERSISTENT UINT32_C(0x1) - /* When this bit is '1', runtime config would be updated. */ - #define HWRM_FW_SECURE_CFG_INPUT_CONFIG_MODE_RUNTIME UINT32_C(0x2) - /* define lock mode for nvram. */ - uint8_t nvm_lock_mode; - /* - * Contents of the entire NVRAM including FW and Config can be - * altered by a HWRM client. - */ - #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_NONE UINT32_C(0x0) - /* - * Only partial sections of the NVM are to be locked. To specify - * section to be locked the 'nvm_partial_lock_mask' should be used. - */ - #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_PARTIAL UINT32_C(0x1) - /* - * Contents of the entire NVM including FW and Config are to be - * locked against any alteration by any HWRM client. - */ - #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_FULL UINT32_C(0x2) - /* - * This is a HW lock of the NVM itself. Once locked firmware has no - * control to unlock. Contents of the NVM cannot be altered. - * Require a power cycle to unlock. - */ - #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_CHIP UINT32_C(0x3) - #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_LAST HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_CHIP - /* - * bit field indicating the type of partial_lock. - * This field is only applicable if the partial_lock is set. - */ - uint8_t nvm_partial_lock_mask; - /* When this bit is '1', updating the FW images are locked. */ - #define HWRM_FW_SECURE_CFG_INPUT_NVM_PARTIAL_LOCK_MASK_EXE UINT32_C(0x1) - /* When this bit is '1', updating the CFG are locked. */ - #define HWRM_FW_SECURE_CFG_INPUT_NVM_PARTIAL_LOCK_MASK_CFG UINT32_C(0x2) - /* specify grc access control for specified HWRM clients. */ - uint8_t grc_ctrl; - /* Read Only */ - #define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RO UINT32_C(0x0) - /* Read-Write */ - #define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RW UINT32_C(0x1) - #define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_LAST HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RW - /* specify debug access control via UART */ - uint8_t uart_ctrl; - /* disable UART access for debugging */ - #define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_DISABLE UINT32_C(0x0) - /* enable UART access for debugging */ - #define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_ENABLE UINT32_C(0x1) - #define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_LAST HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_ENABLE - uint8_t unused_0[2]; - uint64_t unused_1; -} hwrm_fw_secure_cfg_input_t, *phwrm_fw_secure_cfg_input_t; + uint8_t flags; + /* unused is 8 b */ + uint8_t unused; + /* asynchronous event to hosts. */ + uint8_t event_id; + /* PORT ID */ + uint8_t port_id; + /* event data1 of asynchronous event */ + uint32_t event_data1; + /* event data2 of asynchronous event */ + uint32_t event_data2; + uint8_t unused_0[4]; +} hwrm_fw_ipc_mailbox_input_t, *phwrm_fw_ipc_mailbox_input_t; -/* hwrm_fw_secure_cfg_output (size:128b/16B) */ +/* hwrm_fw_ipc_mailbox_output (size:128b/16B) */ -typedef struct hwrm_fw_secure_cfg_output { +typedef struct hwrm_fw_ipc_mailbox_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57722,23 +61259,38 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fw_secure_cfg_output_t, *phwrm_fw_secure_cfg_output_t; +} hwrm_fw_ipc_mailbox_output_t, *phwrm_fw_ipc_mailbox_output_t; -/********************** - * hwrm_exec_fwd_resp * - **********************/ +/* hwrm_fw_ipc_mailbox_cmd_err (size:64b/8B) */ + +typedef struct hwrm_fw_ipc_mailbox_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* invalid event */ + #define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID UINT32_C(0x3) + #define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_LAST HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID + uint8_t unused_0[7]; +} hwrm_fw_ipc_mailbox_cmd_err_t, *phwrm_fw_ipc_mailbox_cmd_err_t; + +/******************* + * hwrm_fw_ecn_cfg * + *******************/ -/* hwrm_exec_fwd_resp_input (size:1024b/128B) */ +/* hwrm_fw_ecn_cfg_input (size:192b/24B) */ -typedef struct hwrm_exec_fwd_resp_input { +typedef struct hwrm_fw_ecn_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57767,27 +61319,25 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint16_t flags; /* - * This is an encapsulated request. This request should - * be executed by the HWRM and the response should be - * provided in the response buffer inside the encapsulated - * request. - */ - uint32_t encap_request[26]; - /* - * This value indicates the target id of the response to - * the encapsulated request. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM + * When this bit is '1', Explicit Congestion Notification (ECN) is + * enabled device-wide. When ECN is enabled on a multi-host system, + * it is enabled for all hosts. This setting takes effect + * immediately. When ECN is enabled, the firmware activates + * additional receive Class of Service (CoS) queues that are enabled + * for ECN marking and steers ECN-capable packets to those queues. + * This setting is not saved persistently. To enable ECN + * persistently, set NVM option 173, ENABLE_ECN. + * Setting this bit to '0' disables ECN immediately. */ - uint16_t encap_resp_target_id; + #define HWRM_FW_ECN_CFG_INPUT_FLAGS_ENABLE_ECN UINT32_C(0x1) uint8_t unused_0[6]; -} hwrm_exec_fwd_resp_input_t, *phwrm_exec_fwd_resp_input_t; +} hwrm_fw_ecn_cfg_input_t, *phwrm_fw_ecn_cfg_input_t; -/* hwrm_exec_fwd_resp_output (size:128b/16B) */ +/* hwrm_fw_ecn_cfg_output (size:128b/16B) */ -typedef struct hwrm_exec_fwd_resp_output { +typedef struct hwrm_fw_ecn_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57799,22 +61349,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_exec_fwd_resp_output_t, *phwrm_exec_fwd_resp_output_t; +} hwrm_fw_ecn_cfg_output_t, *phwrm_fw_ecn_cfg_output_t; -/************************ - * hwrm_reject_fwd_resp * - ************************/ +/******************** + * hwrm_fw_ecn_qcfg * + ********************/ -/* hwrm_reject_fwd_resp_input (size:1024b/128B) */ +/* hwrm_fw_ecn_qcfg_input (size:128b/16B) */ -typedef struct hwrm_reject_fwd_resp_input { +typedef struct hwrm_fw_ecn_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57843,27 +61393,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This is an encapsulated request. This request should - * be rejected by the HWRM and the error response should be - * provided in the response buffer inside the encapsulated - * request. - */ - uint32_t encap_request[26]; - /* - * This value indicates the target id of the response to - * the encapsulated request. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM - */ - uint16_t encap_resp_target_id; - uint8_t unused_0[6]; -} hwrm_reject_fwd_resp_input_t, *phwrm_reject_fwd_resp_input_t; +} hwrm_fw_ecn_qcfg_input_t, *phwrm_fw_ecn_qcfg_input_t; -/* hwrm_reject_fwd_resp_output (size:128b/16B) */ +/* hwrm_fw_ecn_qcfg_output (size:128b/16B) */ -typedef struct hwrm_reject_fwd_resp_output { +typedef struct hwrm_fw_ecn_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57872,25 +61406,28 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + uint16_t flags; + /* When this bit is '1', ECN is enabled device-wide. */ + #define HWRM_FW_ECN_QCFG_OUTPUT_FLAGS_ENABLE_ECN UINT32_C(0x1) + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_reject_fwd_resp_output_t, *phwrm_reject_fwd_resp_output_t; - -/***************** - * hwrm_fwd_resp * - *****************/ +} hwrm_fw_ecn_qcfg_output_t, *phwrm_fw_ecn_qcfg_output_t; +/************************ + * hwrm_fw_health_check * + ************************/ -/* hwrm_fwd_resp_input (size:1024b/128B) */ -typedef struct hwrm_fwd_resp_input { +/* hwrm_fw_health_check_input (size:128b/16B) */ + +typedef struct hwrm_fw_health_check_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -57919,42 +61456,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This value indicates the target id of the encapsulated - * response. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM - */ - uint16_t encap_resp_target_id; - /* - * This value indicates the completion ring the encapsulated - * response will be optionally completed on. If the value is - * -1, then no CR completion shall be generated for the - * encapsulated response. Any other value must be a - * valid CR ring_id value. If a valid encap_resp_cmpl_ring - * is provided, then a CR completion shall be generated for - * the encapsulated response. - */ - uint16_t encap_resp_cmpl_ring; - /* This field indicates the length of encapsulated response. */ - uint16_t encap_resp_len; - uint8_t unused_0; - uint8_t unused_1; - /* - * This is the host address where the encapsulated response - * will be written. - * This area must be 16B aligned and must be cleared to zero - * before the original request is made. - */ - uint64_t encap_resp_addr; - /* This is an encapsulated response. */ - uint32_t encap_resp[24]; -} hwrm_fwd_resp_input_t, *phwrm_fwd_resp_input_t; +} hwrm_fw_health_check_input_t, *phwrm_fw_health_check_input_t; -/* hwrm_fwd_resp_output (size:128b/16B) */ +/* hwrm_fw_health_check_output (size:128b/16B) */ -typedef struct hwrm_fwd_resp_output { +typedef struct hwrm_fw_health_check_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -57963,97 +61469,113 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + uint32_t fw_status; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This bit is '0' if the primary SBI was used this boot, + * or '1' if the secondary SBI was used. */ - uint8_t valid; -} hwrm_fwd_resp_output_t, *phwrm_fwd_resp_output_t; - -/***************************** - * hwrm_fwd_async_event_cmpl * - *****************************/ - - -/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ - -typedef struct hwrm_fwd_async_event_cmpl_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SBI_BOOTED UINT32_C(0x1) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * This bit is '0' if the primary and secondary SBI images + * match, or '1' if they do not match. */ - uint16_t cmpl_ring; + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SBI_MISMATCH UINT32_C(0x2) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * This bit is '0' if the primary SRT was used this boot, + * or '1' if the secondary SRT was used. */ - uint16_t seq_id; + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT_BOOTED UINT32_C(0x4) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * This bit is '0' if the primary and secondary SRT images + * match, or '1' if they do not match. */ - uint16_t target_id; + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT_MISMATCH UINT32_C(0x8) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * This bit is '0' if the primary CRT (or second stage SRT) + * was used this boot, or '1' if the secondary CRT (or + * second stage SRT) was used. */ - uint64_t resp_addr; + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT_BOOTED UINT32_C(0x10) /* - * This value indicates the target id of the encapsulated - * asynchronous event. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - Broadcast to all children VFs (only applicable when - * a PF is the requester) + * This bit is '0' if the primary and secondary CRT images + * (or second stage SRT images) match, or '1' if they do not + * match. */ - uint16_t encap_async_event_target_id; - uint8_t unused_0[6]; - /* This is an encapsulated asynchronous event completion. */ - uint32_t encap_async_event_cmpl[4]; -} hwrm_fwd_async_event_cmpl_input_t, *phwrm_fwd_async_event_cmpl_input_t; - -/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ - -typedef struct hwrm_fwd_async_event_cmpl_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT_MISMATCH UINT32_C(0x20) + /* + * This bit is '0' if the second stage RT image is a CRT, + * or '1' if the second stage RT image is an SRT. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SECOND_RT UINT32_C(0x40) + /* + * This bit is '0' if the image was loaded from flash, + * or '1' if the image was fastbooted. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_FASTBOOTED UINT32_C(0x80) + /* + * This bit is '0' if the primary dir_hdr was used to locate + * the firmware, or '1' if the secondary dir_hdr was used. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_DIR_HDR_BOOTED UINT32_C(0x100) + /* + * This bit is '0' if the primary and secondary dir_hdr match, + * or '1' if they do not match. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_DIR_HDR_MISMATCH UINT32_C(0x200) + /* + * This bit is '0' if the Master Boot Record is in good condition, + * or '1' if it is corrupted. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_MBR_CORRUPT UINT32_C(0x400) + /* + * This bit is '0' if the configuration is in good condition, + * or '1' if it is corrupted. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CFG_MISMATCH UINT32_C(0x800) + /* + * This bit is '0' if both FRU entries match, + * or '1' if they do not match. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_FRU_MISMATCH UINT32_C(0x1000) + /* + * This bit is '0' if the primary CRT2 was used this boot, + * or '1' if the secondary CRT2 was used. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT2_BOOTED UINT32_C(0x2000) + /* + * This bit is '0' if the primary and secondary CRT2 images + * match, or '1' if they do not match. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT2_MISMATCH UINT32_C(0x4000) + /* + * This bit is '0' if the primary GXRT was used this boot, + * or '1' if the secondary GXRT was used. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_GXRT_BOOTED UINT32_C(0x8000) + /* + * This bit is '0' if the primary and secondary GXRT images + * match, or '1' if they do not match. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_GXRT_MISMATCH UINT32_C(0x10000) + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_fwd_async_event_cmpl_output_t, *phwrm_fwd_async_event_cmpl_output_t; +} hwrm_fw_health_check_output_t, *phwrm_fw_health_check_output_t; /*************************** - * hwrm_temp_monitor_query * + * hwrm_fw_livepatch_query * ***************************/ -/* hwrm_temp_monitor_query_input (size:128b/16B) */ +/* hwrm_fw_livepatch_query_input (size:192b/24B) */ -typedef struct hwrm_temp_monitor_query_input { +typedef struct hwrm_fw_livepatch_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58082,11 +61604,19 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_temp_monitor_query_input_t, *phwrm_temp_monitor_query_input_t; + /* Firmware target to which to apply the livepatch query */ + uint8_t fw_target; + /* Common firmware livepatch query. */ + #define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_COMMON_FW UINT32_C(0x1) + /* Secure firmware livepatch query. */ + #define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_SECURE_FW UINT32_C(0x2) + #define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_LAST HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_SECURE_FW + uint8_t unused_0[7]; +} hwrm_fw_livepatch_query_input_t, *phwrm_fw_livepatch_query_input_t; -/* hwrm_temp_monitor_query_output (size:128b/16B) */ +/* hwrm_fw_livepatch_query_output (size:640b/80B) */ -typedef struct hwrm_temp_monitor_query_output { +typedef struct hwrm_fw_livepatch_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58096,90 +61626,39 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * The HWRM shall provide the current temperature of - * the device in Celsius. This is the max of PCIe_temp - * and PM_temp - */ - uint8_t temp; - /* - * The HWRM shall provide the current temperature of - * the phy in Celsius. - */ - uint8_t phy_temp; - /* - * The HWRM shall provide the current temperature of - * the module_index in Celsius. - */ - uint8_t om_temp; - /* Describe individual temperature sensor condition. */ - uint8_t flags; - /* - * "1" in this bit indicates temperature read not - * successful. - */ - #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_TEMP_NOT_AVAILABLE UINT32_C(0x1) - /* - * "1" in this bit indicates phy temperature read not - * successful. - */ - #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_PHY_TEMP_NOT_AVAILABLE UINT32_C(0x2) - /* "1" in this bit indicates optical module(s) not present. */ - #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_OM_NOT_PRESENT UINT32_C(0x4) - /* - * "1" in this bit indicates om temperature read not - * successful. - */ - #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_OM_TEMP_NOT_AVAILABLE UINT32_C(0x8) - /* - * "1" in this bit indicates the extended temperature fields are - * available. - */ - #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_EXT_TEMP_FIELDS_AVAILABLE UINT32_C(0x10) - /* - * This field encodes the current device temperature in Celsius. - * This field is unsigned and the value range of 0 to 255 is used to - * indicate a temperature range from -64 to +191. The actual - * temperature is derived by subtracting 64 from this field. - * Example: A value of 0 represents a temperature of -64, a value of - * 255 represents a temperature of 191. - */ - uint8_t temp2; - /* - * This field encodes the current phy temperature in Celsius. This - * field is unsigned and the value range of 0 to 255 is used to - * indicate a temperature range from -64 to +191. The actual - * temperature is derived by subtracting 64 from this field. - * Example: A value of 0 represents a temperature of -64, a value of - * 255 represents a temperature of 191. + * This field represents the patch version string of the NVM installed + * livepatch. (ASCII chars with NULL at the end). */ - uint8_t phy_temp2; + char install_ver[32]; /* - * This field encodes the current module index temperature in Celsius. - * This field is unsigned and the value range of 0 to 255 is used to - * indicate a temperature range from -64 to +191. The actual - * temperature is derived by subtracting 64 from this field. - * Example: A value of 0 represents a temperature of -64, a value of - * 255 represents a temperature of 191. + * This field represents the patch version string of the active + * livepatch. (ASCII chars with NULL at the end). */ - uint8_t om_temp2; + char active_ver[32]; + uint16_t status_flags; + /* This bit is '1' if a livepatch image is installed to NVM. */ + #define HWRM_FW_LIVEPATCH_QUERY_OUTPUT_STATUS_FLAGS_INSTALL UINT32_C(0x1) + /* This bit is '1' if firmware livepatch is active. */ + #define HWRM_FW_LIVEPATCH_QUERY_OUTPUT_STATUS_FLAGS_ACTIVE UINT32_C(0x2) + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_temp_monitor_query_output_t, *phwrm_temp_monitor_query_output_t; +} hwrm_fw_livepatch_query_output_t, *phwrm_fw_livepatch_query_output_t; -/************************ - * hwrm_reg_power_query * - ************************/ +/********************* + * hwrm_fw_livepatch * + *********************/ -/* hwrm_reg_power_query_input (size:128b/16B) */ +/* hwrm_fw_livepatch_input (size:256b/32B) */ -typedef struct hwrm_reg_power_query_input { +typedef struct hwrm_fw_livepatch_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58208,11 +61687,49 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_reg_power_query_input_t, *phwrm_reg_power_query_input_t; + /* Livepatch operation */ + uint8_t opcode; + /* + * Activate a livepatch that is NVM installed or via direct load + * from host memory. Activate will authenticate a signed patch, + * verify the patch version for compatibility and apply the + * livepatch to existing firmware at run-time. + */ + #define HWRM_FW_LIVEPATCH_INPUT_OPCODE_ACTIVATE UINT32_C(0x1) + /* + * Deactivate a livepatch and restore to the original firmware + * operation state. + */ + #define HWRM_FW_LIVEPATCH_INPUT_OPCODE_DEACTIVATE UINT32_C(0x2) + #define HWRM_FW_LIVEPATCH_INPUT_OPCODE_LAST HWRM_FW_LIVEPATCH_INPUT_OPCODE_DEACTIVATE + /* Firmware target to which to apply the livepatch operation. */ + uint8_t fw_target; + /* Common firmware livepatch. */ + #define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_COMMON_FW UINT32_C(0x1) + /* Secure firmware livepatch. */ + #define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_SECURE_FW UINT32_C(0x2) + #define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_LAST HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_SECURE_FW + /* Load method for livepatch. */ + uint8_t loadtype; + /* Load a livepatch currently installed on NVM. */ + #define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_NVM_INSTALL UINT32_C(0x1) + /* + * Load a livepatch directly from host memory. The livepatch image + * is available at host_addr. + */ + #define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_MEMORY_DIRECT UINT32_C(0x2) + #define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_LAST HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_MEMORY_DIRECT + /* Reserved for future use. */ + uint8_t flags; + /* Length of livepatch image for memory direct loading, in bytes. */ + uint32_t patch_len; + /* 64-bit Host address of livepatch image for memory direct loading. */ + uint64_t host_addr; +} hwrm_fw_livepatch_input_t, *phwrm_fw_livepatch_input_t; -/* hwrm_reg_power_query_output (size:192b/24B) */ +/* hwrm_fw_livepatch_output (size:128b/16B) */ -typedef struct hwrm_reg_power_query_output { +typedef struct hwrm_fw_livepatch_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58221,41 +61738,60 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Describe availability of switching regulator power values. */ - uint32_t flags; - /* When this bit is set to '1', the input power is available. */ - #define HWRM_REG_POWER_QUERY_OUTPUT_FLAGS_IN_POWER_AVAILABLE UINT32_C(0x1) - /* When this bit is set to '1', the output power is available. */ - #define HWRM_REG_POWER_QUERY_OUTPUT_FLAGS_OUT_POWER_AVAILABLE UINT32_C(0x2) + uint8_t unused_0[7]; /* - * The HWRM shall provide the current switching regulator - * input power in mW, if available. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint32_t in_power_mw; + uint8_t valid; +} hwrm_fw_livepatch_output_t, *phwrm_fw_livepatch_output_t; + +/* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ + +typedef struct hwrm_fw_livepatch_cmd_err { /* - * The HWRM shall provide the current switching regulator - * output power in mW, if available. + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. */ - uint32_t out_power_mw; - uint8_t unused_0[3]; + uint8_t code; + /* Unknown error. */ + #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Opcode invalid. */ + #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE UINT32_C(0x1) + /* Firmware target invalid. */ + #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET UINT32_C(0x2) + /* Livepatch operation not supported. */ + #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED UINT32_C(0x3) + /* Livepatch image is not installed in NVRAM. */ + #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED UINT32_C(0x4) + /* Deactivate failed. Firmware is not currently patched. */ + #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED UINT32_C(0x5) + /* Authentication of a signed livepatch failed. */ + #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL UINT32_C(0x6) + /* Livepatch header check failed. Patch incompatible. */ + #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER UINT32_C(0x7) + /* Livepatch size incompatible. */ + #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE UINT32_C(0x8) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Activate failed. Firmware has already been patched. Deactivate + * existing livepatch before proceeding. */ - uint8_t valid; -} hwrm_reg_power_query_output_t, *phwrm_reg_power_query_output_t; + #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED UINT32_C(0x9) + #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_LAST HWRM_FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED + uint8_t unused_0[7]; +} hwrm_fw_livepatch_cmd_err_t, *phwrm_fw_livepatch_cmd_err_t; -/***************************** - * hwrm_core_frequency_query * - *****************************/ +/**************** + * hwrm_fw_sync * + ****************/ -/* hwrm_core_frequency_query_input (size:128b/16B) */ +/* hwrm_fw_sync_input (size:192b/24B) */ -typedef struct hwrm_core_frequency_query_input { +typedef struct hwrm_fw_sync_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58284,11 +61820,80 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_core_frequency_query_input_t, *phwrm_core_frequency_query_input_t; + uint32_t sync_action; + /* + * If action is '1' (sync) and this bit is set, the SBI + * images will be synchronized, copying from the instance + * used for boot to the other instance, if they currently + * do not match. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SBI UINT32_C(0x1) + /* + * If action is '1' (sync) and this bit is set, the SRT + * images will be synchronized, copying from the instance + * used for boot to the other instance, if they currently + * do not match. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SRT UINT32_C(0x2) + /* + * If action is '1' (sync) and this bit is set, the CRT + * images will be synchronized (or second stage SRT if that + * is used in place of CRT), copying from the instance + * used for boot to the other instance, if they currently + * do not match. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CRT UINT32_C(0x4) + /* + * If action is '1' (sync) and this bit is set, the dir_hdr + * partition will be synchronized, copying from the instance + * used for boot to the other instance, if they currently + * do not match. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_DIR_HDR UINT32_C(0x8) + /* + * If action is '1' (sync) and this bit is set, the MBR + * will be erased and reprogrammed with valid content. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_WRITE_MBR UINT32_C(0x10) + /* + * If action is '1' (sync) and this bit is set, the + * configuration will be resynced or repaired as needed. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CFG UINT32_C(0x20) + /* + * If action is '1' (sync) and this bit is set, the + * FRU in NVM file will be synchronized, copying the active + * FRU to the backup FRU. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_FRU UINT32_C(0x40) + /* + * If action is '1' (sync) and this bit is set, the CRT2 + * images will be synchronized, copying from the instance + * used for boot to the other instance, if they currently + * do not match. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CRT2 UINT32_C(0x80) + /* + * If action is '1' (sync) and this bit is set, the GXRT + * images will be synchronized, copying from the instance + * used for boot to the other instance, if they currently + * do not match. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_GXRT UINT32_C(0x100) + /* + * A value of '1' instructs the firmware to perform an image + * synchronization of the firmware types denoted by the + * sync_sbi, sync_srt, sync_crt, sync_crt2 bits. A value of '0' just + * requests the status for the previously requested sync + * operation. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_ACTION UINT32_C(0x80000000) + uint8_t unused_0[4]; +} hwrm_fw_sync_input_t, *phwrm_fw_sync_input_t; -/* hwrm_core_frequency_query_output (size:128b/16B) */ +/* hwrm_fw_sync_output (size:128b/16B) */ -typedef struct hwrm_core_frequency_query_output { +typedef struct hwrm_fw_sync_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58297,27 +61902,55 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The HWRM shall provide the core frequency in Hz. */ - uint32_t core_frequency_hz; + uint32_t sync_status; + /* This bit field indicates the error if 'sync_err' bit is set. */ + #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_MASK UINT32_C(0xff) + #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_SFT 0 + /* Success, no error */ + #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0) + /* + * A previously requested synchronization command is still + * in progress. + */ + #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_IN_PROGRESS UINT32_C(0x1) + /* An NVRAM operation has timed out. */ + #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_TIMEOUT UINT32_C(0x2) + /* General NVRAM error code. */ + #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_GENERAL UINT32_C(0x3) + #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_LAST HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_GENERAL + /* + * This bit is '1' if the synchronization request has completed + * with an error; the 'err_code' field can be used to obtain + * information about error type. + */ + #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_SYNC_ERR UINT32_C(0x40000000) + /* + * This bit is '0' if the previously requested synchronization + * command is still in progress, or '1' if the previously + * requested sync command has completed. If '1', the 'sync_err' + * field will indicate if it completed successfully or with + * an error. + */ + #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_SYNC_COMPLETE UINT32_C(0x80000000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_core_frequency_query_output_t, *phwrm_core_frequency_query_output_t; +} hwrm_fw_sync_output_t, *phwrm_fw_sync_output_t; -/**************************** - * hwrm_reg_power_histogram * - ****************************/ +/*********************** + * hwrm_fw_state_qcaps * + ***********************/ -/* hwrm_reg_power_histogram_input (size:192b/24B) */ +/* hwrm_fw_state_qcaps_input (size:128b/16B) */ -typedef struct hwrm_reg_power_histogram_input { +typedef struct hwrm_fw_state_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58346,19 +61979,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Describe operational mode of power histogram command. */ - uint32_t flags; - /* - * When this bit is set to '1', histogram data for the respective - * client (HWRM or BMC) is cleared after read. - */ - #define HWRM_REG_POWER_HISTOGRAM_INPUT_FLAGS_CLEAR_HISTOGRAM UINT32_C(0x1) - uint32_t unused_0; -} hwrm_reg_power_histogram_input_t, *phwrm_reg_power_histogram_input_t; +} hwrm_fw_state_qcaps_input_t, *phwrm_fw_state_qcaps_input_t; -/* hwrm_reg_power_histogram_output (size:1088b/136B) */ +/* hwrm_fw_state_qcaps_output (size:256b/32B) */ -typedef struct hwrm_reg_power_histogram_output { +typedef struct hwrm_fw_state_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58367,136 +61992,66 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Describe output characteristics of power histogram command. */ - uint16_t flags; - /* - * Indicates whether input or output power is used. Some switching - * regulators provide both input and output voltage and current - * measurements, and others provide only output measurements. When - * both are available, input is used. This value is constant for a - * given board. - */ - #define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT UINT32_C(0x1) - /* - * The switching regulator's input power is used - * data. - */ - #define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_INPUT UINT32_C(0x0) /* - * The switching regulator's output power is used - * data. + * This field indicates the size in bytes required by host backup + * memory. Host software should allocate memory according to this + * size requirement and pass the allocated memory to the + * HWRM_FW_STATE_BACKUP and HWRM_FW_STATE_RESTORE commands in the form + * of PBL data as specified in those commands. */ - #define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_OUTPUT UINT32_C(0x1) - #define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_LAST HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_OUTPUT - uint8_t unused_0[2]; + uint32_t backup_memory; /* - * Time in microseconds between samples. This value is constant in - * firmware. The initial design sets this constant at 10000 us (10 - * ms). Power values for voltage regulators calculate a power value - * over a 300 us period, so a 10 ms sampling period covers 3% of - * time ranges. Future firmware designs may opt for different - * sampling periods, so this value is provided on output. + * This field indicates the max time in milliseconds that firmware + * waits for quiesce to complete. Firmware indicates successful + * quiesce completion if the quiesce operation completes within this + * timeout. If firmware is still waiting for the quiesce operation + * to complete when this timeout is reached, firmware stops waiting + * (without canceling any quiesce action such as pausing or + * clearing meter profiles) and indicates a timeout status result + * via NQE completion notification. This timeout value may also be + * used by the driver to know the max time to wait for any NQE + * notification response to the HWRM_FW_STATE_QUIESCE command. After + * a timeout, the driver may elect to invoke HWRM_FW_STATE_QUIESCE + * again to keep trying or to invoke HWRM_FW_STATE_UNQUIESCE to + * revert the operation. Since there is no identifier correlating + * each HWRM_FW_STATE_QUIESCE command with its NQE response, it is + * important for the driver to wait for the NQE response before + * issuing a subsequent HWRM_FW_STATE_QUIESCE command. */ - uint32_t sampling_period; + uint32_t quiesce_timeout; /* - * Total samples taken since last clear. If no counter has - * saturated, the sum of counts in each bucket equates to this - * sample_count value. If a single counter has saturated, its value - * can be calculated by subtracting the remaining bucket values from - * this sample_count value. + * This field indicates time in milliseconds that the driver should + * wait after return from HWRM_FW_RESET to begin polling the device + * for status 0x8000. */ - uint64_t sample_count; + uint32_t fw_status_blackout; /* - * The power usage expressed in histogram buckets. Bucket value - * ranges and array indices are defined per the enumeration - * power_histogram_bucket_enum. Values saturate at the max 32-bit - * value, 0xFFFFFFFF, and do not roll over. Clients should use the - * clear bit on input to clear the histogram array periodically or - * when saturation is observed. + * This field indicates a max time for firmware to poll for status + * 0x8000 before assuming a reset failure occurred. This time does + * not include fw_status_blackout time which would immediately precede + * this wait. */ - uint32_t power_hist[26]; - uint8_t unused_1[7]; + uint32_t fw_status_max_wait; + uint8_t unused_0[4]; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_reg_power_histogram_output_t, *phwrm_reg_power_histogram_output_t; - -/* - * Count of timer callback routines run with no data measured. This - * may occur when data from the switching regulator is not available - * to the firmware timer callback routine. One possible reason for - * this is contention with other users of the i2c bus which is used - * to communicate with the switching regulator, for example when a - * call to hwrm_reg_power_query occurs while the timer routine is - * running. - */ -#define BUCKET_NO_DATA_FOR_SAMPLE UINT32_C(0x0) -/* Count of samples measured at less than 8W */ -#define BUCKET_RANGE_8W_OR_LESS UINT32_C(0x1) -/* Count of samples measured >= 8 W and < 9 W */ -#define BUCKET_RANGE_8W_TO_9W UINT32_C(0x2) -/* Count of samples measured >= 9 W and < 10 W */ -#define BUCKET_RANGE_9W_TO_10W UINT32_C(0x3) -/* Count of samples measured >= 10 W and < 11 W */ -#define BUCKET_RANGE_10W_TO_11W UINT32_C(0x4) -/* Count of samples measured >= 11 W and < 12 W */ -#define BUCKET_RANGE_11W_TO_12W UINT32_C(0x5) -/* Count of samples measured >= 12 W and < 13 W */ -#define BUCKET_RANGE_12W_TO_13W UINT32_C(0x6) -/* Count of samples measured >= 13 W and < 14 W */ -#define BUCKET_RANGE_13W_TO_14W UINT32_C(0x7) -/* Count of samples measured >= 14 W and < 15 W */ -#define BUCKET_RANGE_14W_TO_15W UINT32_C(0x8) -/* Count of samples measured >= 15 W and < 16 W */ -#define BUCKET_RANGE_15W_TO_16W UINT32_C(0x9) -/* Count of samples measured >= 16 W and < 18 W */ -#define BUCKET_RANGE_16W_TO_18W UINT32_C(0xa) -/* Count of samples measured >= 18 W and < 20 W */ -#define BUCKET_RANGE_18W_TO_20W UINT32_C(0xb) -/* Count of samples measured >= 20 W and < 22 W */ -#define BUCKET_RANGE_20W_TO_22W UINT32_C(0xc) -/* Count of samples measured >= 22 W and < 24 W */ -#define BUCKET_RANGE_22W_TO_24W UINT32_C(0xd) -/* Count of samples measured >= 24 W and < 26 W */ -#define BUCKET_RANGE_24W_TO_26W UINT32_C(0xe) -/* Count of samples measured >= 26 W and < 28 W */ -#define BUCKET_RANGE_26W_TO_28W UINT32_C(0xf) -/* Count of samples measured >= 28 W and < 30 W */ -#define BUCKET_RANGE_28W_TO_30W UINT32_C(0x10) -/* Count of samples measured >= 30 W and < 32 W */ -#define BUCKET_RANGE_30W_TO_32W UINT32_C(0x11) -/* Count of samples measured >= 32 W and < 34 W */ -#define BUCKET_RANGE_32W_TO_34W UINT32_C(0x12) -/* Count of samples measured >= 34 W and < 36 W */ -#define BUCKET_RANGE_34W_TO_36W UINT32_C(0x13) -/* Count of samples measured >= 36 W and < 38 W */ -#define BUCKET_RANGE_36W_TO_38W UINT32_C(0x14) -/* Count of samples measured >= 38 W and < 40 W */ -#define BUCKET_RANGE_38W_TO_40W UINT32_C(0x15) -/* Count of samples measured >= 40 W and < 42 W */ -#define BUCKET_RANGE_40W_TO_42W UINT32_C(0x16) -/* Count of samples measured >= 42 W and < 44 W */ -#define BUCKET_RANGE_42W_TO_44W UINT32_C(0x17) -/* Count of samples measured >= 44 W and < 50 W */ -#define BUCKET_RANGE_44W_TO_50W UINT32_C(0x18) -/* Count of samples measured at 50 W or greater */ -#define BUCKET_RANGE_OVER_50W UINT32_C(0x19) -#define BUCKET_LAST BUCKET_RANGE_OVER_50W - +} hwrm_fw_state_qcaps_output_t, *phwrm_fw_state_qcaps_output_t; /************************* - * hwrm_wol_filter_alloc * + * hwrm_fw_state_quiesce * *************************/ -/* hwrm_wol_filter_alloc_input (size:512b/64B) */ +/* hwrm_fw_state_quiesce_input (size:192b/24B) */ -typedef struct hwrm_wol_filter_alloc_input { +typedef struct hwrm_fw_state_quiesce_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58525,98 +62080,27 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - uint32_t enables; - /* - * This bit must be '1' for the mac_address field to be - * configured. - */ - #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_MAC_ADDRESS UINT32_C(0x1) - /* - * This bit must be '1' for the pattern_offset field to be - * configured. - */ - #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_OFFSET UINT32_C(0x2) - /* - * This bit must be '1' for the pattern_buf_size field to be - * configured. - */ - #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_SIZE UINT32_C(0x4) - /* - * This bit must be '1' for the pattern_buf_addr field to be - * configured. - */ - #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_ADDR UINT32_C(0x8) - /* - * This bit must be '1' for the pattern_mask_addr field to be - * configured. - */ - #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_ADDR UINT32_C(0x10) - /* - * This bit must be '1' for the pattern_mask_size field to be - * configured. - */ - #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_SIZE UINT32_C(0x20) - /* Port ID of port on which WoL filter is configured. */ - uint16_t port_id; - /* This value represents a Wake-on-LAN type. */ - uint8_t wol_type; - /* Magic Packet */ - #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0) - /* Bitmap */ - #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_BMP UINT32_C(0x1) - /* Invalid */ - #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_INVALID UINT32_C(0xff) - #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_LAST HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_INVALID - uint8_t unused_0[5]; - /* - * # If this field is enabled and magic packet WoL filter - * type is specified in this command, the value set in this - * field shall be used in setting the magic packet based - * WoL filter. - * # If this field is not enabled and magic packet WoL - * filter type is specified and port id is specified to - * 0xFF in this command, then the HWRM - * shall use default MAC address configured on the - * function associated with the HWRM client. - * # If this field is not enabled and magic packet WoL - * filter type is specified and port id is not specified to - * 0xFF in this command, then the HWRM - * shall use default MAC address configured on the port. - */ - uint8_t mac_address[6]; - /* - * The offset from the beginning of MAC header where - * pattern should be matched. - * Applies to bitmap WoL. - */ - uint16_t pattern_offset; - /* - * The size of the pattern that is being matched. - * Applies to bitmap WoL. - */ - uint16_t pattern_buf_size; - /* - * The size of the pattern mask. - * Applies to bitmap WoL. - */ - uint16_t pattern_mask_size; - uint8_t unused_1[4]; - /* - * Physical address of the pattern buffer. - * Applies to bitmap WoL. - */ - uint64_t pattern_buf_addr; + uint8_t flags; /* - * Physical address of the pattern mask. - * Applies to bitmap WoL. + * Setting this bit to '1', indicates impactless firmware update + * is in a recovery mode where hardware is in an error state and + * where recovery is desired with reasonably minimal impact to + * connected clients. The quiesce operation may require separate + * steps to handle quiescing when hardware is in a hung or locked + * state. For example, quiesce via draining may not be possible + * depending on the type of error. This flag's state would be kept + * in firmware if recovery-specific steps are also needed for the + * HWRM_FW_STATE_BACKUP. Note this option is available only for + * specific recovery scenarios and may not be operational across + * all controllers. */ - uint64_t pattern_mask_addr; -} hwrm_wol_filter_alloc_input_t, *phwrm_wol_filter_alloc_input_t; + #define HWRM_FW_STATE_QUIESCE_INPUT_FLAGS_ERROR_RECOVERY UINT32_C(0x1) + uint8_t unused_0[7]; +} hwrm_fw_state_quiesce_input_t, *phwrm_fw_state_quiesce_input_t; -/* hwrm_wol_filter_alloc_output (size:128b/16B) */ +/* hwrm_fw_state_quiesce_output (size:192b/24B) */ -typedef struct hwrm_wol_filter_alloc_output { +typedef struct hwrm_fw_state_quiesce_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58625,27 +62109,33 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value identifies a Wake-on-LAN (WoL) filter. */ - uint8_t wol_filter_id; - uint8_t unused_0[6]; + uint32_t quiesce_status; + /* + * This bit is '1' if the quiesce request has been successfully + * initiated. + */ + #define HWRM_FW_STATE_QUIESCE_OUTPUT_QUIESCE_STATUS_INITIATED UINT32_C(0x80000000) + uint8_t unused_0[4]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * is completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When + * writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_wol_filter_alloc_output_t, *phwrm_wol_filter_alloc_output_t; +} hwrm_fw_state_quiesce_output_t, *phwrm_fw_state_quiesce_output_t; -/************************ - * hwrm_wol_filter_free * - ************************/ +/*************************** + * hwrm_fw_state_unquiesce * + ***************************/ -/* hwrm_wol_filter_free_input (size:256b/32B) */ +/* hwrm_fw_state_unquiesce_input (size:128b/16B) */ -typedef struct hwrm_wol_filter_free_input { +typedef struct hwrm_fw_state_unquiesce_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58674,34 +62164,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * # When this bit is set to '1', then all active WoL - * filters on the port are requested to be freed. - * # If the a function driver sets this flag to '1', then - * the HWRM shall free all active WoL filters that are not - * set by other function drivers on that port. - */ - #define HWRM_WOL_FILTER_FREE_INPUT_FLAGS_FREE_ALL_WOL_FILTERS UINT32_C(0x1) - uint32_t enables; - /* - * This bit must be '1' for the wol_filter_id field to be - * configured. - */ - #define HWRM_WOL_FILTER_FREE_INPUT_ENABLES_WOL_FILTER_ID UINT32_C(0x1) - /* Port ID of the port on which WoL filter(s) is (are) being freed. */ - uint16_t port_id; - /* - * The HWRM shall ignore this field if free_all_wol_filters - * flag is set. - */ - uint8_t wol_filter_id; - uint8_t unused_0[5]; -} hwrm_wol_filter_free_input_t, *phwrm_wol_filter_free_input_t; +} hwrm_fw_state_unquiesce_input_t, *phwrm_fw_state_unquiesce_input_t; -/* hwrm_wol_filter_free_output (size:128b/16B) */ +/* hwrm_fw_state_unquiesce_output (size:192b/24B) */ -typedef struct hwrm_wol_filter_free_output { +typedef struct hwrm_fw_state_unquiesce_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58710,25 +62177,29 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + uint32_t unquiesce_status; + /* This bit is '1' if the unquiesce request has fully completed. */ + #define HWRM_FW_STATE_UNQUIESCE_OUTPUT_UNQUIESCE_STATUS_COMPLETE UINT32_C(0x80000000) + uint8_t unused_0[4]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_wol_filter_free_output_t, *phwrm_wol_filter_free_output_t; +} hwrm_fw_state_unquiesce_output_t, *phwrm_fw_state_unquiesce_output_t; /************************ - * hwrm_wol_filter_qcfg * + * hwrm_fw_state_backup * ************************/ -/* hwrm_wol_filter_qcfg_input (size:448b/56B) */ +/* hwrm_fw_state_backup_input (size:256b/32B) */ -typedef struct hwrm_wol_filter_qcfg_input { +typedef struct hwrm_fw_state_backup_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58757,59 +62228,45 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Port ID of port on which WoL filter that is being queried. */ - uint16_t port_id; - /* - * This is an opaque handle used to access filters. - * # The HWRM client shall set this field to 0x0000 to begin - * the query. - * # After the first query, the HWRM client shall retrieve - * next filters (if they exist) using the HWRM provided handle - * in the response. - */ - uint16_t handle; - uint8_t unused_0[4]; - /* - * Physical address of the pattern buffer. - * Applies to bitmap WoL filter only. - * # Value of 0 indicates an invalid buffer address. - * If this field is set to 0, then HWRM shall ignore - * pattern_buf_size. - * # If the HWRM client provides an invalid buffer address - * for the pattern, then the HWRM is not required to - * provide pattern when the response contains a bitmap WoL - * filter. - */ - uint64_t pattern_buf_addr; - /* - * The size of the pattern buffer. - * Applies to bitmap WoL filter only. - */ - uint16_t pattern_buf_size; - uint8_t unused_1[6]; - /* - * Physical address of the pattern mask. - * Applies to bitmap WoL filter only. - * # Value of 0 indicates an invalid pattern mask address. - * If this field is set to 0, then HWRM shall ignore - * pattern_mask_size. - * # If the HWRM client provides an invalid mask address - * for the pattern, then the HWRM is not required to - * provide mask when the response contains a bitmap WoL - * filter. - */ - uint64_t pattern_mask_addr; + /* State backup page size and level. */ + uint8_t backup_pg_size_backup_lvl; + /* State backup PBL indirect levels. */ + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_MASK UINT32_C(0xf) + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_1 UINT32_C(0x1) /* - * The size of the buffer for pattern mask. - * Applies to bitmap WoL filter only. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - uint16_t pattern_mask_size; - uint8_t unused_2[6]; -} hwrm_wol_filter_qcfg_input_t, *phwrm_wol_filter_qcfg_input_t; + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_2 UINT32_C(0x2) + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LAST HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_2 + /* State backup page size. */ + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_LAST HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_1G + uint8_t unused_0[7]; + /* State backup page directory. */ + uint64_t backup_page_dir; +} hwrm_fw_state_backup_input_t, *phwrm_fw_state_backup_input_t; -/* hwrm_wol_filter_qcfg_output (size:256b/32B) */ +/* hwrm_fw_state_backup_output (size:192b/24B) */ -typedef struct hwrm_wol_filter_qcfg_output { +typedef struct hwrm_fw_state_backup_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58818,78 +62275,52 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + uint32_t backup_status; /* - * This is the next handle that is used to access filters. - * # If this field is set to 0x0000, then no WoL filters are - * currently configured on this port and all other fields in - * the output shall be ignored by the HWRM client. - * # If this field is set to neither 0x0000 nor 0xFFFF, then the - * wol_filter_id is valid and the parameters provided in the - * response are based on the wol_type. - * # If this field is set to 0xFFFF, then there are no remaining - * configured WoL filters to be queried for the queried function - * after this response, wol_filter_id is valid and the parameters - * provided in the response are based on the wol_type. - */ - uint16_t next_handle; - /* - * This value identifies the filter returned in this - * response. - */ - uint8_t wol_filter_id; - /* - * This value identifies the type of WoL filter returned - * in this response. - */ - uint8_t wol_type; - /* Magic Packet */ - #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0) - /* Bitmap */ - #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_BMP UINT32_C(0x1) - /* Invalid */ - #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_INVALID UINT32_C(0xff) - #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_LAST HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_INVALID - uint32_t unused_0; - /* - * The MAC address value used by the WoL filter. - * Applies to magic packet based WoL. - */ - uint8_t mac_address[6]; - /* - * The offset from the beginning of MAC header where - * pattern should be matched. - * Applies to bitmap WoL. - */ - uint16_t pattern_offset; - /* - * The actual size of the pattern that is being returned. - * Applies to bitmap WoL. + * This bit field provides additional information if the error if + * error_code in the common HWRM header is set. */ - uint16_t pattern_size; + #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_MASK UINT32_C(0xff) + #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_SFT 0 + /* Success, no error */ + #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0) + /* Data or control plane detected as non-quiesced */ + #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_QUIESCE_ERROR UINT32_C(0x1) + /* General backup error */ + #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_GENERAL UINT32_C(0x3) + #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_LAST HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_GENERAL /* - * The actual size of the pattern mask that is being returned. - * Applies to bitmap WoL. + * This bit is '0' if the backout was done in a way that firmware + * may continue running normally after the backup, for example if + * the host elects to skip the subsequent reset and restore for any + * reason. A value of '1' indicates the act of backing up has left + * the firmware/device in a state where subsequent reset is + * required, for example of probing state of a queue leaves changes + * state in a way that is detectable by users. */ - uint16_t pattern_mask_size; - uint8_t unused_1[3]; + #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_RESET_REQUIRED UINT32_C(0x40000000) + /* This bit is '1' if the backup request has fully completed. */ + #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_COMPLETE UINT32_C(0x80000000) + uint8_t unused_0[4]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_wol_filter_qcfg_output_t, *phwrm_wol_filter_qcfg_output_t; +} hwrm_fw_state_backup_output_t, *phwrm_fw_state_backup_output_t; -/************************ - * hwrm_wol_reason_qcfg * - ************************/ +/************************* + * hwrm_fw_state_restore * + *************************/ -/* hwrm_wol_reason_qcfg_input (size:320b/40B) */ +/* hwrm_fw_state_restore_input (size:256b/32B) */ -typedef struct hwrm_wol_reason_qcfg_input { +typedef struct hwrm_fw_state_restore_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -58918,22 +62349,45 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Port ID of port for which this query is for. */ - uint16_t port_id; - uint8_t unused_0[6]; + /* State restore page size and level. */ + uint8_t restore_pg_size_restore_lvl; + /* State restore PBL indirect levels. */ + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_MASK UINT32_C(0xf) + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_1 UINT32_C(0x1) /* - * Physical address of the packet buffer for querying - * WoL packet. + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. */ - uint64_t wol_pkt_buf_addr; - /* The size of the buffer for the WoL packet. */ - uint16_t wol_pkt_buf_size; - uint8_t unused_1[6]; -} hwrm_wol_reason_qcfg_input_t, *phwrm_wol_reason_qcfg_input_t; + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_2 UINT32_C(0x2) + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LAST HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_2 + /* State restore page size. */ + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_LAST HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_1G + uint8_t unused_0[7]; + /* State restore page directory. */ + uint64_t restore_page_dir; +} hwrm_fw_state_restore_input_t, *phwrm_fw_state_restore_input_t; -/* hwrm_wol_reason_qcfg_output (size:128b/16B) */ +/* hwrm_fw_state_restore_output (size:128b/16B) */ -typedef struct hwrm_wol_reason_qcfg_output { +typedef struct hwrm_fw_state_restore_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -58942,48 +62396,50 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + uint32_t restore_status; /* - * This value identifies the filter that matched - * the last WoL packet. - * This id is only valid with valid WoL reason. + * This bit field provides additional information if the error if + * error_code in the common HWRM header is set. */ - uint8_t wol_filter_id; + #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_MASK UINT32_C(0xff) + #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_SFT 0 + /* Success, no error */ + #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0) + /* General restore error */ + #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_GENERAL UINT32_C(0x1) + /* Format parse error */ + #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_FORMAT_PARSE UINT32_C(0x2) + /* Integrity check error */ + #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_INTEGRITY_CHECK UINT32_C(0x3) + #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_LAST HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_INTEGRITY_CHECK /* - * This value identifies the type of WoL reason returned - * in this response. - * When the wol_type is set to invalid, then there is - * no WoL event that happened during last system - * wake-up. + * If a failure occurs (complete is 0), restore attempts to + * completely roll back any state applied so that the failure + * results in no state change. This flag indicates whether that + * rollback completed successfully and thoroughly. */ - uint8_t wol_reason; - /* Magic Packet */ - #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_MAGICPKT UINT32_C(0x0) - /* Bitmap */ - #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_BMP UINT32_C(0x1) - /* Invalid */ - #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_INVALID UINT32_C(0xff) - #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_LAST HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_INVALID - /* The value identifies the length of the WoL packet in bytes. */ - uint8_t wol_pkt_len; - uint8_t unused_0[4]; + #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_FAILURE_ROLLBACK_COMPLETED UINT32_C(0x40000000) + /* This bit is '1' if the restore request has fully completed. */ + #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_COMPLETE UINT32_C(0x80000000) + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_wol_reason_qcfg_output_t, *phwrm_wol_reason_qcfg_output_t; +} hwrm_fw_state_restore_output_t, *phwrm_fw_state_restore_output_t; -/************************ - * hwrm_dbg_read_direct * - ************************/ +/********************** + * hwrm_fw_secure_cfg * + **********************/ -/* hwrm_dbg_read_direct_input (size:256b/32B) */ +/* hwrm_fw_secure_cfg_input (size:256b/32B) */ -typedef struct hwrm_dbg_read_direct_input { +typedef struct hwrm_fw_secure_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59012,20 +62468,78 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Specify the type of security option. */ + uint8_t enable; + /* Fields for the nvm lock mode are valid. */ + #define HWRM_FW_SECURE_CFG_INPUT_ENABLE_NVRAM UINT32_C(0x1) + /* Fields for the grc access control are valid. */ + #define HWRM_FW_SECURE_CFG_INPUT_ENABLE_GRC UINT32_C(0x2) + /* Fields for the uart access control are valid. */ + #define HWRM_FW_SECURE_CFG_INPUT_ENABLE_UART UINT32_C(0x3) + #define HWRM_FW_SECURE_CFG_INPUT_ENABLE_LAST HWRM_FW_SECURE_CFG_INPUT_ENABLE_UART /* - * host address where the data content will be written - * when the request is complete. This area must be 16B aligned. + * This bit field indicates the type of the configuration to be + * updated. */ - uint64_t host_dest_addr; - /* address(in ChiMP view) to start reading */ - uint32_t read_addr; - /* number of dwords to read */ - uint32_t read_len32; -} hwrm_dbg_read_direct_input_t, *phwrm_dbg_read_direct_input_t; + uint8_t config_mode; + /* When this bit is '1', persistent config would be updated. */ + #define HWRM_FW_SECURE_CFG_INPUT_CONFIG_MODE_PERSISTENT UINT32_C(0x1) + /* When this bit is '1', runtime config would be updated. */ + #define HWRM_FW_SECURE_CFG_INPUT_CONFIG_MODE_RUNTIME UINT32_C(0x2) + /* define lock mode for nvram. */ + uint8_t nvm_lock_mode; + /* + * Contents of the entire NVRAM including FW and Config can be + * altered by a HWRM client. + */ + #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_NONE UINT32_C(0x0) + /* + * Only partial sections of the NVM are to be locked. To specify + * section to be locked the 'nvm_partial_lock_mask' should be used. + */ + #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_PARTIAL UINT32_C(0x1) + /* + * Contents of the entire NVM including FW and Config are to be + * locked against any alteration by any HWRM client. + */ + #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_FULL UINT32_C(0x2) + /* + * This is a HW lock of the NVM itself. Once locked firmware has no + * control to unlock. Contents of the NVM cannot be altered. + * Require a power cycle to unlock. + */ + #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_CHIP UINT32_C(0x3) + #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_LAST HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_CHIP + /* + * bit field indicating the type of partial_lock. + * This field is only applicable if the partial_lock is set. + */ + uint8_t nvm_partial_lock_mask; + /* When this bit is '1', updating the FW images are locked. */ + #define HWRM_FW_SECURE_CFG_INPUT_NVM_PARTIAL_LOCK_MASK_EXE UINT32_C(0x1) + /* When this bit is '1', updating the CFG are locked. */ + #define HWRM_FW_SECURE_CFG_INPUT_NVM_PARTIAL_LOCK_MASK_CFG UINT32_C(0x2) + /* specify grc access control for specified HWRM clients. */ + uint8_t grc_ctrl; + /* Read Only */ + #define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RO UINT32_C(0x0) + /* Read-Write */ + #define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RW UINT32_C(0x1) + #define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_LAST HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RW + /* specify debug access control via UART */ + uint8_t uart_ctrl; + /* disable UART access for debugging */ + #define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_DISABLE UINT32_C(0x0) + /* enable UART access for debugging */ + #define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_ENABLE UINT32_C(0x1) + #define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_LAST HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_ENABLE + uint8_t unused_0[2]; + uint64_t unused_1; +} hwrm_fw_secure_cfg_input_t, *phwrm_fw_secure_cfg_input_t; -/* hwrm_dbg_read_direct_output (size:128b/16B) */ +/* hwrm_fw_secure_cfg_output (size:128b/16B) */ -typedef struct hwrm_dbg_read_direct_output { +typedef struct hwrm_fw_secure_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59034,31 +62548,26 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This field, if not zero, contains the IEEE 802.3 CRC-32 checksum of - * the number of dwords read in this request using this polynomial: - * x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 - */ - uint32_t crc32; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_dbg_read_direct_output_t, *phwrm_dbg_read_direct_output_t; +} hwrm_fw_secure_cfg_output_t, *phwrm_fw_secure_cfg_output_t; -/************************* - * hwrm_dbg_write_direct * - *************************/ +/********************** + * hwrm_exec_fwd_resp * + **********************/ -/* hwrm_dbg_write_direct_input (size:448b/56B) */ +/* hwrm_exec_fwd_resp_input (size:1024b/128B) */ -typedef struct hwrm_dbg_write_direct_input { +typedef struct hwrm_exec_fwd_resp_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59087,17 +62596,27 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* address(in ChiMP view) to start writing */ - uint32_t write_addr; - /* number of dwords to write (up to 8 dwords) */ - uint32_t write_len32; - /* write data (up to 8 dwords) */ - uint32_t write_data[8]; -} hwrm_dbg_write_direct_input_t, *phwrm_dbg_write_direct_input_t; + /* + * This is an encapsulated request. This request should + * be executed by the HWRM and the response should be + * provided in the response buffer inside the encapsulated + * request. + */ + uint32_t encap_request[26]; + /* + * This value indicates the target id of the response to + * the encapsulated request. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM + */ + uint16_t encap_resp_target_id; + uint8_t unused_0[6]; +} hwrm_exec_fwd_resp_input_t, *phwrm_exec_fwd_resp_input_t; -/* hwrm_dbg_write_direct_output (size:128b/16B) */ +/* hwrm_exec_fwd_resp_output (size:128b/16B) */ -typedef struct hwrm_dbg_write_direct_output { +typedef struct hwrm_exec_fwd_resp_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59109,22 +62628,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_write_direct_output_t, *phwrm_dbg_write_direct_output_t; +} hwrm_exec_fwd_resp_output_t, *phwrm_exec_fwd_resp_output_t; -/************************** - * hwrm_dbg_read_indirect * - **************************/ +/************************ + * hwrm_reject_fwd_resp * + ************************/ -/* hwrm_dbg_read_indirect_input (size:640b/80B) */ +/* hwrm_reject_fwd_resp_input (size:1024b/128B) */ -typedef struct hwrm_dbg_read_indirect_input { +typedef struct hwrm_reject_fwd_resp_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59154,87 +62673,26 @@ */ uint64_t resp_addr; /* - * host address where the data content will be written - * when the request is complete. This area must be 16B aligned. - */ - uint64_t host_dest_addr; - /* Length of host buffer used for transferring debug data. */ - uint32_t host_dest_addr_len; - /* Indirect access type to on-chip data structures. */ - uint8_t indirect_access_type; - /* L2 Mgmt filters in Transmit Engine (TE) */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 UINT32_C(0x0) - /* L3/L4 Mgmt filters in Transmit Engine (TE) */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 UINT32_C(0x1) - /* L2 Mgmt filters in Receive Engine (RE) */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 UINT32_C(0x2) - /* L3/L4 Mgmt filters in Receive Engine (RE) */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 UINT32_C(0x3) - /* Statistics contexts */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS UINT32_C(0x4) - /* TX L2 TCAM */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM UINT32_C(0x5) - /* RX L2 TCAM */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM UINT32_C(0x6) - /* TX IPv6 subnet TCAM */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM UINT32_C(0x7) - /* RX IPv6 subnet TCAM */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM UINT32_C(0x8) - /* TX source properties TCAM */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9) - /* RX source properties TCAM */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa) - /* VEB Lookup TCAM */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM UINT32_C(0xb) - /* TX Profile Lookup TCAM */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc) - /* RX Profile Lookup TCAM */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd) - /* TX Lookup TCAM */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM UINT32_C(0xe) - /* RX Lookup TCAM */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM UINT32_C(0xf) - /* MHB registers (valid for multi-host environment) */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB UINT32_C(0x10) - /* PCIE global registers (valid for multi-host environment) */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL UINT32_C(0x11) - /* SOC registers (valid for multi-host environment) */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC UINT32_C(0x12) - /* PCIE private registers */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_PRIVATE UINT32_C(0x13) - /* Host DMA read */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_HOST_DMA UINT32_C(0x14) - /* - * Elog (valid for only smartNIC only) - * Three sub-types will be supported which will be specified - * in the opaque[0] field. - * 1) sub-type CHECK(0) if ELOG is available in media. - * 2) sub-type READ(1) a portion of the elog. - * 3) sub-type ERASE(2) a portion of the elog. - * > opaque[1] Erase offset. - * > opaque[2] Erase size. + * This is an encapsulated request. This request should + * be rejected by the HWRM and the error response should be + * provided in the response buffer inside the encapsulated + * request. */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_SOC_ELOG UINT32_C(0x15) - /* Context operation */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CTX UINT32_C(0x16) - /* Port Stats */ - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS UINT32_C(0x17) - #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_LAST HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS - uint8_t unused_0[3]; - /* Entry number to start reading */ - uint32_t start_index; - /* Total number of entries to read */ - uint32_t num_of_entries; + uint32_t encap_request[26]; /* - * command dependent data (e.g. function id for host dma command or - * sub-code, erase offset and erase size for soc_elog) + * This value indicates the target id of the response to + * the encapsulated request. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM */ - uint32_t opaque[10]; -} hwrm_dbg_read_indirect_input_t, *phwrm_dbg_read_indirect_input_t; + uint16_t encap_resp_target_id; + uint8_t unused_0[6]; +} hwrm_reject_fwd_resp_input_t, *phwrm_reject_fwd_resp_input_t; -/* hwrm_dbg_read_indirect_output (size:128b/16B) */ +/* hwrm_reject_fwd_resp_output (size:128b/16B) */ -typedef struct hwrm_dbg_read_indirect_output { +typedef struct hwrm_reject_fwd_resp_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59246,22 +62704,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_read_indirect_output_t, *phwrm_dbg_read_indirect_output_t; +} hwrm_reject_fwd_resp_output_t, *phwrm_reject_fwd_resp_output_t; -/*************************** - * hwrm_dbg_write_indirect * - ***************************/ +/***************** + * hwrm_fwd_resp * + *****************/ -/* hwrm_dbg_write_indirect_input (size:832b/104B) */ +/* hwrm_fwd_resp_input (size:1024b/128B) */ -typedef struct hwrm_dbg_write_indirect_input { +typedef struct hwrm_fwd_resp_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59290,72 +62748,42 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Indirect access type to on-chip data structures. */ - uint8_t indirect_access_type; - /* L2 Mgmt filters in Transmit Engine (TE) */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 UINT32_C(0x0) - /* L3/L4 Mgmt filters in Transmit Engine (TE) */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 UINT32_C(0x1) - /* L2 Mgmt filters in Receive Engine (RE) */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 UINT32_C(0x2) - /* L3/L4 Mgmt filters in Receive Engine (RE) */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 UINT32_C(0x3) - /* Statistics contexts */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS UINT32_C(0x4) - /* TX L2 TCAM */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM UINT32_C(0x5) - /* RX L2 TCAM */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM UINT32_C(0x6) - /* TX IPv6 subnet TCAM */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM UINT32_C(0x7) - /* RX IPv6 subnet TCAM */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM UINT32_C(0x8) - /* TX source properties TCAM */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9) - /* RX source properties TCAM */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa) - /* VEB Lookup TCAM */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM UINT32_C(0xb) - /* TX Profile Lookup TCAM */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc) - /* RX Profile Lookup TCAM */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd) - /* TX Lookup TCAM */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM UINT32_C(0xe) - /* RX Lookup TCAM */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM UINT32_C(0xf) - /* MHB registers (valid for multi-host environment) */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB UINT32_C(0x10) - /* PCIE global registers (valid for multi-host environment) */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL UINT32_C(0x11) - /* SOC registers (valid for multi-host environment) */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC UINT32_C(0x12) - /* PCIE private registers */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_PRIVATE UINT32_C(0x13) - /* Host DMA write */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_HOST_DMA UINT32_C(0x14) - /* Invalid */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_SOC_ELOG UINT32_C(0x15) - /* Context operation */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CTX UINT32_C(0x16) - /* Port Stats */ - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS UINT32_C(0x17) - #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_LAST HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS - uint8_t unused_0[3]; - /* Entry number to start reading */ - uint32_t start_index; - /* Total number of entries to read */ - uint32_t num_of_entries; - uint8_t unused_1[4]; - /* write data (up to 8 dwords) */ - uint32_t write_data[8]; - /* command dependent data (e.g. function id for host dma command) */ - uint32_t opaque[10]; -} hwrm_dbg_write_indirect_input_t, *phwrm_dbg_write_indirect_input_t; + /* + * This value indicates the target id of the encapsulated + * response. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM + */ + uint16_t encap_resp_target_id; + /* + * This value indicates the completion ring the encapsulated + * response will be optionally completed on. If the value is + * -1, then no CR completion shall be generated for the + * encapsulated response. Any other value must be a + * valid CR ring_id value. If a valid encap_resp_cmpl_ring + * is provided, then a CR completion shall be generated for + * the encapsulated response. + */ + uint16_t encap_resp_cmpl_ring; + /* This field indicates the length of encapsulated response. */ + uint16_t encap_resp_len; + uint8_t unused_0; + uint8_t unused_1; + /* + * This is the host address where the encapsulated response + * will be written. + * This area must be 16B aligned and must be cleared to zero + * before the original request is made. + */ + uint64_t encap_resp_addr; + /* This is an encapsulated response. */ + uint32_t encap_resp[24]; +} hwrm_fwd_resp_input_t, *phwrm_fwd_resp_input_t; -/* hwrm_dbg_write_indirect_output (size:128b/16B) */ +/* hwrm_fwd_resp_output (size:128b/16B) */ -typedef struct hwrm_dbg_write_indirect_output { +typedef struct hwrm_fwd_resp_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59367,22 +62795,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_write_indirect_output_t, *phwrm_dbg_write_indirect_output_t; +} hwrm_fwd_resp_output_t, *phwrm_fwd_resp_output_t; -/***************** - * hwrm_dbg_dump * - *****************/ +/***************************** + * hwrm_fwd_async_event_cmpl * + *****************************/ -/* hwrm_dbg_dump_input (size:320b/40B) */ +/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ -typedef struct hwrm_dbg_dump_input { +typedef struct hwrm_fwd_async_event_cmpl_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59412,24 +62840,22 @@ */ uint64_t resp_addr; /* - * Handle used to dump debug data. - * handle = 0 indicates the beginning of the dump. - * handle != 0 indicates the request to dump the next part. - */ - uint32_t handle; - uint8_t unused_0[4]; - /* - * Address of the host buffer where the debug data is - * requested to be dumped. + * This value indicates the target id of the encapsulated + * asynchronous event. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - Broadcast to all children VFs (only applicable when + * a PF is the requester) */ - uint64_t host_dbg_dump_addr; - /* Length of host buffer used for transferring debug data. */ - uint64_t host_dbg_dump_addr_len; -} hwrm_dbg_dump_input_t, *phwrm_dbg_dump_input_t; + uint16_t encap_async_event_target_id; + uint8_t unused_0[6]; + /* This is an encapsulated asynchronous event completion. */ + uint32_t encap_async_event_cmpl[4]; +} hwrm_fwd_async_event_cmpl_input_t, *phwrm_fwd_async_event_cmpl_input_t; -/* hwrm_dbg_dump_output (size:192b/24B) */ +/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ -typedef struct hwrm_dbg_dump_output { +typedef struct hwrm_fwd_async_event_cmpl_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59438,39 +62864,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Handle used to indicate availability of additional - * debug data. - * nexthandle = 0 indicates that there is no more debug data - * available. - * nexthandle != 0 indicates the handle value that should be used - * to request the next part of debug data. - */ - uint32_t nexthandle; - /* - * The number of bytes of debug data written to debug dump - * buffer. - */ - uint32_t dbg_data_len; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_dump_output_t, *phwrm_dbg_dump_output_t; +} hwrm_fwd_async_event_cmpl_output_t, *phwrm_fwd_async_event_cmpl_output_t; -/********************** - * hwrm_dbg_erase_nvm * - **********************/ +/*************************** + * hwrm_temp_monitor_query * + ***************************/ -/* hwrm_dbg_erase_nvm_input (size:192b/24B) */ +/* hwrm_temp_monitor_query_input (size:128b/16B) */ -typedef struct hwrm_dbg_erase_nvm_input { +typedef struct hwrm_temp_monitor_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59499,15 +62911,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t flags; - /* If set to 1, then erase all locations in persistent storage. */ - #define HWRM_DBG_ERASE_NVM_INPUT_FLAGS_ERASE_ALL UINT32_C(0x1) - uint8_t unused_0[6]; -} hwrm_dbg_erase_nvm_input_t, *phwrm_dbg_erase_nvm_input_t; +} hwrm_temp_monitor_query_input_t, *phwrm_temp_monitor_query_input_t; -/* hwrm_dbg_erase_nvm_output (size:128b/16B) */ +/* hwrm_temp_monitor_query_output (size:192b/24B) */ -typedef struct hwrm_dbg_erase_nvm_output { +typedef struct hwrm_temp_monitor_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59516,126 +62924,119 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * The HWRM shall provide the current temperature of + * the device in Celsius. This is the max of PCIe_temp + * and PM_temp */ - uint8_t valid; -} hwrm_dbg_erase_nvm_output_t, *phwrm_dbg_erase_nvm_output_t; - -/**************** - * hwrm_dbg_cfg * - ****************/ - - -/* hwrm_dbg_cfg_input (size:192b/24B) */ - -typedef struct hwrm_dbg_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + uint8_t temp; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * The HWRM shall provide the current temperature of + * the phy in Celsius. */ - uint16_t cmpl_ring; + uint8_t phy_temp; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * The HWRM shall provide the current temperature of + * the module_index in Celsius. */ - uint16_t seq_id; + uint8_t om_temp; + /* Describe individual temperature sensor condition. */ + uint8_t flags; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * "1" in this bit indicates temperature read not + * successful. */ - uint16_t target_id; + #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_TEMP_NOT_AVAILABLE UINT32_C(0x1) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * "1" in this bit indicates phy temperature read not + * successful. */ - uint64_t resp_addr; - uint32_t flags; + #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_PHY_TEMP_NOT_AVAILABLE UINT32_C(0x2) + /* "1" in this bit indicates optical module(s) not present. */ + #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_OM_NOT_PRESENT UINT32_C(0x4) /* - * If set to 1, then UART logging will be enabled for the primary - * firmware. Disabled otherwise. + * "1" in this bit indicates om temperature read not + * successful. */ - #define HWRM_DBG_CFG_INPUT_FLAGS_UART_LOG UINT32_C(0x1) + #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_OM_TEMP_NOT_AVAILABLE UINT32_C(0x8) /* - * If set to 1, then UART logging will be enabled for the secondary - * firmware. Disabled otherwise. If a single UART is available then - * setting this bit will override the uart_log bit. + * "1" in this bit indicates the extended temperature fields are + * available. */ - #define HWRM_DBG_CFG_INPUT_FLAGS_UART_LOG_SECONDARY UINT32_C(0x2) + #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_EXT_TEMP_FIELDS_AVAILABLE UINT32_C(0x10) /* - * If set to 1, then completion ring logging will be enabled for the - * primary firmware. Disabled otherwise. + * "1" in this bit indicates the thermal threshold values are + * available. */ - #define HWRM_DBG_CFG_INPUT_FLAGS_FW_TRACE UINT32_C(0x4) + #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_THRESHOLD_VALUES_AVAILABLE UINT32_C(0x20) /* - * If set to 1, then completion ring logging will be enabled for the - * secondary firmware. Disabled otherwise. + * This field encodes the current device temperature in Celsius. + * This field is unsigned and the value range of 0 to 255 is used to + * indicate a temperature range from -64 to +191. The actual + * temperature is derived by subtracting 64 from this field. + * Example: A value of 0 represents a temperature of -64, a value of + * 255 represents a temperature of 191. */ - #define HWRM_DBG_CFG_INPUT_FLAGS_FW_TRACE_SECONDARY UINT32_C(0x8) + uint8_t temp2; /* - * If set to 1, firmware will generate debug_notification async - * events to the driver as applicable. + * This field encodes the current phy temperature in Celsius. This + * field is unsigned and the value range of 0 to 255 is used to + * indicate a temperature range from -64 to +191. The actual + * temperature is derived by subtracting 64 from this field. + * Example: A value of 0 represents a temperature of -64, a value of + * 255 represents a temperature of 191. */ - #define HWRM_DBG_CFG_INPUT_FLAGS_DEBUG_NOTIFY UINT32_C(0x10) + uint8_t phy_temp2; /* - * If set to 1, firmware is allowed to be unresponsive to heartbeat - * health checks, allowing for JTAG debugging scenarios where the - * debugger has the firmware processes stopped indefinitely. This - * flag has effect only on debug builds of firmware. + * This field encodes the current module index temperature in Celsius. + * This field is unsigned and the value range of 0 to 255 is used to + * indicate a temperature range from -64 to +191. The actual + * temperature is derived by subtracting 64 from this field. + * Example: A value of 0 represents a temperature of -64, a value of + * 255 represents a temperature of 191. */ - #define HWRM_DBG_CFG_INPUT_FLAGS_JTAG_DEBUG UINT32_C(0x20) + uint8_t om_temp2; /* - * Notification queue (completion ring) used by the firmware to post - * async debug notifications and fw trace logs. This field is valid - * when fw_trace, fw_trace_secondary or debug_notify flags are set. + * This field reports the device's threshold value for reporting + * a warning indication. The temperature is reported in Celsius. */ - uint16_t async_cmpl_ring; - uint8_t unused_0[2]; -} hwrm_dbg_cfg_input_t, *phwrm_dbg_cfg_input_t; - -/* hwrm_dbg_cfg_output (size:128b/16B) */ - -typedef struct hwrm_dbg_cfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint8_t warn_threshold; + /* + * This field reports the device's threshold value for reporting + * a critical indication. The temperature is reported in Celsius. + */ + uint8_t critical_threshold; + /* + * This field reports the device's threshold value for reporting + * a fatal indication. The temperature is reported in Celsius. + */ + uint8_t fatal_threshold; + /* + * This field reports the threshold value at which the device will + * a perform a self shutdown. The temperature is reported in Celsius. + * If the value is zero, then that indicates self shutdown is not + * configured. + */ + uint8_t shutdown_threshold; + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_cfg_output_t, *phwrm_dbg_cfg_output_t; +} hwrm_temp_monitor_query_output_t, *phwrm_temp_monitor_query_output_t; -/***************************** - * hwrm_dbg_crashdump_header * - *****************************/ +/************************ + * hwrm_reg_power_query * + ************************/ -/* hwrm_dbg_crashdump_header_input (size:192b/24B) */ +/* hwrm_reg_power_query_input (size:128b/16B) */ -typedef struct hwrm_dbg_crashdump_header_input { +typedef struct hwrm_reg_power_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59664,12 +63065,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint64_t unused_0; -} hwrm_dbg_crashdump_header_input_t, *phwrm_dbg_crashdump_header_input_t; +} hwrm_reg_power_query_input_t, *phwrm_reg_power_query_input_t; -/* hwrm_dbg_crashdump_header_output (size:512b/64B) */ +/* hwrm_reg_power_query_output (size:192b/24B) */ -typedef struct hwrm_dbg_crashdump_header_output { +typedef struct hwrm_reg_power_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59678,109 +63078,41 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Major version. */ - uint8_t version_hi; - /* Minor version. */ - uint8_t version_low; - /* - * Header length in bytes. This includes all fields from version - * to dev_uid (whose length is specified in dev_uid_length). - */ - uint16_t header_len; - /* This is the crash dump size in bytes. */ - uint32_t dump_size; - /* - * This is a "wall clock" timestamp value of when the crash occurred. - * Format is of time_t type. - */ - uint32_t crash_time; - /* This is the timezone information for the crash_time. */ - int8_t utc_offset; - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_UTC 0 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMSTERDAM 4 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_EGYPT 8 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_EUROPE_MOSCOW 12 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_IRAN 14 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_DUBAI 16 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_KABUL 18 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ANTARCTICA_MAWSON 20 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_COLOMBO 22 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_KATHMANDU 23 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_INDIAN_CHAGOS 24 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_INDIAN_COCOS 26 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_BANGKOK 28 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_HONG_KONG 32 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_PYONGYANG 34 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_EUCLA 35 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_TOKYO 36 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_ADELAIDE 38 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_BROKEN_HILL 38 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_DARWIN 38 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_SYDNEY 40 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_LORD_HOWE 42 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ANTARCTICA_MACQUARIE 44 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ANTARCTICA_SOUTH_POLE 48 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_CHATHAM 51 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_APIA 52 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_KIRITIMATIS 56 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ATLANTIC_CAPE_VERDE -4 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ATLANTIC_SOUTH_GEORGIA -8 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_ARGENTINA_BUENOS_AIRES -12 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_SAO_PAULO -12 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_NEWFOUNDLAND -14 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_BARBADOS -16 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_CANCUN -20 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_COSTA_RICA -24 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_PHOENIX -28 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_US_ARIZONA -28 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_US_PACIFIC -32 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_US_ALASKA -36 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_MARQUESAS -38 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_HAWAII -40 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_MIDWAY -44 - #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_LAST HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_MIDWAY - /* - * This field is a counter value of the crash dump available. This - * value is incremented monotonically at each crash. - */ - uint8_t crash_cntr; - /* - * This specifies the length of the dev_uid in bytes. The maximum - * value is 31. - */ - uint16_t dev_uid_length; + /* Describe availability of switching regulator power values. */ + uint32_t flags; + /* When this bit is set to '1', the input power is available. */ + #define HWRM_REG_POWER_QUERY_OUTPUT_FLAGS_IN_POWER_AVAILABLE UINT32_C(0x1) + /* When this bit is set to '1', the output power is available. */ + #define HWRM_REG_POWER_QUERY_OUTPUT_FLAGS_OUT_POWER_AVAILABLE UINT32_C(0x2) /* - * This is a unique device identifier (e.g. the first port MAC - * address for a network controller or a serial number for an - * en/decryption device) in ASCII format. It is used to identify - * where the crash dump content is coming from. Unused bytes must - * have '\0' character. + * The HWRM shall provide the current switching regulator + * input power in mW, if available. */ - uint8_t dev_uid[32]; + uint32_t in_power_mw; /* - * This is a count value tracking the number of successful boots - * before the crash occurred. + * The HWRM shall provide the current switching regulator + * output power in mW, if available. */ - uint32_t power_on_count; - uint8_t unused_2[3]; + uint32_t out_power_mw; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_crashdump_header_output_t, *phwrm_dbg_crashdump_header_output_t; +} hwrm_reg_power_query_output_t, *phwrm_reg_power_query_output_t; -/**************************** - * hwrm_dbg_crashdump_erase * - ****************************/ +/***************************** + * hwrm_core_frequency_query * + *****************************/ -/* hwrm_dbg_crashdump_erase_input (size:192b/24B) */ +/* hwrm_core_frequency_query_input (size:128b/16B) */ -typedef struct hwrm_dbg_crashdump_erase_input { +typedef struct hwrm_core_frequency_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59809,29 +63141,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The scope of the erase */ - uint8_t scope; - /* - * Wipe all crashdump data blocks, making them available for - * the next crash(es). This is the typical value to be used. - */ - #define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_INVALIDATE UINT32_C(0x0) - /* - * Experimental: Remove all data blocks from the directory - * (without erasing any existing contents), re-allocate and - * re-initialize new ones. In case where the crash dump feature - * stops functioning, this can be used to restore it back to the - * clean slate. - */ - #define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_REINIT UINT32_C(0x1) - #define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_LAST HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_REINIT - uint8_t unused_0[3]; - uint32_t unused_1; -} hwrm_dbg_crashdump_erase_input_t, *phwrm_dbg_crashdump_erase_input_t; +} hwrm_core_frequency_query_input_t, *phwrm_core_frequency_query_input_t; -/* hwrm_dbg_crashdump_erase_output (size:128b/16B) */ +/* hwrm_core_frequency_query_output (size:128b/16B) */ -typedef struct hwrm_dbg_crashdump_erase_output { +typedef struct hwrm_core_frequency_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59840,25 +63154,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_1[7]; + /* The HWRM shall provide the core frequency in Hz. */ + uint32_t core_frequency_hz; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_crashdump_erase_output_t, *phwrm_dbg_crashdump_erase_output_t; +} hwrm_core_frequency_query_output_t, *phwrm_core_frequency_query_output_t; -/****************** - * hwrm_dbg_qcaps * - ******************/ +/**************************** + * hwrm_reg_power_histogram * + ****************************/ -/* hwrm_dbg_qcaps_input (size:192b/24B) */ +/* hwrm_reg_power_histogram_input (size:192b/24B) */ -typedef struct hwrm_dbg_qcaps_input { +typedef struct hwrm_reg_power_histogram_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59887,18 +63203,19 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Describe operational mode of power histogram command. */ + uint32_t flags; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * When this bit is set to '1', histogram data for the respective + * client (HWRM or BMC) is cleared after read. */ - uint16_t fid; - uint8_t unused_0[6]; -} hwrm_dbg_qcaps_input_t, *phwrm_dbg_qcaps_input_t; + #define HWRM_REG_POWER_HISTOGRAM_INPUT_FLAGS_CLEAR_HISTOGRAM UINT32_C(0x1) + uint32_t unused_0; +} hwrm_reg_power_histogram_input_t, *phwrm_reg_power_histogram_input_t; -/* hwrm_dbg_qcaps_output (size:192b/24B) */ +/* hwrm_reg_power_histogram_output (size:1088b/136B) */ -typedef struct hwrm_dbg_qcaps_output { +typedef struct hwrm_reg_power_histogram_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -59907,50 +63224,136 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Describe output characteristics of power histogram command. */ + uint16_t flags; /* - * FID value. This value is used to identify operations on the PCI - * bus as belonging to a particular PCI function. + * Indicates whether input or output power is used. Some switching + * regulators provide both input and output voltage and current + * measurements, and others provide only output measurements. When + * both are available, input is used. This value is constant for a + * given board. */ - uint16_t fid; + #define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT UINT32_C(0x1) + /* + * The switching regulator's input power is used + * data. + */ + #define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_INPUT UINT32_C(0x0) + /* + * The switching regulator's output power is used + * data. + */ + #define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_OUTPUT UINT32_C(0x1) + #define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_LAST HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_OUTPUT uint8_t unused_0[2]; /* - * Bitwise field of components FW supports skipping during collection - * of coredump as part of a crash collection. + * Time in microseconds between samples. This value is constant in + * firmware. The initial design sets this constant at 10000 us (10 + * ms). Power values for voltage regulators calculate a power value + * over a 300 us period, so a 10 ms sampling period covers 3% of + * time ranges. Future firmware designs may opt for different + * sampling periods, so this value is provided on output. */ - uint32_t coredump_component_disable_caps; + uint32_t sampling_period; /* - * If 1, FW supports disabling the collection of NVM during a - * coredump taken as part of crash collection. + * Total samples taken since last clear. If no counter has + * saturated, the sum of counts in each bucket equates to this + * sample_count value. If a single counter has saturated, its value + * can be calculated by subtracting the remaining bucket values from + * this sample_count value. */ - #define HWRM_DBG_QCAPS_OUTPUT_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM UINT32_C(0x1) - uint32_t flags; - /* If 1, FW supports writing a crashdump to NVM. */ - #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_NVM UINT32_C(0x1) - /* If 1, FW supports writing a crashdump to host ddr. */ - #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_HOST_DDR UINT32_C(0x2) - /* If 1, FW supports writing a crashdump to soc ddr. */ - #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_SOC_DDR UINT32_C(0x4) - /* If 1, FW supports USEQ operations */ - #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_USEQ UINT32_C(0x8) - uint8_t unused_1[3]; + uint64_t sample_count; + /* + * The power usage expressed in histogram buckets. Bucket value + * ranges and array indices are defined per the enumeration + * power_histogram_bucket_enum. Values saturate at the max 32-bit + * value, 0xFFFFFFFF, and do not roll over. Clients should use the + * clear bit on input to clear the histogram array periodically or + * when saturation is observed. + */ + uint32_t power_hist[26]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_qcaps_output_t, *phwrm_dbg_qcaps_output_t; +} hwrm_reg_power_histogram_output_t, *phwrm_reg_power_histogram_output_t; -/***************** - * hwrm_dbg_qcfg * - *****************/ +/* + * Count of timer callback routines run with no data measured. This + * may occur when data from the switching regulator is not available + * to the firmware timer callback routine. One possible reason for + * this is contention with other users of the i2c bus which is used + * to communicate with the switching regulator, for example when a + * call to hwrm_reg_power_query occurs while the timer routine is + * running. + */ +#define BUCKET_NO_DATA_FOR_SAMPLE UINT32_C(0x0) +/* Count of samples measured at less than 8W */ +#define BUCKET_RANGE_8W_OR_LESS UINT32_C(0x1) +/* Count of samples measured >= 8 W and < 9 W */ +#define BUCKET_RANGE_8W_TO_9W UINT32_C(0x2) +/* Count of samples measured >= 9 W and < 10 W */ +#define BUCKET_RANGE_9W_TO_10W UINT32_C(0x3) +/* Count of samples measured >= 10 W and < 11 W */ +#define BUCKET_RANGE_10W_TO_11W UINT32_C(0x4) +/* Count of samples measured >= 11 W and < 12 W */ +#define BUCKET_RANGE_11W_TO_12W UINT32_C(0x5) +/* Count of samples measured >= 12 W and < 13 W */ +#define BUCKET_RANGE_12W_TO_13W UINT32_C(0x6) +/* Count of samples measured >= 13 W and < 14 W */ +#define BUCKET_RANGE_13W_TO_14W UINT32_C(0x7) +/* Count of samples measured >= 14 W and < 15 W */ +#define BUCKET_RANGE_14W_TO_15W UINT32_C(0x8) +/* Count of samples measured >= 15 W and < 16 W */ +#define BUCKET_RANGE_15W_TO_16W UINT32_C(0x9) +/* Count of samples measured >= 16 W and < 18 W */ +#define BUCKET_RANGE_16W_TO_18W UINT32_C(0xa) +/* Count of samples measured >= 18 W and < 20 W */ +#define BUCKET_RANGE_18W_TO_20W UINT32_C(0xb) +/* Count of samples measured >= 20 W and < 22 W */ +#define BUCKET_RANGE_20W_TO_22W UINT32_C(0xc) +/* Count of samples measured >= 22 W and < 24 W */ +#define BUCKET_RANGE_22W_TO_24W UINT32_C(0xd) +/* Count of samples measured >= 24 W and < 26 W */ +#define BUCKET_RANGE_24W_TO_26W UINT32_C(0xe) +/* Count of samples measured >= 26 W and < 28 W */ +#define BUCKET_RANGE_26W_TO_28W UINT32_C(0xf) +/* Count of samples measured >= 28 W and < 30 W */ +#define BUCKET_RANGE_28W_TO_30W UINT32_C(0x10) +/* Count of samples measured >= 30 W and < 32 W */ +#define BUCKET_RANGE_30W_TO_32W UINT32_C(0x11) +/* Count of samples measured >= 32 W and < 34 W */ +#define BUCKET_RANGE_32W_TO_34W UINT32_C(0x12) +/* Count of samples measured >= 34 W and < 36 W */ +#define BUCKET_RANGE_34W_TO_36W UINT32_C(0x13) +/* Count of samples measured >= 36 W and < 38 W */ +#define BUCKET_RANGE_36W_TO_38W UINT32_C(0x14) +/* Count of samples measured >= 38 W and < 40 W */ +#define BUCKET_RANGE_38W_TO_40W UINT32_C(0x15) +/* Count of samples measured >= 40 W and < 42 W */ +#define BUCKET_RANGE_40W_TO_42W UINT32_C(0x16) +/* Count of samples measured >= 42 W and < 44 W */ +#define BUCKET_RANGE_42W_TO_44W UINT32_C(0x17) +/* Count of samples measured >= 44 W and < 50 W */ +#define BUCKET_RANGE_44W_TO_50W UINT32_C(0x18) +/* Count of samples measured at 50 W or greater */ +#define BUCKET_RANGE_OVER_50W UINT32_C(0x19) +#define BUCKET_LAST BUCKET_RANGE_OVER_50W -/* hwrm_dbg_qcfg_input (size:192b/24B) */ +/************************* + * hwrm_wol_filter_alloc * + *************************/ -typedef struct hwrm_dbg_qcfg_input { + +/* hwrm_wol_filter_alloc_input (size:512b/64B) */ + +typedef struct hwrm_wol_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -59979,125 +63382,127 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t flags; + uint32_t enables; /* - * Function ID of the function that is being queried. - * 0xFF... (All Fs) if the query is for the requesting - * function. + * This bit must be '1' for the mac_address field to be + * configured. */ - uint16_t fid; - uint16_t flags; + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_MAC_ADDRESS UINT32_C(0x1) /* - * The crashdump size represents size of crashdump - * written to the specified destination. + * This bit must be '1' for the pattern_offset field to be + * configured. */ - #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK UINT32_C(0x3) - #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 - /* crashdump size written to nvm */ - #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM UINT32_C(0x0) - /* crashdump size written to host_ddr */ - #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR UINT32_C(0x1) - /* crashdump size written to soc_ddr */ - #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR UINT32_C(0x2) - #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR - /* - * Bitwise field of components requested for FW to skip when - * calculating the size of a coredump collection. - */ - uint32_t coredump_component_disable_flags; - /* - * If 1, NVM will not be collected during a coredump taken as part - * of crash collection. - */ - #define HWRM_DBG_QCFG_INPUT_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM UINT32_C(0x1) -} hwrm_dbg_qcfg_input_t, *phwrm_dbg_qcfg_input_t; - -/* hwrm_dbg_qcfg_output (size:256b/32B) */ - -typedef struct hwrm_dbg_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_OFFSET UINT32_C(0x2) /* - * FID value. This value is used to identify operations on the PCI - * bus as belonging to a particular PCI function. + * This bit must be '1' for the pattern_buf_size field to be + * configured. */ - uint16_t fid; - uint8_t unused_0[2]; + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_SIZE UINT32_C(0x4) /* - * Size in bytes of a coredump file created by the FW. This takes into - * consideration any components selected in the - * coredump_component_disable_flags field from hwrm_dbg_qcfg_input. + * This bit must be '1' for the pattern_buf_addr field to be + * configured. */ - uint32_t coredump_size; - uint32_t flags; + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_ADDR UINT32_C(0x8) /* - * If set to 1, then UART logging is enabled for the primary - * firmware. Disabled otherwise. + * This bit must be '1' for the pattern_mask_addr field to be + * configured. */ - #define HWRM_DBG_QCFG_OUTPUT_FLAGS_UART_LOG UINT32_C(0x1) + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_ADDR UINT32_C(0x10) /* - * If set to 1, then UART logging is enabled for the secondary - * firmware. Disabled otherwise. + * This bit must be '1' for the pattern_mask_size field to be + * configured. */ - #define HWRM_DBG_QCFG_OUTPUT_FLAGS_UART_LOG_SECONDARY UINT32_C(0x2) + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_SIZE UINT32_C(0x20) + /* Port ID of port on which WoL filter is configured. */ + uint16_t port_id; + /* This value represents a Wake-on-LAN type. */ + uint8_t wol_type; + /* Magic Packet */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0) + /* Bitmap */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_BMP UINT32_C(0x1) + /* Invalid */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_INVALID UINT32_C(0xff) + #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_LAST HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_INVALID + uint8_t unused_0[5]; /* - * If set to 1, then completion ring logging is enabled for the - * primary firmware. Disabled otherwise. + * # If this field is enabled and magic packet WoL filter + * type is specified in this command, the value set in this + * field shall be used in setting the magic packet based + * WoL filter. + * # If this field is not enabled and magic packet WoL + * filter type is specified and port id is specified to + * 0xFF in this command, then the HWRM + * shall use default MAC address configured on the + * function associated with the HWRM client. + * # If this field is not enabled and magic packet WoL + * filter type is specified and port id is not specified to + * 0xFF in this command, then the HWRM + * shall use default MAC address configured on the port. */ - #define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE UINT32_C(0x4) + uint8_t mac_address[6]; /* - * If set to 1, then completion ring logging is enabled for the - * secondary firmware. Disabled otherwise. + * The offset from the beginning of MAC header where + * pattern should be matched. + * Applies to bitmap WoL. */ - #define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE_SECONDARY UINT32_C(0x8) + uint16_t pattern_offset; /* - * If set to 1, firmware will generate debug_notification async - * events to the driver as applicable. + * The size of the pattern that is being matched. + * Applies to bitmap WoL. */ - #define HWRM_DBG_QCFG_OUTPUT_FLAGS_DEBUG_NOTIFY UINT32_C(0x10) + uint16_t pattern_buf_size; /* - * If set to 1, firmware is allowed to be unresponsive to heartbeat - * health checks, allowing for JTAG debugging scenarios where the - * debugger has the firmware processes stopped indefinitely. This - * flag has effect only on debug builds of firmware. + * The size of the pattern mask. + * Applies to bitmap WoL. */ - #define HWRM_DBG_QCFG_OUTPUT_FLAGS_JTAG_DEBUG UINT32_C(0x20) + uint16_t pattern_mask_size; + uint8_t unused_1[4]; /* - * Notification queue (completion ring) used by the firmware to post - * async debug notifications and fw trace logs. This field is valid - * when fw_trace, fw_trace_secondary or debug_notify flags are set. + * Physical address of the pattern buffer. + * Applies to bitmap WoL. */ - uint16_t async_cmpl_ring; - uint8_t unused_2[2]; + uint64_t pattern_buf_addr; /* - * Size in bytes of a crashdump file created by the FW. Uses input - * flags to determine medium destination and corresponding size. + * Physical address of the pattern mask. + * Applies to bitmap WoL. */ - uint32_t crashdump_size; - uint8_t unused_3[3]; + uint64_t pattern_mask_addr; +} hwrm_wol_filter_alloc_input_t, *phwrm_wol_filter_alloc_input_t; + +/* hwrm_wol_filter_alloc_output (size:128b/16B) */ + +typedef struct hwrm_wol_filter_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value identifies a Wake-on-LAN (WoL) filter. */ + uint8_t wol_filter_id; + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_qcfg_output_t, *phwrm_dbg_qcfg_output_t; +} hwrm_wol_filter_alloc_output_t, *phwrm_wol_filter_alloc_output_t; -/********************************* - * hwrm_dbg_crashdump_medium_cfg * - *********************************/ +/************************ + * hwrm_wol_filter_free * + ************************/ -/* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ +/* hwrm_wol_filter_free_input (size:256b/32B) */ -typedef struct hwrm_dbg_crashdump_medium_cfg_input { +typedef struct hwrm_wol_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60126,62 +63531,34 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t output_dest_flags; - /* Destination is DDR ram. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_TYPE_DDR UINT32_C(0x1) - uint16_t pg_size_lvl; - /* PBL indirect levels. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_MASK UINT32_C(0x3) - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_1 UINT32_C(0x1) + uint32_t flags; /* - * PBL pointer points to PDE table with each entry pointing to - * PTE tables. + * # When this bit is set to '1', then all active WoL + * filters on the port are requested to be freed. + * # If the a function driver sets this flag to '1', then + * the HWRM shall free all active WoL filters that are not + * set by other function drivers on that port. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_2 UINT32_C(0x2) - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LAST HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_2 - /* page size. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_MASK UINT32_C(0x1c) - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_SFT 2 - /* 4KB. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_4K (UINT32_C(0x0) << 2) - /* 8KB. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_8K (UINT32_C(0x1) << 2) - /* 64KB. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_64K (UINT32_C(0x2) << 2) - /* 2MB. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_2M (UINT32_C(0x3) << 2) - /* 8MB. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_8M (UINT32_C(0x4) << 2) - /* 1GB. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_1G (UINT32_C(0x5) << 2) - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_LAST HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_1G - /* unused11 is 11 b */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_UNUSED11_MASK UINT32_C(0xffe0) - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_UNUSED11_SFT 5 - /* Crashdump buffer size. */ - uint32_t size; + #define HWRM_WOL_FILTER_FREE_INPUT_FLAGS_FREE_ALL_WOL_FILTERS UINT32_C(0x1) + uint32_t enables; /* - * Bitwise field of components that FW is requested to skip during - * coredump as part of a crash collection. + * This bit must be '1' for the wol_filter_id field to be + * configured. */ - uint32_t coredump_component_disable_flags; + #define HWRM_WOL_FILTER_FREE_INPUT_ENABLES_WOL_FILTER_ID UINT32_C(0x1) + /* Port ID of the port on which WoL filter(s) is (are) being freed. */ + uint16_t port_id; /* - * If 1, then NVM will not be collected during a coredump taken as - * part of crash collection. + * The HWRM shall ignore this field if free_all_wol_filters + * flag is set. */ - #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_NVRAM UINT32_C(0x1) - uint32_t unused_0; - /* Crashdump buffer PBL physical address. */ - uint64_t pbl; -} hwrm_dbg_crashdump_medium_cfg_input_t, *phwrm_dbg_crashdump_medium_cfg_input_t; + uint8_t wol_filter_id; + uint8_t unused_0[5]; +} hwrm_wol_filter_free_input_t, *phwrm_wol_filter_free_input_t; -/* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ +/* hwrm_wol_filter_free_output (size:128b/16B) */ -typedef struct hwrm_dbg_crashdump_medium_cfg_output { +typedef struct hwrm_wol_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60190,58 +63567,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_1[7]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_crashdump_medium_cfg_output_t, *phwrm_dbg_crashdump_medium_cfg_output_t; - -/* coredump_segment_record (size:128b/16B) */ - -typedef struct coredump_segment_record { - /* Component id of the returned component. */ - uint16_t component_id; - /* Segment id of the returned component. */ - uint16_t segment_id; - /* Not used. */ - uint16_t max_instances; - /* Major version. */ - uint8_t version_hi; - /* Minor version. */ - uint8_t version_low; - /* - * bit 0: live data - * bit 1: crashed data - */ - uint8_t seg_flags; - /* This field is used to indicate the segment is compressed. */ - uint8_t compress_flags; - /* - * SFLAG_COMPRESSED_ZLIB indicates that the segment data is - * compressed. - */ - #define SFLAG_COMPRESSED_ZLIB UINT32_C(0x1) - uint8_t unused_0[2]; - /* - * This field is the length of the segment data. It will be zero if - * the firmware does not support returning the segment data length. - */ - uint32_t segment_len; -} coredump_segment_record_t, *pcoredump_segment_record_t; +} hwrm_wol_filter_free_output_t, *phwrm_wol_filter_free_output_t; -/************************** - * hwrm_dbg_coredump_list * - **************************/ +/************************ + * hwrm_wol_filter_qcfg * + ************************/ -/* hwrm_dbg_coredump_list_input (size:256b/32B) */ +/* hwrm_wol_filter_qcfg_input (size:448b/56B) */ -typedef struct hwrm_dbg_coredump_list_input { +typedef struct hwrm_wol_filter_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60270,28 +63614,59 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Port ID of port on which WoL filter that is being queried. */ + uint16_t port_id; /* - * host address where the data content will be written - * when the request is complete. This area must be 16B aligned. + * This is an opaque handle used to access filters. + * # The HWRM client shall set this field to 0x0000 to begin + * the query. + * # After the first query, the HWRM client shall retrieve + * next filters (if they exist) using the HWRM provided handle + * in the response. */ - uint64_t host_dest_addr; - /* Length of host buffer used for transferring debug data. */ - uint32_t host_buf_len; - /* Sequence number of the request. Starts at 0. */ - uint16_t seq_no; - /* */ - uint8_t flags; + uint16_t handle; + uint8_t unused_0[4]; /* - * If set to 1, crash dump is requested. - * If set to 0, both live core and crash dump are requested. + * Physical address of the pattern buffer. + * Applies to bitmap WoL filter only. + * # Value of 0 indicates an invalid buffer address. + * If this field is set to 0, then HWRM shall ignore + * pattern_buf_size. + * # If the HWRM client provides an invalid buffer address + * for the pattern, then the HWRM is not required to + * provide pattern when the response contains a bitmap WoL + * filter. */ - #define HWRM_DBG_COREDUMP_LIST_INPUT_FLAGS_CRASHDUMP UINT32_C(0x1) - uint8_t unused_0[1]; -} hwrm_dbg_coredump_list_input_t, *phwrm_dbg_coredump_list_input_t; + uint64_t pattern_buf_addr; + /* + * The size of the pattern buffer. + * Applies to bitmap WoL filter only. + */ + uint16_t pattern_buf_size; + uint8_t unused_1[6]; + /* + * Physical address of the pattern mask. + * Applies to bitmap WoL filter only. + * # Value of 0 indicates an invalid pattern mask address. + * If this field is set to 0, then HWRM shall ignore + * pattern_mask_size. + * # If the HWRM client provides an invalid mask address + * for the pattern, then the HWRM is not required to + * provide mask when the response contains a bitmap WoL + * filter. + */ + uint64_t pattern_mask_addr; + /* + * The size of the buffer for pattern mask. + * Applies to bitmap WoL filter only. + */ + uint16_t pattern_mask_size; + uint8_t unused_2[6]; +} hwrm_wol_filter_qcfg_input_t, *phwrm_wol_filter_qcfg_input_t; -/* hwrm_dbg_coredump_list_output (size:128b/16B) */ +/* hwrm_wol_filter_qcfg_output (size:256b/32B) */ -typedef struct hwrm_dbg_coredump_list_output { +typedef struct hwrm_wol_filter_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60300,36 +63675,78 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t flags; /* - * Value of 1 means that there is more data available. - * Issue the request again with the next sequence number. + * This is the next handle that is used to access filters. + * # If this field is set to 0x0000, then no WoL filters are + * currently configured on this port and all other fields in + * the output shall be ignored by the HWRM client. + * # If this field is set to neither 0x0000 nor 0xFFFF, then the + * wol_filter_id is valid and the parameters provided in the + * response are based on the wol_type. + * # If this field is set to 0xFFFF, then there are no remaining + * configured WoL filters to be queried for the queried function + * after this response, wol_filter_id is valid and the parameters + * provided in the response are based on the wol_type. */ - #define HWRM_DBG_COREDUMP_LIST_OUTPUT_FLAGS_MORE UINT32_C(0x1) - uint8_t unused_0; - /* Total number of segments to be returned. */ - uint16_t total_segments; - /* Actual length of data returned in bytes. */ - uint16_t data_len; - uint8_t unused_1; + uint16_t next_handle; + /* + * This value identifies the filter returned in this + * response. + */ + uint8_t wol_filter_id; + /* + * This value identifies the type of WoL filter returned + * in this response. + */ + uint8_t wol_type; + /* Magic Packet */ + #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0) + /* Bitmap */ + #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_BMP UINT32_C(0x1) + /* Invalid */ + #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_INVALID UINT32_C(0xff) + #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_LAST HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_INVALID + uint32_t unused_0; + /* + * The MAC address value used by the WoL filter. + * Applies to magic packet based WoL. + */ + uint8_t mac_address[6]; + /* + * The offset from the beginning of MAC header where + * pattern should be matched. + * Applies to bitmap WoL. + */ + uint16_t pattern_offset; + /* + * The actual size of the pattern that is being returned. + * Applies to bitmap WoL. + */ + uint16_t pattern_size; + /* + * The actual size of the pattern mask that is being returned. + * Applies to bitmap WoL. + */ + uint16_t pattern_mask_size; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_coredump_list_output_t, *phwrm_dbg_coredump_list_output_t; +} hwrm_wol_filter_qcfg_output_t, *phwrm_wol_filter_qcfg_output_t; -/****************************** - * hwrm_dbg_coredump_initiate * - ******************************/ +/************************ + * hwrm_wol_reason_qcfg * + ************************/ -/* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ +/* hwrm_wol_reason_qcfg_input (size:320b/40B) */ -typedef struct hwrm_dbg_coredump_initiate_input { +typedef struct hwrm_wol_reason_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60358,26 +63775,22 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Component id of the returned component. */ - uint16_t component_id; - /* Segment id of the returned component. */ - uint16_t segment_id; - /* Not used. */ - uint16_t instance; - /* Not used. */ - uint16_t unused_0; + /* Port ID of port for which this query is for. */ + uint16_t port_id; + uint8_t unused_0[6]; /* - * bit 0: live data - * bit 1: crashed data + * Physical address of the packet buffer for querying + * WoL packet. */ - uint8_t seg_flags; - /* Not used. */ - uint8_t unused_1[7]; -} hwrm_dbg_coredump_initiate_input_t, *phwrm_dbg_coredump_initiate_input_t; + uint64_t wol_pkt_buf_addr; + /* The size of the buffer for the WoL packet. */ + uint16_t wol_pkt_buf_size; + uint8_t unused_1[6]; +} hwrm_wol_reason_qcfg_input_t, *phwrm_wol_reason_qcfg_input_t; -/* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ +/* hwrm_wol_reason_qcfg_output (size:128b/16B) */ -typedef struct hwrm_dbg_coredump_initiate_output { +typedef struct hwrm_wol_reason_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60386,47 +63799,48 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * This value identifies the filter that matched + * the last WoL packet. + * This id is only valid with valid WoL reason. + */ + uint8_t wol_filter_id; + /* + * This value identifies the type of WoL reason returned + * in this response. + * When the wol_type is set to invalid, then there is + * no WoL event that happened during last system + * wake-up. + */ + uint8_t wol_reason; + /* Magic Packet */ + #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_MAGICPKT UINT32_C(0x0) + /* Bitmap */ + #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_BMP UINT32_C(0x1) + /* Invalid */ + #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_INVALID UINT32_C(0xff) + #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_LAST HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_INVALID + /* The value identifies the length of the WoL packet in bytes. */ + uint8_t wol_pkt_len; + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_coredump_initiate_output_t, *phwrm_dbg_coredump_initiate_output_t; - -/* coredump_data_hdr (size:128b/16B) */ - -typedef struct coredump_data_hdr { - /* Starting address of the register range. */ - uint32_t address; - /* - * length: 0 - 23 bits represents the actual data without the pad. - * flags: 24 - 31 bits represents indirect register ranges. - * - bit 24: Set if registers in this segment are indirect accessed. - */ - uint32_t flags_length; - /* These bits represents the actual length of the data segment */ - #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK UINT32_C(0xffffff) - #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 - /* Set if registers in this segment are indirect accessed. */ - #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS UINT32_C(0x1000000) - /* Value in the partner register for indirect or multi-field registers. */ - uint32_t instance; - /* Starting address of the next register after the current data range */ - uint32_t next_offset; -} coredump_data_hdr_t, *pcoredump_data_hdr_t; +} hwrm_wol_reason_qcfg_output_t, *phwrm_wol_reason_qcfg_output_t; -/****************************** - * hwrm_dbg_coredump_retrieve * - ******************************/ +/************************ + * hwrm_dbg_read_direct * + ************************/ -/* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ +/* hwrm_dbg_read_direct_input (size:256b/32B) */ -typedef struct hwrm_dbg_coredump_retrieve_input { +typedef struct hwrm_dbg_read_direct_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60457,38 +63871,18 @@ uint64_t resp_addr; /* * host address where the data content will be written - * when the request is complete. This area must be 16B aligned. + * when the request is complete. This area must be 16B aligned. */ uint64_t host_dest_addr; - /* Length of host buffer used for transferring debug data. */ - uint32_t host_buf_len; - /* Not used. */ - uint32_t unused_0; - /* Component id of the returned component. */ - uint16_t component_id; - /* Segment id of the returned component. */ - uint16_t segment_id; - /* Not used. */ - uint16_t instance; - /* Not used. */ - uint16_t unused_1; - /* - * bit 0: live data - * bit 1: crashed data - */ - uint8_t seg_flags; - uint8_t unused_2; - uint16_t unused_3; - /* Not used. */ - uint32_t unused_4; - /* Sequence number is used per segment request. Starts at 0. */ - uint32_t seq_no; - uint32_t unused_5; -} hwrm_dbg_coredump_retrieve_input_t, *phwrm_dbg_coredump_retrieve_input_t; + /* address(in ChiMP view) to start reading */ + uint32_t read_addr; + /* number of dwords to read */ + uint32_t read_len32; +} hwrm_dbg_read_direct_input_t, *phwrm_dbg_read_direct_input_t; -/* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ +/* hwrm_dbg_read_direct_output (size:128b/16B) */ -typedef struct hwrm_dbg_coredump_retrieve_output { +typedef struct hwrm_dbg_read_direct_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60497,34 +63891,31 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t flags; /* - * Value of 1 means that there is more data available. - * Issue the request again with the next sequence number. + * This field, if not zero, contains the IEEE 802.3 CRC-32 checksum of + * the number of dwords read in this request using this polynomial: + * x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ - #define HWRM_DBG_COREDUMP_RETRIEVE_OUTPUT_FLAGS_MORE UINT32_C(0x1) - uint8_t unused_0; - /* Actual length of data returned in bytes. */ - uint16_t data_len; - uint8_t unused_1[3]; + uint32_t crc32; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_coredump_retrieve_output_t, *phwrm_dbg_coredump_retrieve_output_t; +} hwrm_dbg_read_direct_output_t, *phwrm_dbg_read_direct_output_t; -/******************** - * hwrm_dbg_i2c_cmd * - ********************/ +/************************* + * hwrm_dbg_write_direct * + *************************/ -/* hwrm_dbg_i2c_cmd_input (size:320b/40B) */ +/* hwrm_dbg_write_direct_input (size:448b/56B) */ -typedef struct hwrm_dbg_i2c_cmd_input { +typedef struct hwrm_dbg_write_direct_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60553,54 +63944,17 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * host address where the data content will be read or written. - * For master write, data content will be read from host memory and write - * to i2c slave. (size defined by write_size) - * For master read, data content will be read from i2c slave and write to - * the host memory. (size defined by read_size) - * For master write/read, data content will be first read from host memory - * and write to i2c slave. (size defined by write_size) then data read from - * i2c slave will be written back to the same host memory. (size defined by read_size) - */ - uint64_t host_dest_addr; - /* read size in bytes, valid only for master read and write/read */ - uint16_t read_size; - /* write size in bytes, valid only for master write and write/read */ - uint16_t write_size; - /* - * instance of i2c channel for this operation. Valid if multiple instances - * of i2c channels are connected to external i2c devices. - */ - uint8_t chnl_id; - uint8_t options; - /* - * This bit must be '1' for 10-bit i2c addressing, - * 7-bit addressing otherwise. - */ - #define HWRM_DBG_I2C_CMD_INPUT_OPTIONS_10_BIT_ADDRESSING UINT32_C(0x1) - /* - * This bit must be '1' for 400 kbit/s, 100 kbit/s - * otherwise. - */ - #define HWRM_DBG_I2C_CMD_INPUT_OPTIONS_FAST_MODE UINT32_C(0x2) - /* I2C slave address. */ - uint16_t slave_addr; - /* I2C transfer mode. */ - uint8_t xfer_mode; - /* read data from slave device */ - #define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_READ UINT32_C(0x0) - /* write data to slave device */ - #define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE UINT32_C(0x1) - /* write follow by read data from slave device */ - #define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE_READ UINT32_C(0x2) - #define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_LAST HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE_READ - uint8_t unused_1[7]; -} hwrm_dbg_i2c_cmd_input_t, *phwrm_dbg_i2c_cmd_input_t; + /* address(in ChiMP view) to start writing */ + uint32_t write_addr; + /* number of dwords to write (up to 8 dwords) */ + uint32_t write_len32; + /* write data (up to 8 dwords) */ + uint32_t write_data[8]; +} hwrm_dbg_write_direct_input_t, *phwrm_dbg_write_direct_input_t; -/* hwrm_dbg_i2c_cmd_output (size:128b/16B) */ +/* hwrm_dbg_write_direct_output (size:128b/16B) */ -typedef struct hwrm_dbg_i2c_cmd_output { +typedef struct hwrm_dbg_write_direct_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60612,22 +63966,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_i2c_cmd_output_t, *phwrm_dbg_i2c_cmd_output_t; +} hwrm_dbg_write_direct_output_t, *phwrm_dbg_write_direct_output_t; -/******************* - * hwrm_dbg_fw_cli * - *******************/ +/************************** + * hwrm_dbg_read_indirect * + **************************/ -/* hwrm_dbg_fw_cli_input (size:1024b/128B) */ +/* hwrm_dbg_read_indirect_input (size:640b/80B) */ -typedef struct hwrm_dbg_fw_cli_input { +typedef struct hwrm_dbg_read_indirect_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60657,22 +64011,87 @@ */ uint64_t resp_addr; /* - * Address of the host buffer where debug CLI data - * is requested to be dumped. + * host address where the data content will be written + * when the request is complete. This area must be 16B aligned. */ uint64_t host_dest_addr; /* Length of host buffer used for transferring debug data. */ - uint32_t host_buf_len; - /* Length of CLI command. */ - uint16_t cli_cmd_len; - uint8_t unused_0[2]; - /* CLI command string, a single ASCII encoded null terminated string. */ - uint8_t cli_cmd[96]; -} hwrm_dbg_fw_cli_input_t, *phwrm_dbg_fw_cli_input_t; + uint32_t host_dest_addr_len; + /* Indirect access type to on-chip data structures. */ + uint8_t indirect_access_type; + /* L2 Mgmt filters in Transmit Engine (TE) */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 UINT32_C(0x0) + /* L3/L4 Mgmt filters in Transmit Engine (TE) */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 UINT32_C(0x1) + /* L2 Mgmt filters in Receive Engine (RE) */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 UINT32_C(0x2) + /* L3/L4 Mgmt filters in Receive Engine (RE) */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 UINT32_C(0x3) + /* Statistics contexts */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS UINT32_C(0x4) + /* TX L2 TCAM */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM UINT32_C(0x5) + /* RX L2 TCAM */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM UINT32_C(0x6) + /* TX IPv6 subnet TCAM */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM UINT32_C(0x7) + /* RX IPv6 subnet TCAM */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM UINT32_C(0x8) + /* TX source properties TCAM */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9) + /* RX source properties TCAM */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa) + /* VEB Lookup TCAM */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM UINT32_C(0xb) + /* TX Profile Lookup TCAM */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc) + /* RX Profile Lookup TCAM */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd) + /* TX Lookup TCAM */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM UINT32_C(0xe) + /* RX Lookup TCAM */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM UINT32_C(0xf) + /* MHB registers (valid for multi-host environment) */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB UINT32_C(0x10) + /* PCIE global registers (valid for multi-host environment) */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL UINT32_C(0x11) + /* SOC registers (valid for multi-host environment) */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC UINT32_C(0x12) + /* PCIE private registers */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_PRIVATE UINT32_C(0x13) + /* Host DMA read */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_HOST_DMA UINT32_C(0x14) + /* + * Elog (valid for only smartNIC only) + * Three sub-types will be supported which will be specified + * in the opaque[0] field. + * 1) sub-type CHECK(0) if ELOG is available in media. + * 2) sub-type READ(1) a portion of the elog. + * 3) sub-type ERASE(2) a portion of the elog. + * > opaque[1] Erase offset. + * > opaque[2] Erase size. + */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_SOC_ELOG UINT32_C(0x15) + /* Context operation */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CTX UINT32_C(0x16) + /* Port Stats */ + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS UINT32_C(0x17) + #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_LAST HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS + uint8_t unused_0[3]; + /* Entry number to start reading */ + uint32_t start_index; + /* Total number of entries to read */ + uint32_t num_of_entries; + /* + * command dependent data (e.g. function id for host dma command or + * sub-code, erase offset and erase size for soc_elog) + */ + uint32_t opaque[10]; +} hwrm_dbg_read_indirect_input_t, *phwrm_dbg_read_indirect_input_t; -/* hwrm_dbg_fw_cli_output (size:128b/16B) */ +/* hwrm_dbg_read_indirect_output (size:128b/16B) */ -typedef struct hwrm_dbg_fw_cli_output { +typedef struct hwrm_dbg_read_indirect_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60681,27 +64100,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Size of debug CLI data returned in bytes. */ - uint32_t cli_data_len; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_fw_cli_output_t, *phwrm_dbg_fw_cli_output_t; +} hwrm_dbg_read_indirect_output_t, *phwrm_dbg_read_indirect_output_t; -/************************** - * hwrm_dbg_ring_info_get * - **************************/ +/*************************** + * hwrm_dbg_write_indirect * + ***************************/ -/* hwrm_dbg_ring_info_get_input (size:192b/24B) */ +/* hwrm_dbg_write_indirect_input (size:832b/104B) */ -typedef struct hwrm_dbg_ring_info_get_input { +typedef struct hwrm_dbg_write_indirect_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60730,25 +64147,72 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* Notification Queue (NQ) */ - #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_NQ UINT32_C(0x3) - #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_LAST HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_NQ + /* Indirect access type to on-chip data structures. */ + uint8_t indirect_access_type; + /* L2 Mgmt filters in Transmit Engine (TE) */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 UINT32_C(0x0) + /* L3/L4 Mgmt filters in Transmit Engine (TE) */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 UINT32_C(0x1) + /* L2 Mgmt filters in Receive Engine (RE) */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 UINT32_C(0x2) + /* L3/L4 Mgmt filters in Receive Engine (RE) */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 UINT32_C(0x3) + /* Statistics contexts */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS UINT32_C(0x4) + /* TX L2 TCAM */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM UINT32_C(0x5) + /* RX L2 TCAM */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM UINT32_C(0x6) + /* TX IPv6 subnet TCAM */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM UINT32_C(0x7) + /* RX IPv6 subnet TCAM */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM UINT32_C(0x8) + /* TX source properties TCAM */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9) + /* RX source properties TCAM */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa) + /* VEB Lookup TCAM */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM UINT32_C(0xb) + /* TX Profile Lookup TCAM */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc) + /* RX Profile Lookup TCAM */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd) + /* TX Lookup TCAM */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM UINT32_C(0xe) + /* RX Lookup TCAM */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM UINT32_C(0xf) + /* MHB registers (valid for multi-host environment) */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB UINT32_C(0x10) + /* PCIE global registers (valid for multi-host environment) */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL UINT32_C(0x11) + /* SOC registers (valid for multi-host environment) */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC UINT32_C(0x12) + /* PCIE private registers */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_PRIVATE UINT32_C(0x13) + /* Host DMA write */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_HOST_DMA UINT32_C(0x14) + /* Invalid */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_SOC_ELOG UINT32_C(0x15) + /* Context operation */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CTX UINT32_C(0x16) + /* Port Stats */ + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS UINT32_C(0x17) + #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_LAST HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS uint8_t unused_0[3]; - /* Firmware ring ID associated with ring being queried. */ - uint32_t fw_ring_id; -} hwrm_dbg_ring_info_get_input_t, *phwrm_dbg_ring_info_get_input_t; + /* Entry number to start reading */ + uint32_t start_index; + /* Total number of entries to read */ + uint32_t num_of_entries; + uint8_t unused_1[4]; + /* write data (up to 8 dwords) */ + uint32_t write_data[8]; + /* command dependent data (e.g. function id for host dma command) */ + uint32_t opaque[10]; +} hwrm_dbg_write_indirect_input_t, *phwrm_dbg_write_indirect_input_t; -/* hwrm_dbg_ring_info_get_output (size:192b/24B) */ +/* hwrm_dbg_write_indirect_output (size:128b/16B) */ -typedef struct hwrm_dbg_ring_info_get_output { +typedef struct hwrm_dbg_write_indirect_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60757,34 +64221,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Producer index for the queried ring. */ - uint32_t producer_index; - /* Consumer index for the queried ring. */ - uint32_t consumer_index; - /* - * CAG Vector Control for the queried NQ ring. - * Not valid for other ring types. - */ - uint32_t cag_vector_ctrl; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_ring_info_get_output_t, *phwrm_dbg_ring_info_get_output_t; +} hwrm_dbg_write_indirect_output_t, *phwrm_dbg_write_indirect_output_t; -/********************** - * hwrm_dbg_drv_trace * - **********************/ +/***************** + * hwrm_dbg_dump * + *****************/ -/* hwrm_dbg_drv_trace_input (size:1024b/128B) */ +/* hwrm_dbg_dump_input (size:320b/40B) */ -typedef struct hwrm_dbg_drv_trace_input { +typedef struct hwrm_dbg_dump_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60813,32 +64268,25 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Severity of the message. */ - uint8_t severity; - /* Fatal */ - #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_FATAL UINT32_C(0x0) - /* Error */ - #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_ERROR UINT32_C(0x1) - /* Warning */ - #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_WARNING UINT32_C(0x2) - /* Info */ - #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_INFO UINT32_C(0x3) - /* Debug */ - #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_DEBUG UINT32_C(0x4) - #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_LAST HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_DEBUG - /* Number of bytes to write including terminating 'NULL' if any. */ - uint8_t write_len; - uint8_t unused_0[6]; /* - * This field represents the debug data sent by driver - * ASCII chars, 'NULL' termination not required. + * Handle used to dump debug data. + * handle = 0 indicates the beginning of the dump. + * handle != 0 indicates the request to dump the next part. */ - char trace_data[104]; -} hwrm_dbg_drv_trace_input_t, *phwrm_dbg_drv_trace_input_t; + uint32_t handle; + uint8_t unused_0[4]; + /* + * Address of the host buffer where the debug data is + * requested to be dumped. + */ + uint64_t host_dbg_dump_addr; + /* Length of host buffer used for transferring debug data. */ + uint64_t host_dbg_dump_addr_len; +} hwrm_dbg_dump_input_t, *phwrm_dbg_dump_input_t; -/* hwrm_dbg_drv_trace_output (size:128b/16B) */ +/* hwrm_dbg_dump_output (size:192b/24B) */ -typedef struct hwrm_dbg_drv_trace_output { +typedef struct hwrm_dbg_dump_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60847,25 +64295,39 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* + * Handle used to indicate availability of additional + * debug data. + * nexthandle = 0 indicates that there is no more debug data + * available. + * nexthandle != 0 indicates the handle value that should be used + * to request the next part of debug data. + */ + uint32_t nexthandle; + /* + * The number of bytes of debug data written to debug dump + * buffer. + */ + uint32_t dbg_data_len; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_dbg_drv_trace_output_t, *phwrm_dbg_drv_trace_output_t; +} hwrm_dbg_dump_output_t, *phwrm_dbg_dump_output_t; -/*********************** - * hwrm_dbg_useq_alloc * - ***********************/ +/********************** + * hwrm_dbg_erase_nvm * + **********************/ -/* hwrm_dbg_useq_alloc_input (size:192b/24B) */ +/* hwrm_dbg_erase_nvm_input (size:192b/24B) */ -typedef struct hwrm_dbg_useq_alloc_input { +typedef struct hwrm_dbg_erase_nvm_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60894,17 +64356,15 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Number size of the allocation, in bytes, for the USEQ in the code words array */ - uint32_t size; - /* Number of bytes executing the USEQ will produce. Must be a multiple of 4 */ - uint16_t output_bytes; - /* This field is reserved */ - uint16_t unused_0; -} hwrm_dbg_useq_alloc_input_t, *phwrm_dbg_useq_alloc_input_t; + uint16_t flags; + /* If set to 1, then erase all locations in persistent storage. */ + #define HWRM_DBG_ERASE_NVM_INPUT_FLAGS_ERASE_ALL UINT32_C(0x1) + uint8_t unused_0[6]; +} hwrm_dbg_erase_nvm_input_t, *phwrm_dbg_erase_nvm_input_t; -/* hwrm_dbg_useq_alloc_output (size:256b/32B) */ +/* hwrm_dbg_erase_nvm_output (size:128b/16B) */ -typedef struct hwrm_dbg_useq_alloc_output { +typedef struct hwrm_dbg_erase_nvm_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60913,45 +64373,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Non-zero firmware timestamp */ - uint32_t nz_fw_timestamp; - /* The last selected USID */ - uint16_t last_usid; - /* The number of USEQs currently allocated */ - uint16_t num_useq_allocd; - /* Flags indicating current USEQ engine state */ - uint32_t useq_resp_flags; - /* When set, there is at least some data available to be delivered */ - #define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) - /* When set, all internal buffers are full */ - #define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) - #define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW - /* Current count of the number of full buffers available for delivery */ - uint8_t full_cnt; - /* Reserved */ - uint8_t useq_resp_unused_0[3]; - /* This is the allocated usid */ - uint16_t alloc_usid; - /* This field is reserved */ - uint16_t unused_0; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint32_t valid; -} hwrm_dbg_useq_alloc_output_t, *phwrm_dbg_useq_alloc_output_t; + uint8_t valid; +} hwrm_dbg_erase_nvm_output_t, *phwrm_dbg_erase_nvm_output_t; -/********************** - * hwrm_dbg_useq_free * - **********************/ +/**************** + * hwrm_dbg_cfg * + ****************/ -/* hwrm_dbg_useq_free_input (size:192b/24B) */ +/* hwrm_dbg_cfg_input (size:192b/24B) */ -typedef struct hwrm_dbg_useq_free_input { +typedef struct hwrm_dbg_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -60980,15 +64420,52 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The USID of the sequence to free */ - uint16_t usid; - /* This field is reserved */ - uint8_t unused_0[6]; -} hwrm_dbg_useq_free_input_t, *phwrm_dbg_useq_free_input_t; + uint32_t flags; + /* + * If set to 1, then UART logging will be enabled for the primary + * firmware. Disabled otherwise. + */ + #define HWRM_DBG_CFG_INPUT_FLAGS_UART_LOG UINT32_C(0x1) + /* + * If set to 1, then UART logging will be enabled for the secondary + * firmware. Disabled otherwise. If a single UART is available then + * setting this bit will override the uart_log bit. + */ + #define HWRM_DBG_CFG_INPUT_FLAGS_UART_LOG_SECONDARY UINT32_C(0x2) + /* + * If set to 1, then completion ring logging will be enabled for the + * primary firmware. Disabled otherwise. + */ + #define HWRM_DBG_CFG_INPUT_FLAGS_FW_TRACE UINT32_C(0x4) + /* + * If set to 1, then completion ring logging will be enabled for the + * secondary firmware. Disabled otherwise. + */ + #define HWRM_DBG_CFG_INPUT_FLAGS_FW_TRACE_SECONDARY UINT32_C(0x8) + /* + * If set to 1, firmware will generate debug_notification async + * events to the driver as applicable. + */ + #define HWRM_DBG_CFG_INPUT_FLAGS_DEBUG_NOTIFY UINT32_C(0x10) + /* + * If set to 1, firmware is allowed to be unresponsive to heartbeat + * health checks, allowing for JTAG debugging scenarios where the + * debugger has the firmware processes stopped indefinitely. This + * flag has effect only on debug builds of firmware. + */ + #define HWRM_DBG_CFG_INPUT_FLAGS_JTAG_DEBUG UINT32_C(0x20) + /* + * Notification queue (completion ring) used by the firmware to post + * async debug notifications and fw trace logs. This field is valid + * when fw_trace, fw_trace_secondary or debug_notify flags are set. + */ + uint16_t async_cmpl_ring; + uint8_t unused_0[2]; +} hwrm_dbg_cfg_input_t, *phwrm_dbg_cfg_input_t; -/* hwrm_dbg_useq_free_output (size:256b/32B) */ +/* hwrm_dbg_cfg_output (size:128b/16B) */ -typedef struct hwrm_dbg_useq_free_output { +typedef struct hwrm_dbg_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -60997,43 +64474,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Non-zero firmware timestamp */ - uint32_t nz_fw_timestamp; - /* The last selected USID */ - uint16_t last_usid; - /* The number of USEQs currently allocated */ - uint16_t num_useq_allocd; - /* Flags indicating current USEQ engine state */ - uint32_t useq_resp_flags; - /* When set, there is at least some data available to be delivered */ - #define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) - /* When set, all internal buffers are full */ - #define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) - #define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW - /* Current count of the number of full buffers available for delivery */ - uint8_t full_cnt; - /* Reserved */ - uint8_t useq_resp_unused_0[3]; - /* This field is reserved */ - uint32_t unused_0; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint32_t valid; -} hwrm_dbg_useq_free_output_t, *phwrm_dbg_useq_free_output_t; + uint8_t valid; +} hwrm_dbg_cfg_output_t, *phwrm_dbg_cfg_output_t; -/*********************** - * hwrm_dbg_useq_flush * - ***********************/ +/***************************** + * hwrm_dbg_crashdump_header * + *****************************/ -/* hwrm_dbg_useq_flush_input (size:192b/24B) */ +/* hwrm_dbg_crashdump_header_input (size:192b/24B) */ -typedef struct hwrm_dbg_useq_flush_input { +typedef struct hwrm_dbg_crashdump_header_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61062,20 +64521,12 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Bitwise flags described below */ - uint16_t flags; - /* Flush all USEQ code words, resetting all USIDs to invalid */ - #define HWRM_DBG_USEQ_FLUSH_INPUT_USEQ_CODE_WORDS UINT32_C(0x1) - /* Initialize all buffers, clearing out any collected data */ - #define HWRM_DBG_USEQ_FLUSH_INPUT_BUFFERS UINT32_C(0x2) - #define HWRM_DBG_USEQ_FLUSH_INPUT_LAST HWRM_DBG_USEQ_FLUSH_INPUT_BUFFERS - /* This field is reserved */ - uint8_t unused_0[6]; -} hwrm_dbg_useq_flush_input_t, *phwrm_dbg_useq_flush_input_t; + uint64_t unused_0; +} hwrm_dbg_crashdump_header_input_t, *phwrm_dbg_crashdump_header_input_t; -/* hwrm_dbg_useq_flush_output (size:256b/32B) */ +/* hwrm_dbg_crashdump_header_output (size:512b/64B) */ -typedef struct hwrm_dbg_useq_flush_output { +typedef struct hwrm_dbg_crashdump_header_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61084,43 +64535,109 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Non-zero firmware timestamp */ - uint32_t nz_fw_timestamp; - /* The last selected USID */ - uint16_t last_usid; - /* The number of USEQs currently allocated */ - uint16_t num_useq_allocd; - /* Flags indicating current USEQ engine state */ - uint32_t useq_resp_flags; - /* When set, there is at least some data available to be delivered */ - #define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) - /* When set, all internal buffers are full */ - #define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) - #define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW - /* Current count of the number of full buffers available for delivery */ - uint8_t full_cnt; - /* Reserved */ - uint8_t useq_resp_unused_0[3]; - /* This field is reserved */ - uint32_t unused_0; + /* Major version. */ + uint8_t version_hi; + /* Minor version. */ + uint8_t version_low; + /* + * Header length in bytes. This includes all fields from version + * to dev_uid (whose length is specified in dev_uid_length). + */ + uint16_t header_len; + /* This is the crash dump size in bytes. */ + uint32_t dump_size; + /* + * This is a "wall clock" timestamp value of when the crash occurred. + * Format is of time_t type. + */ + uint32_t crash_time; + /* This is the timezone information for the crash_time. */ + int8_t utc_offset; + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_UTC 0 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMSTERDAM 4 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_EGYPT 8 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_EUROPE_MOSCOW 12 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_IRAN 14 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_DUBAI 16 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_KABUL 18 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ANTARCTICA_MAWSON 20 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_COLOMBO 22 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_KATHMANDU 23 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_INDIAN_CHAGOS 24 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_INDIAN_COCOS 26 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_BANGKOK 28 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_HONG_KONG 32 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_PYONGYANG 34 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_EUCLA 35 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ASIA_TOKYO 36 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_ADELAIDE 38 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_BROKEN_HILL 38 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_DARWIN 38 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_SYDNEY 40 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AUSTRALIA_LORD_HOWE 42 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ANTARCTICA_MACQUARIE 44 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ANTARCTICA_SOUTH_POLE 48 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_CHATHAM 51 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_APIA 52 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_KIRITIMATIS 56 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ATLANTIC_CAPE_VERDE -4 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_ATLANTIC_SOUTH_GEORGIA -8 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_ARGENTINA_BUENOS_AIRES -12 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_SAO_PAULO -12 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_NEWFOUNDLAND -14 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_BARBADOS -16 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_CANCUN -20 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_COSTA_RICA -24 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_AMERICA_PHOENIX -28 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_US_ARIZONA -28 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_US_PACIFIC -32 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_US_ALASKA -36 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_MARQUESAS -38 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_HAWAII -40 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_MIDWAY -44 + #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_LAST HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_PACIFIC_MIDWAY + /* + * This field is a counter value of the crash dump available. This + * value is incremented monotonically at each crash. + */ + uint8_t crash_cntr; + /* + * This specifies the length of the dev_uid in bytes. The maximum + * value is 31. + */ + uint16_t dev_uid_length; + /* + * This is a unique device identifier (e.g. the first port MAC + * address for a network controller or a serial number for an + * en/decryption device) in ASCII format. It is used to identify + * where the crash dump content is coming from. Unused bytes must + * have '\0' character. + */ + uint8_t dev_uid[32]; + /* + * This is a count value tracking the number of successful boots + * before the crash occurred. + */ + uint32_t power_on_count; + uint8_t unused_2[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint32_t valid; -} hwrm_dbg_useq_flush_output_t, *phwrm_dbg_useq_flush_output_t; + uint8_t valid; +} hwrm_dbg_crashdump_header_output_t, *phwrm_dbg_crashdump_header_output_t; -/************************ - * hwrm_dbg_useq_cw_cfg * - ************************/ +/**************************** + * hwrm_dbg_crashdump_erase * + ****************************/ -/* hwrm_dbg_useq_cw_cfg_input (size:960b/120B) */ +/* hwrm_dbg_crashdump_erase_input (size:192b/24B) */ -typedef struct hwrm_dbg_useq_cw_cfg_input { +typedef struct hwrm_dbg_crashdump_erase_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61149,53 +64666,29 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The USID of the sequence being configured */ - uint16_t usid; - /* - * The code words given in this message will be placed - * at this offset from the starting code word for this - * usid. NOTE: when offset is zero, the first 6 32-bit - * words may contain values for F0-F7 as well as the - * main code word index. This is determined by checking - * the usid_ctrl_present flag. - */ - uint16_t offset; - /* - * When the use_dma flag is clear, this is the length in bytes - * to be digested from the opaque data area. - */ - uint16_t size; - /* - * Flags associated with the current message - * data area. - */ - uint16_t flags; - /* - * When set, the opaque data begins with a block of control - * information to be associated with the usid. This includes - * F0-F7 code word indexes as well as the code word index for - * main. - */ - #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USID_CTRL_PRESENT UINT32_C(0x1) + /* The scope of the erase */ + uint8_t scope; /* - * When set, opaque contains a 64b host address used to DMA - * the entire code word sequence. The offset within the - * opaque data depends on the state of other flags. + * Wipe all crashdump data blocks, making them available for + * the next crash(es). This is the typical value to be used. */ - #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USE_DMA UINT32_C(0x2) + #define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_INVALIDATE UINT32_C(0x0) /* - * When set, this message is the last configuration message - * for the given usid. + * Experimental: Remove all data blocks from the directory + * (without erasing any existing contents), re-allocate and + * re-initialize new ones. In case where the crash dump feature + * stops functioning, this can be used to restore it back to the + * clean slate. */ - #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_END UINT32_C(0x8000) - #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_LAST HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_END - /* command dependent data (e.g. function id for host dma command) */ - uint32_t opaque[24]; -} hwrm_dbg_useq_cw_cfg_input_t, *phwrm_dbg_useq_cw_cfg_input_t; + #define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_REINIT UINT32_C(0x1) + #define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_LAST HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_REINIT + uint8_t unused_0[3]; + uint32_t unused_1; +} hwrm_dbg_crashdump_erase_input_t, *phwrm_dbg_crashdump_erase_input_t; -/* hwrm_dbg_useq_cw_cfg_output (size:192b/24B) */ +/* hwrm_dbg_crashdump_erase_output (size:128b/16B) */ -typedef struct hwrm_dbg_useq_cw_cfg_output { +typedef struct hwrm_dbg_crashdump_erase_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61204,33 +64697,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Non-zero firmware timestamp */ - uint32_t nz_fw_timestamp; - /* The last selected USID */ - uint16_t last_usid; - /* The number of USEQs currently allocated */ - uint16_t num_useq_allocd; - /* Flags indicating current USEQ engine state */ - uint32_t useq_resp_flags; - /* When set, there is at least some data available to be delivered */ - #define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) - /* When set, all internal buffers are full */ - #define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) - #define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW - /* Current count of the number of full buffers available for delivery */ - uint8_t full_cnt; - /* Reserved */ - uint8_t useq_resp_unused_0[3]; -} hwrm_dbg_useq_cw_cfg_output_t, *phwrm_dbg_useq_cw_cfg_output_t; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_dbg_crashdump_erase_output_t, *phwrm_dbg_crashdump_erase_output_t; -/*********************** - * hwrm_dbg_useq_qcaps * - ***********************/ +/****************** + * hwrm_dbg_qcaps * + ******************/ -/* hwrm_dbg_useq_qcaps_input (size:128b/16B) */ +/* hwrm_dbg_qcaps_input (size:192b/24B) */ -typedef struct hwrm_dbg_useq_qcaps_input { +typedef struct hwrm_dbg_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61259,11 +64744,18 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_dbg_useq_qcaps_input_t, *phwrm_dbg_useq_qcaps_input_t; + /* + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} hwrm_dbg_qcaps_input_t, *phwrm_dbg_qcaps_input_t; -/* hwrm_dbg_useq_qcaps_output (size:384b/48B) */ +/* hwrm_dbg_qcaps_output (size:192b/24B) */ -typedef struct hwrm_dbg_useq_qcaps_output { +typedef struct hwrm_dbg_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61272,51 +64764,50 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Non-zero firmware timestamp */ - uint32_t nz_fw_timestamp; - /* The last selected USID */ - uint16_t last_usid; - /* The number of USEQs currently allocated */ - uint16_t num_useq_allocd; - /* Flags indicating current USEQ engine state */ - uint32_t useq_resp_flags; - /* When set, there is at least some data available to be delivered */ - #define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) - /* When set, all internal buffers are full */ - #define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) - #define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW - /* Current count of the number of full buffers available for delivery */ - uint8_t full_cnt; - /* Reserved */ - uint8_t useq_resp_unused_0[3]; - /* Maximum number of USEQ that can be tracked by firmware */ - uint32_t max_num_useq; - /* Maximum number of code word bytes for a single USEQ */ - uint32_t max_useq_size; - /* The maximum number of output bytes a single USEQ may generate */ - uint32_t max_useq_32b_output_size; - /* The number of internal USEQ output buffers, each of 4096 bytes */ - uint32_t num_buf; - /* This field is reserved */ - uint32_t unused_0; + /* + * FID value. This value is used to identify operations on the PCI + * bus as belonging to a particular PCI function. + */ + uint16_t fid; + uint8_t unused_0[2]; + /* + * Bitwise field of components FW supports skipping during collection + * of coredump as part of a crash collection. + */ + uint32_t coredump_component_disable_caps; + /* + * If 1, FW supports disabling the collection of NVM during a + * coredump taken as part of crash collection. + */ + #define HWRM_DBG_QCAPS_OUTPUT_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM UINT32_C(0x1) + uint32_t flags; + /* If 1, FW supports writing a crashdump to NVM. */ + #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_NVM UINT32_C(0x1) + /* If 1, FW supports writing a crashdump to host ddr. */ + #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_HOST_DDR UINT32_C(0x2) + /* If 1, FW supports writing a crashdump to soc ddr. */ + #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_SOC_DDR UINT32_C(0x4) + /* If 1, FW supports USEQ operations */ + #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_USEQ UINT32_C(0x8) + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint32_t valid; -} hwrm_dbg_useq_qcaps_output_t, *phwrm_dbg_useq_qcaps_output_t; + uint8_t valid; +} hwrm_dbg_qcaps_output_t, *phwrm_dbg_qcaps_output_t; -/*************************** - * hwrm_dbg_useq_sched_cfg * - ***************************/ +/***************** + * hwrm_dbg_qcfg * + *****************/ -/* hwrm_dbg_useq_sched_cfg_input (size:192b/24B) */ +/* hwrm_dbg_qcfg_input (size:192b/24B) */ -typedef struct hwrm_dbg_useq_sched_cfg_input { +typedef struct hwrm_dbg_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61345,34 +64836,41 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Enumeration values for enabling, disabling scheduler */ - uint16_t global_cfg; - /* This value will leave the global scheduler in its current state */ - #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_NO_CHANGE UINT32_C(0x0) /* - * This value disables the global scheduler. This mode must be used - * when the RUN command is being used to run individual sequences. + * Function ID of the function that is being queried. + * 0xFF... (All Fs) if the query is for the requesting + * function. */ - #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_DISABLE UINT32_C(0x1) + uint16_t fid; + uint16_t flags; /* - * This value enables the global scheduler. When enabled, USEQs will - * be scheduled based on their polling intervals + * The crashdump size represents size of crashdump + * written to the specified destination. */ - #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_ENABLE UINT32_C(0x2) - #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_LAST HWRM_DBG_USEQ_SCHED_CFG_INPUT_ENABLE + #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK UINT32_C(0x3) + #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 + /* crashdump size written to nvm */ + #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM UINT32_C(0x0) + /* crashdump size written to host_ddr */ + #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR UINT32_C(0x1) + /* crashdump size written to soc_ddr */ + #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR UINT32_C(0x2) + #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR /* - * The given polling interval will be associated with this USID. A value - * of -1 indicates that the USID is invalid. The invalid USID is used when - * using this message only for global scheduler configuration. + * Bitwise field of components requested for FW to skip when + * calculating the size of a coredump collection. */ - uint16_t usid; - /* This value represents microseconds between runs of the USEQ */ - uint32_t polling_interval; -} hwrm_dbg_useq_sched_cfg_input_t, *phwrm_dbg_useq_sched_cfg_input_t; + uint32_t coredump_component_disable_flags; + /* + * If 1, NVM will not be collected during a coredump taken as part + * of crash collection. + */ + #define HWRM_DBG_QCFG_INPUT_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM UINT32_C(0x1) +} hwrm_dbg_qcfg_input_t, *phwrm_dbg_qcfg_input_t; -/* hwrm_dbg_useq_sched_cfg_output (size:256b/32B) */ +/* hwrm_dbg_qcfg_output (size:256b/32B) */ -typedef struct hwrm_dbg_useq_sched_cfg_output { +typedef struct hwrm_dbg_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61381,43 +64879,82 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Non-zero firmware timestamp */ - uint32_t nz_fw_timestamp; - /* The last selected USID */ - uint16_t last_usid; - /* The number of USEQs currently allocated */ - uint16_t num_useq_allocd; - /* Flags indicating current USEQ engine state */ - uint32_t useq_resp_flags; - /* When set, there is at least some data available to be delivered */ - #define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) - /* When set, all internal buffers are full */ - #define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) - #define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW - /* Current count of the number of full buffers available for delivery */ - uint8_t full_cnt; - /* Reserved */ - uint8_t useq_resp_unused_0[3]; - /* This field is reserved */ - uint32_t unused_0; + /* + * FID value. This value is used to identify operations on the PCI + * bus as belonging to a particular PCI function. + */ + uint16_t fid; + uint8_t unused_0[2]; + /* + * Size in bytes of a coredump file created by the FW. This takes into + * consideration any components selected in the + * coredump_component_disable_flags field from hwrm_dbg_qcfg_input. + */ + uint32_t coredump_size; + uint32_t flags; + /* + * If set to 1, then UART logging is enabled for the primary + * firmware. Disabled otherwise. + */ + #define HWRM_DBG_QCFG_OUTPUT_FLAGS_UART_LOG UINT32_C(0x1) + /* + * If set to 1, then UART logging is enabled for the secondary + * firmware. Disabled otherwise. + */ + #define HWRM_DBG_QCFG_OUTPUT_FLAGS_UART_LOG_SECONDARY UINT32_C(0x2) + /* + * If set to 1, then completion ring logging is enabled for the + * primary firmware. Disabled otherwise. + */ + #define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE UINT32_C(0x4) + /* + * If set to 1, then completion ring logging is enabled for the + * secondary firmware. Disabled otherwise. + */ + #define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE_SECONDARY UINT32_C(0x8) + /* + * If set to 1, firmware will generate debug_notification async + * events to the driver as applicable. + */ + #define HWRM_DBG_QCFG_OUTPUT_FLAGS_DEBUG_NOTIFY UINT32_C(0x10) + /* + * If set to 1, firmware is allowed to be unresponsive to heartbeat + * health checks, allowing for JTAG debugging scenarios where the + * debugger has the firmware processes stopped indefinitely. This + * flag has effect only on debug builds of firmware. + */ + #define HWRM_DBG_QCFG_OUTPUT_FLAGS_JTAG_DEBUG UINT32_C(0x20) + /* + * Notification queue (completion ring) used by the firmware to post + * async debug notifications and fw trace logs. This field is valid + * when fw_trace, fw_trace_secondary or debug_notify flags are set. + */ + uint16_t async_cmpl_ring; + uint8_t unused_2[2]; + /* + * Size in bytes of a crashdump file created by the FW. Uses input + * flags to determine medium destination and corresponding size. + */ + uint32_t crashdump_size; + uint8_t unused_3[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint32_t valid; -} hwrm_dbg_useq_sched_cfg_output_t, *phwrm_dbg_useq_sched_cfg_output_t; + uint8_t valid; +} hwrm_dbg_qcfg_output_t, *phwrm_dbg_qcfg_output_t; -/********************* - * hwrm_dbg_useq_run * - *********************/ +/********************************* + * hwrm_dbg_crashdump_medium_cfg * + *********************************/ -/* hwrm_dbg_useq_run_input (size:320b/40B) */ +/* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ -typedef struct hwrm_dbg_useq_run_input { +typedef struct hwrm_dbg_crashdump_medium_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61446,50 +64983,62 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The USID to be run */ - uint16_t usid; - /* Type of run to execute for the given USID */ - uint8_t run_type; - /* This run type will execute the requested USEQ only a single time */ - #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_SINGLE UINT32_C(0x0) + uint16_t output_dest_flags; + /* Destination is DDR ram. */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_TYPE_DDR UINT32_C(0x1) + uint16_t pg_size_lvl; + /* PBL indirect levels. */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_MASK UINT32_C(0x3) + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_1 UINT32_C(0x1) /* - * This run type will execute the requested USEQ a number of times given - * by run_cnt with a run interval given by the run_interval parameter. + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. */ - #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_CNT UINT32_C(0x1) + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_2 UINT32_C(0x2) + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LAST HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_2 + /* page size. */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_MASK UINT32_C(0x1c) + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_SFT 2 + /* 4KB. */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_4K (UINT32_C(0x0) << 2) + /* 8KB. */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_8K (UINT32_C(0x1) << 2) + /* 64KB. */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_64K (UINT32_C(0x2) << 2) + /* 2MB. */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_2M (UINT32_C(0x3) << 2) + /* 8MB. */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_8M (UINT32_C(0x4) << 2) + /* 1GB. */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_1G (UINT32_C(0x5) << 2) + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_LAST HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_1G + /* unused11 is 11 b */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_UNUSED11_MASK UINT32_C(0xffe0) + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_UNUSED11_SFT 5 + /* Crashdump buffer size. */ + uint32_t size; /* - * This run type will execute the requested USEQ as many times as it needs - * to fill an entire buffer to return to the host. The runs will occur - * with a run interval given by the run_interval parameter. + * Bitwise field of components that FW is requested to skip during + * coredump as part of a crash collection. */ - #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_FILL_BUF UINT32_C(0x2) - #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_LAST HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_FILL_BUF + uint32_t coredump_component_disable_flags; /* - * If indicated by flags, this represents the number of times to run the USEQ. - * Note that runs are stopped if the buffer fills prior regardless of the - * number of runs. For example, if a run_cnt of 10 is specified and 3 runs - * results in the buffer being full then only 3 runs are executed. - */ - uint8_t run_cnt; - /* - * This value represents microseconds between runs of the USEQ when running - * multiple times as indicated by flags. - */ - uint32_t run_interval; - /* Address of the host buffer where collected USEQ output data will be placed */ - uint64_t host_dest_addr; - /* - * Size, in bytes, of the memory associated with host_dest_addr. It is expected - * that this is >= 4096 + * If 1, then NVM will not be collected during a coredump taken as + * part of crash collection. */ - uint32_t host_dest_len; - /* This field is reserved */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_NVRAM UINT32_C(0x1) uint32_t unused_0; -} hwrm_dbg_useq_run_input_t, *phwrm_dbg_useq_run_input_t; + /* Crashdump buffer PBL physical address. */ + uint64_t pbl; +} hwrm_dbg_crashdump_medium_cfg_input_t, *phwrm_dbg_crashdump_medium_cfg_input_t; -/* hwrm_dbg_useq_run_output (size:256b/32B) */ +/* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ -typedef struct hwrm_dbg_useq_run_output { +typedef struct hwrm_dbg_crashdump_medium_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61498,47 +65047,58 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Non-zero firmware timestamp */ - uint32_t nz_fw_timestamp; - /* The last selected USID */ - uint16_t last_usid; - /* The number of USEQs currently allocated */ - uint16_t num_useq_allocd; - /* Flags indicating current USEQ engine state */ - uint32_t useq_resp_flags; - /* When set, there is at least some data available to be delivered */ - #define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) - /* When set, all internal buffers are full */ - #define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) - #define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW - /* Current count of the number of full buffers available for delivery */ - uint8_t full_cnt; - /* Reserved */ - uint8_t useq_resp_unused_0[3]; - /* - * The length, in bytes, of the amount of data placed in the corresponding - * host_dest_addr given in the input message. This will always be a multiple - * of 4096 - */ - uint32_t host_dest_filled_len; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint32_t valid; -} hwrm_dbg_useq_run_output_t, *phwrm_dbg_useq_run_output_t; + uint8_t valid; +} hwrm_dbg_crashdump_medium_cfg_output_t, *phwrm_dbg_crashdump_medium_cfg_output_t; -/****************************** - * hwrm_dbg_useq_delivery_req * - ******************************/ +/* coredump_segment_record (size:128b/16B) */ + +typedef struct coredump_segment_record { + /* Component id of the returned component. */ + uint16_t component_id; + /* Segment id of the returned component. */ + uint16_t segment_id; + /* Not used. */ + uint16_t max_instances; + /* Major version. */ + uint8_t version_hi; + /* Minor version. */ + uint8_t version_low; + /* + * bit 0: live data + * bit 1: crashed data + */ + uint8_t seg_flags; + /* This field is used to indicate the segment is compressed. */ + uint8_t compress_flags; + /* + * SFLAG_COMPRESSED_ZLIB indicates that the segment data is + * compressed. + */ + #define SFLAG_COMPRESSED_ZLIB UINT32_C(0x1) + uint8_t unused_0[2]; + /* + * This field is the length of the segment data. It will be zero if + * the firmware does not support returning the segment data length. + */ + uint32_t segment_len; +} coredump_segment_record_t, *pcoredump_segment_record_t; +/************************** + * hwrm_dbg_coredump_list * + **************************/ -/* hwrm_dbg_useq_delivery_req_input (size:896b/112B) */ -typedef struct hwrm_dbg_useq_delivery_req_input { +/* hwrm_dbg_coredump_list_input (size:256b/32B) */ + +typedef struct hwrm_dbg_coredump_list_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61568,21 +65128,27 @@ */ uint64_t resp_addr; /* - * Eight destination addresses provide host memory space for FW to deliver - * USEQ output details. A value of 0x0 for the address can be used to - * inform FW that the buffer is not available. + * host address where the data content will be written + * when the request is complete. This area must be 16B aligned. */ - uint64_t host_dest_addrs[8]; + uint64_t host_dest_addr; + /* Length of host buffer used for transferring debug data. */ + uint32_t host_buf_len; + /* Sequence number of the request. Starts at 0. */ + uint16_t seq_no; + /* */ + uint8_t flags; /* - * The length, in bytes, of the corresponding host_dest_addrs array entry. Each - * valid hist_dest_addrs entry must have a len of at least 4096 bytes + * If set to 1, crash dump is requested. + * If set to 0, both live core and crash dump are requested. */ - uint32_t host_dest_len[8]; -} hwrm_dbg_useq_delivery_req_input_t, *phwrm_dbg_useq_delivery_req_input_t; + #define HWRM_DBG_COREDUMP_LIST_INPUT_FLAGS_CRASHDUMP UINT32_C(0x1) + uint8_t unused_0[1]; +} hwrm_dbg_coredump_list_input_t, *phwrm_dbg_coredump_list_input_t; -/* hwrm_dbg_useq_delivery_req_output (size:512b/64B) */ +/* hwrm_dbg_coredump_list_output (size:128b/16B) */ -typedef struct hwrm_dbg_useq_delivery_req_output { +typedef struct hwrm_dbg_coredump_list_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61591,49 +65157,36 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Non-zero firmware timestamp */ - uint32_t nz_fw_timestamp; - /* The last selected USID */ - uint16_t last_usid; - /* The number of USEQs currently allocated */ - uint16_t num_useq_allocd; - /* Flags indicating current USEQ engine state */ - uint32_t useq_resp_flags; - /* When set, there is at least some data available to be delivered */ - #define HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) - /* When set, all internal buffers are full */ - #define HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) - #define HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW - /* Current count of the number of full buffers available for delivery */ - uint8_t full_cnt; - /* Reserved */ - uint8_t useq_resp_unused_0[3]; + uint8_t flags; /* - * The length, in bytes, of the amount of data placed in the corresponding - * host_dest_addrs entry given in the input message. This will always be a - * multiple of 4096 + * Value of 1 means that there is more data available. + * Issue the request again with the next sequence number. */ - uint32_t host_dest_filled_len[8]; - /* This field is reserved */ - uint32_t unused_0; + #define HWRM_DBG_COREDUMP_LIST_OUTPUT_FLAGS_MORE UINT32_C(0x1) + uint8_t unused_0; + /* Total number of segments to be returned. */ + uint16_t total_segments; + /* Actual length of data returned in bytes. */ + uint16_t data_len; + uint8_t unused_1; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint32_t valid; -} hwrm_dbg_useq_delivery_req_output_t, *phwrm_dbg_useq_delivery_req_output_t; + uint8_t valid; +} hwrm_dbg_coredump_list_output_t, *phwrm_dbg_coredump_list_output_t; -/************************** - * hwrm_nvm_raw_write_blk * - **************************/ +/****************************** + * hwrm_dbg_coredump_initiate * + ******************************/ -/* hwrm_nvm_raw_write_blk_input (size:256b/32B) */ +/* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ -typedef struct hwrm_nvm_raw_write_blk_input { +typedef struct hwrm_dbg_coredump_initiate_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61662,23 +65215,26 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Component id of the returned component. */ + uint16_t component_id; + /* Segment id of the returned component. */ + uint16_t segment_id; + /* Not used. */ + uint16_t instance; + /* Not used. */ + uint16_t unused_0; /* - * 64-bit Host Source Address. - * This is the location of the source data to be written. - */ - uint64_t host_src_addr; - /* - * 32-bit Destination Address. - * This is the NVRAM byte-offset where the source data will be written to. + * bit 0: live data + * bit 1: crashed data */ - uint32_t dest_addr; - /* Length of data to be written, in bytes. */ - uint32_t len; -} hwrm_nvm_raw_write_blk_input_t, *phwrm_nvm_raw_write_blk_input_t; + uint8_t seg_flags; + /* Not used. */ + uint8_t unused_1[7]; +} hwrm_dbg_coredump_initiate_input_t, *phwrm_dbg_coredump_initiate_input_t; -/* hwrm_nvm_raw_write_blk_output (size:128b/16B) */ +/* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ -typedef struct hwrm_nvm_raw_write_blk_output { +typedef struct hwrm_dbg_coredump_initiate_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61690,22 +65246,44 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_raw_write_blk_output_t, *phwrm_nvm_raw_write_blk_output_t; +} hwrm_dbg_coredump_initiate_output_t, *phwrm_dbg_coredump_initiate_output_t; -/***************** - * hwrm_nvm_read * - *****************/ +/* coredump_data_hdr (size:128b/16B) */ + +typedef struct coredump_data_hdr { + /* Starting address of the register range. */ + uint32_t address; + /* + * length: 0 - 23 bits represents the actual data without the pad. + * flags: 24 - 31 bits represents indirect register ranges. + * - bit 24: Set if registers in this segment are indirect accessed. + */ + uint32_t flags_length; + /* These bits represents the actual length of the data segment */ + #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK UINT32_C(0xffffff) + #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 + /* Set if registers in this segment are indirect accessed. */ + #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS UINT32_C(0x1000000) + /* Value in the partner register for indirect or multi-field registers. */ + uint32_t instance; + /* Starting address of the next register after the current data range */ + uint32_t next_offset; +} coredump_data_hdr_t, *pcoredump_data_hdr_t; +/****************************** + * hwrm_dbg_coredump_retrieve * + ******************************/ -/* hwrm_nvm_read_input (size:320b/40B) */ -typedef struct hwrm_nvm_read_input { +/* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ + +typedef struct hwrm_dbg_coredump_retrieve_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61735,23 +65313,39 @@ */ uint64_t resp_addr; /* - * 64-bit Host Destination Address. - * This is the host address where the data will be written to. + * host address where the data content will be written + * when the request is complete. This area must be 16B aligned. */ uint64_t host_dest_addr; - /* The 0-based index of the directory entry. */ - uint16_t dir_idx; - uint8_t unused_0[2]; - /* The NVRAM byte-offset to read from. */ - uint32_t offset; - /* The length of the data to be read, in bytes. */ - uint32_t len; - uint8_t unused_1[4]; -} hwrm_nvm_read_input_t, *phwrm_nvm_read_input_t; + /* Length of host buffer used for transferring debug data. */ + uint32_t host_buf_len; + /* Not used. */ + uint32_t unused_0; + /* Component id of the returned component. */ + uint16_t component_id; + /* Segment id of the returned component. */ + uint16_t segment_id; + /* Not used. */ + uint16_t instance; + /* Not used. */ + uint16_t unused_1; + /* + * bit 0: live data + * bit 1: crashed data + */ + uint8_t seg_flags; + uint8_t unused_2; + uint16_t unused_3; + /* Not used. */ + uint32_t unused_4; + /* Sequence number is used per segment request. Starts at 0. */ + uint32_t seq_no; + uint32_t unused_5; +} hwrm_dbg_coredump_retrieve_input_t, *phwrm_dbg_coredump_retrieve_input_t; -/* hwrm_nvm_read_output (size:128b/16B) */ +/* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ -typedef struct hwrm_nvm_read_output { +typedef struct hwrm_dbg_coredump_retrieve_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61760,25 +65354,34 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + uint8_t flags; + /* + * Value of 1 means that there is more data available. + * Issue the request again with the next sequence number. + */ + #define HWRM_DBG_COREDUMP_RETRIEVE_OUTPUT_FLAGS_MORE UINT32_C(0x1) + uint8_t unused_0; + /* Actual length of data returned in bytes. */ + uint16_t data_len; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_read_output_t, *phwrm_nvm_read_output_t; +} hwrm_dbg_coredump_retrieve_output_t, *phwrm_dbg_coredump_retrieve_output_t; -/********************* - * hwrm_nvm_raw_dump * - *********************/ +/******************** + * hwrm_dbg_i2c_cmd * + ********************/ -/* hwrm_nvm_raw_dump_input (size:256b/32B) */ +/* hwrm_dbg_i2c_cmd_input (size:320b/40B) */ -typedef struct hwrm_nvm_raw_dump_input { +typedef struct hwrm_dbg_i2c_cmd_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61808,19 +65411,55 @@ */ uint64_t resp_addr; /* - * 64-bit Host Destination Address. - * This is the host address where the data will be written to. + * host address where the data content will be read or written. + * For master write, data content will be read from host memory and + * write to i2c slave. (size defined by write_size) + * For master read, data content will be read from i2c slave and write + * to the host memory. (size defined by read_size) + * For master write/read, data content will be first read from host + * memory and write to i2c slave. (size defined by write_size) then + * data read from i2c slave will be written back to the same host + * memory. (size defined by read_size) */ uint64_t host_dest_addr; - /* 32-bit NVRAM byte-offset to read from. */ - uint32_t offset; - /* Total length of NVRAM contents to be read, in bytes. */ - uint32_t len; -} hwrm_nvm_raw_dump_input_t, *phwrm_nvm_raw_dump_input_t; + /* read size in bytes, valid only for master read and write/read */ + uint16_t read_size; + /* write size in bytes, valid only for master write and write/read */ + uint16_t write_size; + /* + * instance of i2c channel for this operation. Valid if multiple + * instances + * of i2c channels are connected to external i2c devices. + */ + uint8_t chnl_id; + uint8_t options; + /* + * This bit must be '1' for 10-bit i2c addressing, + * 7-bit addressing otherwise. + */ + #define HWRM_DBG_I2C_CMD_INPUT_OPTIONS_10_BIT_ADDRESSING UINT32_C(0x1) + /* + * This bit must be '1' for 400 kbit/s, 100 kbit/s + * otherwise. + */ + #define HWRM_DBG_I2C_CMD_INPUT_OPTIONS_FAST_MODE UINT32_C(0x2) + /* I2C slave address. */ + uint16_t slave_addr; + /* I2C transfer mode. */ + uint8_t xfer_mode; + /* read data from slave device */ + #define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_READ UINT32_C(0x0) + /* write data to slave device */ + #define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE UINT32_C(0x1) + /* write follow by read data from slave device */ + #define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE_READ UINT32_C(0x2) + #define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_LAST HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE_READ + uint8_t unused_1[7]; +} hwrm_dbg_i2c_cmd_input_t, *phwrm_dbg_i2c_cmd_input_t; -/* hwrm_nvm_raw_dump_output (size:128b/16B) */ +/* hwrm_dbg_i2c_cmd_output (size:128b/16B) */ -typedef struct hwrm_nvm_raw_dump_output { +typedef struct hwrm_dbg_i2c_cmd_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61832,22 +65471,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_raw_dump_output_t, *phwrm_nvm_raw_dump_output_t; +} hwrm_dbg_i2c_cmd_output_t, *phwrm_dbg_i2c_cmd_output_t; -/**************************** - * hwrm_nvm_get_dir_entries * - ****************************/ +/******************* + * hwrm_dbg_fw_cli * + *******************/ -/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ +/* hwrm_dbg_fw_cli_input (size:1024b/128B) */ -typedef struct hwrm_nvm_get_dir_entries_input { +typedef struct hwrm_dbg_fw_cli_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61877,15 +65516,22 @@ */ uint64_t resp_addr; /* - * 64-bit Host Destination Address. - * This is the host address where the directory will be written. + * Address of the host buffer where debug CLI data + * is requested to be dumped. */ uint64_t host_dest_addr; -} hwrm_nvm_get_dir_entries_input_t, *phwrm_nvm_get_dir_entries_input_t; + /* Length of host buffer used for transferring debug data. */ + uint32_t host_buf_len; + /* Length of CLI command. */ + uint16_t cli_cmd_len; + uint8_t unused_0[2]; + /* CLI command string, a single ASCII encoded null terminated string. */ + uint8_t cli_cmd[96]; +} hwrm_dbg_fw_cli_input_t, *phwrm_dbg_fw_cli_input_t; -/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ +/* hwrm_dbg_fw_cli_output (size:128b/16B) */ -typedef struct hwrm_nvm_get_dir_entries_output { +typedef struct hwrm_dbg_fw_cli_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61894,25 +65540,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Size of debug CLI data returned in bytes. */ + uint32_t cli_data_len; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_get_dir_entries_output_t, *phwrm_nvm_get_dir_entries_output_t; +} hwrm_dbg_fw_cli_output_t, *phwrm_dbg_fw_cli_output_t; -/************************* - * hwrm_nvm_get_dir_info * - *************************/ +/************************** + * hwrm_dbg_ring_info_get * + **************************/ -/* hwrm_nvm_get_dir_info_input (size:128b/16B) */ +/* hwrm_dbg_ring_info_get_input (size:192b/24B) */ -typedef struct hwrm_nvm_get_dir_info_input { +typedef struct hwrm_dbg_ring_info_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -61941,11 +65589,25 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_nvm_get_dir_info_input_t, *phwrm_nvm_get_dir_info_input_t; + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* Notification Queue (NQ) */ + #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_NQ UINT32_C(0x3) + #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_LAST HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_NQ + uint8_t unused_0[3]; + /* Firmware ring ID associated with ring being queried. */ + uint32_t fw_ring_id; +} hwrm_dbg_ring_info_get_input_t, *phwrm_dbg_ring_info_get_input_t; -/* hwrm_nvm_get_dir_info_output (size:192b/24B) */ +/* hwrm_dbg_ring_info_get_output (size:192b/24B) */ -typedef struct hwrm_nvm_get_dir_info_output { +typedef struct hwrm_dbg_ring_info_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -61954,29 +65616,40 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of directory entries in the directory. */ - uint32_t entries; - /* Size of each directory entry, in bytes. */ - uint32_t entry_length; - uint8_t unused_0[7]; + /* Producer index for the queried ring. */ + uint32_t producer_index; + /* Consumer index for the queried ring. */ + uint32_t consumer_index; + /* + * CAG Vector Control for the queried NQ ring. + * Not valid for other ring types. + */ + uint32_t cag_vector_ctrl; + /* + * Steering Tag. The current value of the steering tag for the ring. + * The steering tag is only valid if it is advertised by Firmware in + * flags_ext2.steering_tag_supported of hwrm_func_qcaps response. + */ + uint16_t st_tag; + uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_get_dir_info_output_t, *phwrm_nvm_get_dir_info_output_t; +} hwrm_dbg_ring_info_get_output_t, *phwrm_dbg_ring_info_get_output_t; -/****************** - * hwrm_nvm_write * - ******************/ +/********************** + * hwrm_dbg_drv_trace * + **********************/ -/* hwrm_nvm_write_input (size:448b/56B) */ +/* hwrm_dbg_drv_trace_input (size:1024b/128B) */ -typedef struct hwrm_nvm_write_input { +typedef struct hwrm_dbg_drv_trace_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62005,91 +65678,104 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Severity of the message. */ + uint8_t severity; + /* Fatal */ + #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_FATAL UINT32_C(0x0) + /* Error */ + #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_ERROR UINT32_C(0x1) + /* Warning */ + #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_WARNING UINT32_C(0x2) + /* Info */ + #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_INFO UINT32_C(0x3) + /* Debug */ + #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_DEBUG UINT32_C(0x4) + #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_LAST HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_DEBUG + /* Number of bytes to write including terminating 'NULL' if any. */ + uint8_t write_len; + uint8_t unused_0[6]; /* - * 64-bit Host Source Address. - * This is where the source data is. + * This field represents the debug data sent by driver + * ASCII chars, 'NULL' termination not required. */ - uint64_t host_src_addr; + char trace_data[104]; +} hwrm_dbg_drv_trace_input_t, *phwrm_dbg_drv_trace_input_t; + +/* hwrm_dbg_drv_trace_output (size:128b/16B) */ + +typedef struct hwrm_dbg_drv_trace_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * The Directory Entry Type (valid values are defined in the - * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint16_t dir_type; + uint8_t valid; +} hwrm_dbg_drv_trace_output_t, *phwrm_dbg_drv_trace_output_t; + +/*********************** + * hwrm_dbg_useq_alloc * + ***********************/ + + +/* hwrm_dbg_useq_alloc_input (size:192b/24B) */ + +typedef struct hwrm_dbg_useq_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Directory ordinal. - * The 0-based instance of the combined Directory Entry Type and Extension. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t dir_ordinal; + uint16_t cmpl_ring; /* - * The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file - * bnxnvm_defs.h). + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t dir_ext; + uint16_t seq_id; /* - * Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file - * bnxnvm_defs.h). - */ - uint16_t dir_attr; - /* - * Length of data to write, in bytes. May be less than or equal to the - * allocated size for the directory entry. - * The data length stored in the directory entry will be updated to - * reflect this value once the write is complete. - */ - uint32_t dir_data_length; - /* Option. */ - uint16_t option; - uint16_t flags; - /* - * When this bit is '1', the original active image - * will not be removed. TBD: what purpose is this? - */ - #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG UINT32_C(0x1) - /* - * This flag indicates the sender wants to modify a continuous - * NVRAM area using a batch of this HWRM requests. The - * offset of a request must be continuous to the end of previous - * request's. Firmware does not update the directory entry until - * receiving the last request, which is indicated by the batch_last - * flag. This flag is set usually when a sender does not have a - * block of memory that is big enough to hold the entire NVRAM - * data for send at one time. - */ - #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE UINT32_C(0x2) - /* - * This flag can be used only when the batch_mode flag is set. It - * indicates this request is the last of batch requests. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST UINT32_C(0x4) + uint16_t target_id; /* - * The requested length of the allocated NVM for the item, in bytes. - * This value may be greater than or equal to the specified data - * length (dir_data_length). - * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, - * which may be greater than the requested item length. - * The purpose for allocating more than the required number of bytes - * for an item's data is to pre-allocate extra storage (padding) to - * accommodate the potential future growth of an item (e.g. upgraded - * firmware with a size increase, log growth, expanded configuration data). + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t dir_item_length; + uint64_t resp_addr; /* - * 32-bit offset of data blob from where data is being written. - * Only valid for batch mode. For non-batch writes 'dont care'. + * Number size of the allocation, in bytes, for the USEQ in the code + * words array */ - uint32_t offset; + uint32_t size; /* - * Length of data to be written.Should be non-zero. - * Only valid for batch mode. For non-batch writes 'dont care'. + * Number of bytes executing the USEQ will produce. Must be a multiple + * of 4 */ - uint32_t len; - uint32_t unused_0; -} hwrm_nvm_write_input_t, *phwrm_nvm_write_input_t; + uint16_t output_bytes; + /* This field is reserved */ + uint16_t unused_0; +} hwrm_dbg_useq_alloc_input_t, *phwrm_dbg_useq_alloc_input_t; -/* hwrm_nvm_write_output (size:128b/16B) */ +/* hwrm_dbg_useq_alloc_output (size:256b/32B) */ -typedef struct hwrm_nvm_write_output { +typedef struct hwrm_dbg_useq_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62098,53 +65784,45 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Length of the allocated NVM for the item, in bytes. The value may be - * greater than or equal to the specified data length or the requested - * item length. - * The actual item length used when creating a new directory entry will - * be a multiple of an NVM block size. - */ - uint32_t dir_item_length; - /* The directory index of the created or modified item. */ - uint16_t dir_idx; - uint8_t unused_0; + /* Non-zero firmware timestamp */ + uint32_t nz_fw_timestamp; + /* The last selected USID */ + uint16_t last_usid; + /* The number of USEQs currently allocated */ + uint16_t num_useq_allocd; + /* Flags indicating current USEQ engine state */ + uint32_t useq_resp_flags; + /* When set, there is at least some data available to be delivered */ + #define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) + /* When set, all internal buffers are full */ + #define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) + #define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW + /* Current count of the number of full buffers available for delivery */ + uint8_t full_cnt; + /* Reserved */ + uint8_t useq_resp_unused_0[3]; + /* This is the allocated usid */ + uint16_t alloc_usid; + /* This field is reserved */ + uint16_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint8_t valid; -} hwrm_nvm_write_output_t, *phwrm_nvm_write_output_t; - -/* hwrm_nvm_write_cmd_err (size:64b/8B) */ - -typedef struct hwrm_nvm_write_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) - /* nvm is completely full. */ - #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) - #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE - uint8_t unused_0[7]; -} hwrm_nvm_write_cmd_err_t, *phwrm_nvm_write_cmd_err_t; + uint32_t valid; +} hwrm_dbg_useq_alloc_output_t, *phwrm_dbg_useq_alloc_output_t; -/******************* - * hwrm_nvm_modify * - *******************/ +/********************** + * hwrm_dbg_useq_free * + **********************/ -/* hwrm_nvm_modify_input (size:320b/40B) */ +/* hwrm_dbg_useq_free_input (size:192b/24B) */ -typedef struct hwrm_nvm_modify_input { +typedef struct hwrm_dbg_useq_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62173,43 +65851,15 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * 64-bit Host Source Address. - * This is where the modified data is. - */ - uint64_t host_src_addr; - /* 16-bit directory entry index. */ - uint16_t dir_idx; - uint16_t flags; - /* - * This flag indicates the sender wants to modify a continuous NVRAM - * area using a batch of this HWRM requests. The offset of a request - * must be continuous to the end of previous request's. Firmware does - * not update the directory entry until receiving the last request, - * which is indicated by the batch_last flag. - * This flag is set usually when a sender does not have a block of - * memory that is big enough to hold the entire NVRAM data for send - * at one time. - */ - #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1) - /* - * This flag can be used only when the batch_mode flag is set. - * It indicates this request is the last of batch requests. - */ - #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2) - /* 32-bit NVRAM byte-offset to modify content from. */ - uint32_t offset; - /* - * Length of data to be modified, in bytes. The length shall - * be non-zero. - */ - uint32_t len; - uint8_t unused_1[4]; -} hwrm_nvm_modify_input_t, *phwrm_nvm_modify_input_t; + /* The USID of the sequence to free */ + uint16_t usid; + /* This field is reserved */ + uint8_t unused_0[6]; +} hwrm_dbg_useq_free_input_t, *phwrm_dbg_useq_free_input_t; -/* hwrm_nvm_modify_output (size:128b/16B) */ +/* hwrm_dbg_useq_free_output (size:256b/32B) */ -typedef struct hwrm_nvm_modify_output { +typedef struct hwrm_dbg_useq_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62218,25 +65868,43 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Non-zero firmware timestamp */ + uint32_t nz_fw_timestamp; + /* The last selected USID */ + uint16_t last_usid; + /* The number of USEQs currently allocated */ + uint16_t num_useq_allocd; + /* Flags indicating current USEQ engine state */ + uint32_t useq_resp_flags; + /* When set, there is at least some data available to be delivered */ + #define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) + /* When set, all internal buffers are full */ + #define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) + #define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW + /* Current count of the number of full buffers available for delivery */ + uint8_t full_cnt; + /* Reserved */ + uint8_t useq_resp_unused_0[3]; + /* This field is reserved */ + uint32_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint8_t valid; -} hwrm_nvm_modify_output_t, *phwrm_nvm_modify_output_t; + uint32_t valid; +} hwrm_dbg_useq_free_output_t, *phwrm_dbg_useq_free_output_t; -/*************************** - * hwrm_nvm_find_dir_entry * - ***************************/ +/*********************** + * hwrm_dbg_useq_flush * + ***********************/ -/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ +/* hwrm_dbg_useq_flush_input (size:192b/24B) */ -typedef struct hwrm_nvm_find_dir_entry_input { +typedef struct hwrm_dbg_useq_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62265,41 +65933,20 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the dir_idx_valid field to be - * configured. - */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID UINT32_C(0x1) - /* Directory Entry Index */ - uint16_t dir_idx; - /* Directory Entry (Image) Type */ - uint16_t dir_type; - /* - * Directory ordinal. - * The instance of this Directory Type - */ - uint16_t dir_ordinal; - /* The Directory Entry Extension flags. */ - uint16_t dir_ext; - /* This value indicates the search option using dir_ordinal. */ - uint8_t opt_ordinal; - /* This value indicates the search option using dir_ordinal. */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3) - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0 - /* Equal to specified ordinal value. */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0) - /* Greater than or equal to specified ordinal value */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1) - /* Greater than specified ordinal value */ - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2) - #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT - uint8_t unused_0[3]; -} hwrm_nvm_find_dir_entry_input_t, *phwrm_nvm_find_dir_entry_input_t; + /* Bitwise flags described below */ + uint16_t flags; + /* Flush all USEQ code words, resetting all USIDs to invalid */ + #define HWRM_DBG_USEQ_FLUSH_INPUT_USEQ_CODE_WORDS UINT32_C(0x1) + /* Initialize all buffers, clearing out any collected data */ + #define HWRM_DBG_USEQ_FLUSH_INPUT_BUFFERS UINT32_C(0x2) + #define HWRM_DBG_USEQ_FLUSH_INPUT_LAST HWRM_DBG_USEQ_FLUSH_INPUT_BUFFERS + /* This field is reserved */ + uint8_t unused_0[6]; +} hwrm_dbg_useq_flush_input_t, *phwrm_dbg_useq_flush_input_t; -/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ +/* hwrm_dbg_useq_flush_output (size:256b/32B) */ -typedef struct hwrm_nvm_find_dir_entry_output { +typedef struct hwrm_dbg_useq_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62308,39 +65955,43 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Allocated NVRAM for this directory entry, in bytes. */ - uint32_t dir_item_length; - /* Size of the stored data for this directory entry, in bytes. */ - uint32_t dir_data_length; - /* - * Firmware version. - * Only valid if the directory entry is for embedded firmware stored - * in APE_BIN Format. - */ - uint32_t fw_ver; - /* Directory ordinal. */ - uint16_t dir_ordinal; - /* Directory Entry Index */ - uint16_t dir_idx; - uint8_t unused_0[7]; + /* Non-zero firmware timestamp */ + uint32_t nz_fw_timestamp; + /* The last selected USID */ + uint16_t last_usid; + /* The number of USEQs currently allocated */ + uint16_t num_useq_allocd; + /* Flags indicating current USEQ engine state */ + uint32_t useq_resp_flags; + /* When set, there is at least some data available to be delivered */ + #define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) + /* When set, all internal buffers are full */ + #define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) + #define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW + /* Current count of the number of full buffers available for delivery */ + uint8_t full_cnt; + /* Reserved */ + uint8_t useq_resp_unused_0[3]; + /* This field is reserved */ + uint32_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint8_t valid; -} hwrm_nvm_find_dir_entry_output_t, *phwrm_nvm_find_dir_entry_output_t; + uint32_t valid; +} hwrm_dbg_useq_flush_output_t, *phwrm_dbg_useq_flush_output_t; -/**************************** - * hwrm_nvm_erase_dir_entry * - ****************************/ +/************************ + * hwrm_dbg_useq_cw_cfg * + ************************/ -/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ +/* hwrm_dbg_useq_cw_cfg_input (size:960b/120B) */ -typedef struct hwrm_nvm_erase_dir_entry_input { +typedef struct hwrm_dbg_useq_cw_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62369,14 +66020,53 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Directory Entry Index */ - uint16_t dir_idx; - uint8_t unused_0[6]; -} hwrm_nvm_erase_dir_entry_input_t, *phwrm_nvm_erase_dir_entry_input_t; + /* The USID of the sequence being configured */ + uint16_t usid; + /* + * The code words given in this message will be placed + * at this offset from the starting code word for this + * usid. NOTE: when offset is zero, the first 6 32-bit + * words may contain values for F0-F7 as well as the + * main code word index. This is determined by checking + * the usid_ctrl_present flag. + */ + uint16_t offset; + /* + * When the use_dma flag is clear, this is the length in bytes + * to be digested from the opaque data area. + */ + uint16_t size; + /* + * Flags associated with the current message + * data area. + */ + uint16_t flags; + /* + * When set, the opaque data begins with a block of control + * information to be associated with the usid. This includes + * F0-F7 code word indexes as well as the code word index for + * main. + */ + #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USID_CTRL_PRESENT UINT32_C(0x1) + /* + * When set, opaque contains a 64b host address used to DMA + * the entire code word sequence. The offset within the + * opaque data depends on the state of other flags. + */ + #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USE_DMA UINT32_C(0x2) + /* + * When set, this message is the last configuration message + * for the given usid. + */ + #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_END UINT32_C(0x8000) + #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_LAST HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_END + /* command dependent data (e.g. function id for host dma command) */ + uint32_t opaque[24]; +} hwrm_dbg_useq_cw_cfg_input_t, *phwrm_dbg_useq_cw_cfg_input_t; -/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ +/* hwrm_dbg_useq_cw_cfg_output (size:192b/24B) */ -typedef struct hwrm_nvm_erase_dir_entry_output { +typedef struct hwrm_dbg_useq_cw_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62385,25 +66075,33 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} hwrm_nvm_erase_dir_entry_output_t, *phwrm_nvm_erase_dir_entry_output_t; + /* Non-zero firmware timestamp */ + uint32_t nz_fw_timestamp; + /* The last selected USID */ + uint16_t last_usid; + /* The number of USEQs currently allocated */ + uint16_t num_useq_allocd; + /* Flags indicating current USEQ engine state */ + uint32_t useq_resp_flags; + /* When set, there is at least some data available to be delivered */ + #define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) + /* When set, all internal buffers are full */ + #define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) + #define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW + /* Current count of the number of full buffers available for delivery */ + uint8_t full_cnt; + /* Reserved */ + uint8_t useq_resp_unused_0[3]; +} hwrm_dbg_useq_cw_cfg_output_t, *phwrm_dbg_useq_cw_cfg_output_t; -/************************* - * hwrm_nvm_get_dev_info * - *************************/ +/*********************** + * hwrm_dbg_useq_qcaps * + ***********************/ -/* hwrm_nvm_get_dev_info_input (size:128b/16B) */ +/* hwrm_dbg_useq_qcaps_input (size:128b/16B) */ -typedef struct hwrm_nvm_get_dev_info_input { +typedef struct hwrm_dbg_useq_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62432,11 +66130,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_nvm_get_dev_info_input_t, *phwrm_nvm_get_dev_info_input_t; +} hwrm_dbg_useq_qcaps_input_t, *phwrm_dbg_useq_qcaps_input_t; -/* hwrm_nvm_get_dev_info_output (size:640b/80B) */ +/* hwrm_dbg_useq_qcaps_output (size:384b/48B) */ -typedef struct hwrm_nvm_get_dev_info_output { +typedef struct hwrm_dbg_useq_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62445,119 +66143,153 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Manufacturer ID. */ - uint16_t manufacturer_id; - /* Device ID. */ - uint16_t device_id; - /* Sector size of the NVRAM device. */ - uint32_t sector_size; - /* Total size, in bytes of the NVRAM device. */ - uint32_t nvram_size; - uint32_t reserved_size; + /* Non-zero firmware timestamp */ + uint32_t nz_fw_timestamp; + /* The last selected USID */ + uint16_t last_usid; + /* The number of USEQs currently allocated */ + uint16_t num_useq_allocd; + /* Flags indicating current USEQ engine state */ + uint32_t useq_resp_flags; + /* When set, there is at least some data available to be delivered */ + #define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) + /* When set, all internal buffers are full */ + #define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) + #define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW + /* Current count of the number of full buffers available for delivery */ + uint8_t full_cnt; + /* Reserved */ + uint8_t useq_resp_unused_0[3]; + /* Maximum number of USEQ that can be tracked by firmware */ + uint32_t max_num_useq; + /* Maximum number of code word bytes for a single USEQ */ + uint32_t max_useq_size; + /* The maximum number of output bytes a single USEQ may generate */ + uint32_t max_useq_32b_output_size; + /* The number of internal USEQ output buffers, each of 4096 bytes */ + uint32_t num_buf; + /* This field is reserved */ + uint32_t unused_0; /* - * Available size that can be used, in bytes. Available size is the - * NVRAM size take away the used size and reserved size. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint32_t available_size; - /* This field represents the major version of NVM cfg */ - uint8_t nvm_cfg_ver_maj; - /* This field represents the minor version of NVM cfg */ - uint8_t nvm_cfg_ver_min; - /* This field represents the update version of NVM cfg */ - uint8_t nvm_cfg_ver_upd; - uint8_t flags; + uint32_t valid; +} hwrm_dbg_useq_qcaps_output_t, *phwrm_dbg_useq_qcaps_output_t; + +/*************************** + * hwrm_dbg_useq_sched_cfg * + ***************************/ + + +/* hwrm_dbg_useq_sched_cfg_input (size:192b/24B) */ + +typedef struct hwrm_dbg_useq_sched_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * If set to 1, firmware will provide various firmware version - * information stored in the flash. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID UINT32_C(0x1) + uint16_t cmpl_ring; /* - * This field represents the board package name stored in the flash. - * (ASCII chars with NULL at the end). + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - char pkg_name[16]; + uint16_t seq_id; /* - * This field represents the major version of HWRM firmware, stored in - * the flash. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t hwrm_fw_major; + uint16_t target_id; /* - * This field represents the minor version of HWRM firmware, stored in - * the flash. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t hwrm_fw_minor; + uint64_t resp_addr; + /* Enumeration values for enabling, disabling scheduler */ + uint16_t global_cfg; + /* This value will leave the global scheduler in its current state */ + #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_NO_CHANGE UINT32_C(0x0) /* - * This field represents the build version of HWRM firmware, stored in - * the flash. + * This value disables the global scheduler. This mode must be used + * when the RUN command is being used to run individual sequences. */ - uint16_t hwrm_fw_build; + #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_DISABLE UINT32_C(0x1) /* - * This field can be used to represent firmware branches or customer - * specific releases tied to a specific (major, minor, build) version - * of the HWRM firmware. + * This value enables the global scheduler. When enabled, USEQs will + * be scheduled based on their polling intervals */ - uint16_t hwrm_fw_patch; + #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_ENABLE UINT32_C(0x2) + #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_LAST HWRM_DBG_USEQ_SCHED_CFG_INPUT_ENABLE /* - * This field represents the major version of mgmt firmware, stored in - * the flash. - */ - uint16_t mgmt_fw_major; - /* - * This field represents the minor version of mgmt firmware, stored in - * the flash. - */ - uint16_t mgmt_fw_minor; - /* - * This field represents the build version of mgmt firmware, stored in - * the flash. - */ - uint16_t mgmt_fw_build; - /* - * This field can be used to represent firmware branches or customer - * specific releases tied to a specific (major, minor, build) version - * of the mgmt firmware. - */ - uint16_t mgmt_fw_patch; - /* - * This field represents the major version of roce firmware, stored in - * the flash. - */ - uint16_t roce_fw_major; - /* - * This field represents the minor version of roce firmware, stored in - * the flash. - */ - uint16_t roce_fw_minor; - /* - * This field represents the build version of roce firmware, stored in - * the flash. - */ - uint16_t roce_fw_build; - /* - * This field can be used to represent firmware branches or customer - * specific releases tied to a specific (major, minor, build) version - * of the roce firmware. + * The given polling interval will be associated with this USID. A + * value of -1 indicates that the USID is invalid. The invalid USID is + * used when using this message only for global scheduler + * configuration. */ - uint16_t roce_fw_patch; - uint8_t unused_0[7]; + uint16_t usid; + /* This value represents microseconds between runs of the USEQ */ + uint32_t polling_interval; +} hwrm_dbg_useq_sched_cfg_input_t, *phwrm_dbg_useq_sched_cfg_input_t; + +/* hwrm_dbg_useq_sched_cfg_output (size:256b/32B) */ + +typedef struct hwrm_dbg_useq_sched_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Non-zero firmware timestamp */ + uint32_t nz_fw_timestamp; + /* The last selected USID */ + uint16_t last_usid; + /* The number of USEQs currently allocated */ + uint16_t num_useq_allocd; + /* Flags indicating current USEQ engine state */ + uint32_t useq_resp_flags; + /* When set, there is at least some data available to be delivered */ + #define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) + /* When set, all internal buffers are full */ + #define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) + #define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW + /* Current count of the number of full buffers available for delivery */ + uint8_t full_cnt; + /* Reserved */ + uint8_t useq_resp_unused_0[3]; + /* This field is reserved */ + uint32_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint8_t valid; -} hwrm_nvm_get_dev_info_output_t, *phwrm_nvm_get_dev_info_output_t; + uint32_t valid; +} hwrm_dbg_useq_sched_cfg_output_t, *phwrm_dbg_useq_sched_cfg_output_t; -/************************** - * hwrm_nvm_mod_dir_entry * - **************************/ +/********************* + * hwrm_dbg_useq_run * + *********************/ -/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ +/* hwrm_dbg_useq_run_input (size:320b/40B) */ -typedef struct hwrm_nvm_mod_dir_entry_input { +typedef struct hwrm_dbg_useq_run_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62586,39 +66318,56 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; + /* The USID to be run */ + uint16_t usid; + /* Type of run to execute for the given USID */ + uint8_t run_type; + /* This run type will execute the requested USEQ only a single time */ + #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_SINGLE UINT32_C(0x0) /* - * This bit must be '1' for the checksum field to be - * configured. + * This run type will execute the requested USEQ a number of times + * given by run_cnt with a run interval given by the run_interval + * parameter. */ - #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1) - /* Directory Entry Index */ - uint16_t dir_idx; + #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_CNT UINT32_C(0x1) /* - * Directory ordinal. - * The (0-based) instance of this Directory Type. + * This run type will execute the requested USEQ as many times as it + * needs to fill an entire buffer to return to the host. The runs + * will occur with a run interval given by the run_interval + * parameter. */ - uint16_t dir_ordinal; + #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_FILL_BUF UINT32_C(0x2) + #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_LAST HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_FILL_BUF /* - * The Directory Entry Extension flags (see BNX_DIR_EXT_* for - * extension flag definitions). + * If indicated by flags, this represents the number of times to run + * the USEQ. Note that runs are stopped if the buffer fills prior + * regardless of the number of runs. For example, if a run_cnt of 10 is + * specified and 3 runs results in the buffer being full then only 3 + * runs are executed. */ - uint16_t dir_ext; + uint8_t run_cnt; /* - * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute - * flag definitions). + * This value represents microseconds between runs of the USEQ when + * running multiple times as indicated by flags. */ - uint16_t dir_attr; + uint32_t run_interval; /* - * If valid, then this field updates the checksum - * value of the content in the directory entry. + * Address of the host buffer where collected USEQ output data will be + * placed */ - uint32_t checksum; -} hwrm_nvm_mod_dir_entry_input_t, *phwrm_nvm_mod_dir_entry_input_t; + uint64_t host_dest_addr; + /* + * Size, in bytes, of the memory associated with host_dest_addr. It is + * expected that this is >= 4096 + */ + uint32_t host_dest_len; + /* This field is reserved */ + uint32_t unused_0; +} hwrm_dbg_useq_run_input_t, *phwrm_dbg_useq_run_input_t; -/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ +/* hwrm_dbg_useq_run_output (size:256b/32B) */ -typedef struct hwrm_nvm_mod_dir_entry_output { +typedef struct hwrm_dbg_useq_run_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62627,25 +66376,47 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Non-zero firmware timestamp */ + uint32_t nz_fw_timestamp; + /* The last selected USID */ + uint16_t last_usid; + /* The number of USEQs currently allocated */ + uint16_t num_useq_allocd; + /* Flags indicating current USEQ engine state */ + uint32_t useq_resp_flags; + /* When set, there is at least some data available to be delivered */ + #define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) + /* When set, all internal buffers are full */ + #define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) + #define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW + /* Current count of the number of full buffers available for delivery */ + uint8_t full_cnt; + /* Reserved */ + uint8_t useq_resp_unused_0[3]; + /* + * The length, in bytes, of the amount of data placed in the + * corresponding host_dest_addr given in the input message. This will + * always be a multiple of 4096 + */ + uint32_t host_dest_filled_len; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint8_t valid; -} hwrm_nvm_mod_dir_entry_output_t, *phwrm_nvm_mod_dir_entry_output_t; + uint32_t valid; +} hwrm_dbg_useq_run_output_t, *phwrm_dbg_useq_run_output_t; -/************************** - * hwrm_nvm_verify_update * - **************************/ +/****************************** + * hwrm_dbg_useq_delivery_req * + ******************************/ -/* hwrm_nvm_verify_update_input (size:192b/24B) */ +/* hwrm_dbg_useq_delivery_req_input (size:896b/112B) */ -typedef struct hwrm_nvm_verify_update_input { +typedef struct hwrm_dbg_useq_delivery_req_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62674,29 +66445,23 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Directory Entry Type, to be verified. */ - uint16_t dir_type; /* - * Directory ordinal. - * The instance of the Directory Type to be verified. + * Eight destination addresses provide host memory space for FW to + * deliver USEQ output details. A value of 0x0 for the address can be + * used to inform FW that the buffer is not available. */ - uint16_t dir_ordinal; + uint64_t host_dest_addrs[8]; /* - * The Directory Entry Extension flags. - * The "UPDATE" extension flag must be set in this value. - * A corresponding directory entry with the same type and ordinal - * values but *without* - * the "UPDATE" extension flag must also exist. The other flags of - * the extension must - * be identical between the active and update entries. + * The length, in bytes, of the corresponding host_dest_addrs array + * entry. Each valid hist_dest_addrs entry must have a len of at least + * 4096 bytes. */ - uint16_t dir_ext; - uint8_t unused_0[2]; -} hwrm_nvm_verify_update_input_t, *phwrm_nvm_verify_update_input_t; + uint32_t host_dest_len[8]; +} hwrm_dbg_useq_delivery_req_input_t, *phwrm_dbg_useq_delivery_req_input_t; -/* hwrm_nvm_verify_update_output (size:128b/16B) */ +/* hwrm_dbg_useq_delivery_req_output (size:512b/64B) */ -typedef struct hwrm_nvm_verify_update_output { +typedef struct hwrm_dbg_useq_delivery_req_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62705,25 +66470,49 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Non-zero firmware timestamp */ + uint32_t nz_fw_timestamp; + /* The last selected USID */ + uint16_t last_usid; + /* The number of USEQs currently allocated */ + uint16_t num_useq_allocd; + /* Flags indicating current USEQ engine state */ + uint32_t useq_resp_flags; + /* When set, there is at least some data available to be delivered */ + #define HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1) + /* When set, all internal buffers are full */ + #define HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2) + #define HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_LAST HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW + /* Current count of the number of full buffers available for delivery */ + uint8_t full_cnt; + /* Reserved */ + uint8_t useq_resp_unused_0[3]; + /* + * The length, in bytes, of the amount of data placed in the + * corresponding host_dest_addrs entry given in the input message. This + * will always be a multiple of 4096. + */ + uint32_t host_dest_filled_len[8]; + /* This field is reserved */ + uint32_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ - uint8_t valid; -} hwrm_nvm_verify_update_output_t, *phwrm_nvm_verify_update_output_t; + uint32_t valid; +} hwrm_dbg_useq_delivery_req_output_t, *phwrm_dbg_useq_delivery_req_output_t; -/*************************** - * hwrm_nvm_install_update * - ***************************/ +/***************************** + * hwrm_dbg_log_buffer_flush * + *****************************/ -/* hwrm_nvm_install_update_input (size:192b/24B) */ +/* hwrm_dbg_log_buffer_flush_input (size:192b/24B) */ -typedef struct hwrm_nvm_install_update_input { +typedef struct hwrm_dbg_log_buffer_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62752,59 +66541,36 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Type of trace buffer to flush. */ + uint16_t type; + /* SRT trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT_TRACE UINT32_C(0x0) + /* SRT2 trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1) + /* CRT trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT_TRACE UINT32_C(0x2) + /* CRT2 trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT2_TRACE UINT32_C(0x3) + /* RIGP0 trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x4) + /* L2 HWRM trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x5) + /* RoCE HWRM trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6) + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_LAST HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_ROCE_HWRM_TRACE + uint8_t unused_1[2]; + /* Control flags. */ + uint32_t flags; /* - * Installation type. If the value 3 through 0xffff is used, - * only packaged items with that type value will be installed and - * conditional installation directives for those packaged items - * will be over-ridden (i.e. 'create' or 'replace' will be treated - * as 'install'). - */ - uint32_t install_type; - /* - * Perform a normal package installation. Conditional installation - * directives (e.g. 'create' and 'replace') of packaged items - * will be followed. - */ - #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0) - /* - * Install all packaged items regardless of installation directive - * (i.e. treat all packaged items as though they have an installation - * directive of 'install'). - */ - #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL UINT32_C(0xffffffff) - #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL - uint16_t flags; - /* - * If set to 1, then securely erase all unused locations in - * persistent storage. - */ - #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE UINT32_C(0x1) - /* - * If set to 1, then unspecified images, images not in the package - * file, will be safely deleted. - * When combined with erase_unused_space then unspecified images will - * be securely erased. - */ - #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG UINT32_C(0x2) - /* - * If set to 1, FW will defragment the NVM if defragmentation is - * required for the update. - * Allow additional time for this command to complete if this bit is - * set to 1. - */ - #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG UINT32_C(0x4) - /* - * If set to 1, FW will verify the package in the "UPDATE" NVM item - * without installing it. This flag is for FW internal use only. - * Users should not set this flag. The request will otherwise fail. + * When set, it indicates that all buffers should be flushed. + * The type will be ignored. */ - #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY UINT32_C(0x8) - uint8_t unused_0[2]; -} hwrm_nvm_install_update_input_t, *phwrm_nvm_install_update_input_t; + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_FLAGS_FLUSH_ALL_BUFFERS UINT32_C(0x1) +} hwrm_dbg_log_buffer_flush_input_t, *phwrm_dbg_log_buffer_flush_input_t; -/* hwrm_nvm_install_update_output (size:192b/24B) */ +/* hwrm_dbg_log_buffer_flush_output (size:128b/16B) */ -typedef struct hwrm_nvm_install_update_output { +typedef struct hwrm_dbg_log_buffer_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62814,140 +66580,32 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Bit-mask of successfully installed items. - * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc. - * A value of 0 indicates that no items were successfully installed. - */ - uint64_t installed_items; - /* result is 8 b corresponding to BCMRETVAL error codes */ - uint8_t result; - /* There was no problem with the package installation. */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0) - /* Generic failure */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE UINT32_C(0xff) - /* Allocation error malloc failure */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE UINT32_C(0xfd) - /* NVM install error due to invalid index */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER UINT32_C(0xfb) - /* NVM install error due to invalid type */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER UINT32_C(0xf3) - /* Invalid package due to invalid prerequisite */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE UINT32_C(0xf2) - /* Invalid package due to invalid file header */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER UINT32_C(0xec) - /* Invalid package due to invalid format */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE UINT32_C(0xeb) - /* Invalid package due to invalid property stream */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM UINT32_C(0xea) - /* Invalid package due to invalid property length */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH UINT32_C(0xe9) - /* Invalid package due to invalid manifest */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST UINT32_C(0xe8) - /* Invalid package due to invalid trailer */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER UINT32_C(0xe7) - /* Invalid package due to invalid checksum */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM UINT32_C(0xe6) - /* Invalid package due to invalid item checksum */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM UINT32_C(0xe5) - /* Invalid package due to invalid length */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH UINT32_C(0xe4) - /* Invalid package due to invalid directive */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE UINT32_C(0xe1) - /* Invalid device due to unsupported chip revision */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV UINT32_C(0xce) - /* Invalid device due to unsupported device ID */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID UINT32_C(0xcd) - /* Invalid device due to unsupported subsystem vendor */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR UINT32_C(0xcc) - /* Invalid device due to unsupported subsystem ID */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID UINT32_C(0xcb) - /* Invalid device due to unsupported product ID or customer ID */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM UINT32_C(0xc5) - /* Invalid package due to duplicate item */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM UINT32_C(0xc4) - /* Invalid package due to zero length item */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM UINT32_C(0xc3) - /* NVM integrity error checksum */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR UINT32_C(0xb9) - /* NVM integrity error */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR UINT32_C(0xb8) - /* Authentication error */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR UINT32_C(0xb7) - /* NVM install error item not found */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND UINT32_C(0xb0) - /* NVM install error item locked */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED UINT32_C(0xa7) - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED - /* problem_item is 8 b */ - uint8_t problem_item; - /* There was no problem with any packaged items. */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE UINT32_C(0x0) - /* There was a problem with the NVM package itself. */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE UINT32_C(0xff) - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE - /* reset_required is 8 b */ - uint8_t reset_required; - /* - * No reset is required for installed/updated firmware or - * microcode to take effect. - */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE UINT32_C(0x0) - /* - * A PCIe reset (e.g. system reboot) is - * required for newly installed/updated firmware or - * microcode to take effect. - */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI UINT32_C(0x1) - /* - * A controller power reset (e.g. system power-cycle) is - * required for newly installed/updated firmware or - * microcode to take effect. Some newly installed/updated - * firmware or microcode may still take effect upon the - * next PCIe reset. + * Specifies the current host buffer offset. Data up to this offset + * has been populated by the firmware. For example, if the firmware + * has DMA-ed 8192 bytes to the host buffer, then this field has a + * value of 8192. This field rolls over to zero once the firmware + * writes the last page of the host buffer */ - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER UINT32_C(0x2) - #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER - uint8_t unused_0[4]; + uint32_t current_buffer_offset; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_install_update_output_t, *phwrm_nvm_install_update_output_t; - -/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ - -typedef struct hwrm_nvm_install_update_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* Unable to complete operation due to fragmentation */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) - /* nvm is completely full. */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) - /* Firmware update failed due to Anti-rollback. */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK UINT32_C(0x3) - /* Firmware update does not support voltage regulators on the device. */ - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT UINT32_C(0x4) - #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT - uint8_t unused_0[7]; -} hwrm_nvm_install_update_cmd_err_t, *phwrm_nvm_install_update_cmd_err_t; +} hwrm_dbg_log_buffer_flush_output_t, *phwrm_dbg_log_buffer_flush_output_t; -/****************** - * hwrm_nvm_flush * - ******************/ +/************************** + * hwrm_nvm_raw_write_blk * + **************************/ -/* hwrm_nvm_flush_input (size:128b/16B) */ +/* hwrm_nvm_raw_write_blk_input (size:320b/40B) */ -typedef struct hwrm_nvm_flush_input { +typedef struct hwrm_nvm_raw_write_blk_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -62976,11 +66634,34 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_nvm_flush_input_t, *phwrm_nvm_flush_input_t; + /* + * 64-bit Host Source Address. + * This is the location of the source data to be written. + */ + uint64_t host_src_addr; + /* + * 32-bit Destination Address. + * This is the NVRAM byte-offset where the source data will be written + * to. + */ + uint32_t dest_addr; + /* Length of data to be written, in bytes. */ + uint32_t len; + uint8_t flags; + /* + * This bit is only used when external secure SoC is used for + * secure boot. This bit is utilized to differentiate between + * writes for NIC or Security SoC non-volatile storage on the + * device. If this bit is set, then this write is for the + * Security SoC non-volatile storage on the device. + */ + #define HWRM_NVM_RAW_WRITE_BLK_INPUT_FLAGS_SECURITY_SOC_NVM UINT32_C(0x1) + uint8_t unused_0[7]; +} hwrm_nvm_raw_write_blk_input_t, *phwrm_nvm_raw_write_blk_input_t; -/* hwrm_nvm_flush_output (size:128b/16B) */ +/* hwrm_nvm_raw_write_blk_output (size:128b/16B) */ -typedef struct hwrm_nvm_flush_output { +typedef struct hwrm_nvm_raw_write_blk_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -62992,38 +66673,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_flush_output_t, *phwrm_nvm_flush_output_t; - -/* hwrm_nvm_flush_cmd_err (size:64b/8B) */ - -typedef struct hwrm_nvm_flush_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* flush could not be performed */ - #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1) - #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL - uint8_t unused_0[7]; -} hwrm_nvm_flush_cmd_err_t, *phwrm_nvm_flush_cmd_err_t; +} hwrm_nvm_raw_write_blk_output_t, *phwrm_nvm_raw_write_blk_output_t; -/************************* - * hwrm_nvm_get_variable * - *************************/ +/***************** + * hwrm_nvm_read * + *****************/ -/* hwrm_nvm_get_variable_input (size:320b/40B) */ +/* hwrm_nvm_read_input (size:320b/40B) */ -typedef struct hwrm_nvm_get_variable_input { +typedef struct hwrm_nvm_read_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63053,111 +66718,50 @@ */ uint64_t resp_addr; /* - * This is the host address where - * nvm variable will be stored + * 64-bit Host Destination Address. + * This is the host address where the data will be written to. */ - uint64_t dest_data_addr; - /* size of data in bits */ - uint16_t data_len; - /* nvm cfg option number */ - uint16_t option_num; - /* reserved. */ - #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0) - /* reserved. */ - #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff) - #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF - /* - * Number of dimensions for this nvm configuration variable. - * This value indicates how many of the indexN values to use. - * A value of 0 means that none of the indexN values are valid. - * A value of 1 requires at index0 is valued, a value of 2 - * requires that index0 and index1 are valid, and so forth - */ - uint16_t dimensions; - /* index for the 1st dimensions */ - uint16_t index_0; - /* index for the 2nd dimensions */ - uint16_t index_1; - /* index for the 3rd dimensions */ - uint16_t index_2; - /* index for the 4th dimensions */ - uint16_t index_3; - uint8_t flags; - /* - * When this bit is set to 1, the factory default value will be returned, - * 0 returns the operational value. - */ - #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT UINT32_C(0x1) - uint8_t unused_0; -} hwrm_nvm_get_variable_input_t, *phwrm_nvm_get_variable_input_t; - -/* hwrm_nvm_get_variable_output (size:128b/16B) */ - -typedef struct hwrm_nvm_get_variable_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* size of data of the actual variable retrieved in bits */ - uint16_t data_len; - /* - * option_num is the option number for the data retrieved. It is - * possible in the future that the option number returned would be - * different than requested. This condition could occur if an option is - * deprecated and a new option id is defined with similar - * characteristics, but has a slightly different definition. This - * also makes it convenient for the caller to identify the variable - * result with the option id from the response. - */ - uint16_t option_num; - /* reserved. */ - #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0) - /* reserved. */ - #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff) - #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF - uint8_t unused_0[3]; + uint64_t host_dest_addr; + /* The 0-based index of the directory entry. */ + uint16_t dir_idx; + uint8_t unused_0[2]; + /* The NVRAM byte-offset to read from. */ + uint32_t offset; + /* The length of the data to be read, in bytes. */ + uint32_t len; + uint8_t unused_1[4]; +} hwrm_nvm_read_input_t, *phwrm_nvm_read_input_t; + +/* hwrm_nvm_read_output (size:128b/16B) */ + +typedef struct hwrm_nvm_read_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_get_variable_output_t, *phwrm_nvm_get_variable_output_t; - -/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ - -typedef struct hwrm_nvm_get_variable_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* variable does not exist */ - #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1) - /* configuration is corrupted and the variable cannot be saved */ - #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2) - /* length specified is too small */ - #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3) - #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT - uint8_t unused_0[7]; -} hwrm_nvm_get_variable_cmd_err_t, *phwrm_nvm_get_variable_cmd_err_t; +} hwrm_nvm_read_output_t, *phwrm_nvm_read_output_t; -/************************* - * hwrm_nvm_set_variable * - *************************/ +/********************* + * hwrm_nvm_raw_dump * + *********************/ -/* hwrm_nvm_set_variable_input (size:320b/40B) */ +/* hwrm_nvm_raw_dump_input (size:320b/40B) */ -typedef struct hwrm_nvm_set_variable_input { +typedef struct hwrm_nvm_raw_dump_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63187,63 +66791,29 @@ */ uint64_t resp_addr; /* - * This is the host address where - * nvm variable will be copied from - */ - uint64_t src_data_addr; - /* size of data in bits */ - uint16_t data_len; - /* nvm cfg option number */ - uint16_t option_num; - /* reserved. */ - #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0) - /* reserved. */ - #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff) - #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF - /* - * Number of dimensions for this nvm configuration variable. - * This value indicates how many of the indexN values to use. - * A value of 0 means that none of the indexN values are valid. - * A value of 1 requires at index0 is valued, a value of 2 - * requires that index0 and index1 are valid, and so forth + * 64-bit Host Destination Address. + * This is the host address where the data will be written to. */ - uint16_t dimensions; - /* index for the 1st dimensions */ - uint16_t index_0; - /* index for the 2nd dimensions */ - uint16_t index_1; - /* index for the 3rd dimensions */ - uint16_t index_2; - /* index for the 4th dimensions */ - uint16_t index_3; + uint64_t host_dest_addr; + /* 32-bit NVRAM byte-offset to read from. */ + uint32_t offset; + /* Total length of NVRAM contents to be read, in bytes. */ + uint32_t len; uint8_t flags; /* - * When this bit is 1, flush internal cache after this write - * operation (see hwrm_nvm_flush command.) + * This bit is only used when external secure SoC is used for + * secure boot. This bit is utilized to differentiate between + * read for NIC or Security SoC non-volatile storage on the + * device. If this bit is set, then this read is for the Security + * SoC non-volatile storage on the device. */ - #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH UINT32_C(0x1) - /* encryption method */ - #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK UINT32_C(0xe) - #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1 - /* No encryption. */ - #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE (UINT32_C(0x0) << 1) - /* one-way encryption. */ - #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (UINT32_C(0x1) << 1) - /* symmetric AES256 encryption. */ - #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 (UINT32_C(0x2) << 1) - /* SHA1 digest appended to plaintext contents, for authentication */ - #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (UINT32_C(0x3) << 1) - #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH - #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK UINT32_C(0x70) - #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4 - /* When this bit is 1, update the factory default region */ - #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT UINT32_C(0x80) - uint8_t unused_0; -} hwrm_nvm_set_variable_input_t, *phwrm_nvm_set_variable_input_t; + #define HWRM_NVM_RAW_DUMP_INPUT_FLAGS_SECURITY_SOC_NVM UINT32_C(0x1) + uint8_t unused_0[7]; +} hwrm_nvm_raw_dump_input_t, *phwrm_nvm_raw_dump_input_t; -/* hwrm_nvm_set_variable_output (size:128b/16B) */ +/* hwrm_nvm_raw_dump_output (size:128b/16B) */ -typedef struct hwrm_nvm_set_variable_output { +typedef struct hwrm_nvm_raw_dump_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63255,40 +66825,22 @@ uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_set_variable_output_t, *phwrm_nvm_set_variable_output_t; - -/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ - -typedef struct hwrm_nvm_set_variable_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* variable does not exist */ - #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1) - /* configuration is corrupted and the variable cannot be saved */ - #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2) - #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR - uint8_t unused_0[7]; -} hwrm_nvm_set_variable_cmd_err_t, *phwrm_nvm_set_variable_cmd_err_t; +} hwrm_nvm_raw_dump_output_t, *phwrm_nvm_raw_dump_output_t; /**************************** - * hwrm_nvm_validate_option * + * hwrm_nvm_get_dir_entries * ****************************/ -/* hwrm_nvm_validate_option_input (size:320b/40B) */ +/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ -typedef struct hwrm_nvm_validate_option_input { +typedef struct hwrm_nvm_get_dir_entries_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63318,41 +66870,15 @@ */ uint64_t resp_addr; /* - * This is the host address where - * nvm variable will be copied from - */ - uint64_t src_data_addr; - /* size of data in bits */ - uint16_t data_len; - /* nvm cfg option number */ - uint16_t option_num; - /* reserved. */ - #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0) - /* reserved. */ - #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff) - #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF - /* - * Number of dimensions for this nvm configuration variable. - * This value indicates how many of the indexN values to use. - * A value of 0 means that none of the indexN values are valid. - * A value of 1 requires at index0 is valued, a value of 2 - * requires that index0 and index1 are valid, and so forth + * 64-bit Host Destination Address. + * This is the host address where the directory will be written. */ - uint16_t dimensions; - /* index for the 1st dimensions */ - uint16_t index_0; - /* index for the 2nd dimensions */ - uint16_t index_1; - /* index for the 3rd dimensions */ - uint16_t index_2; - /* index for the 4th dimensions */ - uint16_t index_3; - uint8_t unused_0[2]; -} hwrm_nvm_validate_option_input_t, *phwrm_nvm_validate_option_input_t; + uint64_t host_dest_addr; +} hwrm_nvm_get_dir_entries_input_t, *phwrm_nvm_get_dir_entries_input_t; -/* hwrm_nvm_validate_option_output (size:128b/16B) */ +/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ -typedef struct hwrm_nvm_validate_option_output { +typedef struct hwrm_nvm_get_dir_entries_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63361,51 +66887,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t result; - /* - * indicates that the value provided for the option is not matching - * with the saved data. - */ - #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0) - /* - * indicates that the value provided for the option is matching the - * saved data. - */ - #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1) - #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH - uint8_t unused_0[6]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_validate_option_output_t, *phwrm_nvm_validate_option_output_t; - -/* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */ - -typedef struct hwrm_nvm_validate_option_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN - uint8_t unused_0[7]; -} hwrm_nvm_validate_option_cmd_err_t, *phwrm_nvm_validate_option_cmd_err_t; +} hwrm_nvm_get_dir_entries_output_t, *phwrm_nvm_get_dir_entries_output_t; -/***************************** - * hwrm_nvm_factory_defaults * - *****************************/ +/************************* + * hwrm_nvm_get_dir_info * + *************************/ -/* hwrm_nvm_factory_defaults_input (size:192b/24B) */ +/* hwrm_nvm_get_dir_info_input (size:128b/16B) */ -typedef struct hwrm_nvm_factory_defaults_input { +typedef struct hwrm_nvm_get_dir_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63434,40 +66934,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* mode is 8 b */ - uint8_t mode; - /* - * If set to 1, it triggers restoration of factory default data. - * If the selection field is zero, all data are restored to default. - * If the selection field is non-zero, only the selected data are - * restored. - */ - #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0) - /* - * If set to 1, it triggers creation of factory default data. - * If the selection field is zero, all default data are created. - * If the selection field is non-zero, only the selected data are - * created. - */ - #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE UINT32_C(0x1) - #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_LAST HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE - uint8_t unused_0[1]; - /* - * This field selects which data the factory default operation applies. - * If it is '0', the operation applies to all data. If it is not '0', - * the operation only applies to the data selected by this field. - */ - uint16_t selection; - /* When this bit is '1', config option is selected. */ - #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_SELECTION_CFG_OPTION UINT32_C(0x1) - /* When this bit is '1', crashdump is selected. */ - #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_SELECTION_CRASHDUMP UINT32_C(0x2) - uint8_t unused_1[4]; -} hwrm_nvm_factory_defaults_input_t, *phwrm_nvm_factory_defaults_input_t; +} hwrm_nvm_get_dir_info_input_t, *phwrm_nvm_get_dir_info_input_t; -/* hwrm_nvm_factory_defaults_output (size:128b/16B) */ +/* hwrm_nvm_get_dir_info_output (size:192b/24B) */ -typedef struct hwrm_nvm_factory_defaults_output { +typedef struct hwrm_nvm_get_dir_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63476,51 +66947,29 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t result; - /* factory defaults created successfully. */ - #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK UINT32_C(0x0) - /* factory defaults restored successfully. */ - #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK UINT32_C(0x1) - /* factory defaults already created. */ - #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY UINT32_C(0x2) - #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_LAST HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY - uint8_t unused_0[6]; + /* Number of directory entries in the directory. */ + uint32_t entries; + /* Size of each directory entry, in bytes. */ + uint32_t entry_length; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_factory_defaults_output_t, *phwrm_nvm_factory_defaults_output_t; - -/* hwrm_nvm_factory_defaults_cmd_err (size:64b/8B) */ - -typedef struct hwrm_nvm_factory_defaults_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* valid configuration not present to create defaults */ - #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG UINT32_C(0x1) - /* No saved configuration present to restore, restore failed */ - #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG UINT32_C(0x2) - #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_LAST HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG - uint8_t unused_0[7]; -} hwrm_nvm_factory_defaults_cmd_err_t, *phwrm_nvm_factory_defaults_cmd_err_t; +} hwrm_nvm_get_dir_info_output_t, *phwrm_nvm_get_dir_info_output_t; -/**************************** - * hwrm_nvm_req_arbitration * - ****************************/ +/****************** + * hwrm_nvm_write * + ******************/ -/* hwrm_nvm_req_arbitration_input (size:192b/24B) */ +/* hwrm_nvm_write_input (size:448b/56B) */ -typedef struct hwrm_nvm_req_arbitration_input { +typedef struct hwrm_nvm_write_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63549,21 +66998,93 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Type of NVRAM arbitration request */ - uint8_t type; - /* Query if NVRAM arbitration semaphore is acquired outside of Nitro */ - #define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_STATUS UINT32_C(0x0) - /* Acquire NVRAM arbitration semaphore */ - #define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_ACQUIRE UINT32_C(0x1) - /* Release NVRAM arbitration semaphore */ - #define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_RELEASE UINT32_C(0x2) - #define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_LAST HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_RELEASE - uint8_t unused_0[7]; -} hwrm_nvm_req_arbitration_input_t, *phwrm_nvm_req_arbitration_input_t; + /* + * 64-bit Host Source Address. + * This is where the source data is. + */ + uint64_t host_src_addr; + /* + * The Directory Entry Type (valid values are defined in the + * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). + */ + uint16_t dir_type; + /* + * Directory ordinal. + * The 0-based instance of the combined Directory Entry Type and + * Extension. + */ + uint16_t dir_ordinal; + /* + * The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file + * bnxnvm_defs.h). + */ + uint16_t dir_ext; + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file + * bnxnvm_defs.h). + */ + uint16_t dir_attr; + /* + * Length of data to write, in bytes. May be less than or equal to the + * allocated size for the directory entry. + * The data length stored in the directory entry will be updated to + * reflect this value once the write is complete. + */ + uint32_t dir_data_length; + /* Option. */ + uint16_t option; + uint16_t flags; + /* + * When this bit is '1', the original active image + * will not be removed. TBD: what purpose is this? + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG UINT32_C(0x1) + /* + * This flag indicates the sender wants to modify a continuous + * NVRAM area using a batch of this HWRM requests. The + * offset of a request must be continuous to the end of previous + * request's. Firmware does not update the directory entry until + * receiving the last request, which is indicated by the batch_last + * flag. This flag is set usually when a sender does not have a + * block of memory that is big enough to hold the entire NVRAM + * data for send at one time. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE UINT32_C(0x2) + /* + * This flag can be used only when the batch_mode flag is set. It + * indicates this request is the last of batch requests. + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST UINT32_C(0x4) + /* + * The requested length of the allocated NVM for the item, in bytes. + * This value may be greater than or equal to the specified data + * length (dir_data_length). + * If this value is less than the specified data length, it will be + * ignored. The response will contain the actual allocated item length, + * which may be greater than the requested item length. + * The purpose for allocating more than the required number of bytes + * for an item's data is to pre-allocate extra storage (padding) to + * accommodate the potential future growth of an item (e.g. upgraded + * firmware with a size increase, log growth, expanded configuration + * data). + */ + uint32_t dir_item_length; + /* + * 32-bit offset of data blob from where data is being written. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t offset; + /* + * Length of data to be written.Should be non-zero. + * Only valid for batch mode. For non-batch writes 'dont care'. + */ + uint32_t len; + uint32_t unused_0; +} hwrm_nvm_write_input_t, *phwrm_nvm_write_input_t; -/* hwrm_nvm_req_arbitration_output (size:128b/16B) */ +/* hwrm_nvm_write_output (size:128b/16B) */ -typedef struct hwrm_nvm_req_arbitration_output { +typedef struct hwrm_nvm_write_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -63572,27 +67093,53 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* NVRAM arbitration semaphore is acquired if value is 1 */ - uint8_t acquired; - uint8_t unused_0[6]; + /* + * Length of the allocated NVM for the item, in bytes. The value may be + * greater than or equal to the specified data length or the requested + * item length. + * The actual item length used when creating a new directory entry will + * be a multiple of an NVM block size. + */ + uint32_t dir_item_length; + /* The directory index of the created or modified item. */ + uint16_t dir_idx; + uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_nvm_req_arbitration_output_t, *phwrm_nvm_req_arbitration_output_t; +} hwrm_nvm_write_output_t, *phwrm_nvm_write_output_t; + +/* hwrm_nvm_write_cmd_err (size:64b/8B) */ + +typedef struct hwrm_nvm_write_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Unable to complete operation due to fragmentation */ + #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + /* nvm is completely full. */ + #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE + uint8_t unused_0[7]; +} hwrm_nvm_write_cmd_err_t, *phwrm_nvm_write_cmd_err_t; /******************* - * hwrm_nvm_defrag * + * hwrm_nvm_modify * *******************/ -/* hwrm_nvm_defrag_input (size:192b/24B) */ +/* hwrm_nvm_modify_input (size:320b/40B) */ -typedef struct hwrm_nvm_defrag_input { +typedef struct hwrm_nvm_modify_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -63621,2891 +67168,1873 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* This bit must be '1' to perform NVM defragmentation. */ - #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1) - uint8_t unused_0[4]; -} hwrm_nvm_defrag_input_t, *phwrm_nvm_defrag_input_t; - -/* hwrm_nvm_defrag_output (size:128b/16B) */ - -typedef struct hwrm_nvm_defrag_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * 64-bit Host Source Address. + * This is where the modified data is. */ - uint8_t valid; -} hwrm_nvm_defrag_output_t, *phwrm_nvm_defrag_output_t; - -/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ - -typedef struct hwrm_nvm_defrag_cmd_err { + uint64_t host_src_addr; + /* 16-bit directory entry index. */ + uint16_t dir_idx; + uint16_t flags; /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* NVM defragmentation could not be performed */ - #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1) - #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL - uint8_t unused_0[7]; -} hwrm_nvm_defrag_cmd_err_t, *phwrm_nvm_defrag_cmd_err_t; - -#define ROCE_SP_HSI_VERSION_MAJOR 1 -#define ROCE_SP_HSI_VERSION_MINOR 8 -#define ROCE_SP_HSI_VERSION_UPDATE 4 -#define ROCE_SP_HSI_VERSION_STR "1.8.4" -/* - * Following is the signature for ROCE_SP_HSI message field that indicates not - * applicable (All F's). Need to cast it the size of the field if needed. - */ -#define ROCE_SP_HSI_NA_SIGNATURE ((uint32_t)(-1)) + * This flag indicates the sender wants to modify a continuous NVRAM + * area using a batch of this HWRM requests. The offset of a request + * must be continuous to the end of previous request's. Firmware does + * not update the directory entry until receiving the last request, + * which is indicated by the batch_last flag. + * This flag is set usually when a sender does not have a block of + * memory that is big enough to hold the entire NVRAM data for send + * at one time. + */ + #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1) + /* + * This flag can be used only when the batch_mode flag is set. + * It indicates this request is the last of batch requests. + */ + #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2) + /* 32-bit NVRAM byte-offset to modify content from. */ + uint32_t offset; + /* + * Length of data to be modified, in bytes. The length shall + * be non-zero. + */ + uint32_t len; + uint8_t unused_1[4]; +} hwrm_nvm_modify_input_t, *phwrm_nvm_modify_input_t; -/* cmdq_init (size:128b/16B) */ +/* hwrm_nvm_modify_output (size:128b/16B) */ -typedef struct cmdq_init { - /* CMDQ PBL physical address. */ - uint64_t cmdq_pbl; - uint16_t cmdq_size_cmdq_lvl; - /* CMDQ PBL indirection levels. */ - #define CMDQ_INIT_CMDQ_LVL_MASK UINT32_C(0x3) - #define CMDQ_INIT_CMDQ_LVL_SFT 0 - /* CMDQ size. */ - #define CMDQ_INIT_CMDQ_SIZE_MASK UINT32_C(0xfffc) - #define CMDQ_INIT_CMDQ_SIZE_SFT 2 - /* CREQ completion ring id. */ - uint16_t creq_ring_id; - /* Mailbox producer index. MSB must also be set. */ - uint32_t prod_idx; -} cmdq_init_t, *pcmdq_init_t; +typedef struct hwrm_nvm_modify_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_modify_output_t, *phwrm_nvm_modify_output_t; -/* cmdq_update (size:128b/16B) */ +/*************************** + * hwrm_nvm_find_dir_entry * + ***************************/ -typedef struct cmdq_update { - /* reserved64 is 64 b */ - uint64_t reserved64; - /* reserved32 is 32 b */ - uint32_t reserved32; - /* Mailbox producer index. */ - uint32_t prod_idx; -} cmdq_update_t, *pcmdq_update_t; -/* cmdq_base (size:128b/16B) */ +/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ -typedef struct cmdq_base { - /* Command opcode. */ - uint8_t opcode; - /* - * Create QP command allocates QP context with the specified - * SQ, RQ/SRQ, CQ and other parameters. - */ - #define CMDQ_BASE_OPCODE_CREATE_QP UINT32_C(0x1) +typedef struct hwrm_nvm_find_dir_entry_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Destroy QP command deletes the QP context and ceases - * any further reference. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define CMDQ_BASE_OPCODE_DESTROY_QP UINT32_C(0x2) + uint16_t cmpl_ring; /* - * Modify QP command changes QP states and other QP specific - * parameters. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define CMDQ_BASE_OPCODE_MODIFY_QP UINT32_C(0x3) - /* Query QP command retrieves info about the specified QP. */ - #define CMDQ_BASE_OPCODE_QUERY_QP UINT32_C(0x4) - /* Create SRQ command allocates a SRQ with the specified parameters. */ - #define CMDQ_BASE_OPCODE_CREATE_SRQ UINT32_C(0x5) - /* Destroy SRQ command deletes and flushes the specified SRQ. */ - #define CMDQ_BASE_OPCODE_DESTROY_SRQ UINT32_C(0x6) - /* Query SRP command retrieves info about the specified SRQ. */ - #define CMDQ_BASE_OPCODE_QUERY_SRQ UINT32_C(0x8) - /* Create CQ command allocates a CQ with the specified parameters. */ - #define CMDQ_BASE_OPCODE_CREATE_CQ UINT32_C(0x9) - /* Destroy CQ command deletes and flushes the specified CQ. */ - #define CMDQ_BASE_OPCODE_DESTROY_CQ UINT32_C(0xa) - /* Resize CQ command resizes the specified CQ. */ - #define CMDQ_BASE_OPCODE_RESIZE_CQ UINT32_C(0xc) + uint16_t seq_id; /* - * Allocate MRW command allocates a MR/MW with the specified parameters - * and returns the region's L_KEY/R_KEY + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define CMDQ_BASE_OPCODE_ALLOCATE_MRW UINT32_C(0xd) - /* De-allocate key command frees a MR/MW entry associated with the specified key. */ - #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY UINT32_C(0xe) - /* Register MR command registers memory to the specified MR. */ - #define CMDQ_BASE_OPCODE_REGISTER_MR UINT32_C(0xf) - /* Deregister MR command de-registers memory from the specified MR. */ - #define CMDQ_BASE_OPCODE_DEREGISTER_MR UINT32_C(0x10) - /* Add GID command adds a GID to the local address table. */ - #define CMDQ_BASE_OPCODE_ADD_GID UINT32_C(0x11) - /* Delete GID command deletes a GID from the local address table. */ - #define CMDQ_BASE_OPCODE_DELETE_GID UINT32_C(0x12) - /* Modify GID command modifies a GID in the local address table. */ - #define CMDQ_BASE_OPCODE_MODIFY_GID UINT32_C(0x17) - /* Query GID command queries a GID in the local address table. */ - #define CMDQ_BASE_OPCODE_QUERY_GID UINT32_C(0x18) - /* Create QP1 command allocates a QP1 only. */ - #define CMDQ_BASE_OPCODE_CREATE_QP1 UINT32_C(0x13) - /* Destroy QP1 command deletes and flushes the specified QP1. */ - #define CMDQ_BASE_OPCODE_DESTROY_QP1 UINT32_C(0x14) - /* Create AH command allocates an AH with the specified parameters. */ - #define CMDQ_BASE_OPCODE_CREATE_AH UINT32_C(0x15) - /* Destroy AH command deletes the specified AH. */ - #define CMDQ_BASE_OPCODE_DESTROY_AH UINT32_C(0x16) + uint16_t target_id; /* - * Initialize firmware command initializes the firmware with - * the specified parameters. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define CMDQ_BASE_OPCODE_INITIALIZE_FW UINT32_C(0x80) - /* De-initialize firmware command deinitializes the firmware. */ - #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW UINT32_C(0x81) - /* Stop the function */ - #define CMDQ_BASE_OPCODE_STOP_FUNC UINT32_C(0x82) - /* Query the HW capabilities for the function. */ - #define CMDQ_BASE_OPCODE_QUERY_FUNC UINT32_C(0x83) + uint64_t resp_addr; + uint32_t enables; /* - * Set the following resources for the function: - * - Max QP, CQ, MR+MW, SRQ per PF - * - Max QP, CQ, MR+MW, SRQ per VF + * This bit must be '1' for the dir_idx_valid field to be + * configured. */ - #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84) - /* Read the current state of any internal resource context. Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_READ_CONTEXT UINT32_C(0x85) - /* Send a request from VF to pass a command to the PF. VF HSI is suspended until the PF returns the response */ - #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86) - /* Read VF memory (primarily to get the backchannel request blob). Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_READ_VF_MEMORY UINT32_C(0x87) - /* Write VF memory (primarily to put the backchannel response blob), and reenable VF HSI (post a CAG completion to it). Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88) - /* Extend resource (QPC, MRW, CQ, SRQ) array, after the host allocates more. Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY UINT32_C(0x89) - /* Map TC to COS. Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a) - /* Query version. */ - #define CMDQ_BASE_OPCODE_QUERY_VERSION UINT32_C(0x8b) - /* Modify congestion control. Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c) - /* Query congestion control. */ - #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) - /* Query RoCE statistics. */ - #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e) - /* Set LAG mode. */ - #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE UINT32_C(0x8f) - /* Modify CQ */ - #define CMDQ_BASE_OPCODE_MODIFY_CQ UINT32_C(0x90) + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID UINT32_C(0x1) + /* Directory Entry Index */ + uint16_t dir_idx; + /* Directory Entry (Image) Type */ + uint16_t dir_type; /* - * Query QP for a PF other than the requesting PF. Also can query for more - * than one QP. + * Directory ordinal. + * The instance of this Directory Type */ - #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) - /* Query extended RoCE statistics. */ - #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92) - #define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; -} cmdq_base_t, *pcmdq_base_t; + uint16_t dir_ordinal; + /* The Directory Entry Extension flags. */ + uint16_t dir_ext; + /* This value indicates the search option using dir_ordinal. */ + uint8_t opt_ordinal; + /* This value indicates the search option using dir_ordinal. */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3) + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0 + /* Equal to specified ordinal value. */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0) + /* Greater than or equal to specified ordinal value */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1) + /* Greater than specified ordinal value */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2) + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT + uint8_t unused_0[3]; +} hwrm_nvm_find_dir_entry_input_t, *phwrm_nvm_find_dir_entry_input_t; -/* creq_base (size:128b/16B) */ +/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ -typedef struct creq_base { - uint8_t type; +typedef struct hwrm_nvm_find_dir_entry_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Allocated NVRAM for this directory entry, in bytes. */ + uint32_t dir_item_length; + /* Size of the stored data for this directory entry, in bytes. */ + uint32_t dir_data_length; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Firmware version. + * Only valid if the directory entry is for embedded firmware stored + * in APE_BIN Format. */ - #define CREQ_BASE_TYPE_MASK UINT32_C(0x3f) - #define CREQ_BASE_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_BASE_TYPE_QP_EVENT UINT32_C(0x38) - /* Function Async Notification */ - #define CREQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a) - #define CREQ_BASE_TYPE_LAST CREQ_BASE_TYPE_FUNC_EVENT - uint8_t reserved56[7]; - uint8_t v; + uint32_t fw_ver; + /* Directory ordinal. */ + uint16_t dir_ordinal; + /* Directory Entry Index */ + uint16_t dir_idx; + uint8_t unused_0[7]; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define CREQ_BASE_V UINT32_C(0x1) - /* This is the modifier on to the type field. */ - uint8_t event; - uint8_t reserved48[6]; -} creq_base_t, *pcreq_base_t; + uint8_t valid; +} hwrm_nvm_find_dir_entry_output_t, *phwrm_nvm_find_dir_entry_output_t; -/***************** - * query_version * - *****************/ +/**************************** + * hwrm_nvm_erase_dir_entry * + ****************************/ -/* cmdq_query_version (size:128b/16B) */ +/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ -typedef struct cmdq_query_version { - /* Command opcode. */ - uint8_t opcode; - /* Query version. */ - #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION UINT32_C(0x8b) - #define CMDQ_QUERY_VERSION_OPCODE_LAST CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ +typedef struct hwrm_nvm_erase_dir_entry_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ uint64_t resp_addr; -} cmdq_query_version_t, *pcmdq_query_version_t; + /* Directory Entry Index */ + uint16_t dir_idx; + uint8_t unused_0[6]; +} hwrm_nvm_erase_dir_entry_input_t, *phwrm_nvm_erase_dir_entry_input_t; -/* creq_query_version_resp (size:128b/16B) */ +/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ -typedef struct creq_query_version_resp { - uint8_t type; - /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. - */ - #define CREQ_QUERY_VERSION_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_QUERY_VERSION_RESP_TYPE_LAST CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* firmware major version */ - uint8_t fw_maj; - /* firmware minor version */ - uint8_t fw_minor; - /* firmware build version */ - uint8_t fw_bld; - /* firmware reserved version */ - uint8_t fw_rsvd; - uint8_t v; +typedef struct hwrm_nvm_erase_dir_entry_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define CREQ_QUERY_VERSION_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Query firmware and interface version response. */ - #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION UINT32_C(0x8b) - #define CREQ_QUERY_VERSION_RESP_EVENT_LAST CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION - uint16_t reserved16; - /* interface major version */ - uint8_t intf_maj; - /* interface minor version */ - uint8_t intf_minor; - /* interface build version */ - uint8_t intf_bld; - /* interface reserved version */ - uint8_t intf_rsvd; -} creq_query_version_resp_t, *pcreq_query_version_resp_t; + uint8_t valid; +} hwrm_nvm_erase_dir_entry_output_t, *phwrm_nvm_erase_dir_entry_output_t; -/***************** - * initialize_fw * - *****************/ +/************************* + * hwrm_nvm_get_dev_info * + *************************/ -/* cmdq_initialize_fw (size:896b/112B) */ +/* hwrm_nvm_get_dev_info_input (size:128b/16B) */ -typedef struct cmdq_initialize_fw { - /* Command opcode. */ - uint8_t opcode; +typedef struct hwrm_nvm_get_dev_info_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Initialize firmware command initializes the firmware with - * the specified parameters. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW UINT32_C(0x80) - #define CMDQ_INITIALIZE_FW_OPCODE_LAST CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; + uint16_t cmpl_ring; /* - * When set, the 32b `max_mrw_per_vf` field is logically divided - * into two 16b fields, `max_mr_per_vf` and `max_av_per_vf`. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x1) + uint16_t seq_id; /* - * When set, the hardware based requester retransmission - * feature is supported. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED UINT32_C(0x2) - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ uint64_t resp_addr; - uint8_t qpc_pg_size_qpc_lvl; - /* QPC PBL indirect levels. */ - #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK UINT32_C(0xf) - #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 - /* QPC page size. */ - #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK UINT32_C(0xf0) - #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4 - /* 4KB. */ - #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G - uint8_t mrw_pg_size_mrw_lvl; - /* MRW PBL indirect levels. */ - #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK UINT32_C(0xf) - #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 - /* MRW page size. */ - #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK UINT32_C(0xf0) - #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4 - /* 4KB. */ - #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G - uint8_t srq_pg_size_srq_lvl; - /* SRQ PBL indirect levels. */ - #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK UINT32_C(0xf) - #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 - /* SRQ page size. */ - #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK UINT32_C(0xf0) - #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G - uint8_t cq_pg_size_cq_lvl; - /* CQ PBL indirect levels. */ - #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK UINT32_C(0xf) - #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 - /* CQ page size. */ - #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK UINT32_C(0xf0) - #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G - uint8_t tqm_pg_size_tqm_lvl; - /* TQM PBL indirect levels. */ - #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK UINT32_C(0xf) - #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 - /* TQM page size. */ - #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK UINT32_C(0xf0) - #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4 - /* 4KB. */ - #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G - uint8_t tim_pg_size_tim_lvl; - /* TIM PBL indirect levels. */ - #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK UINT32_C(0xf) - #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 - /* TIM page size. */ - #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK UINT32_C(0xf0) - #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4 - /* 4KB. */ - #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G - uint16_t log2_dbr_pg_size; - /* Log base 2 of DBR page size - 12. 0 for 4KB. HW supported values are enumerated below. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK UINT32_C(0xf) - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0 - /* 4KB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K UINT32_C(0x0) - /* 8KB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K UINT32_C(0x1) - /* 16KB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K UINT32_C(0x2) - /* 32KB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K UINT32_C(0x3) - /* 64KB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K UINT32_C(0x4) - /* 128KB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K UINT32_C(0x5) - /* 256KB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K UINT32_C(0x6) - /* 512KB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K UINT32_C(0x7) - /* 1MB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M UINT32_C(0x8) - /* 2MB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M UINT32_C(0x9) - /* 4MB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M UINT32_C(0xa) - /* 8MB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M UINT32_C(0xb) - /* 16MB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M UINT32_C(0xc) - /* 32MB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M UINT32_C(0xd) - /* 64MB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M UINT32_C(0xe) - /* 128MB. */ - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M UINT32_C(0xf) - #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M - /* rsvd is 12 b */ - #define CMDQ_INITIALIZE_FW_RSVD_MASK UINT32_C(0xfff0) - #define CMDQ_INITIALIZE_FW_RSVD_SFT 4 - /* Kernel notification queue page directory. */ - uint64_t qpc_page_dir; - /* MRW page directory. */ - uint64_t mrw_page_dir; - /* SRQ page directory. */ - uint64_t srq_page_dir; - /* CQ page directory. */ - uint64_t cq_page_dir; - /* TQM page directory. */ - uint64_t tqm_page_dir; - /* TIM page directory. */ - uint64_t tim_page_dir; - /* Number of QPs. */ - uint32_t number_of_qp; - /* Number of MRWs. */ - uint32_t number_of_mrw; - /* Number of SRQs. */ - uint32_t number_of_srq; - /* Number of CQs. */ - uint32_t number_of_cq; - /* Number of QPs per VF. */ - uint32_t max_qp_per_vf; - /* - * If the MR/AV split reservation flag is not set, then this field - * represents the total number of MR plus AV entries allowed per - * VF. For versions of firmware that support the split reservation, - * when it is not specified half of the entries will be reserved - * for MRs and the other half for AVs. - * - * If the MR/AV split reservation flag is set, then this - * field is logically divided into two 16b fields. Bits `[31:16]` - * represents the `max_mr_per_vf` and bits `[15:0]` represents - * `max_av_per_vf`. The granularity of these values is defined by - * the `mrav_num_entries_unit` field returned by the - * `backing_store_qcaps` command. - */ - uint32_t max_mrw_per_vf; - /* Number of SRQs per VF. */ - uint32_t max_srq_per_vf; - /* Number of CQs per VF. */ - uint32_t max_cq_per_vf; - /* Number of GIDs per VF. */ - uint32_t max_gid_per_vf; - /* Statistics context index for this function. */ - uint32_t stat_ctx_id; -} cmdq_initialize_fw_t, *pcmdq_initialize_fw_t; +} hwrm_nvm_get_dev_info_input_t, *phwrm_nvm_get_dev_info_input_t; -/* creq_initialize_fw_resp (size:128b/16B) */ +/* hwrm_nvm_get_dev_info_output (size:704b/88B) */ -typedef struct creq_initialize_fw_resp { - uint8_t type; +typedef struct hwrm_nvm_get_dev_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Manufacturer ID. */ + uint16_t manufacturer_id; + /* Device ID. */ + uint16_t device_id; + /* Sector size of the NVRAM device. */ + uint32_t sector_size; + /* Total size, in bytes of the NVRAM device. */ + uint32_t nvram_size; + uint32_t reserved_size; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Available size that can be used, in bytes. Available size is the + * NVRAM size take away the used size and reserved size. */ - #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_INITIALIZE_FW_RESP_TYPE_LAST CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - uint32_t reserved32; - uint8_t v; + uint32_t available_size; + /* This field represents the major version of NVM cfg */ + uint8_t nvm_cfg_ver_maj; + /* This field represents the minor version of NVM cfg */ + uint8_t nvm_cfg_ver_min; + /* This field represents the update version of NVM cfg */ + uint8_t nvm_cfg_ver_upd; + uint8_t flags; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * If set to 1, firmware will provide various firmware version + * information stored in the flash. */ - #define CREQ_INITIALIZE_FW_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Initialize firmware command response. */ - #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW UINT32_C(0x80) - #define CREQ_INITIALIZE_FW_RESP_EVENT_LAST CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW - uint8_t reserved48[6]; -} creq_initialize_fw_resp_t, *pcreq_initialize_fw_resp_t; - -/******************* - * deinitialize_fw * - *******************/ - - -/* cmdq_deinitialize_fw (size:128b/16B) */ - -typedef struct cmdq_deinitialize_fw { - /* Command opcode. */ - uint8_t opcode; - /* De-initialize firmware command deinitializes the firmware. */ - #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW UINT32_C(0x81) - #define CMDQ_DEINITIALIZE_FW_OPCODE_LAST CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; -} cmdq_deinitialize_fw_t, *pcmdq_deinitialize_fw_t; - -/* creq_deinitialize_fw_resp (size:128b/16B) */ - -typedef struct creq_deinitialize_fw_resp { - uint8_t type; + #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID UINT32_C(0x1) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This field represents the board package name stored in the flash. + * (ASCII chars with NULL at the end). */ - #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - uint32_t reserved32; - uint8_t v; + char pkg_name[16]; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This field represents the major version of HWRM firmware, stored in + * the flash. */ - #define CREQ_DEINITIALIZE_FW_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* De-initialize firmware command response. */ - #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW UINT32_C(0x81) - #define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW - uint8_t reserved48[6]; -} creq_deinitialize_fw_resp_t, *pcreq_deinitialize_fw_resp_t; - -/************* - * create_qp * - *************/ - - -/* cmdq_create_qp (size:768b/96B) */ - -typedef struct cmdq_create_qp { - /* Command opcode. */ - uint8_t opcode; + uint16_t hwrm_fw_major; /* - * Create QP command allocates QP context with the specified - * SQ, RQ/SRQ, CQ and other parameters. + * This field represents the minor version of HWRM firmware, stored in + * the flash. */ - #define CMDQ_CREATE_QP_OPCODE_CREATE_QP UINT32_C(0x1) - #define CMDQ_CREATE_QP_OPCODE_LAST CMDQ_CREATE_QP_OPCODE_CREATE_QP - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* QP handle. */ - uint64_t qp_handle; - /* Create QP flags. */ - uint32_t qp_flags; - /* SRQ is used. */ - #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED UINT32_C(0x1) - /* post CQE for all SQ WQEs. */ - #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2) - /* This QP can use reserved L_Key */ - #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4) - /* This QP can fast register physical memory */ - #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED UINT32_C(0x8) - /* This QP can send variable sized WQEs. */ - #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED UINT32_C(0x10) + uint16_t hwrm_fw_minor; /* - * WQEs with inline data sent on this QP are able to flow - * through an optimized transmit path to lower latency. This - * transmit path is opportunistic and not guaranteed to always - * occur. + * This field represents the build version of HWRM firmware, stored in + * the flash. */ - #define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x20) + uint16_t hwrm_fw_build; /* - * For UD QPs the default responder CQE format is `cq_res_ud`. - * This flag specifies the `cq_res_ud_cfa` format to be used - * instead. + * This field can be used to represent firmware branches or customer + * specific releases tied to a specific (major, minor, build) version + * of the HWRM firmware. */ - #define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA UINT32_C(0x40) + uint16_t hwrm_fw_patch; /* - * This QP must be included in the extended RoCE statistics - * that can be queried via `query_roce_stats_ext`. + * This field represents the major version of mgmt firmware, stored in + * the flash. */ - #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED UINT32_C(0x80) - #define CMDQ_CREATE_QP_QP_FLAGS_LAST CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED - /* Supported QP types. */ - uint8_t type; - /* Reliable Connection. */ - #define CMDQ_CREATE_QP_TYPE_RC UINT32_C(0x2) - /* Unreliable Datagram. */ - #define CMDQ_CREATE_QP_TYPE_UD UINT32_C(0x4) - /* Raw Ethertype. */ - #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6) - /* General Services Interface on QP1 over UD. */ - #define CMDQ_CREATE_QP_TYPE_GSI UINT32_C(0x7) - #define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI - uint8_t sq_pg_size_sq_lvl; - /* SQ PBL indirect levels. */ - #define CMDQ_CREATE_QP_SQ_LVL_MASK UINT32_C(0xf) - #define CMDQ_CREATE_QP_SQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2 - /* SQ page size. */ - #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK UINT32_C(0xf0) - #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G - uint8_t rq_pg_size_rq_lvl; - /* RQ PBL indirect levels. */ - #define CMDQ_CREATE_QP_RQ_LVL_MASK UINT32_C(0xf) - #define CMDQ_CREATE_QP_RQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2 - /* RQ page size. */ - #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK UINT32_C(0xf0) - #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4 - /* 4KB. */ - #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) - /* 8KB. */ - #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) - /* 64KB. */ - #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) - /* 2MB. */ - #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) - /* 8MB. */ - #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) - /* 1GB. */ - #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G - uint8_t unused_0; - /* Doorbell page index. */ - uint32_t dpi; - /* Max number of SQ wqes. */ - uint32_t sq_size; - /* Max number of RQ wqes. */ - uint32_t rq_size; - uint16_t sq_fwo_sq_sge; - /* Max send SGEs per SWQE. */ - #define CMDQ_CREATE_QP_SQ_SGE_MASK UINT32_C(0xf) - #define CMDQ_CREATE_QP_SQ_SGE_SFT 0 - /* Offset of First WQE in the first SQ page, in 128 byte units */ - #define CMDQ_CREATE_QP_SQ_FWO_MASK UINT32_C(0xfff0) - #define CMDQ_CREATE_QP_SQ_FWO_SFT 4 - uint16_t rq_fwo_rq_sge; + uint16_t mgmt_fw_major; /* - * Max recv SGEs per RWQE. - * On chips with variable-size WQE support, a value of zero implies 30 SGEs. + * This field represents the minor version of mgmt firmware, stored in + * the flash. */ - #define CMDQ_CREATE_QP_RQ_SGE_MASK UINT32_C(0xf) - #define CMDQ_CREATE_QP_RQ_SGE_SFT 0 - /* Offset of First WQE in the first RQ page, in 128 byte units */ - #define CMDQ_CREATE_QP_RQ_FWO_MASK UINT32_C(0xfff0) - #define CMDQ_CREATE_QP_RQ_FWO_SFT 4 - /* Send CQ context id. */ - uint32_t scq_cid; - /* Receive CQ context id. */ - uint32_t rcq_cid; - /* SRQ context id. */ - uint32_t srq_cid; - /* Protection domain id. */ - uint32_t pd_id; - /* SQ PBL physical address. */ - uint64_t sq_pbl; - /* RQ PBL physical address. */ - uint64_t rq_pbl; - /* IRRQ address. */ - uint64_t irrq_addr; - /* ORRQ address. */ - uint64_t orrq_addr; -} cmdq_create_qp_t, *pcmdq_create_qp_t; - -/* creq_create_qp_resp (size:128b/16B) */ - -typedef struct creq_create_qp_resp { - uint8_t type; + uint16_t mgmt_fw_minor; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This field represents the build version of mgmt firmware, stored in + * the flash. */ - #define CREQ_CREATE_QP_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_CREATE_QP_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_CREATE_QP_RESP_TYPE_LAST CREQ_CREATE_QP_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* QP context id */ - uint32_t xid; - uint8_t v; + uint16_t mgmt_fw_build; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This field can be used to represent firmware branches or customer + * specific releases tied to a specific (major, minor, build) version + * of the mgmt firmware. */ - #define CREQ_CREATE_QP_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Create QP command response. */ - #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP UINT32_C(0x1) - #define CREQ_CREATE_QP_RESP_EVENT_LAST CREQ_CREATE_QP_RESP_EVENT_CREATE_QP + uint16_t mgmt_fw_patch; /* - * Support for optimized transmit path to lower latency - * for WQEs with inline data has been enabled for this QP. + * This field represents the major version of roce firmware, stored in + * the flash. */ - uint8_t optimized_transmit_enabled; - uint8_t reserved48[5]; -} creq_create_qp_resp_t, *pcreq_create_qp_resp_t; - -/************** - * destroy_qp * - **************/ - - -/* cmdq_destroy_qp (size:192b/24B) */ - -typedef struct cmdq_destroy_qp { - /* Command opcode. */ - uint8_t opcode; + uint16_t roce_fw_major; /* - * Destroy QP command deletes the QP context and ceases - * any further reference. + * This field represents the minor version of roce firmware, stored in + * the flash. */ - #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP UINT32_C(0x2) - #define CMDQ_DESTROY_QP_OPCODE_LAST CMDQ_DESTROY_QP_OPCODE_DESTROY_QP - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* QP context id */ - uint32_t qp_cid; - uint32_t unused_0; -} cmdq_destroy_qp_t, *pcmdq_destroy_qp_t; - -/* creq_destroy_qp_resp (size:128b/16B) */ - -typedef struct creq_destroy_qp_resp { - uint8_t type; + uint16_t roce_fw_minor; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This field represents the build version of roce firmware, stored in + * the flash. */ - #define CREQ_DESTROY_QP_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_DESTROY_QP_RESP_TYPE_LAST CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* QP context id */ - uint32_t xid; - uint8_t v; + uint16_t roce_fw_build; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This field can be used to represent firmware branches or customer + * specific releases tied to a specific (major, minor, build) version + * of the roce firmware. */ - #define CREQ_DESTROY_QP_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Destroy QP command response. */ - #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP UINT32_C(0x2) - #define CREQ_DESTROY_QP_RESP_EVENT_LAST CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP - uint8_t reserved48[6]; -} creq_destroy_qp_resp_t, *pcreq_destroy_qp_resp_t; + uint16_t roce_fw_patch; + /* + * This field represents the major version of network control firmware, + * stored in the flash. + */ + uint16_t netctrl_fw_major; + /* + * This field represents the minor version of network control firmware, + * stored in the flash. + */ + uint16_t netctrl_fw_minor; + /* + * This field represents the build version of network control firmware, + * stored in the flash. + */ + uint16_t netctrl_fw_build; + /* + * This field can be used to represent firmware branches or customer + * specific releases tied to a specific (major, minor, build) version + * of the network control firmware. + */ + uint16_t netctrl_fw_patch; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_get_dev_info_output_t, *phwrm_nvm_get_dev_info_output_t; -/************* - * modify_qp * - *************/ +/************************** + * hwrm_nvm_mod_dir_entry * + **************************/ -/* cmdq_modify_qp (size:1024b/128B) */ +/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ -typedef struct cmdq_modify_qp { - /* Command opcode. */ - uint8_t opcode; +typedef struct hwrm_nvm_mod_dir_entry_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Modify QP command changes QP states and other QP specific - * parameters. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP UINT32_C(0x3) - #define CMDQ_MODIFY_QP_OPCODE_LAST CMDQ_MODIFY_QP_OPCODE_MODIFY_QP - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* Modify mask signifies the field that is requesting the change. */ - uint32_t modify_mask; - /* QP state change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE UINT32_C(0x1) - /* Enable SQ drain asynchronous notification change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY UINT32_C(0x2) - /* Access change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS UINT32_C(0x4) - /* P_KEY change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY UINT32_C(0x8) - /* Q_KEY index change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY UINT32_C(0x10) - /* Destination GID change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID UINT32_C(0x20) - /* Flow label change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL UINT32_C(0x40) - /* SGID change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX UINT32_C(0x80) - /* Hop limit change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT UINT32_C(0x100) - /* Traffic class change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS UINT32_C(0x200) - /* destination MAC change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC UINT32_C(0x400) - /* Ping pong push mode change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE UINT32_C(0x800) - /* Path MTU change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU UINT32_C(0x1000) - /* Timeout change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT UINT32_C(0x2000) - /* Retry count change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT UINT32_C(0x4000) - /* RNR Retry change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY UINT32_C(0x8000) - /* RQ start packet sequence number change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN UINT32_C(0x10000) - /* Max outstanding RDMA read atomic change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC UINT32_C(0x20000) - /* RNR minimum timer change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER UINT32_C(0x40000) - /* SQ start packet sequence number change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN UINT32_C(0x80000) - /* Max destination outstanding RDMA read atomic change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC UINT32_C(0x100000) - /* Max send WQE change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE UINT32_C(0x200000) - /* Max recv WQE change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE UINT32_C(0x400000) - /* Max recv SGEs per SWQE change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE UINT32_C(0x800000) - /* Max send SGEs per RWQE change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE UINT32_C(0x1000000) - /* Max inline data length change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA UINT32_C(0x2000000) - /* Destination QP id change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID UINT32_C(0x4000000) - /* Source MAC change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC UINT32_C(0x8000000) - /* Source VLAN id change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID UINT32_C(0x10000000) - /* Congestion control RoCE v2 change. */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC UINT32_C(0x20000000) - /* IP TOS ECN change */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN UINT32_C(0x40000000) - /* IP TOS DSCP change */ - #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP UINT32_C(0x80000000) - /* QP context id */ - uint32_t qp_cid; - uint8_t network_type_en_sqd_async_notify_new_state; - /* New QP state. */ - #define CMDQ_MODIFY_QP_NEW_STATE_MASK UINT32_C(0xf) - #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0 - /* Reset. */ - #define CMDQ_MODIFY_QP_NEW_STATE_RESET UINT32_C(0x0) - /* Init. */ - #define CMDQ_MODIFY_QP_NEW_STATE_INIT UINT32_C(0x1) - /* Ready To Receive. */ - #define CMDQ_MODIFY_QP_NEW_STATE_RTR UINT32_C(0x2) - /* Ready To Send. */ - #define CMDQ_MODIFY_QP_NEW_STATE_RTS UINT32_C(0x3) - /* SQ Drain. */ - #define CMDQ_MODIFY_QP_NEW_STATE_SQD UINT32_C(0x4) - /* SQ Error. */ - #define CMDQ_MODIFY_QP_NEW_STATE_SQE UINT32_C(0x5) - /* Error. */ - #define CMDQ_MODIFY_QP_NEW_STATE_ERR UINT32_C(0x6) - #define CMDQ_MODIFY_QP_NEW_STATE_LAST CMDQ_MODIFY_QP_NEW_STATE_ERR - /* Enable SQ drain asynchronous notification. */ - #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10) - /* unused1 is 1 b */ - #define CMDQ_MODIFY_QP_UNUSED1 UINT32_C(0x20) - /* network type. */ - #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK UINT32_C(0xc0) - #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6 - /* RoCEv1. */ - #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (UINT32_C(0x0) << 6) - /* RoCEv2 IPv4. */ - #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (UINT32_C(0x2) << 6) - /* RoCEv2 IPv6. */ - #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (UINT32_C(0x3) << 6) - #define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 - /* Access flags. */ - uint8_t access; - #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK UINT32_C(0xff) - #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0 - /* Local write access. */ - #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE UINT32_C(0x1) - /* Remote write access. */ - #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE UINT32_C(0x2) - /* Remote read access. */ - #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ UINT32_C(0x4) - /* Remote atomic access. */ - #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC UINT32_C(0x8) - /* P_KEY. */ - uint16_t pkey; - /* Q_KEY. */ - uint32_t qkey; - /* Destination GID. */ - uint32_t dgid[4]; - /* Flow label. */ - uint32_t flow_label; - /* Source GID index. */ - uint16_t sgid_index; - /* Hop limit. */ - uint8_t hop_limit; - /* Traffic class. */ - uint8_t traffic_class; - /* Destination MAC address. */ - uint16_t dest_mac[3]; - uint8_t tos_dscp_tos_ecn; - /* IP TOS ECN. Valid values are 1 or 2 when ECN is enabled. */ - #define CMDQ_MODIFY_QP_TOS_ECN_MASK UINT32_C(0x3) - #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0 - /* IP TOS DSCP. */ - #define CMDQ_MODIFY_QP_TOS_DSCP_MASK UINT32_C(0xfc) - #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2 - uint8_t path_mtu_pingpong_push_enable; + uint16_t cmpl_ring; /* - * Driver requests for ping pong push mode to be enabled for this - * QP. This request can be done only during modify from RST to INIT - * state. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE UINT32_C(0x1) - /* unused3 is 3 b */ - #define CMDQ_MODIFY_QP_UNUSED3_MASK UINT32_C(0xe) - #define CMDQ_MODIFY_QP_UNUSED3_SFT 1 - /* Path MTU. */ - #define CMDQ_MODIFY_QP_PATH_MTU_MASK UINT32_C(0xf0) - #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4 - /* 256. */ - #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (UINT32_C(0x0) << 4) - /* 512. */ - #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (UINT32_C(0x1) << 4) - /* 1024. */ - #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 4) - /* 2048. */ - #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 4) - /* 4096. */ - #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 4) - /* 8192. */ - #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 4) - #define CMDQ_MODIFY_QP_PATH_MTU_LAST CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 - /* Timeout value for SWQEs. */ - uint8_t timeout; - /* Max retry count for WQEs. */ - uint8_t retry_cnt; - /* Max RNR retry count for WQEs. */ - uint8_t rnr_retry; - /* Min RNR timer that the QP will report to the remote. */ - uint8_t min_rnr_timer; - /* RQ start packet sequence number. */ - uint32_t rq_psn; - /* SQ start packet sequence number. */ - uint32_t sq_psn; - /* Max outstanding RDMA read atomic. */ - uint8_t max_rd_atomic; - /* Max destination outstanding RDMA read atomic. */ - uint8_t max_dest_rd_atomic; - uint16_t enable_cc; - /* Enable congestion control. */ - #define CMDQ_MODIFY_QP_ENABLE_CC UINT32_C(0x1) - /* unused15 is 15 b */ - #define CMDQ_MODIFY_QP_UNUSED15_MASK UINT32_C(0xfffe) - #define CMDQ_MODIFY_QP_UNUSED15_SFT 1 - /* Max send WQE. */ - uint32_t sq_size; - /* Max recv WQE. */ - uint32_t rq_size; - /* Max send SGEs per SWQE. */ - uint16_t sq_sge; - /* Max recv SGEs per RWQE. */ - uint16_t rq_sge; - /* Max inline data length (upto 120 bytes). */ - uint32_t max_inline_data; - /* Destination QP id. */ - uint32_t dest_qp_id; - /* This is the DPI RoCE driver allocated for ping pong push. */ - uint32_t pingpong_push_dpi; - /* Source MAC. (Unused. Comes from Source GID index) */ - uint16_t src_mac[3]; - uint16_t vlan_pcp_vlan_dei_vlan_id; - /* VLAN id. (Unused. Comes from Source GID index) */ - #define CMDQ_MODIFY_QP_VLAN_ID_MASK UINT32_C(0xfff) - #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0 - /* VLAN DEI field - Drop Eligibility Indicator. */ - #define CMDQ_MODIFY_QP_VLAN_DEI UINT32_C(0x1000) - /* VLAN PCP field - Priority Code Point. */ - #define CMDQ_MODIFY_QP_VLAN_PCP_MASK UINT32_C(0xe000) - #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13 - /* IRRQ address. */ - uint64_t irrq_addr; - /* ORRQ address. */ - uint64_t orrq_addr; -} cmdq_modify_qp_t, *pcmdq_modify_qp_t; - -/* creq_modify_qp_resp (size:128b/16B) */ - -typedef struct creq_modify_qp_resp { - uint8_t type; + uint16_t seq_id; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define CREQ_MODIFY_QP_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_MODIFY_QP_RESP_TYPE_LAST CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* QP context id */ - uint32_t xid; - uint8_t v; + uint16_t target_id; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define CREQ_MODIFY_QP_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Modify QP command response. */ - #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP UINT32_C(0x3) - #define CREQ_MODIFY_QP_RESP_EVENT_LAST CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP - uint8_t pingpong_push_state_index_enabled; + uint64_t resp_addr; + uint32_t enables; /* - * When set it indicates that FW was able to successfully enable - * ping pong push mode for this QP. + * This bit must be '1' for the checksum field to be + * configured. */ - #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED UINT32_C(0x1) + #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1) + /* Directory Entry Index */ + uint16_t dir_idx; /* - * When ping pong push mode is enabled this field will give the - * index into the push page where the QP has been mapped. + * Directory ordinal. + * The (0-based) instance of this Directory Type. */ - #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK UINT32_C(0xe) - #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1 + uint16_t dir_ordinal; /* - * This bit will tell whether to use ping or pong buffer - * for first push operation. 0 - ping buffer, 1 - pong buffer. + * The Directory Entry Extension flags (see BNX_DIR_EXT_* for + * extension flag definitions). */ - #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE UINT32_C(0x10) - uint8_t reserved8; - /* Scrambled src mac needed to calculate UDP source port. */ - uint32_t lag_src_mac; -} creq_modify_qp_resp_t, *pcreq_modify_qp_resp_t; + uint16_t dir_ext; + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute + * flag definitions). + */ + uint16_t dir_attr; + /* + * If valid, then this field updates the checksum + * value of the content in the directory entry. + */ + uint32_t checksum; +} hwrm_nvm_mod_dir_entry_input_t, *phwrm_nvm_mod_dir_entry_input_t; -/************ - * query_qp * - ************/ +/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ +typedef struct hwrm_nvm_mod_dir_entry_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_mod_dir_entry_output_t, *phwrm_nvm_mod_dir_entry_output_t; -/* cmdq_query_qp (size:192b/24B) */ +/************************** + * hwrm_nvm_verify_update * + **************************/ -typedef struct cmdq_query_qp { - /* Command opcode. */ - uint8_t opcode; - /* Query QP command retrieves info about the specified QP. */ - #define CMDQ_QUERY_QP_OPCODE_QUERY_QP UINT32_C(0x4) - #define CMDQ_QUERY_QP_OPCODE_LAST CMDQ_QUERY_QP_OPCODE_QUERY_QP - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* QP context id */ - uint32_t qp_cid; - uint32_t unused_0; -} cmdq_query_qp_t, *pcmdq_query_qp_t; -/* creq_query_qp_resp (size:128b/16B) */ +/* hwrm_nvm_verify_update_input (size:192b/24B) */ -typedef struct creq_query_qp_resp { - uint8_t type; +typedef struct hwrm_nvm_verify_update_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define CREQ_QUERY_QP_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_QUERY_QP_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_QUERY_QP_RESP_TYPE_LAST CREQ_QUERY_QP_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Side buffer size in 16-byte units */ - uint32_t size; - uint8_t v; + uint16_t cmpl_ring; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define CREQ_QUERY_QP_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Query QP command response. */ - #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP UINT32_C(0x4) - #define CREQ_QUERY_QP_RESP_EVENT_LAST CREQ_QUERY_QP_RESP_EVENT_QUERY_QP - uint8_t reserved48[6]; -} creq_query_qp_resp_t, *pcreq_query_qp_resp_t; - -/* Query QP command response side buffer structure. */ -/* creq_query_qp_resp_sb (size:832b/104B) */ - -typedef struct creq_query_qp_resp_sb { - /* Command opcode. */ - uint8_t opcode; - /* Query QP command response. */ - #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP UINT32_C(0x4) - #define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* QP context id */ - uint32_t xid; - uint8_t en_sqd_async_notify_state; - /* QP state */ - #define CREQ_QUERY_QP_RESP_SB_STATE_MASK UINT32_C(0xf) - #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0 - /* Reset. */ - #define CREQ_QUERY_QP_RESP_SB_STATE_RESET UINT32_C(0x0) - /* Init. */ - #define CREQ_QUERY_QP_RESP_SB_STATE_INIT UINT32_C(0x1) - /* Ready To Receive. */ - #define CREQ_QUERY_QP_RESP_SB_STATE_RTR UINT32_C(0x2) - /* Ready To Send. */ - #define CREQ_QUERY_QP_RESP_SB_STATE_RTS UINT32_C(0x3) - /* SQ Drain. */ - #define CREQ_QUERY_QP_RESP_SB_STATE_SQD UINT32_C(0x4) - /* SQ Error. */ - #define CREQ_QUERY_QP_RESP_SB_STATE_SQE UINT32_C(0x5) - /* Error. */ - #define CREQ_QUERY_QP_RESP_SB_STATE_ERR UINT32_C(0x6) - #define CREQ_QUERY_QP_RESP_SB_STATE_LAST CREQ_QUERY_QP_RESP_SB_STATE_ERR - /* SQ drain asynchronous notification. */ - #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10) - /* Enable congestion control. */ - #define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK UINT32_C(0xe0) - #define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT 5 - /* Access flags. */ - uint8_t access; - #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK UINT32_C(0xff) - #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0 - /* Local write access. */ - #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE UINT32_C(0x1) - /* Remote write access. */ - #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE UINT32_C(0x2) - /* Remote read access. */ - #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ UINT32_C(0x4) - /* Remote atomic access. */ - #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC UINT32_C(0x8) - /* P_KEY index. */ - uint16_t pkey; - /* Q_KEY. */ - uint32_t qkey; - uint32_t reserved32; - /* Destination GID. */ - uint32_t dgid[4]; - /* Flow label. */ - uint32_t flow_label; - /* Source GID index. */ - uint16_t sgid_index; - /* Hop limit. */ - uint8_t hop_limit; - /* Traffic class. */ - uint8_t traffic_class; - /* Destination MAC address. */ - uint16_t dest_mac[3]; - uint16_t path_mtu_dest_vlan_id; - /* Destination VLAN ID. */ - #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK UINT32_C(0xfff) - #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0 - /* Path MTU. */ - #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK UINT32_C(0xf000) - #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12 - /* 256. */ - #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (UINT32_C(0x0) << 12) - /* 512. */ - #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (UINT32_C(0x1) << 12) - /* 1024. */ - #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 12) - /* 2048. */ - #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 12) - /* 4096. */ - #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 12) - /* 8192. */ - #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 12) - #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 - /* Timeout value for SWQEs. */ - uint8_t timeout; - /* Max retry count for WQEs. */ - uint8_t retry_cnt; - /* Max RNR retry count for WQEs. */ - uint8_t rnr_retry; - /* Min RNR timer that the QP will report to the remote. */ - uint8_t min_rnr_timer; - /* RQ start packet sequence number. */ - uint32_t rq_psn; - /* SQ start packet sequence number. */ - uint32_t sq_psn; - /* Max outstanding RDMA read atomic. */ - uint8_t max_rd_atomic; - /* Max destination outstanding RDMA read atomic. */ - uint8_t max_dest_rd_atomic; - uint8_t tos_dscp_tos_ecn; - /* IP TOS ECN. */ - #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK UINT32_C(0x3) - #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0 - /* IP TOS DSCP. */ - #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc) - #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2 - uint8_t enable_cc; - /* enable_cc is 1 b */ - #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC UINT32_C(0x1) - /* Max send WQE. */ - uint32_t sq_size; - /* Max recv WQE. */ - uint32_t rq_size; - /* Max send SGEs per SWQE. */ - uint16_t sq_sge; - /* Max recv SGEs per RWQE (NOT SUPPORTED BY HARDWARE). */ - uint16_t rq_sge; - /* Max inline data length (upto 120 bytes). */ - uint32_t max_inline_data; - /* Destination QP id. */ - uint32_t dest_qp_id; - /* Port ID associated with the QP. */ - uint16_t port_id; - uint8_t unused_0; - /* Statistic collection ID allocated for this QP. */ - uint8_t stat_collection_id; - /* Source MAC. */ - uint16_t src_mac[3]; - uint16_t vlan_pcp_vlan_dei_vlan_id; - /* Source VLAN id. */ - #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK UINT32_C(0xfff) - #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0 - /* VLAN DEI field - Drop Eligibility Indicator. */ - #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI UINT32_C(0x1000) - /* VLAN PCP field - Priority Code Point. */ - #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK UINT32_C(0xe000) - #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13 -} creq_query_qp_resp_sb_t, *pcreq_query_qp_resp_sb_t; - -/******************* - * query_qp_extend * - *******************/ - - -/* cmdq_query_qp_extend (size:192b/24B) */ - -typedef struct cmdq_query_qp_extend { - /* Command opcode. */ - uint8_t opcode; + uint16_t seq_id; /* - * Query QP extend command retrieves info about multiple QPs associated - * with a specific PF. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) - #define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - /* Number of QPs for which FW needs to query and provide info back to host. */ - uint8_t num_qps; - /* Host address of the response. */ - uint64_t resp_addr; - /* Unique identified for a function */ - uint32_t function_id; - /* PF number */ - #define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK UINT32_C(0xff) - #define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0 - /* VF number */ - #define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK UINT32_C(0xffff00) - #define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT 8 - /* When set the vf_num is valid. */ - #define CMDQ_QUERY_QP_EXTEND_VF_VALID UINT32_C(0x1000000) + uint16_t target_id; /* - * This is the current index where firmware left off for query qp. Driver - * will pass this back in the next query_qp_extend command. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t current_index; -} cmdq_query_qp_extend_t, *pcmdq_query_qp_extend_t; - -/* creq_query_qp_extend_resp (size:128b/16B) */ - -typedef struct creq_query_qp_extend_resp { - uint8_t type; + uint64_t resp_addr; + /* Directory Entry Type, to be verified. */ + uint16_t dir_type; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Directory ordinal. + * The instance of the Directory Type to be verified. */ - #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Side buffer size in 16-byte units */ - uint32_t size; - uint8_t v; + uint16_t dir_ordinal; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * The Directory Entry Extension flags. + * The "UPDATE" extension flag must be set in this value. + * A corresponding directory entry with the same type and ordinal + * values but *without* + * the "UPDATE" extension flag must also exist. The other flags of + * the extension must + * be identical between the active and update entries. */ - #define CREQ_QUERY_QP_EXTEND_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Query QP extend command response. */ - #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND UINT32_C(0x91) - #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND - uint16_t reserved16; + uint16_t dir_ext; + uint8_t unused_0[2]; +} hwrm_nvm_verify_update_input_t, *phwrm_nvm_verify_update_input_t; + +/* hwrm_nvm_verify_update_output (size:128b/16B) */ + +typedef struct hwrm_nvm_verify_update_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This is the current index where firmware left off for query qp. Driver - * will pass this back in the next query_qp_extend command. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint32_t current_index; -} creq_query_qp_extend_resp_t, *pcreq_query_qp_extend_resp_t; + uint8_t valid; +} hwrm_nvm_verify_update_output_t, *phwrm_nvm_verify_update_output_t; -/* Query QP extend command response side buffer structure. */ -/* creq_query_qp_extend_resp_sb (size:384b/48B) */ +/*************************** + * hwrm_nvm_install_update * + ***************************/ -typedef struct creq_query_qp_extend_resp_sb { - /* Command opcode. */ - uint8_t opcode; - /* Query QP command extend response. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) - #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* QP context id */ - uint32_t xid; - uint8_t state; - /* QP state */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK UINT32_C(0xf) - #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0 - /* Reset. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET UINT32_C(0x0) - /* Init. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT UINT32_C(0x1) - /* Ready To Receive. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR UINT32_C(0x2) - /* Ready To Send. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS UINT32_C(0x3) - /* SQ Drain. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD UINT32_C(0x4) - /* SQ Error. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE UINT32_C(0x5) - /* Error. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR UINT32_C(0x6) - #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR - /* */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK UINT32_C(0xf0) - #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4 - uint8_t reserved_8; - /* Port ID associated with the QP. */ - uint16_t port_id; - /* Q_KEY. */ - uint32_t qkey; - /* Source GID index. */ - uint16_t sgid_index; - /* Network type. */ - uint8_t network_type; - /* RoCEv1. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 UINT32_C(0x0) - /* RoCEv2 IPv4. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 UINT32_C(0x2) - /* RoCEv2 IPv6. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 UINT32_C(0x3) - #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 - uint8_t unused_0; - /* Destination GID. */ - uint32_t dgid[4]; - /* Destination QP id. */ - uint32_t dest_qp_id; - /* Statistic collection ID allocated for this QP. */ - uint8_t stat_collection_id; - uint8_t reservred_8; - uint16_t reserved_16; -} creq_query_qp_extend_resp_sb_t, *pcreq_query_qp_extend_resp_sb_t; -/* - * TLV encapsulated Query QP extend control command response - * side buffer. - */ -/* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */ +/* hwrm_nvm_install_update_input (size:192b/24B) */ -typedef struct creq_query_qp_extend_resp_sb_tlv { +typedef struct hwrm_nvm_install_update_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The command discriminator is used to differentiate between various - * types of HWRM messages. This includes legacy HWRM and RoCE slowpath - * command messages as well as newer TLV encapsulated HWRM commands. - * - * For TLV encapsulated messages this field must be 0x8000. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t cmd_discr; - uint8_t reserved_8b; - uint8_t tlv_flags; + uint16_t cmpl_ring; /* - * Indicates the presence of additional TLV encapsulated data - * follows this TLV. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1) - /* Last TLV in a sequence of TLVs. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) - /* More TLVs follow this TLV. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + uint16_t seq_id; /* - * When an HWRM receiver detects a TLV type that it does not - * support with the TLV required flag set, the receiver must - * reject the HWRM message with an error code indicating an - * unsupported TLV type. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) - /* No */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) - /* Yes */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES + uint16_t target_id; /* - * This field defines the TLV type value which is divided into - * two ranges to differentiate between global and local TLV types. - * Global TLV types must be unique across all defined TLV types. - * Local TLV types are valid only for extensions to a given - * HWRM message and may be repeated across different HWRM message - * types. There is a direct correlation of each HWRM message type - * to a single global TLV type value. - * - * Global TLV range: `0 - (63k-1)` - * - * Local TLV range: `63k - (64k-1)` + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t tlv_type; + uint64_t resp_addr; /* - * Length of the message data encapsulated by this TLV in bytes. - * This length does not include the size of the TLV header itself - * and it must be an integer multiple of 8B. + * Installation type. If the value 3 through 0xffff is used, + * only packaged items with that type value will be installed and + * conditional installation directives for those packaged items + * will be over-ridden (i.e. 'create' or 'replace' will be treated + * as 'install'). */ - uint16_t length; + uint32_t install_type; /* - * Size of the tlv encapsulated response, - * including all tlvs and extension data in 16-byte units. + * Perform a normal package installation. Conditional installation + * directives (e.g. 'create' and 'replace') of packaged items + * will be followed. */ - uint8_t total_size; - uint8_t reserved56[7]; - /* Command opcode. */ - uint8_t opcode; - /* Query QP command extend response. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Flags and attribs of the command. */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0) + /* + * Install all packaged items regardless of installation directive + * (i.e. treat all packaged items as though they have an installation + * directive of 'install'). + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL UINT32_C(0xffffffff) + #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL uint16_t flags; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* QP context id */ - uint32_t xid; - uint8_t state; - /* QP state */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK UINT32_C(0xf) - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0 - /* Reset. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET UINT32_C(0x0) - /* Init. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT UINT32_C(0x1) - /* Ready To Receive. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR UINT32_C(0x2) - /* Ready To Send. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS UINT32_C(0x3) - /* SQ Drain. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD UINT32_C(0x4) - /* SQ Error. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE UINT32_C(0x5) - /* Error. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR UINT32_C(0x6) - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR - /* */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK UINT32_C(0xf0) - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4 - uint8_t reserved_8; - /* Port ID associated with the QP. */ - uint16_t port_id; - /* Q_KEY. */ - uint32_t qkey; - /* Source GID index. */ - uint16_t sgid_index; - /* Network type. */ - uint8_t network_type; - /* RoCEv1. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 UINT32_C(0x0) - /* RoCEv2 IPv4. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 UINT32_C(0x2) - /* RoCEv2 IPv6. */ - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 UINT32_C(0x3) - #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 - uint8_t unused_0; - /* Destination GID. */ - uint32_t dgid[4]; - /* Destination QP id. */ - uint32_t dest_qp_id; - /* Statistic collection ID allocated for this QP. */ - uint8_t stat_collection_id; - uint8_t reservred_8; - uint16_t reserved_16; -} creq_query_qp_extend_resp_sb_tlv_t, *pcreq_query_qp_extend_resp_sb_tlv_t; - -/************** - * create_srq * - **************/ - + /* + * If set to 1, then securely erase all unused locations in + * persistent storage. + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE UINT32_C(0x1) + /* + * If set to 1, then unspecified images, images not in the package + * file, will be safely deleted. + * When combined with erase_unused_space then unspecified images will + * be securely erased. + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG UINT32_C(0x2) + /* + * If set to 1, FW will defragment the NVM if defragmentation is + * required for the update. + * Allow additional time for this command to complete if this bit is + * set to 1. + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG UINT32_C(0x4) + /* + * If set to 1, FW will verify the package in the "UPDATE" NVM item + * without installing it. This flag is for FW internal use only. + * Users should not set this flag. The request will otherwise fail. + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY UINT32_C(0x8) + uint8_t unused_0[2]; +} hwrm_nvm_install_update_input_t, *phwrm_nvm_install_update_input_t; -/* cmdq_create_srq (size:384b/48B) */ +/* hwrm_nvm_install_update_output (size:192b/24B) */ -typedef struct cmdq_create_srq { - /* Command opcode. */ - uint8_t opcode; - /* Create SRQ command allocates a SRQ with the specified parameters. */ - #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ UINT32_C(0x5) - #define CMDQ_CREATE_SRQ_OPCODE_LAST CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* SRQ handle. */ - uint64_t srq_handle; - uint16_t pg_size_lvl; - /* SRQ PBL indirect levels. */ - #define CMDQ_CREATE_SRQ_LVL_MASK UINT32_C(0x3) - #define CMDQ_CREATE_SRQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_CREATE_SRQ_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_CREATE_SRQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_CREATE_SRQ_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2 - /* page size. */ - #define CMDQ_CREATE_SRQ_PG_SIZE_MASK UINT32_C(0x1c) - #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2 - /* 4KB. */ - #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2) - /* 8KB. */ - #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2) - /* 64KB. */ - #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2) - /* 2MB. */ - #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2) - /* 8MB. */ - #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2) - /* 1GB. */ - #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2) - #define CMDQ_CREATE_SRQ_PG_SIZE_LAST CMDQ_CREATE_SRQ_PG_SIZE_PG_1G - /* unused11 is 11 b */ - #define CMDQ_CREATE_SRQ_UNUSED11_MASK UINT32_C(0xffe0) - #define CMDQ_CREATE_SRQ_UNUSED11_SFT 5 - uint16_t eventq_id; - /* eventq_id is 12 b */ - #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK UINT32_C(0xfff) - #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0 - /* unused4 is 4 b */ - #define CMDQ_CREATE_SRQ_UNUSED4_MASK UINT32_C(0xf000) - #define CMDQ_CREATE_SRQ_UNUSED4_SFT 12 - /* Max number of SRQ wqes. */ - uint16_t srq_size; - /* Offset of first WQE in the first page of SRQ, in 128 byte units */ - uint16_t srq_fwo; - /* Doorbell page index. */ - uint32_t dpi; - /* Protection domain id. */ - uint32_t pd_id; - /* RQ PBL physical address. */ - uint64_t pbl; -} cmdq_create_srq_t, *pcmdq_create_srq_t; - -/* creq_create_srq_resp (size:128b/16B) */ - -typedef struct creq_create_srq_resp { - uint8_t type; +typedef struct hwrm_nvm_install_update_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Bit-mask of successfully installed items. + * Bit-0 corresponding to the first packaged item, Bit-1 for the second + * item, etc. A value of 0 indicates that no items were successfully + * installed. */ - #define CREQ_CREATE_SRQ_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_CREATE_SRQ_RESP_TYPE_LAST CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* SRQ context id */ - uint32_t xid; - uint8_t v; + uint64_t installed_items; + /* result is 8 b corresponding to BCMRETVAL error codes */ + uint8_t result; + /* There was no problem with the package installation. */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0) + /* Generic failure */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE UINT32_C(0xff) + /* Allocation error malloc failure */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE UINT32_C(0xfd) + /* NVM install error due to invalid index */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER UINT32_C(0xfb) + /* NVM install error due to invalid type */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER UINT32_C(0xf3) + /* Invalid package due to invalid prerequisite */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE UINT32_C(0xf2) + /* Invalid package due to invalid file header */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER UINT32_C(0xec) + /* Invalid package due to invalid format */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE UINT32_C(0xeb) + /* Invalid package due to invalid property stream */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM UINT32_C(0xea) + /* Invalid package due to invalid property length */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH UINT32_C(0xe9) + /* Invalid package due to invalid manifest */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST UINT32_C(0xe8) + /* Invalid package due to invalid trailer */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER UINT32_C(0xe7) + /* Invalid package due to invalid checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM UINT32_C(0xe6) + /* Invalid package due to invalid item checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM UINT32_C(0xe5) + /* Invalid package due to invalid length */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH UINT32_C(0xe4) + /* Invalid package due to invalid directive */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE UINT32_C(0xe1) + /* Invalid device due to unsupported chip revision */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV UINT32_C(0xce) + /* Invalid device due to unsupported device ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID UINT32_C(0xcd) + /* Invalid device due to unsupported subsystem vendor */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR UINT32_C(0xcc) + /* Invalid device due to unsupported subsystem ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID UINT32_C(0xcb) + /* Invalid device due to unsupported product ID or customer ID */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM UINT32_C(0xc5) + /* Invalid package due to duplicate item */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM UINT32_C(0xc4) + /* Invalid package due to zero length item */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM UINT32_C(0xc3) + /* NVM integrity error checksum */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR UINT32_C(0xb9) + /* NVM integrity error */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR UINT32_C(0xb8) + /* Authentication error */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR UINT32_C(0xb7) + /* NVM install error item not found */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND UINT32_C(0xb0) + /* NVM install error item locked */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED UINT32_C(0xa7) + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED + /* problem_item is 8 b */ + uint8_t problem_item; + /* There was no problem with any packaged items. */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE UINT32_C(0x0) + /* There was a problem with the NVM package itself. */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE UINT32_C(0xff) + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE + /* reset_required is 8 b */ + uint8_t reset_required; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * No reset is required for installed/updated firmware or + * microcode to take effect. */ - #define CREQ_CREATE_SRQ_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Create SRQ command response. */ - #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ UINT32_C(0x5) - #define CREQ_CREATE_SRQ_RESP_EVENT_LAST CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ - uint8_t reserved48[6]; -} creq_create_srq_resp_t, *pcreq_create_srq_resp_t; + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE UINT32_C(0x0) + /* + * A PCIe reset (e.g. system reboot) is + * required for newly installed/updated firmware or + * microcode to take effect. + */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI UINT32_C(0x1) + /* + * A controller power reset (e.g. system power-cycle) is + * required for newly installed/updated firmware or + * microcode to take effect. Some newly installed/updated + * firmware or microcode may still take effect upon the + * next PCIe reset. + */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER UINT32_C(0x2) + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER + uint8_t unused_0[4]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_install_update_output_t, *phwrm_nvm_install_update_output_t; -/*************** - * destroy_srq * - ***************/ +/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ +typedef struct hwrm_nvm_install_update_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Unable to complete operation due to fragmentation */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1) + /* nvm is completely full. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2) + /* Firmware update failed due to Anti-rollback. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK UINT32_C(0x3) + /* Firmware update does not support voltage regulators on the device. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT UINT32_C(0x4) + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT + uint8_t unused_0[7]; +} hwrm_nvm_install_update_cmd_err_t, *phwrm_nvm_install_update_cmd_err_t; -/* cmdq_destroy_srq (size:192b/24B) */ +/****************** + * hwrm_nvm_flush * + ******************/ -typedef struct cmdq_destroy_srq { - /* Command opcode. */ - uint8_t opcode; - /* Destroy SRQ command deletes and flushes the specified SRQ. */ - #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ UINT32_C(0x6) - #define CMDQ_DESTROY_SRQ_OPCODE_LAST CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* SRQ context id */ - uint32_t srq_cid; - uint32_t unused_0; -} cmdq_destroy_srq_t, *pcmdq_destroy_srq_t; -/* creq_destroy_srq_resp (size:128b/16B) */ +/* hwrm_nvm_flush_input (size:128b/16B) */ -typedef struct creq_destroy_srq_resp { - uint8_t type; +typedef struct hwrm_nvm_flush_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_DESTROY_SRQ_RESP_TYPE_LAST CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* SRQ context id */ - uint32_t xid; - uint8_t v; + uint16_t cmpl_ring; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define CREQ_DESTROY_SRQ_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Destroy SRQ command response. */ - #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ UINT32_C(0x6) - #define CREQ_DESTROY_SRQ_RESP_EVENT_LAST CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ - uint16_t enable_for_arm[3]; - #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK UINT32_C(0xffff) - #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0 - /* Set to 1 if this SRQ is allowed to be armed for threshold async event */ - #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK UINT32_C(0x30000) - #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16 -} creq_destroy_srq_resp_t, *pcreq_destroy_srq_resp_t; - -/************* - * query_srq * - *************/ - - -/* cmdq_query_srq (size:192b/24B) */ - -typedef struct cmdq_query_srq { - /* Command opcode. */ - uint8_t opcode; - /* Query SRP command retrieves info about the specified SRQ. */ - #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ UINT32_C(0x8) - #define CMDQ_QUERY_SRQ_OPCODE_LAST CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ uint64_t resp_addr; - /* SRQ context id */ - uint32_t srq_cid; - uint32_t unused_0; -} cmdq_query_srq_t, *pcmdq_query_srq_t; +} hwrm_nvm_flush_input_t, *phwrm_nvm_flush_input_t; -/* creq_query_srq_resp (size:128b/16B) */ +/* hwrm_nvm_flush_output (size:128b/16B) */ -typedef struct creq_query_srq_resp { - uint8_t type; - /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. - */ - #define CREQ_QUERY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_QUERY_SRQ_RESP_TYPE_LAST CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Side buffer size in 16-byte units */ - uint32_t size; - uint8_t v; +typedef struct hwrm_nvm_flush_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define CREQ_QUERY_SRQ_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Query SRQ command response. */ - #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ UINT32_C(0x8) - #define CREQ_QUERY_SRQ_RESP_EVENT_LAST CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ - uint8_t reserved48[6]; -} creq_query_srq_resp_t, *pcreq_query_srq_resp_t; + uint8_t valid; +} hwrm_nvm_flush_output_t, *phwrm_nvm_flush_output_t; -/* Query SRQ command response side buffer structure. */ -/* creq_query_srq_resp_sb (size:256b/32B) */ +/* hwrm_nvm_flush_cmd_err (size:64b/8B) */ -typedef struct creq_query_srq_resp_sb { - /* Command opcode. */ - uint8_t opcode; - /* Query SRQ command response. */ - #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ UINT32_C(0x8) - #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* SRQ context id */ - uint32_t xid; - /* Watermark value to generate a SRQ limit event. */ - uint16_t srq_limit; - uint16_t reserved16; - /* data is 128 b */ - uint32_t data[4]; -} creq_query_srq_resp_sb_t, *pcreq_query_srq_resp_sb_t; +typedef struct hwrm_nvm_flush_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* flush could not be performed */ + #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1) + #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL + uint8_t unused_0[7]; +} hwrm_nvm_flush_cmd_err_t, *phwrm_nvm_flush_cmd_err_t; -/************* - * create_cq * - *************/ +/************************* + * hwrm_nvm_get_variable * + *************************/ -/* cmdq_create_cq (size:384b/48B) */ +/* hwrm_nvm_get_variable_input (size:320b/40B) */ -typedef struct cmdq_create_cq { - /* Command opcode. */ - uint8_t opcode; - /* Create CQ command allocates a CQ with the specified parameters. */ - #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ UINT32_C(0x9) - #define CMDQ_CREATE_CQ_OPCODE_LAST CMDQ_CREATE_CQ_OPCODE_CREATE_CQ - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; +typedef struct hwrm_nvm_get_variable_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When the HW Doorbell Drop Recovery feature is enabled, - * HW can flag false CQ overflow when CQ consumer index - * doorbells are dropped when there really wasn't any overflow. - * The CQE values could have already been processed by the driver, - * but HW doesn't know about this because of the doorbell drop. - * To avoid false detection of CQ overflow events, - * it is recommended that CQ overflow detection is disabled - * by the driver when HW based doorbell recovery is enabled. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x1) - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* CQ handle. */ - uint64_t cq_handle; - uint32_t pg_size_lvl; - /* PBL indirect levels. */ - #define CMDQ_CREATE_CQ_LVL_MASK UINT32_C(0x3) - #define CMDQ_CREATE_CQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_CREATE_CQ_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_CREATE_CQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_CREATE_CQ_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2 - /* page size. */ - #define CMDQ_CREATE_CQ_PG_SIZE_MASK UINT32_C(0x1c) - #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2 - /* 4KB. */ - #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2) - /* 8KB. */ - #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2) - /* 64KB. */ - #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2) - /* 2MB. */ - #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2) - /* 8MB. */ - #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2) - /* 1GB. */ - #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2) - #define CMDQ_CREATE_CQ_PG_SIZE_LAST CMDQ_CREATE_CQ_PG_SIZE_PG_1G - /* unused27 is 27 b */ - #define CMDQ_CREATE_CQ_UNUSED27_MASK UINT32_C(0xffffffe0) - #define CMDQ_CREATE_CQ_UNUSED27_SFT 5 - uint32_t cq_fco_cnq_id; - /* cnq_id is 12 b */ - #define CMDQ_CREATE_CQ_CNQ_ID_MASK UINT32_C(0xfff) - #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0 - /* Offset of first CQE in the first Page, in 32 byte units */ - #define CMDQ_CREATE_CQ_CQ_FCO_MASK UINT32_C(0xfffff000) - #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12 - /* Doorbell page index. */ - uint32_t dpi; - /* Max number of CQ wqes. */ - uint32_t cq_size; - /* CQ PBL physical address. */ - uint64_t pbl; -} cmdq_create_cq_t, *pcmdq_create_cq_t; - -/* creq_create_cq_resp (size:128b/16B) */ - -typedef struct creq_create_cq_resp { - uint8_t type; + uint16_t cmpl_ring; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define CREQ_CREATE_CQ_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_CREATE_CQ_RESP_TYPE_LAST CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* CQ context id */ - uint32_t xid; - uint8_t v; + uint16_t seq_id; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define CREQ_CREATE_CQ_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Create CQ command response. */ - #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ UINT32_C(0x9) - #define CREQ_CREATE_CQ_RESP_EVENT_LAST CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ - uint8_t reserved48[6]; -} creq_create_cq_resp_t, *pcreq_create_cq_resp_t; - -/************** - * destroy_cq * - **************/ - - -/* cmdq_destroy_cq (size:192b/24B) */ - -typedef struct cmdq_destroy_cq { - /* Command opcode. */ - uint8_t opcode; - /* Destroy CQ command deletes and flushes the specified CQ. */ - #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ UINT32_C(0xa) - #define CMDQ_DESTROY_CQ_OPCODE_LAST CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ uint64_t resp_addr; - /* CQ context id */ - uint32_t cq_cid; - uint32_t unused_0; -} cmdq_destroy_cq_t, *pcmdq_destroy_cq_t; - -/* creq_destroy_cq_resp (size:128b/16B) */ - -typedef struct creq_destroy_cq_resp { - uint8_t type; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This is the host address where + * nvm variable will be stored */ - #define CREQ_DESTROY_CQ_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_DESTROY_CQ_RESP_TYPE_LAST CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* CQ context id */ - uint32_t xid; - uint8_t v; + uint64_t dest_data_addr; + /* size of data in bits */ + uint16_t data_len; + /* nvm cfg option number */ + uint16_t option_num; + /* reserved. */ + #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0) + /* reserved. */ + #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff) + #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Number of dimensions for this nvm configuration variable. + * This value indicates how many of the indexN values to use. + * A value of 0 means that none of the indexN values are valid. + * A value of 1 requires at index0 is valued, a value of 2 + * requires that index0 and index1 are valid, and so forth */ - #define CREQ_DESTROY_CQ_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Destroy CQ command response. */ - #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ UINT32_C(0xa) - #define CREQ_DESTROY_CQ_RESP_EVENT_LAST CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ - uint16_t cq_arm_lvl; + uint16_t dimensions; + /* index for the 1st dimensions */ + uint16_t index_0; + /* index for the 2nd dimensions */ + uint16_t index_1; + /* index for the 3rd dimensions */ + uint16_t index_2; + /* index for the 4th dimensions */ + uint16_t index_3; + uint8_t flags; /* - * CQ ARM Level: - * 0 ? Not Armed - * 1 ? Arm SE Only, Generate CNQE only for incoming Solicited Events - * 2 ? Arm all, Generate CNQE for Rx and Tx + * When this bit is set to 1, the factory default value will be + * returned, 0 returns the operational value. */ - #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK UINT32_C(0x3) - #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0 + #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT UINT32_C(0x1) + uint8_t unused_0; +} hwrm_nvm_get_variable_input_t, *phwrm_nvm_get_variable_input_t; + +/* hwrm_nvm_get_variable_output (size:128b/16B) */ + +typedef struct hwrm_nvm_get_variable_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* size of data of the actual variable retrieved in bits */ + uint16_t data_len; /* - * The total number of CNQ events for the CQ, incremented on each CNQ event for the CQ - * (including firmware-generated CQ error notification). + * option_num is the option number for the data retrieved. It is + * possible in the future that the option number returned would be + * different than requested. This condition could occur if an option is + * deprecated and a new option id is defined with similar + * characteristics, but has a slightly different definition. This + * also makes it convenient for the caller to identify the variable + * result with the option id from the response. */ - uint16_t total_cnq_events; - uint16_t reserved16; -} creq_destroy_cq_resp_t, *pcreq_destroy_cq_resp_t; + uint16_t option_num; + /* reserved. */ + #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0) + /* reserved. */ + #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff) + #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_get_variable_output_t, *phwrm_nvm_get_variable_output_t; -/************* - * resize_cq * - *************/ +/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ +typedef struct hwrm_nvm_get_variable_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* variable does not exist */ + #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1) + /* configuration is corrupted and the variable cannot be saved */ + #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2) + /* length specified is too small */ + #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3) + #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT + uint8_t unused_0[7]; +} hwrm_nvm_get_variable_cmd_err_t, *phwrm_nvm_get_variable_cmd_err_t; -/* cmdq_resize_cq (size:320b/40B) */ +/************************* + * hwrm_nvm_set_variable * + *************************/ -typedef struct cmdq_resize_cq { - /* Command opcode. */ - uint8_t opcode; - /* Resize CQ command resizes the specified CQ. */ - #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ UINT32_C(0xc) - #define CMDQ_RESIZE_CQ_OPCODE_LAST CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* CQ context id */ - uint32_t cq_cid; - uint32_t new_cq_size_pg_size_lvl; - /* PBL indirect levels. */ - #define CMDQ_RESIZE_CQ_LVL_MASK UINT32_C(0x3) - #define CMDQ_RESIZE_CQ_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_RESIZE_CQ_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_RESIZE_CQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_RESIZE_CQ_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2 - /* page size. */ - #define CMDQ_RESIZE_CQ_PG_SIZE_MASK UINT32_C(0x1c) - #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2 - /* 4KB. */ - #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2) - /* 8KB. */ - #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2) - /* 64KB. */ - #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2) - /* 2MB. */ - #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2) - /* 8MB. */ - #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2) - /* 1GB. */ - #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2) - #define CMDQ_RESIZE_CQ_PG_SIZE_LAST CMDQ_RESIZE_CQ_PG_SIZE_PG_1G - /* New max number of CQ wqes. */ - #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK UINT32_C(0x1fffffe0) - #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5 - /* CQ PBL physical address. */ - uint64_t new_pbl; - /* Offset of first CQE in the first Page, in 32 byte units */ - uint32_t new_cq_fco; - uint32_t unused_0; -} cmdq_resize_cq_t, *pcmdq_resize_cq_t; -/* creq_resize_cq_resp (size:128b/16B) */ +/* hwrm_nvm_set_variable_input (size:320b/40B) */ -typedef struct creq_resize_cq_resp { - uint8_t type; +typedef struct hwrm_nvm_set_variable_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define CREQ_RESIZE_CQ_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_RESIZE_CQ_RESP_TYPE_LAST CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* CQ context id */ - uint32_t xid; - uint8_t v; + uint16_t cmpl_ring; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define CREQ_RESIZE_CQ_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Resize CQ command response. */ - #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ UINT32_C(0xc) - #define CREQ_RESIZE_CQ_RESP_EVENT_LAST CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ - uint8_t reserved48[6]; -} creq_resize_cq_resp_t, *pcreq_resize_cq_resp_t; - -/************* - * modify_cq * - *************/ - - -/* cmdq_modify_cq (size:512b/64B) */ - -typedef struct cmdq_modify_cq { - /* Command opcode. */ - uint8_t opcode; - /* Modify CQ updates specific params in the CQ context. */ - #define CMDQ_MODIFY_CQ_OPCODE_MODIFY_CQ UINT32_C(0x90) - #define CMDQ_MODIFY_CQ_OPCODE_LAST CMDQ_MODIFY_CQ_OPCODE_MODIFY_CQ - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; + uint16_t seq_id; /* - * When the HW Doorbell Drop Recovery feature is enabled, - * HW can flag false CQ overflow when CQ consumer index - * doorbells are dropped when there really wasn't any overflow. - * The CQE values could have already been processed by the driver, - * but HW doesn't know about this because of the doorbell drop. - * To avoid false detection of CQ overflow events, - * it is recommended that CQ overflow detection is disabled - * by the driver when HW based doorbell recovery is enabled. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define CMDQ_MODIFY_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x1) - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ uint64_t resp_addr; - /* Modify mask signifies the field that is requesting the change. */ - uint32_t modify_mask; - /* Enable change. */ - #define CMDQ_MODIFY_CQ_MODIFY_MASK_CQ_HANDLE UINT32_C(0x1) - /* CNQ ID */ - #define CMDQ_MODIFY_CQ_MODIFY_MASK_CNQ_ID UINT32_C(0x2) - /* Offset of first CQE in the first page, in 32 byte units */ - #define CMDQ_MODIFY_CQ_MODIFY_MASK_FCO UINT32_C(0x4) - /* Doorbell page index */ - #define CMDQ_MODIFY_CQ_MODIFY_MASK_DPI UINT32_C(0x8) - /* Max number of CQ Wqes */ - #define CMDQ_MODIFY_CQ_MODIFY_MASK_CQ_SIZE UINT32_C(0x10) - /* CQ PBL physical address */ - #define CMDQ_MODIFY_CQ_MODIFY_MASK_PBL UINT32_C(0x20) - /* reserved32 is 32 b */ - uint32_t reserved32; - /* CQ handle. */ - uint64_t cq_handle; - uint32_t cq_fco_cnq_id; - /* cnq_id is 12 b */ - #define CMDQ_MODIFY_CQ_CNQ_ID_MASK UINT32_C(0xfff) - #define CMDQ_MODIFY_CQ_CNQ_ID_SFT 0 - /* Offset of first CQE in the first Page, in 32 byte units */ - #define CMDQ_MODIFY_CQ_CQ_FCO_MASK UINT32_C(0xfffff000) - #define CMDQ_MODIFY_CQ_CQ_FCO_SFT 12 - /* Doorbell page index. */ - uint32_t dpi; - /* Max number of CQ wqes. */ - uint32_t cq_size; - /* reserved32_1 is 32 b */ - uint32_t reserved32_1; - /* CQ PBL physical address. */ - uint64_t pbl; - /* reserved64 is 64 b */ - uint64_t reserved64; -} cmdq_modify_cq_t, *pcmdq_modify_cq_t; + /* + * This is the host address where + * nvm variable will be copied from + */ + uint64_t src_data_addr; + /* size of data in bits */ + uint16_t data_len; + /* nvm cfg option number */ + uint16_t option_num; + /* reserved. */ + #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0) + /* reserved. */ + #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff) + #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF + /* + * Number of dimensions for this nvm configuration variable. + * This value indicates how many of the indexN values to use. + * A value of 0 means that none of the indexN values are valid. + * A value of 1 requires at index0 is valued, a value of 2 + * requires that index0 and index1 are valid, and so forth + */ + uint16_t dimensions; + /* index for the 1st dimensions */ + uint16_t index_0; + /* index for the 2nd dimensions */ + uint16_t index_1; + /* index for the 3rd dimensions */ + uint16_t index_2; + /* index for the 4th dimensions */ + uint16_t index_3; + uint8_t flags; + /* + * When this bit is 1, flush internal cache after this write + * operation (see hwrm_nvm_flush command.) + */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH UINT32_C(0x1) + /* encryption method */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK UINT32_C(0xe) + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1 + /* No encryption. */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE (UINT32_C(0x0) << 1) + /* one-way encryption. */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (UINT32_C(0x1) << 1) + /* symmetric AES256 encryption. */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 (UINT32_C(0x2) << 1) + /* SHA1 digest appended to plaintext contents, for authentication */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (UINT32_C(0x3) << 1) + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK UINT32_C(0x70) + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4 + /* When this bit is 1, update the factory default region */ + #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT UINT32_C(0x80) + uint8_t unused_0; +} hwrm_nvm_set_variable_input_t, *phwrm_nvm_set_variable_input_t; -/* creq_modify_cq_resp (size:128b/16B) */ +/* hwrm_nvm_set_variable_output (size:128b/16B) */ -typedef struct creq_modify_cq_resp { - uint8_t type; +typedef struct hwrm_nvm_set_variable_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define CREQ_MODIFY_CQ_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_MODIFY_CQ_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_MODIFY_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_MODIFY_CQ_RESP_TYPE_LAST CREQ_MODIFY_CQ_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* CQ context id */ - uint32_t xid; - uint8_t v; + uint8_t valid; +} hwrm_nvm_set_variable_output_t, *phwrm_nvm_set_variable_output_t; + +/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ + +typedef struct hwrm_nvm_set_variable_cmd_err { /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. */ - #define CREQ_MODIFY_CQ_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Modify CQ command response. */ - #define CREQ_MODIFY_CQ_RESP_EVENT_MODIFY_CQ UINT32_C(0x9) - #define CREQ_MODIFY_CQ_RESP_EVENT_LAST CREQ_MODIFY_CQ_RESP_EVENT_MODIFY_CQ - uint8_t reserved48[6]; -} creq_modify_cq_resp_t, *pcreq_modify_cq_resp_t; + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* variable does not exist */ + #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1) + /* configuration is corrupted and the variable cannot be saved */ + #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2) + #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR + uint8_t unused_0[7]; +} hwrm_nvm_set_variable_cmd_err_t, *phwrm_nvm_set_variable_cmd_err_t; -/**************** - * allocate_mrw * - ****************/ +/**************************** + * hwrm_nvm_validate_option * + ****************************/ -/* cmdq_allocate_mrw (size:256b/32B) */ +/* hwrm_nvm_validate_option_input (size:320b/40B) */ -typedef struct cmdq_allocate_mrw { - /* Command opcode. */ - uint8_t opcode; +typedef struct hwrm_nvm_validate_option_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Allocate MRW command allocates a MR/MW with the specified parameters - * and returns the region's L_KEY/R_KEY + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW UINT32_C(0xd) - #define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ uint64_t resp_addr; - /* MRW handle. */ - uint64_t mrw_handle; - uint8_t mrw_flags; - /* Allocate MRW flags. */ - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK UINT32_C(0xf) - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0 - /* Allocate Memory Region */ - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR UINT32_C(0x0) - /* Allocate Physical Memory Region */ - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR UINT32_C(0x1) - /* Allocate Memory Window (type 1) */ - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2) - /* Allocate Memory Window (type 2A) */ - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3) - /* Allocate Memory Window (type 2B) */ - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4) - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B - /* unused4 is 4 b */ - #define CMDQ_ALLOCATE_MRW_UNUSED4_MASK UINT32_C(0xf0) - #define CMDQ_ALLOCATE_MRW_UNUSED4_SFT 4 - /* Access flags. */ - uint8_t access; - /* Consumer owns the key */ - #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY UINT32_C(0x20) - /* unused16 is 16 b */ - uint16_t unused16; - /* Protection domain id. */ - uint32_t pd_id; -} cmdq_allocate_mrw_t, *pcmdq_allocate_mrw_t; + /* + * This is the host address where + * nvm variable will be copied from + */ + uint64_t src_data_addr; + /* size of data in bits */ + uint16_t data_len; + /* nvm cfg option number */ + uint16_t option_num; + /* reserved. */ + #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0) + /* reserved. */ + #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff) + #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF + /* + * Number of dimensions for this nvm configuration variable. + * This value indicates how many of the indexN values to use. + * A value of 0 means that none of the indexN values are valid. + * A value of 1 requires at index0 is valued, a value of 2 + * requires that index0 and index1 are valid, and so forth + */ + uint16_t dimensions; + /* index for the 1st dimensions */ + uint16_t index_0; + /* index for the 2nd dimensions */ + uint16_t index_1; + /* index for the 3rd dimensions */ + uint16_t index_2; + /* index for the 4th dimensions */ + uint16_t index_3; + uint8_t unused_0[2]; +} hwrm_nvm_validate_option_input_t, *phwrm_nvm_validate_option_input_t; -/* creq_allocate_mrw_resp (size:128b/16B) */ +/* hwrm_nvm_validate_option_output (size:128b/16B) */ -typedef struct creq_allocate_mrw_resp { - uint8_t type; +typedef struct hwrm_nvm_validate_option_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t result; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * indicates that the value provided for the option is not matching + * with the saved data. */ - #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* L_KEY for MR, R_KEY for MW */ - uint32_t xid; - uint8_t v; + #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * indicates that the value provided for the option is matching the + * saved data. */ - #define CREQ_ALLOCATE_MRW_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Allocate MRW command response. */ - #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW UINT32_C(0xd) - #define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW - uint8_t reserved48[6]; -} creq_allocate_mrw_resp_t, *pcreq_allocate_mrw_resp_t; + #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1) + #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_validate_option_output_t, *phwrm_nvm_validate_option_output_t; -/****************** - * deallocate_key * - ******************/ +/* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */ +typedef struct hwrm_nvm_validate_option_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN + uint8_t unused_0[7]; +} hwrm_nvm_validate_option_cmd_err_t, *phwrm_nvm_validate_option_cmd_err_t; -/* cmdq_deallocate_key (size:192b/24B) */ +/***************************** + * hwrm_nvm_factory_defaults * + *****************************/ -typedef struct cmdq_deallocate_key { - /* Command opcode. */ - uint8_t opcode; - /* De-allocate key command frees a MR/MW entry associated with the specified key. */ - #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY UINT32_C(0xe) - #define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - uint8_t mrw_flags; - /* Deallocate MRW flags. */ - #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK UINT32_C(0xf) - #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0 - /* Deallocate Memory Region */ - #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR UINT32_C(0x0) - /* Deallocate Physical Memory Region */ - #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR UINT32_C(0x1) - /* Deallocate Memory Window (type 1) */ - #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2) - /* Deallocate Memory Window (type 2A) */ - #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3) - /* Deallocate Memory Window (type 2B) */ - #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4) - #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B - /* unused4 is 4 b */ - #define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK UINT32_C(0xf0) - #define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT 4 - /* unused24 is 24 b */ - uint8_t unused24[3]; - /* key is 32 b */ - uint32_t key; -} cmdq_deallocate_key_t, *pcmdq_deallocate_key_t; -/* creq_deallocate_key_resp (size:128b/16B) */ +/* hwrm_nvm_factory_defaults_input (size:192b/24B) */ -typedef struct creq_deallocate_key_resp { - uint8_t type; +typedef struct hwrm_nvm_factory_defaults_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* L_KEY for MR, R_KEY for MW */ - uint32_t xid; - uint8_t v; + uint16_t cmpl_ring; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define CREQ_DEALLOCATE_KEY_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* De-allocate key command response. */ - #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY UINT32_C(0xe) - #define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY - uint16_t reserved16; + uint16_t seq_id; /* - * This is advisory data to facilitate eventual destruction of lingering memory regions in Windows. - * For memory window, it contains non-zero HWID of a region this window was bound to (without the 8-bit key portion). - * The host may check if the region is lingering in destroyed state and try to destroy it now. - * For memory region, if deallocation fails because there are windows bound to this region, this field will contain - * approximate number of those windows. This number is read from the context right before the - * deregistration is attempted and can potentially be slightly different from the current number. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint32_t bound_window_info; -} creq_deallocate_key_resp_t, *pcreq_deallocate_key_resp_t; - -/*************** - * register_mr * - ***************/ - - -/* cmdq_register_mr (size:384b/48B) */ - -typedef struct cmdq_register_mr { - /* Command opcode. */ - uint8_t opcode; - /* Register MR command registers memory to the specified MR. */ - #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR UINT32_C(0xf) - #define CMDQ_REGISTER_MR_OPCODE_LAST CMDQ_REGISTER_MR_OPCODE_REGISTER_MR - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; + uint16_t target_id; /* - * When set, a new MR will be allocated first and then registered - * using the fields in this command. Note that for MR allocation - * the `key` field doesn't hold a valid L_KEY and is instead - * overloaded to hold the Protection Domain ID `pd_id`. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR UINT32_C(0x1) - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ uint64_t resp_addr; - uint8_t log2_pg_size_lvl; - /* PBL indirect levels. */ - #define CMDQ_REGISTER_MR_LVL_MASK UINT32_C(0x3) - #define CMDQ_REGISTER_MR_LVL_SFT 0 - /* PBL pointer is physical start address. */ - #define CMDQ_REGISTER_MR_LVL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define CMDQ_REGISTER_MR_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_REGISTER_MR_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2 - /* Log base 2 of page size; 12 is the minimum for 4KB. HW supported values are enumerated below. */ - #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK UINT32_C(0x7c) - #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2 - /* 4KB. */ - #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (UINT32_C(0xc) << 2) - /* 8KB. */ - #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (UINT32_C(0xd) << 2) - /* 64KB. */ - #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (UINT32_C(0x10) << 2) - /* 256KB. */ - #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (UINT32_C(0x12) << 2) - /* 1MB. */ - #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (UINT32_C(0x14) << 2) - /* 2MB. */ - #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (UINT32_C(0x15) << 2) - /* 4MB. */ - #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (UINT32_C(0x16) << 2) - /* 1GB. */ - #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (UINT32_C(0x1e) << 2) - #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G - /* unused1 is 1 b */ - #define CMDQ_REGISTER_MR_UNUSED1 UINT32_C(0x80) - /* Access flags. */ - uint8_t access; - /* Local write access. */ - #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE UINT32_C(0x1) - /* Remote read access. */ - #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ UINT32_C(0x2) - /* Remote write access. */ - #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE UINT32_C(0x4) - /* Remote atomic access. */ - #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC UINT32_C(0x8) - /* Bind access allowed. */ - #define CMDQ_REGISTER_MR_ACCESS_MW_BIND UINT32_C(0x10) - /* Indicate Zero Based Virtual Address (ZBVA). */ - #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED UINT32_C(0x20) - uint16_t log2_pbl_pg_size; - /* Log base 2 of PBL page size; 12 is the minimum for 4KB. HW supported values are enumerated below */ - #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK UINT32_C(0x1f) - #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0 - /* 4KB. */ - #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K UINT32_C(0xc) - /* 8KB. */ - #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K UINT32_C(0xd) - /* 64KB. */ - #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K UINT32_C(0x10) - /* 256KB. */ - #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K UINT32_C(0x12) - /* 1MB. */ - #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M UINT32_C(0x14) - /* 2MB. */ - #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M UINT32_C(0x15) - /* 4MB. */ - #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M UINT32_C(0x16) - /* 1GB. */ - #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G UINT32_C(0x1e) - #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G - /* unused11 is 11 b */ - #define CMDQ_REGISTER_MR_UNUSED11_MASK UINT32_C(0xffe0) - #define CMDQ_REGISTER_MR_UNUSED11_SFT 5 + /* mode is 8 b */ + uint8_t mode; /* - * L_KEY of the previously allocated MR. - * - * If the `ALLOC_MR` flag is set then this field does not hold an - * L_KEY and instead contains the Protection Domain ID `pd_id`. + * If set to 1, it triggers restoration of factory default data. + * If the selection field is zero, all data are restored to default. + * If the selection field is non-zero, only the selected data are + * restored. */ - uint32_t key; - /* Page table of the MR memory. */ - uint64_t pbl; - /* Virtual address of the MR. */ - uint64_t va; - /* Size of the MR. */ - uint64_t mr_size; -} cmdq_register_mr_t, *pcmdq_register_mr_t; - -/* creq_register_mr_resp (size:128b/16B) */ - -typedef struct creq_register_mr_resp { - uint8_t type; + #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * If set to 1, it triggers creation of factory default data. + * If the selection field is zero, all default data are created. + * If the selection field is non-zero, only the selected data are + * created. */ - #define CREQ_REGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_REGISTER_MR_RESP_TYPE_LAST CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* L_KEY */ - uint32_t xid; - uint8_t v; + #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE UINT32_C(0x1) + #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_LAST HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE + uint8_t unused_0[1]; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This field selects which data the factory default operation applies. + * If it is '0', the operation applies to all data. If it is not '0', + * the operation only applies to the data selected by this field. */ - #define CREQ_REGISTER_MR_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Register MR command response. */ - #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR UINT32_C(0xf) - #define CREQ_REGISTER_MR_RESP_EVENT_LAST CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR - uint8_t reserved48[6]; -} creq_register_mr_resp_t, *pcreq_register_mr_resp_t; + uint16_t selection; + /* When this bit is '1', config option is selected. */ + #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_SELECTION_CFG_OPTION UINT32_C(0x1) + /* When this bit is '1', crashdump is selected. */ + #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_SELECTION_CRASHDUMP UINT32_C(0x2) + uint8_t unused_1[4]; +} hwrm_nvm_factory_defaults_input_t, *phwrm_nvm_factory_defaults_input_t; -/***************** - * deregister_mr * - *****************/ +/* hwrm_nvm_factory_defaults_output (size:128b/16B) */ + +typedef struct hwrm_nvm_factory_defaults_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t result; + /* factory defaults created successfully. */ + #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK UINT32_C(0x0) + /* factory defaults restored successfully. */ + #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK UINT32_C(0x1) + /* factory defaults already created. */ + #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY UINT32_C(0x2) + #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_LAST HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_factory_defaults_output_t, *phwrm_nvm_factory_defaults_output_t; +/* hwrm_nvm_factory_defaults_cmd_err (size:64b/8B) */ -/* cmdq_deregister_mr (size:192b/24B) */ +typedef struct hwrm_nvm_factory_defaults_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* valid configuration not present to create defaults */ + #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG UINT32_C(0x1) + /* No saved configuration present to restore, restore failed */ + #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG UINT32_C(0x2) + #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_LAST HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG + uint8_t unused_0[7]; +} hwrm_nvm_factory_defaults_cmd_err_t, *phwrm_nvm_factory_defaults_cmd_err_t; -typedef struct cmdq_deregister_mr { - /* Command opcode. */ - uint8_t opcode; - /* Deregister MR command de-registers memory from the specified MR. */ - #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR UINT32_C(0x10) - #define CMDQ_DEREGISTER_MR_OPCODE_LAST CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* L_KEY of the MR. */ - uint32_t lkey; - uint32_t unused_0; -} cmdq_deregister_mr_t, *pcmdq_deregister_mr_t; +/**************************** + * hwrm_nvm_req_arbitration * + ****************************/ -/* creq_deregister_mr_resp (size:128b/16B) */ -typedef struct creq_deregister_mr_resp { - uint8_t type; +/* hwrm_nvm_req_arbitration_input (size:192b/24B) */ + +typedef struct hwrm_nvm_req_arbitration_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_DEREGISTER_MR_RESP_TYPE_LAST CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* L_KEY */ - uint32_t xid; - uint8_t v; + uint16_t cmpl_ring; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define CREQ_DEREGISTER_MR_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Deregister MR command response. */ - #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR UINT32_C(0x10) - #define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR - uint16_t reserved16; + uint16_t seq_id; /* - * If deregister fails because there are windows bound to this region, this field will contain - * approximate number of those windows. This number is read from the context right before the - * deregistration is attempted and can potentially be slightly different from the current number. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint32_t bound_windows; -} creq_deregister_mr_resp_t, *pcreq_deregister_mr_resp_t; + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Type of NVRAM arbitration request */ + uint8_t type; + /* Query if NVRAM arbitration semaphore is acquired outside of Nitro */ + #define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_STATUS UINT32_C(0x0) + /* Acquire NVRAM arbitration semaphore */ + #define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_ACQUIRE UINT32_C(0x1) + /* Release NVRAM arbitration semaphore */ + #define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_RELEASE UINT32_C(0x2) + #define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_LAST HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_RELEASE + uint8_t unused_0[7]; +} hwrm_nvm_req_arbitration_input_t, *phwrm_nvm_req_arbitration_input_t; -/*********** - * add_gid * - ***********/ +/* hwrm_nvm_req_arbitration_output (size:128b/16B) */ + +typedef struct hwrm_nvm_req_arbitration_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* NVRAM arbitration semaphore is acquired if value is 1 */ + uint8_t acquired; + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_req_arbitration_output_t, *phwrm_nvm_req_arbitration_output_t; +/******************* + * hwrm_nvm_defrag * + *******************/ -/* cmdq_add_gid (size:384b/48B) */ -typedef struct cmdq_add_gid { +/* hwrm_nvm_defrag_input (size:192b/24B) */ + +typedef struct hwrm_nvm_defrag_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* This bit must be '1' to perform NVM defragmentation. */ + #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1) + uint8_t unused_0[4]; +} hwrm_nvm_defrag_input_t, *phwrm_nvm_defrag_input_t; + +/* hwrm_nvm_defrag_output (size:128b/16B) */ + +typedef struct hwrm_nvm_defrag_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_defrag_output_t, *phwrm_nvm_defrag_output_t; + +/* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ + +typedef struct hwrm_nvm_defrag_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* NVM defragmentation could not be performed */ + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1) + #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_LAST HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL + uint8_t unused_0[7]; +} hwrm_nvm_defrag_cmd_err_t, *phwrm_nvm_defrag_cmd_err_t; + +/******************************* + * hwrm_nvm_get_vpd_field_info * + *******************************/ + + +/* hwrm_nvm_get_vpd_field_info_input (size:192b/24B) */ + +typedef struct hwrm_nvm_get_vpd_field_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Tag ID of the requested field. To request the Product Name + * a value of [0x00, 0x82] should be used. All other fields + * would use the two byte hexadecimal value of the ASCII + * characters. The first letter of the ASCII keyword is recorded + * in tag_id[0] and the next letter in tag_id[1]. + */ + uint8_t tag_id[2]; + uint8_t unused_0[6]; +} hwrm_nvm_get_vpd_field_info_input_t, *phwrm_nvm_get_vpd_field_info_input_t; + +/* hwrm_nvm_get_vpd_field_info_output (size:2176b/272B) */ + +typedef struct hwrm_nvm_get_vpd_field_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Data retrieved from VPD field */ + uint8_t data[256]; + /* size of data retrieved in bytes */ + uint16_t data_len; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_get_vpd_field_info_output_t, *phwrm_nvm_get_vpd_field_info_output_t; + +/******************************* + * hwrm_nvm_set_vpd_field_info * + *******************************/ + + +/* hwrm_nvm_set_vpd_field_info_input (size:256b/32B) */ + +typedef struct hwrm_nvm_set_vpd_field_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This is the host address where + * VPD data value will be copied from + */ + uint64_t host_src_addr; + /* + * Tag ID of the requested field. To request the Product Name + * a value of [0x00, 0x82] should be used. All other fields + * would use the two byte hexadecimal value of the ASCII + * characters. The first letter of the ASCII keyword is recorded + * in tag_id[0] and the next letter in tag_id[1]. + */ + uint8_t tag_id[2]; + /* size of data in bytes */ + uint16_t data_len; + uint8_t unused_0[4]; +} hwrm_nvm_set_vpd_field_info_input_t, *phwrm_nvm_set_vpd_field_info_input_t; + +/* hwrm_nvm_set_vpd_field_info_output (size:128b/16B) */ + +typedef struct hwrm_nvm_set_vpd_field_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_set_vpd_field_info_output_t, *phwrm_nvm_set_vpd_field_info_output_t; + +#define ROCE_SP_HSI_VERSION_MAJOR 1 +#define ROCE_SP_HSI_VERSION_MINOR 8 +#define ROCE_SP_HSI_VERSION_UPDATE 4 +#define ROCE_SP_HSI_VERSION_STR "1.8.4" +/* + * Following is the signature for ROCE_SP_HSI message field that indicates + * not applicable (All F's). Need to cast it the size of the field if + * needed. + */ +#define ROCE_SP_HSI_NA_SIGNATURE ((uint32_t)(-1)) + +/* cmdq_init (size:128b/16B) */ + +typedef struct cmdq_init { + /* CMDQ PBL physical address. */ + uint64_t cmdq_pbl; + uint16_t cmdq_size_cmdq_lvl; + /* CMDQ PBL indirection levels. */ + #define CMDQ_INIT_CMDQ_LVL_MASK UINT32_C(0x3) + #define CMDQ_INIT_CMDQ_LVL_SFT 0 + /* CMDQ size. */ + #define CMDQ_INIT_CMDQ_SIZE_MASK UINT32_C(0xfffc) + #define CMDQ_INIT_CMDQ_SIZE_SFT 2 + /* CREQ completion ring id. */ + uint16_t creq_ring_id; + /* Mailbox producer index. MSB must also be set. */ + uint32_t prod_idx; +} cmdq_init_t, *pcmdq_init_t; + +/* cmdq_update (size:128b/16B) */ + +typedef struct cmdq_update { + /* reserved64 is 64 b */ + uint64_t reserved64; + /* reserved32 is 32 b */ + uint32_t reserved32; + /* Mailbox producer index. */ + uint32_t prod_idx; +} cmdq_update_t, *pcmdq_update_t; + +/* cmdq_base (size:128b/16B) */ + +typedef struct cmdq_base { /* Command opcode. */ uint8_t opcode; + /* + * Create QP command allocates QP context with the specified + * SQ, RQ/SRQ, CQ and other parameters. + */ + #define CMDQ_BASE_OPCODE_CREATE_QP UINT32_C(0x1) + /* + * Destroy QP command deletes the QP context and ceases + * any further reference. + */ + #define CMDQ_BASE_OPCODE_DESTROY_QP UINT32_C(0x2) + /* + * Modify QP command changes QP states and other QP specific + * parameters. + */ + #define CMDQ_BASE_OPCODE_MODIFY_QP UINT32_C(0x3) + /* Query QP command retrieves info about the specified QP. */ + #define CMDQ_BASE_OPCODE_QUERY_QP UINT32_C(0x4) + /* Create SRQ command allocates a SRQ with the specified parameters. */ + #define CMDQ_BASE_OPCODE_CREATE_SRQ UINT32_C(0x5) + /* Destroy SRQ command deletes and flushes the specified SRQ. */ + #define CMDQ_BASE_OPCODE_DESTROY_SRQ UINT32_C(0x6) + /* Query SRP command retrieves info about the specified SRQ. */ + #define CMDQ_BASE_OPCODE_QUERY_SRQ UINT32_C(0x8) + /* Create CQ command allocates a CQ with the specified parameters. */ + #define CMDQ_BASE_OPCODE_CREATE_CQ UINT32_C(0x9) + /* Destroy CQ command deletes and flushes the specified CQ. */ + #define CMDQ_BASE_OPCODE_DESTROY_CQ UINT32_C(0xa) + /* Resize CQ command resizes the specified CQ. */ + #define CMDQ_BASE_OPCODE_RESIZE_CQ UINT32_C(0xc) + /* + * Allocate MRW command allocates a MR/MW with the specified parameters + * and returns the region's L_KEY/R_KEY + */ + #define CMDQ_BASE_OPCODE_ALLOCATE_MRW UINT32_C(0xd) + /* + * De-allocate key command frees a MR/MW entry associated with the + * specified key. + */ + #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY UINT32_C(0xe) + /* Register MR command registers memory to the specified MR. */ + #define CMDQ_BASE_OPCODE_REGISTER_MR UINT32_C(0xf) + /* Deregister MR command de-registers memory from the specified MR. */ + #define CMDQ_BASE_OPCODE_DEREGISTER_MR UINT32_C(0x10) /* Add GID command adds a GID to the local address table. */ - #define CMDQ_ADD_GID_OPCODE_ADD_GID UINT32_C(0x11) - #define CMDQ_ADD_GID_OPCODE_LAST CMDQ_ADD_GID_OPCODE_ADD_GID + #define CMDQ_BASE_OPCODE_ADD_GID UINT32_C(0x11) + /* Delete GID command deletes a GID from the local address table. */ + #define CMDQ_BASE_OPCODE_DELETE_GID UINT32_C(0x12) + /* Modify GID command modifies a GID in the local address table. */ + #define CMDQ_BASE_OPCODE_MODIFY_GID UINT32_C(0x17) + /* Query GID command queries a GID in the local address table. */ + #define CMDQ_BASE_OPCODE_QUERY_GID UINT32_C(0x18) + /* Create QP1 command allocates a QP1 only. */ + #define CMDQ_BASE_OPCODE_CREATE_QP1 UINT32_C(0x13) + /* Destroy QP1 command deletes and flushes the specified QP1. */ + #define CMDQ_BASE_OPCODE_DESTROY_QP1 UINT32_C(0x14) + /* Create AH command allocates an AH with the specified parameters. */ + #define CMDQ_BASE_OPCODE_CREATE_AH UINT32_C(0x15) + /* Destroy AH command deletes the specified AH. */ + #define CMDQ_BASE_OPCODE_DESTROY_AH UINT32_C(0x16) + /* + * Initialize firmware command initializes the firmware with + * the specified parameters. + */ + #define CMDQ_BASE_OPCODE_INITIALIZE_FW UINT32_C(0x80) + /* De-initialize firmware command deinitializes the firmware. */ + #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW UINT32_C(0x81) + /* Stop the function */ + #define CMDQ_BASE_OPCODE_STOP_FUNC UINT32_C(0x82) + /* Query the HW capabilities for the function. */ + #define CMDQ_BASE_OPCODE_QUERY_FUNC UINT32_C(0x83) + /* + * Set the following resources for the function: + * - Max QP, CQ, MR+MW, SRQ per PF + * - Max QP, CQ, MR+MW, SRQ per VF + */ + #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84) + /* + * Read the current state of any internal resource context. Can only be + * issued from a PF. + */ + #define CMDQ_BASE_OPCODE_READ_CONTEXT UINT32_C(0x85) + /* + * Send a request from VF to pass a command to the PF. VF HSI is + * suspended until the PF returns the response + */ + #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86) + /* + * Read VF memory (primarily to get the backchannel request blob). Can + * only be issued from a PF. + */ + #define CMDQ_BASE_OPCODE_READ_VF_MEMORY UINT32_C(0x87) + /* + * Write VF memory (primarily to put the backchannel response blob), + * and reenable VF HSI (post a CAG completion to it). Can only be + * issued from a PF. + */ + #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88) + /* + * Deprecated. + * Extend resource (QPC, MRW, CQ, SRQ) array, after the host allocates + * more. Can only be issued from a PF. + */ + #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRAY_DEPRECATED UINT32_C(0x89) + /* Map TC to COS. Can only be issued from a PF. */ + #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a) + /* Query version. */ + #define CMDQ_BASE_OPCODE_QUERY_VERSION UINT32_C(0x8b) + /* Modify congestion control. Can only be issued from a PF. */ + #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c) + /* Query congestion control. */ + #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) + /* Query RoCE statistics. */ + #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e) + /* Set LAG mode. */ + #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE UINT32_C(0x8f) + /* Modify CQ */ + #define CMDQ_BASE_OPCODE_MODIFY_CQ UINT32_C(0x90) + /* + * Query QP for a PF other than the requesting PF. Also can query for + * more than one QP. + */ + #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) + /* Query extended RoCE statistics. */ + #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92) + /* + * This command updates the QP context id ranges on the PF, + * to orchestrate QP context id range migration. + * This command is valid for devices that + * support the pseudo-static QP allocation feature. + */ + #define CMDQ_BASE_OPCODE_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93) + /* + * This command allocates a batch of the requested count of QPs + * in a sequential range. + */ + #define CMDQ_BASE_OPCODE_CREATE_QP_BATCH UINT32_C(0x94) + /* + * This command deletes a batch of the requested count of QPs. + * The starting QP ID can be specified to request a batch deletion + * of a sequential range. + */ + #define CMDQ_BASE_OPCODE_DESTROY_QP_BATCH UINT32_C(0x95) + /* + * This command allocates an extended RoCE statistics context + * that supports periodic DMA to a host address. The extended + * statistics context id can be assigned by the driver + * via `create_qp`, `create_qp_batch`, or `modify_qp` to a specific QP, + * a subset of QPs or to all QPs of a specific function. + * These statistics can be queried via `query_roce_stats_ext_v2`. + */ + #define CMDQ_BASE_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96) + /* This command deallocates an extended RoCE statistics context. */ + #define CMDQ_BASE_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97) + /* + * This command queries extended RoCE statistics for context + * allocated via `allocate_roce_stats_ext_ctx`. + */ + #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98) + #define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT_V2 /* Size of the command in 16-byte units. */ uint8_t cmd_size; /* Flags and attribs of the command. */ @@ -66517,56 +69046,11 @@ uint8_t reserved8; /* Host address of the response. */ uint64_t resp_addr; - /* GID, specified in LE format. */ - uint32_t gid[4]; - /* Source MAC. */ - uint16_t src_mac[3]; - /* flags. */ - uint16_t vlan; - #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK UINT32_C(0xffff) - #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 - /* Source VLAN id. */ - #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff) - #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0 - /* This set of bits select the TPID of the VLAN Tag. */ - #define CMDQ_ADD_GID_VLAN_TPID_MASK UINT32_C(0x7000) - #define CMDQ_ADD_GID_VLAN_TPID_SFT 12 - /* TPID = 0x88A8. */ - #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12) - /* TPID = 0x8100. */ - #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12) - /* TPID = 0x9100. */ - #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12) - /* TPID = 0x9200. */ - #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12) - /* TPID = 0x9300. */ - #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12) - /* TPID = Configurable 1. */ - #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12) - /* TPID = Configurable 2. */ - #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12) - /* TPID = Configurable 3. */ - #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12) - #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 - /* Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE header. */ - #define CMDQ_ADD_GID_VLAN_VLAN_EN UINT32_C(0x8000) - /* Identifier field in the IP header. */ - uint16_t ipid; - /* Stats context ID to use with this SGID */ - uint16_t stats_ctx; - #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK UINT32_C(0xffff) - #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0 - /* stats_ctx_id is 15 b */ - #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff) - #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0 - /* Setting this bit to 1 enables use of own stats context ID instead of per-function */ - #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000) - uint32_t unused_0; -} cmdq_add_gid_t, *pcmdq_add_gid_t; +} cmdq_base_t, *pcmdq_base_t; -/* creq_add_gid_resp (size:128b/16B) */ +/* creq_base (size:128b/16B) */ -typedef struct creq_add_gid_resp { +typedef struct creq_base { uint8_t type; /* * This field indicates the exact type of the completion. @@ -66575,508 +69059,423 @@ * records. Odd values indicate 32B * records. */ - #define CREQ_ADD_GID_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_ADD_GID_RESP_TYPE_SFT 0 + #define CREQ_BASE_TYPE_MASK UINT32_C(0x3f) + #define CREQ_BASE_TYPE_SFT 0 /* QP Async Notification */ - #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_ADD_GID_RESP_TYPE_LAST CREQ_ADD_GID_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* GID index */ - uint32_t xid; + #define CREQ_BASE_TYPE_QP_EVENT UINT32_C(0x38) + /* Function Async Notification */ + #define CREQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a) + #define CREQ_BASE_TYPE_LAST CREQ_BASE_TYPE_FUNC_EVENT + uint8_t reserved56[7]; uint8_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define CREQ_ADD_GID_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ + #define CREQ_BASE_V UINT32_C(0x1) + /* This is the modifier on to the type field. */ uint8_t event; - /* Add GID command response. */ - #define CREQ_ADD_GID_RESP_EVENT_ADD_GID UINT32_C(0x11) - #define CREQ_ADD_GID_RESP_EVENT_LAST CREQ_ADD_GID_RESP_EVENT_ADD_GID uint8_t reserved48[6]; -} creq_add_gid_resp_t, *pcreq_add_gid_resp_t; - -/************** - * delete_gid * - **************/ - +} creq_base_t, *pcreq_base_t; -/* cmdq_delete_gid (size:192b/24B) */ +/* creq_resp_sb_hdr (size:64b/8B) */ -typedef struct cmdq_delete_gid { +typedef struct creq_resp_sb_hdr { /* Command opcode. */ uint8_t opcode; - /* Delete GID command deletes a GID from the local address table. */ - #define CMDQ_DELETE_GID_OPCODE_DELETE_GID UINT32_C(0x12) - #define CMDQ_DELETE_GID_OPCODE_LAST CMDQ_DELETE_GID_OPCODE_DELETE_GID - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; + /* Query QP command response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_QP UINT32_C(0x4) + /* Query SRQ command response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_SRQ UINT32_C(0x8) + /* Query GID command response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_GID UINT32_C(0x18) + /* Query info PF command response */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_FUNC UINT32_C(0x83) + /* Query version response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_VERSION UINT32_C(0x8b) + /* Query congestion control response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) + /* Query RoCE statistics response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e) + /* Query QP extended response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) + /* Query extended RoCE statistics response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92) + /* Query extended RoCE statistics v2 response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98) + #define CREQ_RESP_SB_HDR_OPCODE_LAST CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT_V2 + /* Status of the response. */ + uint8_t status; /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; /* Size of the response buffer in 16-byte units. */ uint8_t resp_size; uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* GID index */ - uint16_t gid_index; - uint8_t unused_0[6]; -} cmdq_delete_gid_t, *pcmdq_delete_gid_t; +} creq_resp_sb_hdr_t, *pcreq_resp_sb_hdr_t; -/* creq_delete_gid_resp (size:128b/16B) */ +/* + * Structure to be used for the qp_params array of + * the `create_qp_batch` command. + */ +/* create_qp_batch_data (size:768b/96B) */ -typedef struct creq_delete_gid_resp { - uint8_t type; +typedef struct create_qp_batch_data { + /* QP handle. */ + uint64_t qp_handle; + /* Create QP flags. */ + uint32_t qp_flags; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * SRQ is used. + * This flag is not supported on express mode QPs. */ - #define CREQ_DELETE_GID_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_DELETE_GID_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_DELETE_GID_RESP_TYPE_LAST CREQ_DELETE_GID_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* GID index */ - uint32_t xid; - uint8_t v; + #define CREATE_QP_BATCH_DATA_QP_FLAGS_SRQ_USED UINT32_C(0x1) + /* post CQE for all SQ WQEs. */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2) + /* This QP can use reserved L_Key */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4) + /* This QP can fast register physical memory */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_FR_PMR_ENABLED UINT32_C(0x8) + /* This QP can send variable sized WQEs. */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED UINT32_C(0x10) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * WQEs with inline data sent on this QP are able to flow + * through an optimized transmit path to lower latency. This + * transmit path is opportunistic and not guaranteed to always + * occur. */ - #define CREQ_DELETE_GID_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Delete GID command response. */ - #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID UINT32_C(0x12) - #define CREQ_DELETE_GID_RESP_EVENT_LAST CREQ_DELETE_GID_RESP_EVENT_DELETE_GID - uint8_t reserved48[6]; -} creq_delete_gid_resp_t, *pcreq_delete_gid_resp_t; - -/************** - * modify_gid * - **************/ - - -/* cmdq_modify_gid (size:384b/48B) */ - -typedef struct cmdq_modify_gid { - /* Command opcode. */ - uint8_t opcode; - /* Modify GID command modifies a GID in the local address table. */ - #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID UINT32_C(0x17) - #define CMDQ_MODIFY_GID_OPCODE_LAST CMDQ_MODIFY_GID_OPCODE_MODIFY_GID - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* GID */ - uint32_t gid[4]; - /* Source MAC. */ - uint16_t src_mac[3]; - /* flags. */ - uint16_t vlan; - /* Source VLAN id. */ - #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff) - #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0 - /* This set of bits select the TPID of the VLAN Tag. */ - #define CMDQ_MODIFY_GID_VLAN_TPID_MASK UINT32_C(0x7000) - #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12 - /* TPID = 0x88A8. */ - #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12) - /* TPID = 0x8100. */ - #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12) - /* TPID = 0x9100. */ - #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12) - /* TPID = 0x9200. */ - #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12) - /* TPID = 0x9300. */ - #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12) - /* TPID = Configurable 1. */ - #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12) - /* TPID = Configurable 2. */ - #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12) - /* TPID = Configurable 3. */ - #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12) - #define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 - /* Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE header. */ - #define CMDQ_MODIFY_GID_VLAN_VLAN_EN UINT32_C(0x8000) - /* Identifier field in the IP header. */ - uint16_t ipid; - /* GID index */ - uint16_t gid_index; - /* Stats context ID to use with this SGID */ - uint16_t stats_ctx; - /* stats_ctx_id is 15 b */ - #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff) - #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0 - /* Setting this bit to 1 enables use of own stats context ID instead of per-function */ - #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000) - uint16_t unused_0; -} cmdq_modify_gid_t, *pcmdq_modify_gid_t; - -/* creq_modify_gid_resp (size:128b/16B) */ - -typedef struct creq_modify_gid_resp { - uint8_t type; + #define CREATE_QP_BATCH_DATA_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x20) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * For UD QPs the default responder CQE format is `cq_res_ud`. + * This flag specifies the `cq_res_ud_cfa` format to be used + * instead. */ - #define CREQ_MODIFY_GID_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_MODIFY_GID_RESP_TYPE_LAST CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* GID index */ - uint32_t xid; - uint8_t v; + #define CREATE_QP_BATCH_DATA_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA UINT32_C(0x40) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This QP must be included in the extended RoCE statistics + * that can be queried via `query_roce_stats_ext`. */ - #define CREQ_MODIFY_GID_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Add GID command response. */ - #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID UINT32_C(0x11) - #define CREQ_MODIFY_GID_RESP_EVENT_LAST CREQ_MODIFY_GID_RESP_EVENT_ADD_GID - uint8_t reserved48[6]; -} creq_modify_gid_resp_t, *pcreq_modify_gid_resp_t; - -/************* - * query_gid * - *************/ - - -/* cmdq_query_gid (size:192b/24B) */ - -typedef struct cmdq_query_gid { - /* Command opcode. */ - uint8_t opcode; - /* Query GID command queries a GID in the local address table. */ - #define CMDQ_QUERY_GID_OPCODE_QUERY_GID UINT32_C(0x18) - #define CMDQ_QUERY_GID_OPCODE_LAST CMDQ_QUERY_GID_OPCODE_QUERY_GID - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* GID index */ - uint16_t gid_index; - /* unused16 is 16 b */ - uint8_t unused16[6]; -} cmdq_query_gid_t, *pcmdq_query_gid_t; - -/* creq_query_gid_resp (size:128b/16B) */ - -typedef struct creq_query_gid_resp { - uint8_t type; + #define CREATE_QP_BATCH_DATA_QP_FLAGS_EXT_STATS_ENABLED UINT32_C(0x80) + /* This QP uses express mode. */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_EXPRESS_MODE_ENABLED UINT32_C(0x100) + /* This QP uses the steering tag specified in the command. */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_STEERING_TAG_VALID UINT32_C(0x200) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This QP can be used for RDMA Read or Atomic operations. + * This value is used to optimize metadata memory allocation + * when the device supports `internal_queue_memory` feature. */ - #define CREQ_QUERY_GID_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_QUERY_GID_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_QUERY_GID_RESP_TYPE_LAST CREQ_QUERY_GID_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Side buffer size in 16-byte units */ - uint32_t size; - uint8_t v; + #define CREATE_QP_BATCH_DATA_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED UINT32_C(0x400) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This QP must be included in the extended RoCE statistics context + * specified in the field `ext_stats_ctx_id` */ - #define CREQ_QUERY_GID_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Query GID command response. */ - #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID UINT32_C(0x18) - #define CREQ_QUERY_GID_RESP_EVENT_LAST CREQ_QUERY_GID_RESP_EVENT_QUERY_GID - uint8_t reserved48[6]; -} creq_query_gid_resp_t, *pcreq_query_gid_resp_t; - -/* Query GID command response side buffer structure */ -/* creq_query_gid_resp_sb (size:320b/40B) */ - -typedef struct creq_query_gid_resp_sb { - /* Command opcode. */ - uint8_t opcode; - /* Query GID command response. */ - #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID UINT32_C(0x18) - #define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* GID */ - uint32_t gid[4]; - /* Source MAC. */ - uint16_t src_mac[3]; - /* flags. */ - uint16_t vlan; - #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK UINT32_C(0xffff) - #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 - /* Source VLAN id. */ - #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK UINT32_C(0xfff) - #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0 - /* This set of bits select the TPID of the VLAN Tag. */ - #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK UINT32_C(0x7000) - #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12 - /* TPID = 0x88A8. */ - #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12) - /* TPID = 0x8100. */ - #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12) - /* TPID = 0x9100. */ - #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12) - /* TPID = 0x9200. */ - #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12) - /* TPID = 0x9300. */ - #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12) - /* TPID = Configurable 1. */ - #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12) - /* TPID = Configurable 2. */ - #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12) - /* TPID = Configurable 3. */ - #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12) - #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 - /* Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE header. */ - #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN UINT32_C(0x8000) - /* Identifier field in the IP header. */ - uint16_t ipid; - /* GID index */ - uint16_t gid_index; - uint32_t unused_0; -} creq_query_gid_resp_sb_t, *pcreq_query_gid_resp_sb_t; - -/************** - * create_qp1 * - **************/ - - -/* cmdq_create_qp1 (size:640b/80B) */ - -typedef struct cmdq_create_qp1 { - /* Command opcode. */ - uint8_t opcode; - /* Create QP1 command allocates a QP1 only. */ - #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 UINT32_C(0x13) - #define CMDQ_CREATE_QP1_OPCODE_LAST CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* QP1 handle. */ - uint64_t qp_handle; - /* Create QP1 flags. */ - uint32_t qp_flags; - /* SRQ is used. */ - #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED UINT32_C(0x1) - /* post CQE for all SQ WQEs. */ - #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2) - /* This QP can use reserved L_Key */ - #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4) - #define CMDQ_CREATE_QP1_QP_FLAGS_LAST CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE - /* Supported QP1 types. */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_EXT_STATS_CTX_VALID UINT32_C(0x800) + /* The schq_id field passed in by the caller is valid. */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_SCHQ_ID_VALID UINT32_C(0x1000) + #define CREATE_QP_BATCH_DATA_QP_FLAGS_LAST CREATE_QP_BATCH_DATA_QP_FLAGS_SCHQ_ID_VALID + /* Supported QP types. */ uint8_t type; - /* General Services Interface on QP 1. */ - #define CMDQ_CREATE_QP1_TYPE_GSI UINT32_C(0x1) - #define CMDQ_CREATE_QP1_TYPE_LAST CMDQ_CREATE_QP1_TYPE_GSI + /* Reliable Connection. */ + #define CREATE_QP_BATCH_DATA_TYPE_RC UINT32_C(0x2) + /* Unreliable Datagram. */ + #define CREATE_QP_BATCH_DATA_TYPE_UD UINT32_C(0x4) + /* Raw Ethertype. */ + #define CREATE_QP_BATCH_DATA_TYPE_RAW_ETHERTYPE UINT32_C(0x6) + /* General Services Interface on QP1 over UD. */ + #define CREATE_QP_BATCH_DATA_TYPE_GSI UINT32_C(0x7) + #define CREATE_QP_BATCH_DATA_TYPE_LAST CREATE_QP_BATCH_DATA_TYPE_GSI uint8_t sq_pg_size_sq_lvl; - /* SQ PBL indirect levels. */ - #define CMDQ_CREATE_QP1_SQ_LVL_MASK UINT32_C(0xf) - #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0 + /* + * SQ PBL indirect levels. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_SQ_LVL_MASK UINT32_C(0xf) + #define CREATE_QP_BATCH_DATA_SQ_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 UINT32_C(0x0) + #define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2 - /* SQ page size. */ - #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK UINT32_C(0xf0) - #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4 + #define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_2 UINT32_C(0x2) + #define CREATE_QP_BATCH_DATA_SQ_LVL_LAST CREATE_QP_BATCH_DATA_SQ_LVL_LVL_2 + /* + * SQ page size. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_MASK UINT32_C(0xf0) + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_SFT 4 /* 4KB. */ - #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) /* 8KB. */ - #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) /* 64KB. */ - #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) /* 2MB. */ - #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) /* 8MB. */ - #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) /* 1GB. */ - #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define CMDQ_CREATE_QP1_SQ_PG_SIZE_LAST CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_LAST CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_1G uint8_t rq_pg_size_rq_lvl; - /* RQ PBL indirect levels. */ - #define CMDQ_CREATE_QP1_RQ_LVL_MASK UINT32_C(0xf) - #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0 + /* + * RQ PBL indirect levels. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_RQ_LVL_MASK UINT32_C(0xf) + #define CREATE_QP_BATCH_DATA_RQ_LVL_SFT 0 /* PBL pointer is physical start address. */ - #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 UINT32_C(0x0) + #define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ - #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 UINT32_C(0x2) - #define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2 - /* RQ page size. */ - #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK UINT32_C(0xf0) - #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4 + #define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_2 UINT32_C(0x2) + #define CREATE_QP_BATCH_DATA_RQ_LVL_LAST CREATE_QP_BATCH_DATA_RQ_LVL_LVL_2 + /* + * RQ page size. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_MASK UINT32_C(0xf0) + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_SFT 4 /* 4KB. */ - #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) /* 8KB. */ - #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) /* 64KB. */ - #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) /* 2MB. */ - #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) /* 8MB. */ - #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) /* 1GB. */ - #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) - #define CMDQ_CREATE_QP1_RQ_PG_SIZE_LAST CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_LAST CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_1G uint8_t unused_0; /* Doorbell page index. */ uint32_t dpi; - /* Max number of SQ wqes. */ + /* + * When the SQ is configured to use variable-size WQE, 'sq_size' + * denotes the SQ size with a unit of 16B. When the SQ is configured + * to use fixed-size WQE, 'sq_size' denotes the max number of SQ WQEs. + */ uint32_t sq_size; /* Max number of RQ wqes. */ uint32_t rq_size; uint16_t sq_fwo_sq_sge; - /* Max send SGEs per SWQE. */ - #define CMDQ_CREATE_QP1_SQ_SGE_MASK UINT32_C(0xf) - #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0 - /* Offset of First WQE in the first SQ page, in 128 byte units */ - #define CMDQ_CREATE_QP1_SQ_FWO_MASK UINT32_C(0xfff0) - #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4 + /* + * Max send SGEs per SWQE. This is only applicable to fixed-size + * WQE support. On variable-size WQE, this is ignored. + */ + #define CREATE_QP_BATCH_DATA_SQ_SGE_MASK UINT32_C(0xf) + #define CREATE_QP_BATCH_DATA_SQ_SGE_SFT 0 + /* + * Offset of First WQE in the first SQ page, in 128 byte units. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_SQ_FWO_MASK UINT32_C(0xfff0) + #define CREATE_QP_BATCH_DATA_SQ_FWO_SFT 4 uint16_t rq_fwo_rq_sge; - /* Max recv SGEs per RWQE (NOT SUPPORTED BY HARDWARE). */ - #define CMDQ_CREATE_QP1_RQ_SGE_MASK UINT32_C(0xf) - #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0 - /* Offset of First WQE in the first RQ page, in 128 byte units */ - #define CMDQ_CREATE_QP1_RQ_FWO_MASK UINT32_C(0xfff0) - #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4 + /* + * Max recv SGEs per RWQE. + * On chips with variable-size WQE support, a value of zero implies + * 30 SGEs. + */ + #define CREATE_QP_BATCH_DATA_RQ_SGE_MASK UINT32_C(0xf) + #define CREATE_QP_BATCH_DATA_RQ_SGE_SFT 0 + /* + * Offset of First WQE in the first RQ page, in 128 byte units. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_RQ_FWO_MASK UINT32_C(0xfff0) + #define CREATE_QP_BATCH_DATA_RQ_FWO_SFT 4 /* Send CQ context id. */ uint32_t scq_cid; /* Receive CQ context id. */ uint32_t rcq_cid; - /* SRQ CQ context id. */ + /* SRQ context id. */ uint32_t srq_cid; /* Protection domain id. */ uint32_t pd_id; - /* SQ PBL physical address. */ + /* + * SQ PBL physical address. + * This field is ignored for express mode QPs. + */ uint64_t sq_pbl; - /* RQ PBL physical address. */ + /* + * RQ PBL physical address. + * This field is ignored for express mode QPs. + */ uint64_t rq_pbl; -} cmdq_create_qp1_t, *pcmdq_create_qp1_t; + /* + * IRRQ address. This field is ignored on devices that + * support the `internal_queue_memory` feature. + */ + uint64_t irrq_addr; + /* + * ORRQ address. This field is ignored on devices that + * support the `internal_queue_memory` feature. + */ + uint64_t orrq_addr; + /* + * xid to use for the non-QP1 QP. + * The requested xid must be within the valid range + * of the predetermined assignment scheme of the + * pseudo static QP allocation feature. The valid range + * for the data QPs is determined by the start_qid and + * max_qp fields of query_func response. When the value is zero, + * firmware will automatically choose an xid from its free pool. + * QP1 allocation, indicated by specifying `type` field as gsi, + * must specify a request_xid as zero. + * This field is ignored on devices that do not support + * the pseudo static QP allocation feature. + */ + uint32_t request_xid; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + /* + * This value is used to optimize metadata memory allocation when + * the device supports `internal_queue_memory` feature. + * When the SQ is configured to use variable-size WQEs, the SQ size is + * only specified in units of 16 Bytes. This value hints the max number + * of WQEs that would ever be present on the SQ. + */ + uint16_t sq_max_num_wqes; + /* Extended RoCE statistics context id. */ + uint32_t ext_stats_ctx_id; + /* + * Identifies the new scheduling queue to associate with + * the RoCE QP. A value of zero indicates that the QP is being + * created with the default scheduling queue. Can only be specified + * by the PF driver. VFs get assigned a scheduling queue based on PF + * configuration (via HWRM_FUNC_CFG). Specified scheduling queue id is + * allocated by firmware (via HWRM_SCHQ_ALLOC) when the device supports + * the `scheduling queue` feature. + */ + uint16_t schq_id; + uint16_t reserved16; +} create_qp_batch_data_t, *pcreate_qp_batch_data_t; -/* creq_create_qp1_resp (size:128b/16B) */ +/* Periodic extended RoCE statistics context DMA to host. */ +/* roce_stats_ext_ctx (size:1856b/232B) */ -typedef struct creq_create_qp1_resp { - uint8_t type; +typedef struct roce_stats_ext_ctx { + /* Number of transmitted Atomic request packets without errors. */ + uint64_t tx_atomic_req_pkts; + /* Number of transmitted Read request packets without errors. */ + uint64_t tx_read_req_pkts; + /* Number of transmitted Read response packets without errors. */ + uint64_t tx_read_res_pkts; + /* Number of transmitted Write request packets without errors. */ + uint64_t tx_write_req_pkts; + /* Number of transmitted RC Send packets without errors. */ + uint64_t tx_rc_send_req_pkts; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Number of transmitted UD Send (including QP1) packets + * without errors. */ - #define CREQ_CREATE_QP1_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_CREATE_QP1_RESP_TYPE_LAST CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* QP1 context id */ - uint32_t xid; - uint8_t v; + uint64_t tx_ud_send_req_pkts; + /* Number of transmitted CNPs. Includes DCN_CNPs. */ + uint64_t tx_cnp_pkts; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Number of transmitted RoCE packets. + * This includes RC, UD, RawEth, and QP1 packets */ - #define CREQ_CREATE_QP1_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Create QP1 command response. */ - #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 UINT32_C(0x13) - #define CREQ_CREATE_QP1_RESP_EVENT_LAST CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 - uint8_t reserved48[6]; -} creq_create_qp1_resp_t, *pcreq_create_qp1_resp_t; + uint64_t tx_roce_pkts; + /* + * Number of transmitted RoCE header and payload bytes. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t tx_roce_bytes; + /* + * Number of drops that occurred to lack of buffers. + * This count includes RC sends, RC writes with immediate, + * UD sends, RawEth, and QP1 packets dropped due to lack of buffers. + */ + uint64_t rx_out_of_buffer_pkts; + /* Number of packets that were received out of sequence. */ + uint64_t rx_out_of_sequence_pkts; + /* + * Number of duplicate read/atomic requests resulting in responder + * hardware retransmission. + */ + uint64_t dup_req; + /* + * Number of missing response packets resulting in hardware + * retransmission. + */ + uint64_t missing_resp; + /* + * Number of sequence error NAKs received resulting in hardware + * retransmission. + */ + uint64_t seq_err_naks_rcvd; + /* Number of RNR NAKs received resulting in hardware retransmission. */ + uint64_t rnr_naks_rcvd; + /* Number of timeouts resulting in hardware retransmission. */ + uint64_t to_retransmits; + /* Number of received Atomic request packets without errors. */ + uint64_t rx_atomic_req_pkts; + /* Number of received Read request packets without errors. */ + uint64_t rx_read_req_pkts; + /* Number of received Read response packets without errors. */ + uint64_t rx_read_res_pkts; + /* Number of received Write request packets without errors. */ + uint64_t rx_write_req_pkts; + /* Number of received RC Send packets without errors. */ + uint64_t rx_rc_send_pkts; + /* Number of received UD Send packets without errors. */ + uint64_t rx_ud_send_pkts; + /* Number of received DCN payload cut packets. */ + uint64_t rx_dcn_payload_cut; + /* Number of received ECN-marked packets. */ + uint64_t rx_ecn_marked_pkts; + /* Number of received CNP packets. Includes DCN_CNPs. */ + uint64_t rx_cnp_pkts; + /* + * Number of received RoCE packets including RoCE packets with errors. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t rx_roce_pkts; + /* + * Number of received RoCE header and payload bytes including RoCE + * packets with errors. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t rx_roce_bytes; + /* + * Number of received RoCE packets without errors. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t rx_roce_good_pkts; + /* + * Number of received RoCE header and payload bytes without errors. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t rx_roce_good_bytes; +} roce_stats_ext_ctx_t, *proce_stats_ext_ctx_t; -/*************** - * destroy_qp1 * - ***************/ +/***************** + * query_version * + *****************/ -/* cmdq_destroy_qp1 (size:192b/24B) */ +/* cmdq_query_version (size:128b/16B) */ -typedef struct cmdq_destroy_qp1 { +typedef struct cmdq_query_version { /* Command opcode. */ uint8_t opcode; - /* Destroy QP1 command deletes and flushes the specified QP1. */ - #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 UINT32_C(0x14) - #define CMDQ_DESTROY_QP1_OPCODE_LAST CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 + /* Query version. */ + #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION UINT32_C(0x8b) + #define CMDQ_QUERY_VERSION_OPCODE_LAST CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION /* Size of the command in 16-byte units. */ uint8_t cmd_size; /* Flags and attribs of the command. */ @@ -67088,14 +69487,11 @@ uint8_t reserved8; /* Host address of the response. */ uint64_t resp_addr; - /* QP1 context id */ - uint32_t qp1_cid; - uint32_t unused_0; -} cmdq_destroy_qp1_t, *pcmdq_destroy_qp1_t; +} cmdq_query_version_t, *pcmdq_query_version_t; -/* creq_destroy_qp1_resp (size:128b/16B) */ +/* creq_query_version_resp (size:128b/16B) */ -typedef struct creq_destroy_qp1_resp { +typedef struct creq_query_version_resp { uint8_t type; /* * This field indicates the exact type of the completion. @@ -67104,49 +69500,85 @@ * records. Odd values indicate 32B * records. */ - #define CREQ_DESTROY_QP1_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0 + #define CREQ_QUERY_VERSION_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0 /* QP Async Notification */ - #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_DESTROY_QP1_RESP_TYPE_LAST CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT + #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QUERY_VERSION_RESP_TYPE_LAST CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT /* Status of the response. */ uint8_t status; /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; - /* QP1 context id */ - uint32_t xid; + /* firmware major version */ + uint8_t fw_maj; + /* firmware minor version */ + uint8_t fw_minor; + /* firmware build version */ + uint8_t fw_bld; + /* firmware reserved version */ + uint8_t fw_rsvd; uint8_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define CREQ_DESTROY_QP1_RESP_V UINT32_C(0x1) + #define CREQ_QUERY_VERSION_RESP_V UINT32_C(0x1) /* Event or command opcode. */ uint8_t event; - /* Destroy QP1 command response. */ - #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 UINT32_C(0x14) - #define CREQ_DESTROY_QP1_RESP_EVENT_LAST CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 - uint8_t reserved48[6]; -} creq_destroy_qp1_resp_t, *pcreq_destroy_qp1_resp_t; + /* Query firmware and interface version response. */ + #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION UINT32_C(0x8b) + #define CREQ_QUERY_VERSION_RESP_EVENT_LAST CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION + uint16_t reserved16; + /* interface major version */ + uint8_t intf_maj; + /* interface minor version */ + uint8_t intf_minor; + /* interface build version */ + uint8_t intf_bld; + /* interface reserved version */ + uint8_t intf_rsvd; +} creq_query_version_resp_t, *pcreq_query_version_resp_t; -/************* - * create_ah * - *************/ +/***************** + * initialize_fw * + *****************/ -/* cmdq_create_ah (size:512b/64B) */ +/* cmdq_initialize_fw (size:1024b/128B) */ -typedef struct cmdq_create_ah { +typedef struct cmdq_initialize_fw { /* Command opcode. */ uint8_t opcode; - /* Create AH command allocates an AH with the specified parameters. */ - #define CMDQ_CREATE_AH_OPCODE_CREATE_AH UINT32_C(0x15) - #define CMDQ_CREATE_AH_OPCODE_LAST CMDQ_CREATE_AH_OPCODE_CREATE_AH + /* + * Initialize firmware command initializes the firmware with + * the specified parameters. + */ + #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW UINT32_C(0x80) + #define CMDQ_INITIALIZE_FW_OPCODE_LAST CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW /* Size of the command in 16-byte units. */ uint8_t cmd_size; /* Flags and attribs of the command. */ uint16_t flags; + /* + * When set, the 32b `max_mrw_per_vf` field is logically divided + * into two 16b fields, `max_mr_per_vf` and `max_av_per_vf`. + */ + #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x1) + /* + * When set, the hardware based requester retransmission + * feature is supported. + */ + #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED UINT32_C(0x2) + /* When set, the driver version is provided. */ + #define CMDQ_INITIALIZE_FW_FLAGS_DRV_VERSION UINT32_C(0x4) + /* When set, driver supports optimizing Modify QP operation. */ + #define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED UINT32_C(0x8) + /* + * When set, the VF RoCE resources will be managed by the L2 + * driver via func_cfg. + */ + #define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT UINT32_C(0x10) /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; /* Size of the response buffer in 16-byte units. */ @@ -67154,45 +69586,322 @@ uint8_t reserved8; /* Host address of the response. */ uint64_t resp_addr; - /* AH handle. */ - uint64_t ah_handle; - /* Destination GID, specified in BE format. */ - uint32_t dgid[4]; - /* V1, V2IPv4 or V2IPv6. */ - uint8_t type; - /* V2IPv4. */ - #define CMDQ_CREATE_AH_TYPE_V1 UINT32_C(0x0) - /* V2IPv4. */ - #define CMDQ_CREATE_AH_TYPE_V2IPV4 UINT32_C(0x2) - /* V2IPv6. */ - #define CMDQ_CREATE_AH_TYPE_V2IPV6 UINT32_C(0x3) - #define CMDQ_CREATE_AH_TYPE_LAST CMDQ_CREATE_AH_TYPE_V2IPV6 - /* IPv6 Hop limit. */ - uint8_t hop_limit; - /* SGID index. */ - uint16_t sgid_index; - uint32_t dest_vlan_id_flow_label; - /* Flow label. */ - #define CMDQ_CREATE_AH_FLOW_LABEL_MASK UINT32_C(0xfffff) - #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0 - /* Destination VLAN ID. */ - #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK UINT32_C(0xfff00000) - #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20 - /* Protection domain id. */ - uint32_t pd_id; - uint32_t unused_0; - /* Destination MAC address. */ - uint16_t dest_mac[3]; - /* Traffic class. */ - uint8_t traffic_class; - uint8_t enable_cc; - /* Enable congestion control. */ - #define CMDQ_CREATE_AH_ENABLE_CC UINT32_C(0x1) -} cmdq_create_ah_t, *pcmdq_create_ah_t; + uint8_t qpc_pg_size_qpc_lvl; + /* QPC PBL indirect levels. */ + #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK UINT32_C(0xf) + #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 + /* QPC page size. */ + #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK UINT32_C(0xf0) + #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4 + /* 4KB. */ + #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G + uint8_t mrw_pg_size_mrw_lvl; + /* MRW PBL indirect levels. */ + #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK UINT32_C(0xf) + #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 + /* MRW page size. */ + #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK UINT32_C(0xf0) + #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4 + /* 4KB. */ + #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G + uint8_t srq_pg_size_srq_lvl; + /* SRQ PBL indirect levels. */ + #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK UINT32_C(0xf) + #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 + /* SRQ page size. */ + #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK UINT32_C(0xf0) + #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G + uint8_t cq_pg_size_cq_lvl; + /* CQ PBL indirect levels. */ + #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK UINT32_C(0xf) + #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 + /* CQ page size. */ + #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK UINT32_C(0xf0) + #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G + uint8_t tqm_pg_size_tqm_lvl; + /* TQM PBL indirect levels. */ + #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK UINT32_C(0xf) + #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 + /* TQM page size. */ + #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK UINT32_C(0xf0) + #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4 + /* 4KB. */ + #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G + uint8_t tim_pg_size_tim_lvl; + /* TIM PBL indirect levels. */ + #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK UINT32_C(0xf) + #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 + /* TIM page size. */ + #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK UINT32_C(0xf0) + #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4 + /* 4KB. */ + #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G + uint16_t log2_dbr_pg_size; + /* + * Log base 2 of DBR page size - 12. 0 for 4KB. HW supported values + * are enumerated below. + */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK UINT32_C(0xf) + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0 + /* 4KB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K UINT32_C(0x0) + /* 8KB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K UINT32_C(0x1) + /* 16KB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K UINT32_C(0x2) + /* 32KB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K UINT32_C(0x3) + /* 64KB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K UINT32_C(0x4) + /* 128KB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K UINT32_C(0x5) + /* 256KB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K UINT32_C(0x6) + /* 512KB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K UINT32_C(0x7) + /* 1MB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M UINT32_C(0x8) + /* 2MB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M UINT32_C(0x9) + /* 4MB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M UINT32_C(0xa) + /* 8MB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M UINT32_C(0xb) + /* 16MB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M UINT32_C(0xc) + /* 32MB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M UINT32_C(0xd) + /* 64MB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M UINT32_C(0xe) + /* 128MB. */ + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M UINT32_C(0xf) + #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M + /* rsvd is 12 b */ + #define CMDQ_INITIALIZE_FW_RSVD_MASK UINT32_C(0xfff0) + #define CMDQ_INITIALIZE_FW_RSVD_SFT 4 + /* Kernel notification queue page directory. */ + uint64_t qpc_page_dir; + /* MRW page directory. */ + uint64_t mrw_page_dir; + /* SRQ page directory. */ + uint64_t srq_page_dir; + /* CQ page directory. */ + uint64_t cq_page_dir; + /* TQM page directory. */ + uint64_t tqm_page_dir; + /* TIM page directory. */ + uint64_t tim_page_dir; + /* + * Number of QPs. This field is ignored when the backing store HWRM's + * are used. + */ + uint32_t number_of_qp; + /* + * Number of MRWs. This field is ignored when the backing store HWRM's + * are used. + */ + uint32_t number_of_mrw; + /* + * Number of SRQs. This field is ignored when the backing store HWRM's + * are used. + */ + uint32_t number_of_srq; + /* + * Number of CQs. This field is ignored when the backing store HWRM's + * are used. + */ + uint32_t number_of_cq; + /* + * Number of QPs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ + uint32_t max_qp_per_vf; + /* + * If the MR/AV split reservation flag is not set, then this field + * represents the total number of MR plus AV entries allowed per + * VF. For versions of firmware that support the split reservation, + * when it is not specified half of the entries will be reserved + * for MRs and the other half for AVs. + * + * If the MR/AV split reservation flag is set, then this + * field is logically divided into two 16b fields. Bits `[31:16]` + * represents the `max_mr_per_vf` and bits `[15:0]` represents + * `max_av_per_vf`. The granularity of these values is defined by + * the `mrav_num_entries_unit` field returned by the + * `backing_store_qcaps` command. + * + * This field must be set to zero when the flag, l2_vf_resource_mgmt, + * is set and RoCE SRIOV is enabled. + */ + uint32_t max_mrw_per_vf; + /* + * Number of SRQs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ + uint32_t max_srq_per_vf; + /* + * Number of CQs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ + uint32_t max_cq_per_vf; + /* + * Number of GIDs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ + uint32_t max_gid_per_vf; + /* Statistics context index for this function. */ + uint32_t stat_ctx_id; + /* The driver HSI major version number. */ + uint8_t drv_hsi_ver_maj; + /* The driver HSI minor version number. */ + uint8_t drv_hsi_ver_min; + /* The driver HSI update version number. */ + uint8_t drv_hsi_ver_upd; + /* This is the 40bit unused. */ + uint8_t unused40[5]; + /* The driver build major version number. */ + uint16_t drv_build_ver_maj; + /* The driver build minor version number. */ + uint16_t drv_build_ver_min; + /* The driver build update version number. */ + uint16_t drv_build_ver_upd; + /* The driver build patch version number. */ + uint16_t drv_build_ver_patch; +} cmdq_initialize_fw_t, *pcmdq_initialize_fw_t; -/* creq_create_ah_resp (size:128b/16B) */ +/* creq_initialize_fw_resp (size:128b/16B) */ -typedef struct creq_create_ah_resp { +typedef struct creq_initialize_fw_resp { uint8_t type; /* * This field indicates the exact type of the completion. @@ -67201,45 +69910,44 @@ * records. Odd values indicate 32B * records. */ - #define CREQ_CREATE_AH_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_CREATE_AH_RESP_TYPE_SFT 0 + #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0 /* QP Async Notification */ - #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_CREATE_AH_RESP_TYPE_LAST CREQ_CREATE_AH_RESP_TYPE_QP_EVENT + #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_INITIALIZE_FW_RESP_TYPE_LAST CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT /* Status of the response. */ uint8_t status; /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; - /* AH context id */ - uint32_t xid; + uint32_t reserved32; uint8_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define CREQ_CREATE_AH_RESP_V UINT32_C(0x1) + #define CREQ_INITIALIZE_FW_RESP_V UINT32_C(0x1) /* Event or command opcode. */ uint8_t event; - /* Create AH command response. */ - #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH UINT32_C(0x15) - #define CREQ_CREATE_AH_RESP_EVENT_LAST CREQ_CREATE_AH_RESP_EVENT_CREATE_AH + /* Initialize firmware command response. */ + #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW UINT32_C(0x80) + #define CREQ_INITIALIZE_FW_RESP_EVENT_LAST CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW uint8_t reserved48[6]; -} creq_create_ah_resp_t, *pcreq_create_ah_resp_t; +} creq_initialize_fw_resp_t, *pcreq_initialize_fw_resp_t; -/************** - * destroy_ah * - **************/ +/******************* + * deinitialize_fw * + *******************/ -/* cmdq_destroy_ah (size:192b/24B) */ +/* cmdq_deinitialize_fw (size:128b/16B) */ -typedef struct cmdq_destroy_ah { +typedef struct cmdq_deinitialize_fw { /* Command opcode. */ uint8_t opcode; - /* Destroy AH command deletes the specified AH. */ - #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH UINT32_C(0x16) - #define CMDQ_DESTROY_AH_OPCODE_LAST CMDQ_DESTROY_AH_OPCODE_DESTROY_AH + /* De-initialize firmware command deinitializes the firmware. */ + #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW UINT32_C(0x81) + #define CMDQ_DEINITIALIZE_FW_OPCODE_LAST CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW /* Size of the command in 16-byte units. */ uint8_t cmd_size; /* Flags and attribs of the command. */ @@ -67251,14 +69959,11 @@ uint8_t reserved8; /* Host address of the response. */ uint64_t resp_addr; - /* AH context id */ - uint32_t ah_cid; - uint32_t unused_0; -} cmdq_destroy_ah_t, *pcmdq_destroy_ah_t; +} cmdq_deinitialize_fw_t, *pcmdq_deinitialize_fw_t; -/* creq_destroy_ah_resp (size:128b/16B) */ +/* creq_deinitialize_fw_resp (size:128b/16B) */ -typedef struct creq_destroy_ah_resp { +typedef struct creq_deinitialize_fw_resp { uint8_t type; /* * This field indicates the exact type of the completion. @@ -67267,5460 +69972,15144 @@ * records. Odd values indicate 32B * records. */ - #define CREQ_DESTROY_AH_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0 + #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0 /* QP Async Notification */ - #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_DESTROY_AH_RESP_TYPE_LAST CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT + #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT /* Status of the response. */ uint8_t status; /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; - /* AH context id */ - uint32_t xid; + uint32_t reserved32; uint8_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define CREQ_DESTROY_AH_RESP_V UINT32_C(0x1) + #define CREQ_DEINITIALIZE_FW_RESP_V UINT32_C(0x1) /* Event or command opcode. */ uint8_t event; - /* Destroy AH command response. */ - #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH UINT32_C(0x16) - #define CREQ_DESTROY_AH_RESP_EVENT_LAST CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH + /* De-initialize firmware command response. */ + #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW UINT32_C(0x81) + #define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW uint8_t reserved48[6]; -} creq_destroy_ah_resp_t, *pcreq_destroy_ah_resp_t; +} creq_deinitialize_fw_resp_t, *pcreq_deinitialize_fw_resp_t; -/******************** - * query_roce_stats * - ********************/ +/************* + * create_qp * + *************/ -/* cmdq_query_roce_stats (size:192b/24B) */ +/* cmdq_create_qp (size:896b/112B) */ -typedef struct cmdq_query_roce_stats { +typedef struct cmdq_create_qp { /* Command opcode. */ uint8_t opcode; - /* Query RoCE statistics. */ - #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e) - #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS + /* + * Create QP command allocates QP context with the specified + * SQ, RQ/SRQ, CQ and other parameters. + */ + #define CMDQ_CREATE_QP_OPCODE_CREATE_QP UINT32_C(0x1) + #define CMDQ_CREATE_QP_OPCODE_LAST CMDQ_CREATE_QP_OPCODE_CREATE_QP /* Size of the command in 16-byte units. */ uint8_t cmd_size; /* Flags and attribs of the command. */ uint16_t flags; - /* - * When this bit is set FW will use the collection_id to extract RoCE statistics. - * If function_id is also specified the FW will return stats corresponding to the - * collection for the function_id specified. - */ - #define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID UINT32_C(0x1) - /* - * When this bit is set FW will use the function_id to extract RoCE statistics. - * When collection is specified then FW will return the specific collection - * stats and if the collection is not specified then FW will return the default - * stats which will be for all QPs. - */ - #define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID UINT32_C(0x2) /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; /* Size of the response buffer in 16-byte units. */ uint8_t resp_size; - /* The specific statistics group being queried. */ - uint8_t collection_id; + uint8_t reserved8; /* Host address of the response. */ uint64_t resp_addr; - /* Unique identifier for a function */ - uint32_t function_id; - /* PF number */ - #define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK UINT32_C(0xff) - #define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0 - /* VF number */ - #define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK UINT32_C(0xffff00) - #define CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT 8 - /* When set the vf_num is valid. */ - #define CMDQ_QUERY_ROCE_STATS_VF_VALID UINT32_C(0x1000000) - uint32_t reserved32; -} cmdq_query_roce_stats_t, *pcmdq_query_roce_stats_t; - -/* creq_query_roce_stats_resp (size:128b/16B) */ - -typedef struct creq_query_roce_stats_resp { - uint8_t type; - /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. - */ - #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Side buffer size in 16-byte units */ - uint32_t size; - uint8_t v; + /* QP handle. */ + uint64_t qp_handle; + /* Create QP flags. */ + uint32_t qp_flags; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * SRQ is used. + * This flag is not supported on express mode QPs. */ - #define CREQ_QUERY_ROCE_STATS_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Query RoCE statistics. */ - #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS UINT32_C(0x8e) - #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS - uint8_t reserved48[6]; -} creq_query_roce_stats_resp_t, *pcreq_query_roce_stats_resp_t; + #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED UINT32_C(0x1) + /* post CQE for all SQ WQEs. */ + #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2) + /* This QP can use reserved L_Key */ + #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4) + /* This QP can fast register physical memory */ + #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED UINT32_C(0x8) + /* This QP can send variable sized WQEs. */ + #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED UINT32_C(0x10) + /* + * WQEs with inline data sent on this QP are able to flow + * through an optimized transmit path to lower latency. This + * transmit path is opportunistic and not guaranteed to always + * occur. + */ + #define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x20) + /* + * For UD QPs the default responder CQE format is `cq_res_ud`. + * This flag specifies the `cq_res_ud_cfa` format to be used + * instead. + */ + #define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA UINT32_C(0x40) + /* + * This QP must be included in the extended RoCE statistics + * that can be queried via `query_roce_stats_ext`. + */ + #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED UINT32_C(0x80) + /* This QP uses express mode. */ + #define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED UINT32_C(0x100) + /* This QP uses the steering tag specified in the command. */ + #define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID UINT32_C(0x200) + /* + * This QP can be used for RDMA Read or Atomic operations. + * This value is used to optimize metadata memory allocation + * when the device supports `internal_queue_memory` feature. + */ + #define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED UINT32_C(0x400) + /* + * This QP must be included in the extended RoCE statistics context + * specified in the field `ext_stats_ctx_id` + */ + #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_CTX_VALID UINT32_C(0x800) + /* The schq_id field passed in by the caller is valid. */ + #define CMDQ_CREATE_QP_QP_FLAGS_SCHQ_ID_VALID UINT32_C(0x1000) + #define CMDQ_CREATE_QP_QP_FLAGS_LAST CMDQ_CREATE_QP_QP_FLAGS_SCHQ_ID_VALID + /* Supported QP types. */ + uint8_t type; + /* Reliable Connection. */ + #define CMDQ_CREATE_QP_TYPE_RC UINT32_C(0x2) + /* Unreliable Datagram. */ + #define CMDQ_CREATE_QP_TYPE_UD UINT32_C(0x4) + /* Raw Ethertype. */ + #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6) + /* General Services Interface on QP1 over UD. */ + #define CMDQ_CREATE_QP_TYPE_GSI UINT32_C(0x7) + #define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI + uint8_t sq_pg_size_sq_lvl; + /* + * SQ PBL indirect levels. + * This field is ignored for express mode QPs. + */ + #define CMDQ_CREATE_QP_SQ_LVL_MASK UINT32_C(0xf) + #define CMDQ_CREATE_QP_SQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2 + /* + * SQ page size. + * This field is ignored for express mode QPs. + */ + #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK UINT32_C(0xf0) + #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G + uint8_t rq_pg_size_rq_lvl; + /* + * RQ PBL indirect levels. + * This field is ignored for express mode QPs. + */ + #define CMDQ_CREATE_QP_RQ_LVL_MASK UINT32_C(0xf) + #define CMDQ_CREATE_QP_RQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2 + /* + * RQ page size. + * This field is ignored for express mode QPs. + */ + #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK UINT32_C(0xf0) + #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G + uint8_t unused_0; + /* Doorbell page index. */ + uint32_t dpi; + /* + * When the SQ is configured to use variable-size WQE, 'sq_size' + * denotes the SQ size with a unit of 16B. When the SQ is configured + * to use fixed-size WQE, 'sq_size' denotes the max number of SQ WQEs. + */ + uint32_t sq_size; + /* Max number of RQ wqes. */ + uint32_t rq_size; + uint16_t sq_fwo_sq_sge; + /* + * Max send SGEs per SWQE. This is only applicable to fixed-size + * WQE support. On variable-size WQE, this is ignored. + */ + #define CMDQ_CREATE_QP_SQ_SGE_MASK UINT32_C(0xf) + #define CMDQ_CREATE_QP_SQ_SGE_SFT 0 + /* + * Offset of First WQE in the first SQ page, in 128 byte units. + * This field is ignored for express mode QPs. + */ + #define CMDQ_CREATE_QP_SQ_FWO_MASK UINT32_C(0xfff0) + #define CMDQ_CREATE_QP_SQ_FWO_SFT 4 + uint16_t rq_fwo_rq_sge; + /* + * Max recv SGEs per RWQE. + * On chips with variable-size WQE support, a value of zero implies + * 30 SGEs. + */ + #define CMDQ_CREATE_QP_RQ_SGE_MASK UINT32_C(0xf) + #define CMDQ_CREATE_QP_RQ_SGE_SFT 0 + /* + * Offset of First WQE in the first RQ page, in 128 byte units. + * This field is ignored for express mode QPs. + */ + #define CMDQ_CREATE_QP_RQ_FWO_MASK UINT32_C(0xfff0) + #define CMDQ_CREATE_QP_RQ_FWO_SFT 4 + /* Send CQ context id. */ + uint32_t scq_cid; + /* Receive CQ context id. */ + uint32_t rcq_cid; + /* SRQ context id. */ + uint32_t srq_cid; + /* Protection domain id. */ + uint32_t pd_id; + /* + * SQ PBL physical address. + * This field is ignored for express mode QPs. + */ + uint64_t sq_pbl; + /* + * RQ PBL physical address. + * This field is ignored for express mode QPs. + */ + uint64_t rq_pbl; + /* + * IRRQ address. This field is ignored on devices that + * support the `internal_queue_memory` feature. + */ + uint64_t irrq_addr; + /* + * ORRQ address. This field is ignored on devices that + * support the `internal_queue_memory` feature. + */ + uint64_t orrq_addr; + /* + * xid to use for the non-QP1 QP. + * The requested xid must be within the valid range + * of the predetermined assignment scheme of the + * pseudo static QP allocation feature. The valid range + * for the data QPs is determined by the start_qid and + * max_qp fields of query_func response. When the value is zero, + * firmware will automatically choose an xid from its free pool. + * QP1 allocation, indicated by specifying `type` field as gsi, + * must specify a request_xid as zero. + * This field is ignored on devices that do not support + * the pseudo static QP allocation feature. + */ + uint32_t request_xid; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + /* + * This value is used to optimize metadata memory allocation when + * the device supports `internal_queue_memory` feature. + * When the SQ is configured to use variable-size WQEs, the SQ size is + * only specified in units of 16 Bytes. This value hints the max number + * of WQEs that would ever be present on the SQ. + */ + uint16_t sq_max_num_wqes; + /* Extended RoCE statistics context id. */ + uint32_t ext_stats_ctx_id; + /* + * Identifies the new scheduling queue to associate with + * the RoCE QP. A value of zero indicates that the QP is being + * created with the default scheduling queue. Can only be specified + * by the PF driver. VFs get assigned a scheduling queue based on PF + * configuration (via HWRM_FUNC_CFG). Specified scheduling queue id is + * allocated by firmware (via HWRM_SCHQ_ALLOC) when the device supports + * the `scheduling queue` feature. + */ + uint16_t schq_id; + uint16_t reserved16; +} cmdq_create_qp_t, *pcmdq_create_qp_t; -/* Query RoCE Stats command response side buffer structure. */ -/* creq_query_roce_stats_resp_sb (size:2944b/368B) */ +/* creq_create_qp_resp (size:128b/16B) */ -typedef struct creq_query_roce_stats_resp_sb { - /* Command opcode. */ - uint8_t opcode; - /* Query RoCE statistics. */ - #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e) - #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS +typedef struct creq_create_qp_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_CREATE_QP_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_CREATE_QP_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_CREATE_QP_RESP_TYPE_LAST CREQ_CREATE_QP_RESP_TYPE_QP_EVENT /* Status of the response. */ uint8_t status; /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; + /* QP context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_CREATE_QP_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Create QP command response. */ + #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP UINT32_C(0x1) + #define CREQ_CREATE_QP_RESP_EVENT_LAST CREQ_CREATE_QP_RESP_EVENT_CREATE_QP + /* + * Support for optimized transmit path to lower latency + * for WQEs with inline data has been enabled for this QP. + */ + uint8_t optimized_transmit_enabled; + uint8_t reserved48[5]; +} creq_create_qp_resp_t, *pcreq_create_qp_resp_t; + +/************** + * destroy_qp * + **************/ + + +/* cmdq_destroy_qp (size:192b/24B) */ + +typedef struct cmdq_destroy_qp { + /* Command opcode. */ + uint8_t opcode; + /* + * Destroy QP command deletes the QP context and ceases + * any further reference. + */ + #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP UINT32_C(0x2) + #define CMDQ_DESTROY_QP_OPCODE_LAST CMDQ_DESTROY_QP_OPCODE_DESTROY_QP + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; /* Flags and attribs of the command. */ uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; /* Size of the response buffer in 16-byte units. */ uint8_t resp_size; - uint8_t rsvd; - uint32_t num_counters; - uint32_t rsvd1; - uint64_t to_retransmits; - /* seq_err_naks_rcvd is 64 b */ - uint64_t seq_err_naks_rcvd; - /* max_retry_exceeded is 64 b */ - uint64_t max_retry_exceeded; - /* rnr_naks_rcvd is 64 b */ - uint64_t rnr_naks_rcvd; - uint64_t missing_resp; - /* unrecoverable_err is 64 b */ - uint64_t unrecoverable_err; - /* bad_resp_err is 64 b */ - uint64_t bad_resp_err; - /* local_qp_op_err is 64 b */ - uint64_t local_qp_op_err; - /* local_protection_err is 64 b */ - uint64_t local_protection_err; - /* mem_mgmt_op_err is 64 b */ - uint64_t mem_mgmt_op_err; - /* remote_invalid_req_err is 64 b */ - uint64_t remote_invalid_req_err; - /* remote_access_err is 64 b */ - uint64_t remote_access_err; - /* remote_op_err is 64 b */ - uint64_t remote_op_err; - /* dup_req is 64 b */ - uint64_t dup_req; - /* res_exceed_max is 64 b */ - uint64_t res_exceed_max; - /* res_length_mismatch is 64 b */ - uint64_t res_length_mismatch; - /* res_exceeds_wqe is 64 b */ - uint64_t res_exceeds_wqe; - /* res_opcode_err is 64 b */ - uint64_t res_opcode_err; - /* res_rx_invalid_rkey is 64 b */ - uint64_t res_rx_invalid_rkey; - /* res_rx_domain_err is 64 b */ - uint64_t res_rx_domain_err; - /* res_rx_no_perm is 64 b */ - uint64_t res_rx_no_perm; - /* res_rx_range_err is 64 b */ - uint64_t res_rx_range_err; - /* res_tx_invalid_rkey is 64 b */ - uint64_t res_tx_invalid_rkey; - /* res_tx_domain_err is 64 b */ - uint64_t res_tx_domain_err; - /* res_tx_no_perm is 64 b */ - uint64_t res_tx_no_perm; - /* res_tx_range_err is 64 b */ - uint64_t res_tx_range_err; - /* res_irrq_oflow is 64 b */ - uint64_t res_irrq_oflow; - /* res_unsup_opcode is 64 b */ - uint64_t res_unsup_opcode; - /* res_unaligned_atomic is 64 b */ - uint64_t res_unaligned_atomic; - /* res_rem_inv_err is 64 b */ - uint64_t res_rem_inv_err; - /* res_mem_error is 64 b */ - uint64_t res_mem_error; - /* res_srq_err is 64 b */ - uint64_t res_srq_err; - /* res_cmp_err is 64 b */ - uint64_t res_cmp_err; - /* res_invalid_dup_rkey is 64 b */ - uint64_t res_invalid_dup_rkey; - /* res_wqe_format_err is 64 b */ - uint64_t res_wqe_format_err; - /* res_cq_load_err is 64 b */ - uint64_t res_cq_load_err; - /* res_srq_load_err is 64 b */ - uint64_t res_srq_load_err; - /* res_tx_pci_err is 64 b */ - uint64_t res_tx_pci_err; - /* res_rx_pci_err is 64 b */ - uint64_t res_rx_pci_err; - /* res_oos_drop_count is 64 b */ - uint64_t res_oos_drop_count; - /* active_qp_count_p0 is 64 b */ - uint64_t active_qp_count_p0; - /* active_qp_count_p1 is 64 b */ - uint64_t active_qp_count_p1; - /* active_qp_count_p2 is 64 b */ - uint64_t active_qp_count_p2; - /* active_qp_count_p3 is 64 b */ - uint64_t active_qp_count_p3; -} creq_query_roce_stats_resp_sb_t, *pcreq_query_roce_stats_resp_sb_t; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* QP context id */ + uint32_t qp_cid; + uint32_t unused_0; +} cmdq_destroy_qp_t, *pcmdq_destroy_qp_t; -/************************ - * query_roce_stats_ext * - ************************/ +/* creq_destroy_qp_resp (size:128b/16B) */ + +typedef struct creq_destroy_qp_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DESTROY_QP_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DESTROY_QP_RESP_TYPE_LAST CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* QP context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DESTROY_QP_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Destroy QP command response. */ + #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP UINT32_C(0x2) + #define CREQ_DESTROY_QP_RESP_EVENT_LAST CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP + uint8_t reserved48[6]; +} creq_destroy_qp_resp_t, *pcreq_destroy_qp_resp_t; + +/************* + * modify_qp * + *************/ -/* cmdq_query_roce_stats_ext (size:192b/24B) */ +/* cmdq_modify_qp (size:1152b/144B) */ -typedef struct cmdq_query_roce_stats_ext { +typedef struct cmdq_modify_qp { /* Command opcode. */ uint8_t opcode; - /* Query extended RoCE statistics. */ - #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS UINT32_C(0x92) - #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS + /* + * Modify QP command changes QP states and other QP specific + * parameters. + */ + #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP UINT32_C(0x3) + #define CMDQ_MODIFY_QP_OPCODE_LAST CMDQ_MODIFY_QP_OPCODE_MODIFY_QP /* Size of the command in 16-byte units. */ uint8_t cmd_size; /* Flags and attribs of the command. */ uint16_t flags; /* - * When this bit is set FW will use the collection_id to extract RoCE statistics. - * If function_id is also specified the FW will return stats corresponding to the - * collection for the function_id specified. + * This field, used by firmware for optimizing Modify QP operation, + * must be set when the driver has indicated support for the + * optimize_modify_qp_supported feature in cmdq_initialize_fw and + * when QP Type RC is configured to use SRQ. + */ + #define CMDQ_MODIFY_QP_FLAGS_SRQ_USED UINT32_C(0x1) + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + /* + * This field, used by firmware for optimizing Modify QP operation, + * must be set when the driver has indicated support for the + * optimize_modify_qp_supported feature in cmdq_initialize_fw. + */ + uint8_t qp_type; + /* Reliable Connection. */ + #define CMDQ_MODIFY_QP_QP_TYPE_RC UINT32_C(0x2) + /* Unreliable Datagram. */ + #define CMDQ_MODIFY_QP_QP_TYPE_UD UINT32_C(0x4) + /* Raw Ethertype. */ + #define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6) + /* General Services Interface on QP1 over UD. */ + #define CMDQ_MODIFY_QP_QP_TYPE_GSI UINT32_C(0x7) + #define CMDQ_MODIFY_QP_QP_TYPE_LAST CMDQ_MODIFY_QP_QP_TYPE_GSI + /* Host address of the response. */ + uint64_t resp_addr; + /* Modify mask signifies the field that is requesting the change. */ + uint32_t modify_mask; + /* QP state change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE UINT32_C(0x1) + /* Enable SQ drain asynchronous notification change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY UINT32_C(0x2) + /* Access change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS UINT32_C(0x4) + /* P_KEY change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY UINT32_C(0x8) + /* Q_KEY index change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY UINT32_C(0x10) + /* Destination GID change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID UINT32_C(0x20) + /* Flow label change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL UINT32_C(0x40) + /* SGID change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX UINT32_C(0x80) + /* Hop limit change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT UINT32_C(0x100) + /* Traffic class change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS UINT32_C(0x200) + /* destination MAC change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC UINT32_C(0x400) + /* Ping pong push mode change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE UINT32_C(0x800) + /* Path MTU change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU UINT32_C(0x1000) + /* Timeout change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT UINT32_C(0x2000) + /* Retry count change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT UINT32_C(0x4000) + /* RNR Retry change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY UINT32_C(0x8000) + /* RQ start packet sequence number change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN UINT32_C(0x10000) + /* Max outstanding RDMA read atomic change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC UINT32_C(0x20000) + /* RNR minimum timer change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER UINT32_C(0x40000) + /* SQ start packet sequence number change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN UINT32_C(0x80000) + /* Max destination outstanding RDMA read atomic change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC UINT32_C(0x100000) + /* Max send WQE change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE UINT32_C(0x200000) + /* Max recv WQE change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE UINT32_C(0x400000) + /* Max recv SGEs per SWQE change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE UINT32_C(0x800000) + /* Max send SGEs per RWQE change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE UINT32_C(0x1000000) + /* Max inline data length change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA UINT32_C(0x2000000) + /* Destination QP id change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID UINT32_C(0x4000000) + /* Source MAC change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC UINT32_C(0x8000000) + /* Source VLAN id change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID UINT32_C(0x10000000) + /* Congestion control RoCE v2 change. */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC UINT32_C(0x20000000) + /* IP TOS ECN change */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN UINT32_C(0x40000000) + /* IP TOS DSCP change */ + #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP UINT32_C(0x80000000) + /* QP context id */ + uint32_t qp_cid; + uint8_t network_type_en_sqd_async_notify_new_state; + /* New QP state. */ + #define CMDQ_MODIFY_QP_NEW_STATE_MASK UINT32_C(0xf) + #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0 + /* Reset. */ + #define CMDQ_MODIFY_QP_NEW_STATE_RESET UINT32_C(0x0) + /* Init. */ + #define CMDQ_MODIFY_QP_NEW_STATE_INIT UINT32_C(0x1) + /* Ready To Receive. */ + #define CMDQ_MODIFY_QP_NEW_STATE_RTR UINT32_C(0x2) + /* Ready To Send. */ + #define CMDQ_MODIFY_QP_NEW_STATE_RTS UINT32_C(0x3) + /* SQ Drain. */ + #define CMDQ_MODIFY_QP_NEW_STATE_SQD UINT32_C(0x4) + /* SQ Error. */ + #define CMDQ_MODIFY_QP_NEW_STATE_SQE UINT32_C(0x5) + /* Error. */ + #define CMDQ_MODIFY_QP_NEW_STATE_ERR UINT32_C(0x6) + #define CMDQ_MODIFY_QP_NEW_STATE_LAST CMDQ_MODIFY_QP_NEW_STATE_ERR + /* Enable SQ drain asynchronous notification. */ + #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10) + /* unused1 is 1 b */ + #define CMDQ_MODIFY_QP_UNUSED1 UINT32_C(0x20) + /* network type. */ + #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK UINT32_C(0xc0) + #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6 + /* RoCEv1. */ + #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (UINT32_C(0x0) << 6) + /* RoCEv2 IPv4. */ + #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (UINT32_C(0x2) << 6) + /* RoCEv2 IPv6. */ + #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (UINT32_C(0x3) << 6) + #define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 + /* Access flags. */ + uint8_t access; + #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK UINT32_C(0xff) + #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0 + /* Local write access. */ + #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE UINT32_C(0x1) + /* Remote write access. */ + #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE UINT32_C(0x2) + /* Remote read access. */ + #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ UINT32_C(0x4) + /* + * Remote atomic access. Applicable to devices that support + * Atomic operations. + */ + #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC UINT32_C(0x8) + /* P_KEY. */ + uint16_t pkey; + /* Q_KEY. */ + uint32_t qkey; + /* Destination GID. */ + uint32_t dgid[4]; + /* Flow label. */ + uint32_t flow_label; + /* Source GID index. */ + uint16_t sgid_index; + /* Hop limit. */ + uint8_t hop_limit; + /* Traffic class. */ + uint8_t traffic_class; + /* Destination MAC address. */ + uint16_t dest_mac[3]; + uint8_t tos_dscp_tos_ecn; + /* IP TOS ECN. Valid values are 1 or 2 when ECN is enabled. */ + #define CMDQ_MODIFY_QP_TOS_ECN_MASK UINT32_C(0x3) + #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0 + /* IP TOS DSCP. */ + #define CMDQ_MODIFY_QP_TOS_DSCP_MASK UINT32_C(0xfc) + #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2 + uint8_t path_mtu_pingpong_push_enable; + /* + * Driver requests for ping pong push mode to be enabled for this + * QP. This request can be done only during modify from RST to INIT + * state. + */ + #define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE UINT32_C(0x1) + /* unused3 is 3 b */ + #define CMDQ_MODIFY_QP_UNUSED3_MASK UINT32_C(0xe) + #define CMDQ_MODIFY_QP_UNUSED3_SFT 1 + /* Path MTU. */ + #define CMDQ_MODIFY_QP_PATH_MTU_MASK UINT32_C(0xf0) + #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4 + /* 256. */ + #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (UINT32_C(0x0) << 4) + /* 512. */ + #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (UINT32_C(0x1) << 4) + /* 1024. */ + #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 4) + /* 2048. */ + #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 4) + /* 4096. */ + #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 4) + /* 8192. */ + #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 4) + #define CMDQ_MODIFY_QP_PATH_MTU_LAST CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 + /* Timeout value for SWQEs. */ + uint8_t timeout; + /* Max retry count for WQEs. */ + uint8_t retry_cnt; + /* Max RNR retry count for WQEs. */ + uint8_t rnr_retry; + /* Min RNR timer that the QP will report to the remote. */ + uint8_t min_rnr_timer; + /* RQ start packet sequence number. */ + uint32_t rq_psn; + /* SQ start packet sequence number. */ + uint32_t sq_psn; + /* Max outstanding RDMA read atomic. */ + uint8_t max_rd_atomic; + /* Max destination outstanding RDMA read atomic. */ + uint8_t max_dest_rd_atomic; + uint16_t enable_cc; + /* Enable congestion control. */ + #define CMDQ_MODIFY_QP_ENABLE_CC UINT32_C(0x1) + /* unused15 is 15 b */ + #define CMDQ_MODIFY_QP_UNUSED15_MASK UINT32_C(0xfffe) + #define CMDQ_MODIFY_QP_UNUSED15_SFT 1 + /* Max send WQE. */ + uint32_t sq_size; + /* Max recv WQE. */ + uint32_t rq_size; + /* Max send SGEs per SWQE. */ + uint16_t sq_sge; + /* Max recv SGEs per RWQE. */ + uint16_t rq_sge; + /* Max inline data length (up to 120 bytes). */ + uint32_t max_inline_data; + /* Destination QP id. */ + uint32_t dest_qp_id; + /* This is the DPI RoCE driver allocated for ping pong push. */ + uint32_t pingpong_push_dpi; + /* Source MAC. (Unused. Comes from Source GID index) */ + uint16_t src_mac[3]; + uint16_t vlan_pcp_vlan_dei_vlan_id; + /* VLAN id. (Unused. Comes from Source GID index) */ + #define CMDQ_MODIFY_QP_VLAN_ID_MASK UINT32_C(0xfff) + #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0 + /* VLAN DEI field - Drop Eligibility Indicator. */ + #define CMDQ_MODIFY_QP_VLAN_DEI UINT32_C(0x1000) + /* VLAN PCP field - Priority Code Point. */ + #define CMDQ_MODIFY_QP_VLAN_PCP_MASK UINT32_C(0xe000) + #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13 + /* IRRQ address. */ + uint64_t irrq_addr; + /* ORRQ address. */ + uint64_t orrq_addr; + /* + * Extended Modify mask signifies the field that is requesting the + * change. + */ + uint32_t ext_modify_mask; + /* Extended RoCE statistics context id change */ + #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX UINT32_C(0x1) + /* The schq_id field is valid */ + #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID UINT32_C(0x2) + /* Extended RoCE statistics context id. */ + uint32_t ext_stats_ctx_id; + /* + * Identifies the new scheduling queue to associate to the RoCE QP. + * A value of zero indicates that the QP is being modified to use + * the default scheduling queue. Specified scheduling queue id is + * allocated by firmware (via HWRM_SCHQ_ALLOC) when the device supports + * the `scheduling queue` feature. + */ + uint16_t schq_id; + /* unused_0 is 16 b */ + uint16_t unused_0; + /* reserved32 is 32 b */ + uint32_t reserved32; +} cmdq_modify_qp_t, *pcmdq_modify_qp_t; + +/* creq_modify_qp_resp (size:128b/16B) */ + +typedef struct creq_modify_qp_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_MODIFY_QP_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_MODIFY_QP_RESP_TYPE_LAST CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* QP context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_MODIFY_QP_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Modify QP command response. */ + #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP UINT32_C(0x3) + #define CREQ_MODIFY_QP_RESP_EVENT_LAST CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP + uint8_t pingpong_push_state_index_enabled; + /* + * When set it indicates that FW was able to successfully enable + * ping pong push mode for this QP. + */ + #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED UINT32_C(0x1) + /* + * When ping pong push mode is enabled this field will give the + * index into the push page where the QP has been mapped. + */ + #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK UINT32_C(0xe) + #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1 + /* + * This bit will tell whether to use ping or pong buffer + * for first push operation. 0 - ping buffer, 1 - pong buffer. + */ + #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE UINT32_C(0x10) + uint8_t reserved8; + /* Scrambled src mac needed to calculate UDP source port. */ + uint32_t lag_src_mac; +} creq_modify_qp_resp_t, *pcreq_modify_qp_resp_t; + +/************ + * query_qp * + ************/ + + +/* cmdq_query_qp (size:192b/24B) */ + +typedef struct cmdq_query_qp { + /* Command opcode. */ + uint8_t opcode; + /* Query QP command retrieves info about the specified QP. */ + #define CMDQ_QUERY_QP_OPCODE_QUERY_QP UINT32_C(0x4) + #define CMDQ_QUERY_QP_OPCODE_LAST CMDQ_QUERY_QP_OPCODE_QUERY_QP + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* QP context id */ + uint32_t qp_cid; + uint32_t unused_0; +} cmdq_query_qp_t, *pcmdq_query_qp_t; + +/* creq_query_qp_resp (size:128b/16B) */ + +typedef struct creq_query_qp_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QUERY_QP_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QUERY_QP_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QUERY_QP_RESP_TYPE_LAST CREQ_QUERY_QP_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Side buffer size in 16-byte units */ + uint32_t size; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QUERY_QP_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Query QP command response. */ + #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP UINT32_C(0x4) + #define CREQ_QUERY_QP_RESP_EVENT_LAST CREQ_QUERY_QP_RESP_EVENT_QUERY_QP + uint8_t reserved48[6]; +} creq_query_qp_resp_t, *pcreq_query_qp_resp_t; + +/* Query QP command response side buffer structure. */ +/* creq_query_qp_resp_sb (size:832b/104B) */ + +typedef struct creq_query_qp_resp_sb { + /* Command opcode. */ + uint8_t opcode; + /* Query QP command response. */ + #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP UINT32_C(0x4) + #define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* QP context id */ + uint32_t xid; + uint8_t en_sqd_async_notify_state; + /* QP state */ + #define CREQ_QUERY_QP_RESP_SB_STATE_MASK UINT32_C(0xf) + #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0 + /* Reset. */ + #define CREQ_QUERY_QP_RESP_SB_STATE_RESET UINT32_C(0x0) + /* Init. */ + #define CREQ_QUERY_QP_RESP_SB_STATE_INIT UINT32_C(0x1) + /* Ready To Receive. */ + #define CREQ_QUERY_QP_RESP_SB_STATE_RTR UINT32_C(0x2) + /* Ready To Send. */ + #define CREQ_QUERY_QP_RESP_SB_STATE_RTS UINT32_C(0x3) + /* SQ Drain. */ + #define CREQ_QUERY_QP_RESP_SB_STATE_SQD UINT32_C(0x4) + /* SQ Error. */ + #define CREQ_QUERY_QP_RESP_SB_STATE_SQE UINT32_C(0x5) + /* Error. */ + #define CREQ_QUERY_QP_RESP_SB_STATE_ERR UINT32_C(0x6) + #define CREQ_QUERY_QP_RESP_SB_STATE_LAST CREQ_QUERY_QP_RESP_SB_STATE_ERR + /* SQ drain asynchronous notification. */ + #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10) + /* Enable congestion control. */ + #define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK UINT32_C(0xe0) + #define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT 5 + /* Access flags. */ + uint8_t access; + #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK UINT32_C(0xff) + #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0 + /* Local write access. */ + #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE UINT32_C(0x1) + /* Remote write access. */ + #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE UINT32_C(0x2) + /* Remote read access. */ + #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ UINT32_C(0x4) + /* Remote atomic access. */ + #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC UINT32_C(0x8) + /* P_KEY index. */ + uint16_t pkey; + /* Q_KEY. */ + uint32_t qkey; + /* + * UDP source port used in RoCEv2 packets. Valid only when + * change_udp_src_port_wqe_supported feature is advertised. + */ + uint16_t udp_src_port; + uint16_t reserved16; + /* Destination GID. */ + uint32_t dgid[4]; + /* Flow label. */ + uint32_t flow_label; + /* Source GID index. */ + uint16_t sgid_index; + /* Hop limit. */ + uint8_t hop_limit; + /* Traffic class. */ + uint8_t traffic_class; + /* Destination MAC address. */ + uint16_t dest_mac[3]; + uint16_t path_mtu_dest_vlan_id; + /* Destination VLAN ID. */ + #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK UINT32_C(0xfff) + #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0 + /* Path MTU. */ + #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK UINT32_C(0xf000) + #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12 + /* 256. */ + #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (UINT32_C(0x0) << 12) + /* 512. */ + #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (UINT32_C(0x1) << 12) + /* 1024. */ + #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 12) + /* 2048. */ + #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 12) + /* 4096. */ + #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 12) + /* 8192. */ + #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 12) + #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 + /* Timeout value for SWQEs. */ + uint8_t timeout; + /* Max retry count for WQEs. */ + uint8_t retry_cnt; + /* Max RNR retry count for WQEs. */ + uint8_t rnr_retry; + /* Min RNR timer that the QP will report to the remote. */ + uint8_t min_rnr_timer; + /* RQ start packet sequence number. */ + uint32_t rq_psn; + /* SQ start packet sequence number. */ + uint32_t sq_psn; + /* Max outstanding RDMA read atomic. */ + uint8_t max_rd_atomic; + /* Max destination outstanding RDMA read atomic. */ + uint8_t max_dest_rd_atomic; + uint8_t tos_dscp_tos_ecn; + /* IP TOS ECN. */ + #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK UINT32_C(0x3) + #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0 + /* IP TOS DSCP. */ + #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc) + #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2 + uint8_t enable_cc; + /* enable_cc is 1 b */ + #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC UINT32_C(0x1) + /* Max send WQE. */ + uint32_t sq_size; + /* Max recv WQE. */ + uint32_t rq_size; + /* Max send SGEs per SWQE. */ + uint16_t sq_sge; + /* Max recv SGEs per RWQE (NOT SUPPORTED BY HARDWARE). */ + uint16_t rq_sge; + /* Max inline data length (up to 120 bytes). */ + uint32_t max_inline_data; + /* Destination QP id. */ + uint32_t dest_qp_id; + /* Port ID associated with the QP. */ + uint16_t port_id; + uint8_t unused_0; + /* Statistic collection ID allocated for this QP. */ + uint8_t stat_collection_id; + /* Source MAC. */ + uint16_t src_mac[3]; + uint16_t vlan_pcp_vlan_dei_vlan_id; + /* Source VLAN id. */ + #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK UINT32_C(0xfff) + #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0 + /* VLAN DEI field - Drop Eligibility Indicator. */ + #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI UINT32_C(0x1000) + /* VLAN PCP field - Priority Code Point. */ + #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK UINT32_C(0xe000) + #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13 +} creq_query_qp_resp_sb_t, *pcreq_query_qp_resp_sb_t; + +/******************* + * query_qp_extend * + *******************/ + + +/* cmdq_query_qp_extend (size:192b/24B) */ + +typedef struct cmdq_query_qp_extend { + /* Command opcode. */ + uint8_t opcode; + /* + * Query QP extend command retrieves info about multiple QPs + * associated with a specific PF. + */ + #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) + #define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + /* + * Number of QPs for which FW needs to query and provide info back to + * host. + */ + uint8_t num_qps; + /* Host address of the response. */ + uint64_t resp_addr; + /* Unique identified for a function */ + uint32_t function_id; + /* PF number */ + #define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK UINT32_C(0xff) + #define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0 + /* VF number */ + #define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK UINT32_C(0xffff00) + #define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT 8 + /* When set the vf_num is valid. */ + #define CMDQ_QUERY_QP_EXTEND_VF_VALID UINT32_C(0x1000000) + /* + * This is the current index where firmware left off for query qp. + * Driver will pass this back in the next query_qp_extend command. + */ + uint32_t current_index; +} cmdq_query_qp_extend_t, *pcmdq_query_qp_extend_t; + +/* creq_query_qp_extend_resp (size:128b/16B) */ + +typedef struct creq_query_qp_extend_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Side buffer size in 16-byte units */ + uint32_t size; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QUERY_QP_EXTEND_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Query QP extend command response. */ + #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND UINT32_C(0x91) + #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND + uint16_t reserved16; + /* + * This is the current index where firmware left off for query qp. + * Driver will pass this back in the next query_qp_extend command. + */ + uint32_t current_index; +} creq_query_qp_extend_resp_t, *pcreq_query_qp_extend_resp_t; + +/* Query QP extend command response side buffer structure. */ +/* creq_query_qp_extend_resp_sb (size:384b/48B) */ + +typedef struct creq_query_qp_extend_resp_sb { + /* Command opcode. */ + uint8_t opcode; + /* Query QP command extend response. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) + #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* QP context id */ + uint32_t xid; + uint8_t state; + /* QP state */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK UINT32_C(0xf) + #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0 + /* Reset. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET UINT32_C(0x0) + /* Init. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT UINT32_C(0x1) + /* Ready To Receive. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR UINT32_C(0x2) + /* Ready To Send. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS UINT32_C(0x3) + /* SQ Drain. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD UINT32_C(0x4) + /* SQ Error. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE UINT32_C(0x5) + /* Error. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR UINT32_C(0x6) + #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR + /* */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK UINT32_C(0xf0) + #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4 + uint8_t reserved_8; + /* Port ID associated with the QP. */ + uint16_t port_id; + /* Q_KEY. */ + uint32_t qkey; + /* Source GID index. */ + uint16_t sgid_index; + /* Network type. */ + uint8_t network_type; + /* RoCEv1. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 UINT32_C(0x0) + /* RoCEv2 IPv4. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 UINT32_C(0x2) + /* RoCEv2 IPv6. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 UINT32_C(0x3) + #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 + uint8_t unused_0; + /* Destination GID. */ + uint32_t dgid[4]; + /* Destination QP id. */ + uint32_t dest_qp_id; + /* Statistic collection ID allocated for this QP. */ + uint8_t stat_collection_id; + uint8_t reserved2_8; + uint16_t reserved_16; +} creq_query_qp_extend_resp_sb_t, *pcreq_query_qp_extend_resp_sb_t; + +/* + * TLV encapsulated Query QP extend control command response + * side buffer. + */ +/* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */ + +typedef struct creq_query_qp_extend_resp_sb_tlv { + /* + * The command discriminator is used to differentiate between various + * types of HWRM messages. This includes legacy HWRM and RoCE slowpath + * command messages as well as newer TLV encapsulated HWRM commands. + * + * For TLV encapsulated messages this field must be 0x8000. + */ + uint16_t cmd_discr; + uint8_t reserved_8b; + uint8_t tlv_flags; + /* + * Indicates the presence of additional TLV encapsulated data + * follows this TLV. + */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1) + /* Last TLV in a sequence of TLVs. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) + /* More TLVs follow this TLV. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + /* + * When an HWRM receiver detects a TLV type that it does not + * support with the TLV required flag set, the receiver must + * reject the HWRM message with an error code indicating an + * unsupported TLV type. + */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) + /* No */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) + /* Yes */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES + /* + * This field defines the TLV type value which is divided into + * two ranges to differentiate between global and local TLV types. + * Global TLV types must be unique across all defined TLV types. + * Local TLV types are valid only for extensions to a given + * HWRM message and may be repeated across different HWRM message + * types. There is a direct correlation of each HWRM message type + * to a single global TLV type value. + * + * Global TLV range: `0 - (63k-1)` + * + * Local TLV range: `63k - (64k-1)` + */ + uint16_t tlv_type; + /* + * Length of the message data encapsulated by this TLV in bytes. + * This length does not include the size of the TLV header itself + * and it must be an integer multiple of 8B. + */ + uint16_t length; + /* + * Size of the tlv encapsulated response, + * including all tlvs and extension data in 16-byte units. + */ + uint8_t total_size; + uint8_t reserved56[7]; + /* Command opcode. */ + uint8_t opcode; + /* Query QP command extend response. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* QP context id */ + uint32_t xid; + uint8_t state; + /* QP state */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK UINT32_C(0xf) + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0 + /* Reset. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET UINT32_C(0x0) + /* Init. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT UINT32_C(0x1) + /* Ready To Receive. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR UINT32_C(0x2) + /* Ready To Send. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS UINT32_C(0x3) + /* SQ Drain. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD UINT32_C(0x4) + /* SQ Error. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE UINT32_C(0x5) + /* Error. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR UINT32_C(0x6) + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR + /* */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK UINT32_C(0xf0) + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4 + uint8_t reserved_8; + /* Port ID associated with the QP. */ + uint16_t port_id; + /* Q_KEY. */ + uint32_t qkey; + /* Source GID index. */ + uint16_t sgid_index; + /* Network type. */ + uint8_t network_type; + /* RoCEv1. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 UINT32_C(0x0) + /* RoCEv2 IPv4. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 UINT32_C(0x2) + /* RoCEv2 IPv6. */ + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 UINT32_C(0x3) + #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 + uint8_t unused_0; + /* Destination GID. */ + uint32_t dgid[4]; + /* Destination QP id. */ + uint32_t dest_qp_id; + /* Statistic collection ID allocated for this QP. */ + uint8_t stat_collection_id; + uint8_t reserved2_8; + uint16_t reserved_16; +} creq_query_qp_extend_resp_sb_tlv_t, *pcreq_query_qp_extend_resp_sb_tlv_t; + +/************** + * create_srq * + **************/ + + +/* cmdq_create_srq (size:512b/64B) */ + +typedef struct cmdq_create_srq { + /* Command opcode. */ + uint8_t opcode; + /* Create SRQ command allocates a SRQ with the specified parameters. */ + #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ UINT32_C(0x5) + #define CMDQ_CREATE_SRQ_OPCODE_LAST CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* This SRQ uses the steering tag specified in the command. */ + #define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID UINT32_C(0x1) + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* SRQ handle. */ + uint64_t srq_handle; + uint16_t pg_size_lvl; + /* SRQ PBL indirect levels. */ + #define CMDQ_CREATE_SRQ_LVL_MASK UINT32_C(0x3) + #define CMDQ_CREATE_SRQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_CREATE_SRQ_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_CREATE_SRQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define CMDQ_CREATE_SRQ_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2 + /* page size. */ + #define CMDQ_CREATE_SRQ_PG_SIZE_MASK UINT32_C(0x1c) + #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2 + /* 4KB. */ + #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2) + /* 8KB. */ + #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2) + /* 64KB. */ + #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2) + /* 2MB. */ + #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2) + /* 8MB. */ + #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2) + /* 1GB. */ + #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2) + #define CMDQ_CREATE_SRQ_PG_SIZE_LAST CMDQ_CREATE_SRQ_PG_SIZE_PG_1G + /* unused11 is 11 b */ + #define CMDQ_CREATE_SRQ_UNUSED11_MASK UINT32_C(0xffe0) + #define CMDQ_CREATE_SRQ_UNUSED11_SFT 5 + uint16_t eventq_id; + /* eventq_id is 12 b */ + #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK UINT32_C(0xfff) + #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0 + /* unused4 is 4 b */ + #define CMDQ_CREATE_SRQ_UNUSED4_MASK UINT32_C(0xf000) + #define CMDQ_CREATE_SRQ_UNUSED4_SFT 12 + /* Max number of SRQ wqes. */ + uint16_t srq_size; + uint16_t srq_fwo; + /* Offset of first WQE in the first page of SRQ, in 128 byte units */ + #define CMDQ_CREATE_SRQ_SRQ_FWO_MASK UINT32_C(0xfff) + #define CMDQ_CREATE_SRQ_SRQ_FWO_SFT 0 + /* + * Max SGEs per SRQ WQE. This field is enabled if flag, + * create_srq_sge_supported, is set in query_func response. + */ + #define CMDQ_CREATE_SRQ_SRQ_SGE_MASK UINT32_C(0xf000) + #define CMDQ_CREATE_SRQ_SRQ_SGE_SFT 12 + /* Doorbell page index. */ + uint32_t dpi; + /* Protection domain id. */ + uint32_t pd_id; + /* RQ PBL physical address. */ + uint64_t pbl; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + uint8_t reserved48[6]; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_create_srq_t, *pcmdq_create_srq_t; + +/* creq_create_srq_resp (size:128b/16B) */ + +typedef struct creq_create_srq_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_CREATE_SRQ_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_CREATE_SRQ_RESP_TYPE_LAST CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* SRQ context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_CREATE_SRQ_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Create SRQ command response. */ + #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ UINT32_C(0x5) + #define CREQ_CREATE_SRQ_RESP_EVENT_LAST CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ + uint8_t reserved48[6]; +} creq_create_srq_resp_t, *pcreq_create_srq_resp_t; + +/*************** + * destroy_srq * + ***************/ + + +/* cmdq_destroy_srq (size:192b/24B) */ + +typedef struct cmdq_destroy_srq { + /* Command opcode. */ + uint8_t opcode; + /* Destroy SRQ command deletes and flushes the specified SRQ. */ + #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ UINT32_C(0x6) + #define CMDQ_DESTROY_SRQ_OPCODE_LAST CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* SRQ context id */ + uint32_t srq_cid; + uint32_t unused_0; +} cmdq_destroy_srq_t, *pcmdq_destroy_srq_t; + +/* creq_destroy_srq_resp (size:128b/16B) */ + +typedef struct creq_destroy_srq_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DESTROY_SRQ_RESP_TYPE_LAST CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* SRQ context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DESTROY_SRQ_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Destroy SRQ command response. */ + #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ UINT32_C(0x6) + #define CREQ_DESTROY_SRQ_RESP_EVENT_LAST CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ + uint16_t enable_for_arm[3]; + #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK UINT32_C(0xffff) + #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0 + /* + * Set to 1 if this SRQ is allowed to be armed for threshold async + * event + */ + #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK UINT32_C(0x30000) + #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16 +} creq_destroy_srq_resp_t, *pcreq_destroy_srq_resp_t; + +/************* + * query_srq * + *************/ + + +/* cmdq_query_srq (size:192b/24B) */ + +typedef struct cmdq_query_srq { + /* Command opcode. */ + uint8_t opcode; + /* Query SRP command retrieves info about the specified SRQ. */ + #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ UINT32_C(0x8) + #define CMDQ_QUERY_SRQ_OPCODE_LAST CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* SRQ context id */ + uint32_t srq_cid; + uint32_t unused_0; +} cmdq_query_srq_t, *pcmdq_query_srq_t; + +/* creq_query_srq_resp (size:128b/16B) */ + +typedef struct creq_query_srq_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QUERY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QUERY_SRQ_RESP_TYPE_LAST CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Side buffer size in 16-byte units */ + uint32_t size; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QUERY_SRQ_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Query SRQ command response. */ + #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ UINT32_C(0x8) + #define CREQ_QUERY_SRQ_RESP_EVENT_LAST CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ + uint8_t reserved48[6]; +} creq_query_srq_resp_t, *pcreq_query_srq_resp_t; + +/* Query SRQ command response side buffer structure. */ +/* creq_query_srq_resp_sb (size:256b/32B) */ + +typedef struct creq_query_srq_resp_sb { + /* Command opcode. */ + uint8_t opcode; + /* Query SRQ command response. */ + #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ UINT32_C(0x8) + #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* SRQ context id */ + uint32_t xid; + /* Watermark value to generate a SRQ limit event. */ + uint16_t srq_limit; + uint16_t reserved16; + /* data is 128 b */ + uint32_t data[4]; +} creq_query_srq_resp_sb_t, *pcreq_query_srq_resp_sb_t; + +/************* + * create_cq * + *************/ + + +/* cmdq_create_cq (size:512b/64B) */ + +typedef struct cmdq_create_cq { + /* Command opcode. */ + uint8_t opcode; + /* Create CQ command allocates a CQ with the specified parameters. */ + #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ UINT32_C(0x9) + #define CMDQ_CREATE_CQ_OPCODE_LAST CMDQ_CREATE_CQ_OPCODE_CREATE_CQ + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* + * When the HW Doorbell Drop Recovery feature is enabled, + * HW can flag false CQ overflow when CQ consumer index + * doorbells are dropped when there really wasn't any overflow. + * The CQE values could have already been processed by the driver, + * but HW doesn't know about this because of the doorbell drop. + * To avoid false detection of CQ overflow events, + * it is recommended that CQ overflow detection is disabled + * by the driver when HW based doorbell recovery is enabled. + */ + #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x1) + /* This CQ uses the steering tag specified in the command. */ + #define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID UINT32_C(0x2) + /* + * This CQ uses the infinite CQ mode. + * In the infinite CQ mode, all CQEs are written to the same + * address. Note that this mode implies a HW client is + * handling each entry instantly and avoiding overwrites. + * The following limitations apply when this mode is enabled: + * -cq_size field must be 1 + * -disable_cq_overflow_detection flag must be true. + * -the CQ will never be armed. + * -the consumer index of CQ will never be changed + */ + #define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE UINT32_C(0x4) + /* + * This CQ uses coalescing data specified in the command. + * This feature is not supported if infinite_cq_mode is also enabled. + */ + #define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID UINT32_C(0x8) + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* CQ handle. */ + uint64_t cq_handle; + uint32_t pg_size_lvl; + /* PBL indirect levels. */ + #define CMDQ_CREATE_CQ_LVL_MASK UINT32_C(0x3) + #define CMDQ_CREATE_CQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_CREATE_CQ_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_CREATE_CQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define CMDQ_CREATE_CQ_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2 + /* page size. */ + #define CMDQ_CREATE_CQ_PG_SIZE_MASK UINT32_C(0x1c) + #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2 + /* 4KB. */ + #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2) + /* 8KB. */ + #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2) + /* 64KB. */ + #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2) + /* 2MB. */ + #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2) + /* 8MB. */ + #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2) + /* 1GB. */ + #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2) + #define CMDQ_CREATE_CQ_PG_SIZE_LAST CMDQ_CREATE_CQ_PG_SIZE_PG_1G + /* unused27 is 27 b */ + #define CMDQ_CREATE_CQ_UNUSED27_MASK UINT32_C(0xffffffe0) + #define CMDQ_CREATE_CQ_UNUSED27_SFT 5 + uint32_t cq_fco_cnq_id; + /* cnq_id is 12 b */ + #define CMDQ_CREATE_CQ_CNQ_ID_MASK UINT32_C(0xfff) + #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0 + /* Offset of first CQE in the first Page, in 32 byte units */ + #define CMDQ_CREATE_CQ_CQ_FCO_MASK UINT32_C(0xfffff000) + #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12 + /* Doorbell page index. */ + uint32_t dpi; + /* Max number of CQ wqes. */ + uint32_t cq_size; + /* CQ PBL physical address. */ + uint64_t pbl; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + uint8_t reserved16[2]; + uint32_t coalescing; + /* + * Buffer Max time before flushing buffer (units of 1us). This + * specifies the maximum time before completion buffers are + * flushed out to host memory even if the number of coalesced + * buffers is less than the threshold. buf_maxtime is 9 bits. + */ + #define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK UINT32_C(0x1ff) + #define CMDQ_CREATE_CQ_BUF_MAXTIME_SFT 0 + /* + * This specifies the number of buffers coalesced before sending + * to memory during normal operation. Buffer unit is 16B + * completions. normal_maxbuf is 5 bits. + */ + #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_MASK UINT32_C(0x3e00) + #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_SFT 9 + /* + * This specifies the number of buffers coalesced before sending + * to memory when the interrupt is masked. Buffer unit is 16B + * completions. during_maxbuf is 5 bits. + */ + #define CMDQ_CREATE_CQ_DURING_MAXBUF_MASK UINT32_C(0x7c000) + #define CMDQ_CREATE_CQ_DURING_MAXBUF_SFT 14 + /* + * This field is used to enable ring for global idle mode interrupt + * generation. This mode will generate a notification (interrupt) + * if armed when only one completion has been generated if the chip + * is globally idle as determined by the device. + * enable_ring_idle_mode is 1 bit. + */ + #define CMDQ_CREATE_CQ_ENABLE_RING_IDLE_MODE UINT32_C(0x80000) + /* unused12 is 12 b */ + #define CMDQ_CREATE_CQ_UNUSED12_MASK UINT32_C(0xfff00000) + #define CMDQ_CREATE_CQ_UNUSED12_SFT 20 + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_create_cq_t, *pcmdq_create_cq_t; + +/* creq_create_cq_resp (size:128b/16B) */ + +typedef struct creq_create_cq_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_CREATE_CQ_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_CREATE_CQ_RESP_TYPE_LAST CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* CQ context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_CREATE_CQ_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Create CQ command response. */ + #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ UINT32_C(0x9) + #define CREQ_CREATE_CQ_RESP_EVENT_LAST CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ + uint8_t reserved48[6]; +} creq_create_cq_resp_t, *pcreq_create_cq_resp_t; + +/************** + * destroy_cq * + **************/ + + +/* cmdq_destroy_cq (size:192b/24B) */ + +typedef struct cmdq_destroy_cq { + /* Command opcode. */ + uint8_t opcode; + /* Destroy CQ command deletes and flushes the specified CQ. */ + #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ UINT32_C(0xa) + #define CMDQ_DESTROY_CQ_OPCODE_LAST CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* CQ context id */ + uint32_t cq_cid; + uint32_t unused_0; +} cmdq_destroy_cq_t, *pcmdq_destroy_cq_t; + +/* creq_destroy_cq_resp (size:128b/16B) */ + +typedef struct creq_destroy_cq_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DESTROY_CQ_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DESTROY_CQ_RESP_TYPE_LAST CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* CQ context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DESTROY_CQ_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Destroy CQ command response. */ + #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ UINT32_C(0xa) + #define CREQ_DESTROY_CQ_RESP_EVENT_LAST CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ + uint16_t cq_arm_lvl; + /* + * CQ ARM Level: + * 0 ? Not Armed + * 1 ? Arm SE Only, Generate CNQE only for incoming Solicited Events + * 2 ? Arm all, Generate CNQE for Rx and Tx + */ + #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK UINT32_C(0x3) + #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0 + /* + * The total number of CNQ events for the CQ, incremented on each CNQ + * event for the CQ (including firmware-generated CQ error + * notification). + */ + uint16_t total_cnq_events; + uint16_t reserved16; +} creq_destroy_cq_resp_t, *pcreq_destroy_cq_resp_t; + +/************* + * resize_cq * + *************/ + + +/* cmdq_resize_cq (size:320b/40B) */ + +typedef struct cmdq_resize_cq { + /* Command opcode. */ + uint8_t opcode; + /* Resize CQ command resizes the specified CQ. */ + #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ UINT32_C(0xc) + #define CMDQ_RESIZE_CQ_OPCODE_LAST CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* CQ context id */ + uint32_t cq_cid; + uint32_t new_cq_size_pg_size_lvl; + /* PBL indirect levels. */ + #define CMDQ_RESIZE_CQ_LVL_MASK UINT32_C(0x3) + #define CMDQ_RESIZE_CQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_RESIZE_CQ_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_RESIZE_CQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define CMDQ_RESIZE_CQ_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2 + /* page size. */ + #define CMDQ_RESIZE_CQ_PG_SIZE_MASK UINT32_C(0x1c) + #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2 + /* 4KB. */ + #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2) + /* 8KB. */ + #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2) + /* 64KB. */ + #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2) + /* 2MB. */ + #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2) + /* 8MB. */ + #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2) + /* 1GB. */ + #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2) + #define CMDQ_RESIZE_CQ_PG_SIZE_LAST CMDQ_RESIZE_CQ_PG_SIZE_PG_1G + /* New max number of CQ wqes. */ + #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK UINT32_C(0x1fffffe0) + #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5 + /* CQ PBL physical address. */ + uint64_t new_pbl; + /* Offset of first CQE in the first Page, in 32 byte units */ + uint32_t new_cq_fco; + uint32_t unused_0; +} cmdq_resize_cq_t, *pcmdq_resize_cq_t; + +/* creq_resize_cq_resp (size:128b/16B) */ + +typedef struct creq_resize_cq_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_RESIZE_CQ_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_RESIZE_CQ_RESP_TYPE_LAST CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* CQ context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_RESIZE_CQ_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Resize CQ command response. */ + #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ UINT32_C(0xc) + #define CREQ_RESIZE_CQ_RESP_EVENT_LAST CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ + uint8_t reserved48[6]; +} creq_resize_cq_resp_t, *pcreq_resize_cq_resp_t; + +/************* + * modify_cq * + *************/ + + +/* cmdq_modify_cq (size:512b/64B) */ + +typedef struct cmdq_modify_cq { + /* Command opcode. */ + uint8_t opcode; + /* Modify CQ updates specific params in the CQ context. */ + #define CMDQ_MODIFY_CQ_OPCODE_MODIFY_CQ UINT32_C(0x90) + #define CMDQ_MODIFY_CQ_OPCODE_LAST CMDQ_MODIFY_CQ_OPCODE_MODIFY_CQ + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* + * When the HW Doorbell Drop Recovery feature is enabled, + * HW can flag false CQ overflow when CQ consumer index + * doorbells are dropped when there really wasn't any overflow. + * The CQE values could have already been processed by the driver, + * but HW doesn't know about this because of the doorbell drop. + * To avoid false detection of CQ overflow events, + * it is recommended that CQ overflow detection is disabled + * by the driver when HW based doorbell recovery is enabled. + */ + #define CMDQ_MODIFY_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x1) + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Modify mask signifies the field that is requesting the change. */ + uint32_t modify_mask; + /* Enable change. */ + #define CMDQ_MODIFY_CQ_MODIFY_MASK_CQ_HANDLE UINT32_C(0x1) + /* CNQ ID */ + #define CMDQ_MODIFY_CQ_MODIFY_MASK_CNQ_ID UINT32_C(0x2) + /* Offset of first CQE in the first page, in 32 byte units */ + #define CMDQ_MODIFY_CQ_MODIFY_MASK_FCO UINT32_C(0x4) + /* Doorbell page index */ + #define CMDQ_MODIFY_CQ_MODIFY_MASK_DPI UINT32_C(0x8) + /* Max number of CQ Wqes */ + #define CMDQ_MODIFY_CQ_MODIFY_MASK_CQ_SIZE UINT32_C(0x10) + /* CQ PBL physical address */ + #define CMDQ_MODIFY_CQ_MODIFY_MASK_PBL UINT32_C(0x20) + /* reserved32 is 32 b */ + uint32_t reserved32; + /* CQ handle. */ + uint64_t cq_handle; + uint32_t cq_fco_cnq_id; + /* cnq_id is 12 b */ + #define CMDQ_MODIFY_CQ_CNQ_ID_MASK UINT32_C(0xfff) + #define CMDQ_MODIFY_CQ_CNQ_ID_SFT 0 + /* Offset of first CQE in the first Page, in 32 byte units */ + #define CMDQ_MODIFY_CQ_CQ_FCO_MASK UINT32_C(0xfffff000) + #define CMDQ_MODIFY_CQ_CQ_FCO_SFT 12 + /* Doorbell page index. */ + uint32_t dpi; + /* Max number of CQ wqes. */ + uint32_t cq_size; + /* reserved32_1 is 32 b */ + uint32_t reserved32_1; + /* CQ PBL physical address. */ + uint64_t pbl; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_modify_cq_t, *pcmdq_modify_cq_t; + +/* creq_modify_cq_resp (size:128b/16B) */ + +typedef struct creq_modify_cq_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_MODIFY_CQ_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_MODIFY_CQ_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_MODIFY_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_MODIFY_CQ_RESP_TYPE_LAST CREQ_MODIFY_CQ_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* CQ context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_MODIFY_CQ_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Modify CQ command response. */ + #define CREQ_MODIFY_CQ_RESP_EVENT_MODIFY_CQ UINT32_C(0x9) + #define CREQ_MODIFY_CQ_RESP_EVENT_LAST CREQ_MODIFY_CQ_RESP_EVENT_MODIFY_CQ + uint8_t reserved48[6]; +} creq_modify_cq_resp_t, *pcreq_modify_cq_resp_t; + +/**************** + * allocate_mrw * + ****************/ + + +/* cmdq_allocate_mrw (size:256b/32B) */ + +typedef struct cmdq_allocate_mrw { + /* Command opcode. */ + uint8_t opcode; + /* + * Allocate MRW command allocates a MR/MW with the specified + * parameters and returns the region's L_KEY/R_KEY + */ + #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW UINT32_C(0xd) + #define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* MRW handle. */ + uint64_t mrw_handle; + uint8_t mrw_flags; + /* Allocate MRW flags. */ + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK UINT32_C(0xf) + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0 + /* Allocate Memory Region */ + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR UINT32_C(0x0) + /* Allocate Physical Memory Region */ + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR UINT32_C(0x1) + /* Allocate Memory Window (type 1) */ + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2) + /* Allocate Memory Window (type 2A) */ + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3) + /* Allocate Memory Window (type 2B) */ + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4) + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B + /* + * This Memory Region / Memory Window uses the + * steering tag specified in the command. + */ + #define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID UINT32_C(0x10) + /* unused3 is 3 b */ + #define CMDQ_ALLOCATE_MRW_UNUSED3_MASK UINT32_C(0xe0) + #define CMDQ_ALLOCATE_MRW_UNUSED3_SFT 5 + /* Access flags. */ + uint8_t access; + /* Consumer owns the key */ + #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY UINT32_C(0x20) + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + /* Protection domain id. */ + uint32_t pd_id; +} cmdq_allocate_mrw_t, *pcmdq_allocate_mrw_t; + +/* creq_allocate_mrw_resp (size:128b/16B) */ + +typedef struct creq_allocate_mrw_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* L_KEY for MR, R_KEY for MW */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_ALLOCATE_MRW_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Allocate MRW command response. */ + #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW UINT32_C(0xd) + #define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW + uint8_t reserved48[6]; +} creq_allocate_mrw_resp_t, *pcreq_allocate_mrw_resp_t; + +/****************** + * deallocate_key * + ******************/ + + +/* cmdq_deallocate_key (size:192b/24B) */ + +typedef struct cmdq_deallocate_key { + /* Command opcode. */ + uint8_t opcode; + /* + * De-allocate key command frees a MR/MW entry associated with the + * specified key. + */ + #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY UINT32_C(0xe) + #define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + uint8_t mrw_flags; + /* Deallocate MRW flags. */ + #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK UINT32_C(0xf) + #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0 + /* Deallocate Memory Region */ + #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR UINT32_C(0x0) + /* Deallocate Physical Memory Region */ + #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR UINT32_C(0x1) + /* Deallocate Memory Window (type 1) */ + #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2) + /* Deallocate Memory Window (type 2A) */ + #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3) + /* Deallocate Memory Window (type 2B) */ + #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4) + #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B + /* unused4 is 4 b */ + #define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK UINT32_C(0xf0) + #define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT 4 + /* unused24 is 24 b */ + uint8_t unused24[3]; + /* key is 32 b */ + uint32_t key; +} cmdq_deallocate_key_t, *pcmdq_deallocate_key_t; + +/* creq_deallocate_key_resp (size:128b/16B) */ + +typedef struct creq_deallocate_key_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* L_KEY for MR, R_KEY for MW */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DEALLOCATE_KEY_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* De-allocate key command response. */ + #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY UINT32_C(0xe) + #define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY + uint16_t reserved16; + /* + * This is advisory data to facilitate eventual destruction of + * lingering memory regions in Windows. For memory window, it contains + * non-zero HWID of a region this window was bound to (without the + * 8-bit key portion). The host may check if the region is lingering in + * destroyed state and try to destroy it now. For memory region, if + * deallocation fails because there are windows bound to this region, + * this field will contain approximate number of those windows. This + * number is read from the context right before the deregistration is + * attempted and can potentially be slightly different from the current + * number. + */ + uint32_t bound_window_info; +} creq_deallocate_key_resp_t, *pcreq_deallocate_key_resp_t; + +/*************** + * register_mr * + ***************/ + + +/* cmdq_register_mr (size:512b/64B) */ + +typedef struct cmdq_register_mr { + /* Command opcode. */ + uint8_t opcode; + /* Register MR command registers memory to the specified MR. */ + #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR UINT32_C(0xf) + #define CMDQ_REGISTER_MR_OPCODE_LAST CMDQ_REGISTER_MR_OPCODE_REGISTER_MR + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* + * When set, a new MR will be allocated first and then registered + * using the fields in this command. Note that for MR allocation + * the `key` field doesn't hold a valid L_KEY and is instead + * overloaded to hold the Protection Domain ID `pd_id`. + */ + #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR UINT32_C(0x1) + /* + * This MR uses the steering tag specified in the command. + * This flag can only be enabled when the command is used + * to allocate a new MR first. + */ + #define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID UINT32_C(0x2) + /* When set, enable per MR relaxed ordering support. */ + #define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO UINT32_C(0x4) + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + uint8_t log2_pg_size_lvl; + /* PBL indirect levels. */ + #define CMDQ_REGISTER_MR_LVL_MASK UINT32_C(0x3) + #define CMDQ_REGISTER_MR_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_REGISTER_MR_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_REGISTER_MR_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define CMDQ_REGISTER_MR_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2 + /* + * Log base 2 of page size; 12 is the minimum for 4KB. HW supported + * values are enumerated below. + */ + #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK UINT32_C(0x7c) + #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2 + /* 4KB. */ + #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (UINT32_C(0xc) << 2) + /* 8KB. */ + #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (UINT32_C(0xd) << 2) + /* 64KB. */ + #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (UINT32_C(0x10) << 2) + /* 256KB. */ + #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (UINT32_C(0x12) << 2) + /* 1MB. */ + #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (UINT32_C(0x14) << 2) + /* 2MB. */ + #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (UINT32_C(0x15) << 2) + /* 4MB. */ + #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (UINT32_C(0x16) << 2) + /* 1GB. */ + #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (UINT32_C(0x1e) << 2) + #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G + /* unused1 is 1 b */ + #define CMDQ_REGISTER_MR_UNUSED1 UINT32_C(0x80) + /* Access flags. */ + uint8_t access; + /* Local write access. */ + #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE UINT32_C(0x1) + /* Remote read access. */ + #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ UINT32_C(0x2) + /* Remote write access. */ + #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE UINT32_C(0x4) + /* Remote atomic access. */ + #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC UINT32_C(0x8) + /* Bind access allowed. */ + #define CMDQ_REGISTER_MR_ACCESS_MW_BIND UINT32_C(0x10) + /* Indicate Zero Based Virtual Address (ZBVA). */ + #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED UINT32_C(0x20) + uint16_t log2_pbl_pg_size; + /* + * Log base 2 of PBL page size; 12 is the minimum for 4KB. HW + * supported values are enumerated below + */ + #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK UINT32_C(0x1f) + #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0 + /* 4KB. */ + #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K UINT32_C(0xc) + /* 8KB. */ + #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K UINT32_C(0xd) + /* 64KB. */ + #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K UINT32_C(0x10) + /* 256KB. */ + #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K UINT32_C(0x12) + /* 1MB. */ + #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M UINT32_C(0x14) + /* 2MB. */ + #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M UINT32_C(0x15) + /* 4MB. */ + #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M UINT32_C(0x16) + /* 1GB. */ + #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G UINT32_C(0x1e) + #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G + /* unused11 is 11 b */ + #define CMDQ_REGISTER_MR_UNUSED11_MASK UINT32_C(0xffe0) + #define CMDQ_REGISTER_MR_UNUSED11_SFT 5 + /* + * L_KEY of the previously allocated MR. + * + * If the `ALLOC_MR` flag is set then this field does not hold an + * L_KEY and instead contains the Protection Domain ID `pd_id`. + */ + uint32_t key; + /* Page table of the MR memory. */ + uint64_t pbl; + /* Virtual address of the MR. */ + uint64_t va; + /* Size of the MR. */ + uint64_t mr_size; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + uint8_t reserved48[6]; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_register_mr_t, *pcmdq_register_mr_t; + +/* creq_register_mr_resp (size:128b/16B) */ + +typedef struct creq_register_mr_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_REGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_REGISTER_MR_RESP_TYPE_LAST CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* L_KEY */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_REGISTER_MR_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Register MR command response. */ + #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR UINT32_C(0xf) + #define CREQ_REGISTER_MR_RESP_EVENT_LAST CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR + uint8_t reserved48[6]; +} creq_register_mr_resp_t, *pcreq_register_mr_resp_t; + +/***************** + * deregister_mr * + *****************/ + + +/* cmdq_deregister_mr (size:192b/24B) */ + +typedef struct cmdq_deregister_mr { + /* Command opcode. */ + uint8_t opcode; + /* Deregister MR command de-registers memory from the specified MR. */ + #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR UINT32_C(0x10) + #define CMDQ_DEREGISTER_MR_OPCODE_LAST CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* L_KEY of the MR. */ + uint32_t lkey; + uint32_t unused_0; +} cmdq_deregister_mr_t, *pcmdq_deregister_mr_t; + +/* creq_deregister_mr_resp (size:128b/16B) */ + +typedef struct creq_deregister_mr_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DEREGISTER_MR_RESP_TYPE_LAST CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* L_KEY */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DEREGISTER_MR_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Deregister MR command response. */ + #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR UINT32_C(0x10) + #define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR + uint16_t reserved16; + /* + * If deregister fails because there are windows bound to this region, + * this field will contain approximate number of those windows. This + * number is read from the context right before the deregistration is + * attempted and can potentially be slightly different from the current + * number. + */ + uint32_t bound_windows; +} creq_deregister_mr_resp_t, *pcreq_deregister_mr_resp_t; + +/*********** + * add_gid * + ***********/ + + +/* cmdq_add_gid (size:384b/48B) */ + +typedef struct cmdq_add_gid { + /* Command opcode. */ + uint8_t opcode; + /* Add GID command adds a GID to the local address table. */ + #define CMDQ_ADD_GID_OPCODE_ADD_GID UINT32_C(0x11) + #define CMDQ_ADD_GID_OPCODE_LAST CMDQ_ADD_GID_OPCODE_ADD_GID + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* GID, specified in LE format. */ + uint32_t gid[4]; + /* Source MAC. */ + uint16_t src_mac[3]; + /* flags. */ + uint16_t vlan; + #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK UINT32_C(0xffff) + #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 + /* Source VLAN id. */ + #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff) + #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0 + /* This set of bits select the TPID of the VLAN Tag. */ + #define CMDQ_ADD_GID_VLAN_TPID_MASK UINT32_C(0x7000) + #define CMDQ_ADD_GID_VLAN_TPID_SFT 12 + /* TPID = 0x88A8. */ + #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12) + /* TPID = 0x8100. */ + #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12) + /* TPID = 0x9100. */ + #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12) + /* TPID = 0x9200. */ + #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12) + /* TPID = 0x9300. */ + #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12) + /* TPID = Configurable 1. */ + #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12) + /* TPID = Configurable 2. */ + #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12) + /* TPID = Configurable 3. */ + #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12) + #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 + /* + * Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE + * header. + */ + #define CMDQ_ADD_GID_VLAN_VLAN_EN UINT32_C(0x8000) + /* Identifier field in the IP header. */ + uint16_t ipid; + /* Stats context ID to use with this SGID */ + uint16_t stats_ctx; + #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK UINT32_C(0xffff) + #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0 + /* stats_ctx_id is 15 b */ + #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff) + #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0 + /* + * Setting this bit to 1 enables use of own stats context ID + * instead of per-function. + */ + #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000) + uint32_t unused_0; +} cmdq_add_gid_t, *pcmdq_add_gid_t; + +/* creq_add_gid_resp (size:128b/16B) */ + +typedef struct creq_add_gid_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_ADD_GID_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_ADD_GID_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_ADD_GID_RESP_TYPE_LAST CREQ_ADD_GID_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* GID index */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_ADD_GID_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Add GID command response. */ + #define CREQ_ADD_GID_RESP_EVENT_ADD_GID UINT32_C(0x11) + #define CREQ_ADD_GID_RESP_EVENT_LAST CREQ_ADD_GID_RESP_EVENT_ADD_GID + uint8_t reserved48[6]; +} creq_add_gid_resp_t, *pcreq_add_gid_resp_t; + +/************** + * delete_gid * + **************/ + + +/* cmdq_delete_gid (size:192b/24B) */ + +typedef struct cmdq_delete_gid { + /* Command opcode. */ + uint8_t opcode; + /* Delete GID command deletes a GID from the local address table. */ + #define CMDQ_DELETE_GID_OPCODE_DELETE_GID UINT32_C(0x12) + #define CMDQ_DELETE_GID_OPCODE_LAST CMDQ_DELETE_GID_OPCODE_DELETE_GID + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* GID index */ + uint16_t gid_index; + uint8_t unused_0[6]; +} cmdq_delete_gid_t, *pcmdq_delete_gid_t; + +/* creq_delete_gid_resp (size:128b/16B) */ + +typedef struct creq_delete_gid_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DELETE_GID_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DELETE_GID_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DELETE_GID_RESP_TYPE_LAST CREQ_DELETE_GID_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* GID index */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DELETE_GID_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Delete GID command response. */ + #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID UINT32_C(0x12) + #define CREQ_DELETE_GID_RESP_EVENT_LAST CREQ_DELETE_GID_RESP_EVENT_DELETE_GID + uint8_t reserved48[6]; +} creq_delete_gid_resp_t, *pcreq_delete_gid_resp_t; + +/************** + * modify_gid * + **************/ + + +/* cmdq_modify_gid (size:384b/48B) */ + +typedef struct cmdq_modify_gid { + /* Command opcode. */ + uint8_t opcode; + /* Modify GID command modifies a GID in the local address table. */ + #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID UINT32_C(0x17) + #define CMDQ_MODIFY_GID_OPCODE_LAST CMDQ_MODIFY_GID_OPCODE_MODIFY_GID + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* GID */ + uint32_t gid[4]; + /* Source MAC. */ + uint16_t src_mac[3]; + /* flags. */ + uint16_t vlan; + /* Source VLAN id. */ + #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff) + #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0 + /* This set of bits select the TPID of the VLAN Tag. */ + #define CMDQ_MODIFY_GID_VLAN_TPID_MASK UINT32_C(0x7000) + #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12 + /* TPID = 0x88A8. */ + #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12) + /* TPID = 0x8100. */ + #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12) + /* TPID = 0x9100. */ + #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12) + /* TPID = 0x9200. */ + #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12) + /* TPID = 0x9300. */ + #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12) + /* TPID = Configurable 1. */ + #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12) + /* TPID = Configurable 2. */ + #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12) + /* TPID = Configurable 3. */ + #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12) + #define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 + /* + * Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE + * header. + */ + #define CMDQ_MODIFY_GID_VLAN_VLAN_EN UINT32_C(0x8000) + /* Identifier field in the IP header. */ + uint16_t ipid; + /* GID index */ + uint16_t gid_index; + /* Stats context ID to use with this SGID */ + uint16_t stats_ctx; + /* stats_ctx_id is 15 b */ + #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff) + #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0 + /* + * Setting this bit to 1 enables use of own stats context ID + * instead of per-function. + */ + #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000) + uint16_t unused_0; +} cmdq_modify_gid_t, *pcmdq_modify_gid_t; + +/* creq_modify_gid_resp (size:128b/16B) */ + +typedef struct creq_modify_gid_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_MODIFY_GID_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_MODIFY_GID_RESP_TYPE_LAST CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* GID index */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_MODIFY_GID_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Add GID command response. */ + #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID UINT32_C(0x11) + #define CREQ_MODIFY_GID_RESP_EVENT_LAST CREQ_MODIFY_GID_RESP_EVENT_ADD_GID + uint8_t reserved48[6]; +} creq_modify_gid_resp_t, *pcreq_modify_gid_resp_t; + +/************* + * query_gid * + *************/ + + +/* cmdq_query_gid (size:192b/24B) */ + +typedef struct cmdq_query_gid { + /* Command opcode. */ + uint8_t opcode; + /* Query GID command queries a GID in the local address table. */ + #define CMDQ_QUERY_GID_OPCODE_QUERY_GID UINT32_C(0x18) + #define CMDQ_QUERY_GID_OPCODE_LAST CMDQ_QUERY_GID_OPCODE_QUERY_GID + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* GID index */ + uint16_t gid_index; + /* unused16 is 16 b */ + uint8_t unused16[6]; +} cmdq_query_gid_t, *pcmdq_query_gid_t; + +/* creq_query_gid_resp (size:128b/16B) */ + +typedef struct creq_query_gid_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QUERY_GID_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QUERY_GID_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QUERY_GID_RESP_TYPE_LAST CREQ_QUERY_GID_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Side buffer size in 16-byte units */ + uint32_t size; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QUERY_GID_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Query GID command response. */ + #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID UINT32_C(0x18) + #define CREQ_QUERY_GID_RESP_EVENT_LAST CREQ_QUERY_GID_RESP_EVENT_QUERY_GID + uint8_t reserved48[6]; +} creq_query_gid_resp_t, *pcreq_query_gid_resp_t; + +/* Query GID command response side buffer structure */ +/* creq_query_gid_resp_sb (size:320b/40B) */ + +typedef struct creq_query_gid_resp_sb { + /* Command opcode. */ + uint8_t opcode; + /* Query GID command response. */ + #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID UINT32_C(0x18) + #define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* GID */ + uint32_t gid[4]; + /* Source MAC. */ + uint16_t src_mac[3]; + /* flags. */ + uint16_t vlan; + #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK UINT32_C(0xffff) + #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0 + /* Source VLAN id. */ + #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK UINT32_C(0xfff) + #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0 + /* This set of bits select the TPID of the VLAN Tag. */ + #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK UINT32_C(0x7000) + #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12 + /* TPID = 0x88A8. */ + #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12) + /* TPID = 0x8100. */ + #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12) + /* TPID = 0x9100. */ + #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12) + /* TPID = 0x9200. */ + #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12) + /* TPID = 0x9300. */ + #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12) + /* TPID = Configurable 1. */ + #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12) + /* TPID = Configurable 2. */ + #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12) + /* TPID = Configurable 3. */ + #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12) + #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 + /* + * Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE + * header. + */ + #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN UINT32_C(0x8000) + /* Identifier field in the IP header. */ + uint16_t ipid; + /* GID index */ + uint16_t gid_index; + uint32_t unused_0; +} creq_query_gid_resp_sb_t, *pcreq_query_gid_resp_sb_t; + +/************** + * create_qp1 * + **************/ + + +/* cmdq_create_qp1 (size:640b/80B) */ + +typedef struct cmdq_create_qp1 { + /* Command opcode. */ + uint8_t opcode; + /* Create QP1 command allocates a QP1 only. */ + #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 UINT32_C(0x13) + #define CMDQ_CREATE_QP1_OPCODE_LAST CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* QP1 handle. */ + uint64_t qp_handle; + /* Create QP1 flags. */ + uint32_t qp_flags; + /* SRQ is used. */ + #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED UINT32_C(0x1) + /* post CQE for all SQ WQEs. */ + #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2) + /* This QP can use reserved L_Key */ + #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4) + #define CMDQ_CREATE_QP1_QP_FLAGS_LAST CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE + /* Supported QP1 types. */ + uint8_t type; + /* General Services Interface on QP 1. */ + #define CMDQ_CREATE_QP1_TYPE_GSI UINT32_C(0x1) + #define CMDQ_CREATE_QP1_TYPE_LAST CMDQ_CREATE_QP1_TYPE_GSI + uint8_t sq_pg_size_sq_lvl; + /* SQ PBL indirect levels. */ + #define CMDQ_CREATE_QP1_SQ_LVL_MASK UINT32_C(0xf) + #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2 + /* SQ page size. */ + #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK UINT32_C(0xf0) + #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CMDQ_CREATE_QP1_SQ_PG_SIZE_LAST CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G + uint8_t rq_pg_size_rq_lvl; + /* RQ PBL indirect levels. */ + #define CMDQ_CREATE_QP1_RQ_LVL_MASK UINT32_C(0xf) + #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 UINT32_C(0x2) + #define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2 + /* RQ page size. */ + #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK UINT32_C(0xf0) + #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CMDQ_CREATE_QP1_RQ_PG_SIZE_LAST CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G + uint8_t unused_0; + /* Doorbell page index. */ + uint32_t dpi; + /* Max number of SQ wqes. */ + uint32_t sq_size; + /* Max number of RQ wqes. */ + uint32_t rq_size; + uint16_t sq_fwo_sq_sge; + /* Max send SGEs per SWQE. */ + #define CMDQ_CREATE_QP1_SQ_SGE_MASK UINT32_C(0xf) + #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0 + /* Offset of First WQE in the first SQ page, in 128 byte units */ + #define CMDQ_CREATE_QP1_SQ_FWO_MASK UINT32_C(0xfff0) + #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4 + uint16_t rq_fwo_rq_sge; + /* Max recv SGEs per RWQE (NOT SUPPORTED BY HARDWARE). */ + #define CMDQ_CREATE_QP1_RQ_SGE_MASK UINT32_C(0xf) + #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0 + /* Offset of First WQE in the first RQ page, in 128 byte units */ + #define CMDQ_CREATE_QP1_RQ_FWO_MASK UINT32_C(0xfff0) + #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4 + /* Send CQ context id. */ + uint32_t scq_cid; + /* Receive CQ context id. */ + uint32_t rcq_cid; + /* SRQ CQ context id. */ + uint32_t srq_cid; + /* Protection domain id. */ + uint32_t pd_id; + /* SQ PBL physical address. */ + uint64_t sq_pbl; + /* RQ PBL physical address. */ + uint64_t rq_pbl; +} cmdq_create_qp1_t, *pcmdq_create_qp1_t; + +/* creq_create_qp1_resp (size:128b/16B) */ + +typedef struct creq_create_qp1_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_CREATE_QP1_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_CREATE_QP1_RESP_TYPE_LAST CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* QP1 context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_CREATE_QP1_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Create QP1 command response. */ + #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 UINT32_C(0x13) + #define CREQ_CREATE_QP1_RESP_EVENT_LAST CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 + uint8_t reserved48[6]; +} creq_create_qp1_resp_t, *pcreq_create_qp1_resp_t; + +/*************** + * destroy_qp1 * + ***************/ + + +/* cmdq_destroy_qp1 (size:192b/24B) */ + +typedef struct cmdq_destroy_qp1 { + /* Command opcode. */ + uint8_t opcode; + /* Destroy QP1 command deletes and flushes the specified QP1. */ + #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 UINT32_C(0x14) + #define CMDQ_DESTROY_QP1_OPCODE_LAST CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* QP1 context id */ + uint32_t qp1_cid; + uint32_t unused_0; +} cmdq_destroy_qp1_t, *pcmdq_destroy_qp1_t; + +/* creq_destroy_qp1_resp (size:128b/16B) */ + +typedef struct creq_destroy_qp1_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DESTROY_QP1_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DESTROY_QP1_RESP_TYPE_LAST CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* QP1 context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DESTROY_QP1_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Destroy QP1 command response. */ + #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 UINT32_C(0x14) + #define CREQ_DESTROY_QP1_RESP_EVENT_LAST CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 + uint8_t reserved48[6]; +} creq_destroy_qp1_resp_t, *pcreq_destroy_qp1_resp_t; + +/************* + * create_ah * + *************/ + + +/* cmdq_create_ah (size:512b/64B) */ + +typedef struct cmdq_create_ah { + /* Command opcode. */ + uint8_t opcode; + /* Create AH command allocates an AH with the specified parameters. */ + #define CMDQ_CREATE_AH_OPCODE_CREATE_AH UINT32_C(0x15) + #define CMDQ_CREATE_AH_OPCODE_LAST CMDQ_CREATE_AH_OPCODE_CREATE_AH + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* AH handle. */ + uint64_t ah_handle; + /* Destination GID, specified in BE format. */ + uint32_t dgid[4]; + /* V1, V2IPv4 or V2IPv6. */ + uint8_t type; + /* V2IPv4. */ + #define CMDQ_CREATE_AH_TYPE_V1 UINT32_C(0x0) + /* V2IPv4. */ + #define CMDQ_CREATE_AH_TYPE_V2IPV4 UINT32_C(0x2) + /* V2IPv6. */ + #define CMDQ_CREATE_AH_TYPE_V2IPV6 UINT32_C(0x3) + #define CMDQ_CREATE_AH_TYPE_LAST CMDQ_CREATE_AH_TYPE_V2IPV6 + /* IPv6 Hop limit. */ + uint8_t hop_limit; + /* SGID index. */ + uint16_t sgid_index; + uint32_t dest_vlan_id_flow_label; + /* Flow label. */ + #define CMDQ_CREATE_AH_FLOW_LABEL_MASK UINT32_C(0xfffff) + #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0 + /* Destination VLAN ID. */ + #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK UINT32_C(0xfff00000) + #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20 + /* Protection domain id. */ + uint32_t pd_id; + uint32_t unused_0; + /* Destination MAC address. */ + uint16_t dest_mac[3]; + /* Traffic class. */ + uint8_t traffic_class; + uint8_t enable_cc; + /* Enable congestion control. */ + #define CMDQ_CREATE_AH_ENABLE_CC UINT32_C(0x1) +} cmdq_create_ah_t, *pcmdq_create_ah_t; + +/* creq_create_ah_resp (size:128b/16B) */ + +typedef struct creq_create_ah_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_CREATE_AH_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_CREATE_AH_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_CREATE_AH_RESP_TYPE_LAST CREQ_CREATE_AH_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* AH context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_CREATE_AH_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Create AH command response. */ + #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH UINT32_C(0x15) + #define CREQ_CREATE_AH_RESP_EVENT_LAST CREQ_CREATE_AH_RESP_EVENT_CREATE_AH + uint8_t reserved48[6]; +} creq_create_ah_resp_t, *pcreq_create_ah_resp_t; + +/************** + * destroy_ah * + **************/ + + +/* cmdq_destroy_ah (size:192b/24B) */ + +typedef struct cmdq_destroy_ah { + /* Command opcode. */ + uint8_t opcode; + /* Destroy AH command deletes the specified AH. */ + #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH UINT32_C(0x16) + #define CMDQ_DESTROY_AH_OPCODE_LAST CMDQ_DESTROY_AH_OPCODE_DESTROY_AH + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* AH context id */ + uint32_t ah_cid; + uint32_t unused_0; +} cmdq_destroy_ah_t, *pcmdq_destroy_ah_t; + +/* creq_destroy_ah_resp (size:128b/16B) */ + +typedef struct creq_destroy_ah_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DESTROY_AH_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DESTROY_AH_RESP_TYPE_LAST CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* AH context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DESTROY_AH_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Destroy AH command response. */ + #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH UINT32_C(0x16) + #define CREQ_DESTROY_AH_RESP_EVENT_LAST CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH + uint8_t reserved48[6]; +} creq_destroy_ah_resp_t, *pcreq_destroy_ah_resp_t; + +/******************** + * query_roce_stats * + ********************/ + + +/* cmdq_query_roce_stats (size:192b/24B) */ + +typedef struct cmdq_query_roce_stats { + /* Command opcode. */ + uint8_t opcode; + /* Query RoCE statistics. */ + #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e) + #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* + * When this bit is set FW will use the collection_id to extract + * RoCE statistics. If function_id is also specified the FW will + * return stats corresponding to the collection for the function_id + * specified. + */ + #define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID UINT32_C(0x1) + /* + * When this bit is set FW will use the function_id to extract RoCE + * statistics. When collection is specified then FW will return the + * specific collection stats and if the collection is not specified + * then FW will return the default stats which will be for all QPs. + */ + #define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID UINT32_C(0x2) + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + /* The specific statistics group being queried. */ + uint8_t collection_id; + /* Host address of the response. */ + uint64_t resp_addr; + /* Unique identifier for a function */ + uint32_t function_id; + /* PF number */ + #define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK UINT32_C(0xff) + #define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0 + /* VF number */ + #define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK UINT32_C(0xffff00) + #define CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT 8 + /* When set the vf_num is valid. */ + #define CMDQ_QUERY_ROCE_STATS_VF_VALID UINT32_C(0x1000000) + uint32_t reserved32; +} cmdq_query_roce_stats_t, *pcmdq_query_roce_stats_t; + +/* creq_query_roce_stats_resp (size:128b/16B) */ + +typedef struct creq_query_roce_stats_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Side buffer size in 16-byte units */ + uint32_t size; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QUERY_ROCE_STATS_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Query RoCE statistics. */ + #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS UINT32_C(0x8e) + #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS + uint8_t reserved48[6]; +} creq_query_roce_stats_resp_t, *pcreq_query_roce_stats_resp_t; + +/* Query RoCE Stats command response side buffer structure. */ +/* creq_query_roce_stats_resp_sb (size:3072b/384B) */ + +typedef struct creq_query_roce_stats_resp_sb { + /* Command opcode. */ + uint8_t opcode; + /* Query RoCE statistics. */ + #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e) + #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t rsvd; + uint32_t num_counters; + uint32_t rsvd1; + uint64_t to_retransmits; + /* seq_err_naks_rcvd is 64 b */ + uint64_t seq_err_naks_rcvd; + /* max_retry_exceeded is 64 b */ + uint64_t max_retry_exceeded; + /* rnr_naks_rcvd is 64 b */ + uint64_t rnr_naks_rcvd; + uint64_t missing_resp; + /* unrecoverable_err is 64 b */ + uint64_t unrecoverable_err; + /* bad_resp_err is 64 b */ + uint64_t bad_resp_err; + /* local_qp_op_err is 64 b */ + uint64_t local_qp_op_err; + /* local_protection_err is 64 b */ + uint64_t local_protection_err; + /* mem_mgmt_op_err is 64 b */ + uint64_t mem_mgmt_op_err; + /* remote_invalid_req_err is 64 b */ + uint64_t remote_invalid_req_err; + /* remote_access_err is 64 b */ + uint64_t remote_access_err; + /* remote_op_err is 64 b */ + uint64_t remote_op_err; + /* dup_req is 64 b */ + uint64_t dup_req; + /* res_exceed_max is 64 b */ + uint64_t res_exceed_max; + /* res_length_mismatch is 64 b */ + uint64_t res_length_mismatch; + /* res_exceeds_wqe is 64 b */ + uint64_t res_exceeds_wqe; + /* res_opcode_err is 64 b */ + uint64_t res_opcode_err; + /* res_rx_invalid_rkey is 64 b */ + uint64_t res_rx_invalid_rkey; + /* res_rx_domain_err is 64 b */ + uint64_t res_rx_domain_err; + /* res_rx_no_perm is 64 b */ + uint64_t res_rx_no_perm; + /* res_rx_range_err is 64 b */ + uint64_t res_rx_range_err; + /* res_tx_invalid_rkey is 64 b */ + uint64_t res_tx_invalid_rkey; + /* res_tx_domain_err is 64 b */ + uint64_t res_tx_domain_err; + /* res_tx_no_perm is 64 b */ + uint64_t res_tx_no_perm; + /* res_tx_range_err is 64 b */ + uint64_t res_tx_range_err; + /* res_irrq_oflow is 64 b */ + uint64_t res_irrq_oflow; + /* res_unsup_opcode is 64 b */ + uint64_t res_unsup_opcode; + /* res_unaligned_atomic is 64 b */ + uint64_t res_unaligned_atomic; + /* res_rem_inv_err is 64 b */ + uint64_t res_rem_inv_err; + /* res_mem_error is 64 b */ + uint64_t res_mem_error; + /* res_srq_err is 64 b */ + uint64_t res_srq_err; + /* res_cmp_err is 64 b */ + uint64_t res_cmp_err; + /* res_invalid_dup_rkey is 64 b */ + uint64_t res_invalid_dup_rkey; + /* res_wqe_format_err is 64 b */ + uint64_t res_wqe_format_err; + /* res_cq_load_err is 64 b */ + uint64_t res_cq_load_err; + /* res_srq_load_err is 64 b */ + uint64_t res_srq_load_err; + /* res_tx_pci_err is 64 b */ + uint64_t res_tx_pci_err; + /* res_rx_pci_err is 64 b */ + uint64_t res_rx_pci_err; + /* res_oos_drop_count is 64 b */ + uint64_t res_oos_drop_count; + /* active_qp_count_p0 is 64 b */ + uint64_t active_qp_count_p0; + /* active_qp_count_p1 is 64 b */ + uint64_t active_qp_count_p1; + /* active_qp_count_p2 is 64 b */ + uint64_t active_qp_count_p2; + /* active_qp_count_p3 is 64 b */ + uint64_t active_qp_count_p3; + /* express mode SQ doorbell overflow error 64b counter. */ + uint64_t xp_sq_overflow_err; + /* express mode RQ doorbell overflow error 64b counter. */ + uint64_t xp_rq_overflow_error; +} creq_query_roce_stats_resp_sb_t, *pcreq_query_roce_stats_resp_sb_t; + +/************************ + * query_roce_stats_ext * + ************************/ + + +/* cmdq_query_roce_stats_ext (size:192b/24B) */ + +typedef struct cmdq_query_roce_stats_ext { + /* Command opcode. */ + uint8_t opcode; + /* Query extended RoCE statistics. */ + #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS UINT32_C(0x92) + #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* + * When this bit is set FW will use the collection_id to extract + * RoCE statistics. If function_id is also specified the FW will + * return stats corresponding to the collection for the function_id + * specified. + */ + #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID UINT32_C(0x1) + /* + * When this bit is set FW will use the function_id to extract RoCE + * statistics. When collection is specified then FW will return the + * specific collection stats and if the collection is not specified + * then FW will return the default stats which will be for all QPs. + */ + #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID UINT32_C(0x2) + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + /* The specific statistics group being queried. */ + uint8_t collection_id; + /* Host address of the response. */ + uint64_t resp_addr; + /* Unique identifier for a function */ + uint32_t function_id; + /* PF number */ + #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK UINT32_C(0xff) + #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0 + /* VF number */ + #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK UINT32_C(0xffff00) + #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8 + /* When set the vf_num is valid. */ + #define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID UINT32_C(0x1000000) + uint32_t reserved32; +} cmdq_query_roce_stats_ext_t, *pcmdq_query_roce_stats_ext_t; + +/* creq_query_roce_stats_ext_resp (size:128b/16B) */ + +typedef struct creq_query_roce_stats_ext_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Side buffer size in 16-byte units */ + uint32_t size; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QUERY_ROCE_STATS_EXT_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Query extended RoCE statistics. */ + #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT UINT32_C(0x92) + #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT + uint8_t reserved48[6]; +} creq_query_roce_stats_ext_resp_t, *pcreq_query_roce_stats_ext_resp_t; + +/* Query extended RoCE Stats command response side buffer structure. */ +/* creq_query_roce_stats_ext_resp_sb (size:2304b/288B) */ + +typedef struct creq_query_roce_stats_ext_resp_sb { + /* Command opcode. */ + uint8_t opcode; + /* Query extended RoCE statistics. */ + #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92) + #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t rsvd; + /* Number of transmitted Atomic request packets. */ + uint64_t tx_atomic_req_pkts; + /* Number of transmitted Read request packets. */ + uint64_t tx_read_req_pkts; + /* Number of transmitted Read response packets. */ + uint64_t tx_read_res_pkts; + /* Number of transmitted Write request packets. */ + uint64_t tx_write_req_pkts; + /* + * Number of transmitted Send request packets. + * This is for RC QPs only. + */ + uint64_t tx_send_req_pkts; + /* + * Number of transmitted RoCE packets. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t tx_roce_pkts; + /* + * Number of transmitted RoCE header and payload bytes. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t tx_roce_bytes; + /* Number of received Atomic request packets. */ + uint64_t rx_atomic_req_pkts; + /* Number of received Read request packets. */ + uint64_t rx_read_req_pkts; + /* Number of received Read response packets. */ + uint64_t rx_read_res_pkts; + /* Number of received Write request packets. */ + uint64_t rx_write_req_pkts; + /* + * Number of received Send request packets. + * This is for RC QPs only. + */ + uint64_t rx_send_req_pkts; + /* + * Number of received RoCE packets including RoCE packets with errors. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t rx_roce_pkts; + /* + * Number of received RoCE header and payload bytes including RoCE + * packets with errors. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t rx_roce_bytes; + /* + * Number of received RoCE packets. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t rx_roce_good_pkts; + /* + * Number of received RoCE header and payload bytes. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t rx_roce_good_bytes; + /* + * Number of drops that occurred to lack of buffers. + * This is for RC QPs only. + */ + uint64_t rx_out_of_buffer_pkts; + /* Number of packets that were received out of sequence. */ + uint64_t rx_out_of_sequence_pkts; + /* Number of transmitted CNP packets. The counter is per port. */ + uint64_t tx_cnp_pkts; + /* Number of received CNP packets. The counter is per port. */ + uint64_t rx_cnp_pkts; + /* Number of received ECN-marked RoCE packets. The counter is per port. */ + uint64_t rx_ecn_marked_pkts; + /* Number of transmitted CNP bytes. */ + uint64_t tx_cnp_bytes; + /* Number of received CNP bytes. */ + uint64_t rx_cnp_bytes; + /* + * Number of sequence error NAKs received. + * This counter is only applicable for devices that support + * hardware based retransmission. + */ + uint64_t seq_err_naks_rcvd; + /* + * Number of RNR NAKs received. + * This counter is only applicable for devices that support + * hardware based retransmission. + */ + uint64_t rnr_naks_rcvd; + /* + * Number of missing response resulting in HW retransmission. + * This counter is only applicable for devices that support + * hardware based retransmission. + */ + uint64_t missing_resp; + /* + * Number of timeouts resulting in HW retransmission. + * This counter is only applicable for devices that support + * hardware based retransmission. + */ + uint64_t to_retransmit; + /* + * Number of duplicate read/atomic requests resulting in HW + * retransmission. + * This counter is only applicable for devices that support + * hardware based retransmission. + */ + uint64_t dup_req; + /* + * Number of received DCN payload cut packets. + * This counter is only applicable for devices that support + * the DCN Payload Cut feature. + */ + uint64_t rx_dcn_payload_cut; + /* Number of transmitted packets that bypassed the transmit engine. */ + uint64_t te_bypassed; + /* + * Number of transmitted DCN CNP packets. + * This counter is only applicable for devices that support + * the DCN Payload Cut feature. + */ + uint64_t tx_dcn_cnp; + /* + * Number of received DCN CNP packets. + * This counter is only applicable for devices that support + * the DCN Payload Cut feature. + */ + uint64_t rx_dcn_cnp; + /* + * Number of received DCN payload cut packets. + * This counter is only applicable for devices that support + * the DCN Payload Cut feature. + */ + uint64_t rx_payload_cut; + /* + * Number of received DCN payload cut packets that are ignored + * because they failed the PSN checks. + * This counter is only applicable for devices that support + * the DCN Payload Cut feature. + */ + uint64_t rx_payload_cut_ignored; + /* + * Number of received DCN CNP packets that are ignored either + * because the ECN is not enabled on the QP or the ECN is enabled + * but the CNP packets do not pass the packet validation checks. + * This counter is only applicable for devices that support + * the DCN Payload Cut feature. + */ + uint64_t rx_dcn_cnp_ignored; +} creq_query_roce_stats_ext_resp_sb_t, *pcreq_query_roce_stats_ext_resp_sb_t; + +/************** + * query_func * + **************/ + + +/* cmdq_query_func (size:128b/16B) */ + +typedef struct cmdq_query_func { + /* Command opcode. */ + uint8_t opcode; + /* Query the HW capabilities for the function. */ + #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC UINT32_C(0x83) + #define CMDQ_QUERY_FUNC_OPCODE_LAST CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; +} cmdq_query_func_t, *pcmdq_query_func_t; + +/* creq_query_func_resp (size:128b/16B) */ + +typedef struct creq_query_func_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QUERY_FUNC_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QUERY_FUNC_RESP_TYPE_LAST CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Side buffer size in 16-byte units */ + uint32_t size; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QUERY_FUNC_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Query info PF command response. */ + #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC UINT32_C(0x83) + #define CREQ_QUERY_FUNC_RESP_EVENT_LAST CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC + uint8_t reserved48[6]; +} creq_query_func_resp_t, *pcreq_query_func_resp_t; + +/* Query function command response side buffer structure. */ +/* creq_query_func_resp_sb (size:1280b/160B) */ + +typedef struct creq_query_func_resp_sb { + /* Command opcode. */ + uint8_t opcode; + /* Query info PF command response. */ + #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC UINT32_C(0x83) + #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_LAST CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Max MR size supported. */ + uint64_t max_mr_size; + /* + * Max QP supported. + * For devices that support the pseudo static allocation scheme, + * this count: + * -excludes the QP1 count. + * -includes the count of QPs that can be migrated from the other PF + * Therefore, during normal operation when both PFs are active, + * the supported number of RoCE QPs for each of the PF is half + * of the advertised value. + */ + uint32_t max_qp; + /* Max WQEs per QP. */ + uint16_t max_qp_wr; + /* Device capability flags. */ + uint16_t dev_cap_flags; + /* Allow QP resizing. */ + #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP UINT32_C(0x1) + /* Specifies Congestion Control (CC) generation. */ + #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK UINT32_C(0xe) + #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1 + /* + * Includes support for DCTCP and TCP CC algorithms, + * enabling operation in networks where PFC is enabled. + */ + #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (UINT32_C(0x0) << 1) + /* + * Enhances cc_gen0 support with probabilistic marking algorithm, + * enabling fast ramp up and convergence, + * as well as operation in networks where PFC is not enabled. + * Includes a number of parameters that are different from cc_gen0 + * chips as well as new parameters. TCP CC algorithm is not + * supported. + */ + #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (UINT32_C(0x1) << 1) + /* + * Enhances cc_gen1 support for additional CC parameters: + * reduce_init_en, reduce_init_cong_free_rtts_th, random_no_red_en, + * actual_cr_shift_correction_en, quota_period_adjust_en + */ + #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (UINT32_C(0x2) << 1) + /* + * Enhances cc_gen1_ext support, to include support for DCN/SARA. + * Enables query and modification of Queue level table attributes, + * which are used by the hardware to determine the QP's flow rate + * based on congestion level and thereby reduce RoCE packet drop + * due to network congestion. + */ + #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2 (UINT32_C(0x3) << 1) + #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2 + /* + * Support for the extended RoCE statistics is available. These + * statistics are queried via the `query_roce_stats_ext` command + * and are enabled on a per-QP basis via `create_qp`. + */ + #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS UINT32_C(0x10) + /* + * Support for both allocating and registering a new MR via the + * `register_mr` command is available. With this feature the + * `allocate_mrw` command does not have to be called before + * registering. + */ + #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC UINT32_C(0x20) + /* + * Support for optimized transmit path to lower latency for WQEs + * with inline data. + */ + #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x40) + /* + * The underlying HW uses the version 2 of the CQEs definitions for + * the following CQE types: + * RES_UD, RES_RAWETH_QP1, RES_UD_CFA + */ + #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 UINT32_C(0x80) + /* Support for ping pong push mode is available. */ + #define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE UINT32_C(0x100) + /* Support for hardware requester retransmission is enabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED UINT32_C(0x200) + /* Support for hardware responder retransmission is enabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED UINT32_C(0x400) + /* Support for link aggregation is enabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED UINT32_C(0x800) + /* link_aggr_supported is valid. */ + #define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED_VALID UINT32_C(0x1000) + /* + * Support for pseudo static QP allocation is enabled. + * This feature enables the following capabilities: + * - QP context ID space is pseudo-static partitioned across PFs. + * - An application can use a predetermined + * QP context ID assignment scheme for specific operations. + * - For 2-port adapters, the application can migrate the QP context + * ID range across PFs, using the `orchestrate_qid_migration` HWRM, + * during network events such as Link Down. + */ + #define CREQ_QUERY_FUNC_RESP_SB_PSEUDO_STATIC_QP_ALLOC_SUPPORTED UINT32_C(0x2000) + /* + * Support for Express Mode is enabled. + * For Express mode, the QP resources (SQ/RQ) are allocated in + * on-chip queue memory. The host driver should not allocate memory + * for these queue structures. + */ + #define CREQ_QUERY_FUNC_RESP_SB_EXPRESS_MODE_SUPPORTED UINT32_C(0x4000) + /* + * IRRQ/ORRQ and MSN Table structures are allocated in internal + * queue memory. + */ + #define CREQ_QUERY_FUNC_RESP_SB_INTERNAL_QUEUE_MEMORY UINT32_C(0x8000) + /* Max CQs supported. */ + uint32_t max_cq; + /* Max CQEs per CQ supported. */ + uint32_t max_cqe; + /* Max PDs supported. */ + uint32_t max_pd; + /* + * Max SGEs per QP WQE supported. On chips with variable-size WQE + * support, this field is applicable only for the backward compatible + * mode. + */ + uint8_t max_sge; + /* Max SGEs per SRQ WQE supported. */ + uint8_t max_srq_sge; + /* Max outstanding RDMA read & atomic supported. */ + uint8_t max_qp_rd_atom; + /* + * Max outstanding RDMA read & atomic that can be sent from an + * initiator. + */ + uint8_t max_qp_init_rd_atom; + /* Max MRs supported. */ + uint32_t max_mr; + /* Max MWs supported. */ + uint32_t max_mw; + /* Max Raw Ethertype QPs supported. */ + uint32_t max_raw_eth_qp; + /* Max AHs supported. */ + uint32_t max_ah; + /* Max FMRs supported. */ + uint32_t max_fmr; + /* Max WQEs per SRQ supported. */ + uint32_t max_srq_wr; + /* Max PKEYs supported. */ + uint32_t max_pkeys; + /* + * Max inline data supported. On chips with variable-size WQE support, + * this field is applicable only for the backward compatible mode. + */ + uint32_t max_inline_data; + /* Max mappings per FMR supported. */ + uint8_t max_map_per_fmr; + /* L2 DB space size in pages. */ + uint8_t l2_db_space_size; + /* Max SRQs supported. */ + uint16_t max_srq; + /* Max GIDs supported. */ + uint32_t max_gid; + /* + * An array of 48 8-bit values to specify allocation multiplier for TQM + * host buffer regions. Each region occupies 16 MB of TQM PBL address + * space: 0x00000000, 0x01000000, 0x02000000, etc. + * The host needs to allocate (*multiplier, rounded up + * to page size) of physical memory for non-zero slots and map the + * pages to the corresponding 16MB regions. Typically there are total + * 3 non-zero values in this array, their values are 16, 16, 12. + * Cu+ will only populate up to index 11. SR may populate up to + * index 47. + */ + uint32_t tqm_alloc_reqs[12]; + /* Max Doorbell page indices supported. */ + uint32_t max_dpi; + /* Max SGEs per QP WQE supported in the variable-size WQE mode. */ + uint8_t max_sge_var_wqe; + /* Device capability extended flags. */ + uint8_t dev_cap_ext_flags; + /* RDMA Atomic operations are not supported. */ + #define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED UINT32_C(0x1) + /* Support driver version registration. */ + #define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED UINT32_C(0x2) + /* Support for batch allocation of QPs is enabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED UINT32_C(0x4) + /* Support for batch deletion of QPs is enabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED UINT32_C(0x8) + /* + * Support for extended RoCE statistics context + * with periodic DMA is enabled. The statistics contexts + * are allocated via `allocate_roce_stats_ext_ctx` + * and deallocated via `deallocate_roce_stats_ext_ctx`. + * These contexts are assigned on a per-QP, per-group of QPs + * or per-function basis via `create_qp`, `create_qp_batch` + * or `modify_qp`command. + * In addition to periodic DMA to a host address, + * these statistics can be queried via `query_roce_stats_ext_v2`. + */ + #define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED UINT32_C(0x10) + /* + * Support for the srq_sge field in the create_srq command is + * enabled. + */ + #define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED UINT32_C(0x20) + /* Support for fixed size SQ wqe (128B) is disabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED UINT32_C(0x40) + /* Support for DCN (Drop Congestion Notification) is enabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED UINT32_C(0x80) + /* Max inline data supported in the variable-size WQE mode. */ + uint16_t max_inline_data_var_wqe; + /* + * starting xid of the predetermined assignment scheme supported + * by the pseudo static allocation feature. Note that for a PF, + * the start_qid is itself pseudo_static, and can change when the QP + * context id range is migrated by the driver using the + * cmdq_orchestrate_qid_migration. The supported QP count is + * available in the `max_qp` field of `cmdq_query_func`. + */ + uint32_t start_qid; + /* + * Max number of MSN table entries supported for devices that support + * the `internal_queue_memory` feature. + */ + uint8_t max_msn_table_size; + /* reserved8_1 is 8 b */ + uint8_t reserved8_1; + /* Device capability extended flags_2 */ + uint16_t dev_cap_ext_flags_2; + /* Firmware support for optimizing Modify QP operation */ + #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED UINT32_C(0x1) + /* + * Device supports changing UDP source port of RoCEv2 packets using + * WQE. + */ + #define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED UINT32_C(0x2) + /* Device supports CQ Coalescing. */ + #define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED UINT32_C(0x4) + /* + * Device allows a memory region to be designated as + * relaxed-ordering enabled or disabled. + */ + #define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED UINT32_C(0x8) + /* The type of lookup table used for requester retransmission. */ + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK UINT32_C(0x30) + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_SFT 4 + /* Requester Retransmission uses a PSN table in host memory. */ + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE (UINT32_C(0x0) << 4) + /* Requester Retransmission uses an MSN table in host memory. */ + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE (UINT32_C(0x1) << 4) + /* + * Requester Retransmission uses an MSN table in Device Internal + * Queue Memory. + */ + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE (UINT32_C(0x2) << 4) + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_LAST CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE + /* + * Max number of 16B IQM memory slots supported by SQ or RQ + * when QP is in express mode. + * This field is only valid for express mode QPs. + */ + uint16_t max_xp_qp_size; + /* + * Max number of QPs that can be created in one `create_qp_batch` + * command. + */ + uint16_t create_qp_batch_size; + /* + * Max number of QPs that can be destroyed in one `destroy_qp_batch` + * command. + */ + uint16_t destroy_qp_batch_size; + uint16_t reserved16; + uint64_t reserved64; +} creq_query_func_resp_sb_t, *pcreq_query_func_resp_sb_t; + +/********************** + * set_func_resources * + **********************/ + + +/* cmdq_set_func_resources (size:448b/56B) */ + +typedef struct cmdq_set_func_resources { + /* Command opcode. */ + uint8_t opcode; + /* + * Set the following resources for the function: + * - Max QP, CQ, MR+MW, SRQ per PF + * - Max QP, CQ, MR+MW, SRQ per VF + */ + #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84) + #define CMDQ_SET_FUNC_RESOURCES_OPCODE_LAST CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* + * When set, the 32b `max_mrw_per_vf` field is logically divided + * into two 16b fields, `max_mr_per_vf` and `max_av_per_vf`. + */ + #define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x1) + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* + * Number of QPs. It is the responsibility of the host to first extend + * the existing PBL with new addresses to pages to handle the + * adjustment. Must be greater or equal to current. + */ + uint32_t number_of_qp; + /* + * Number of MRWs. It is the responsibility of the host to first extend + * the existing PBL with new addresses to pages to handle the + * adjustment. Must be greater or equal to current. + */ + uint32_t number_of_mrw; + /* + * Number of SRQs. It is the responsibility of the host to first extend + * the existing PBL with new addresses to pages to handle the + * adjustment. Must be greater or equal to current. + */ + uint32_t number_of_srq; + /* + * Number of CQs. It is the responsibility of the host to first extend + * the existing PBL with new addresses to pages to handle the + * adjustment. Must be greater or equal to current. + */ + uint32_t number_of_cq; + /* + * Number of QPs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ + uint32_t max_qp_per_vf; + /* + * If the MR/AV split reservation flag is not set, then this field + * represents the total number of MR plus AV entries allowed per + * VF. For versions of firmware that support the split reservation, + * when it is not specified half of the entries will be reserved + * for MRs and the other half for AVs. + * + * If the MR/AV split reservation flag is set, then this + * field is logically divided into two 16b fields. Bits `[31:16]` + * represents the `max_mr_per_vf` and bits `[15:0]` represents + * `max_av_per_vf`. The granularity of these values is defined by + * the `mrav_num_entries_unit` field returned by the + * `backing_store_qcaps` command. + * + * This field must be set to zero when the flag, l2_vf_resource_mgmt, + * is set and RoCE SRIOV is enabled. + */ + uint32_t max_mrw_per_vf; + /* + * Number of SRQs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ + uint32_t max_srq_per_vf; + /* + * Number of CQs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ + uint32_t max_cq_per_vf; + /* + * Number of GIDs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ + uint32_t max_gid_per_vf; + /* Statistics context index for this function. */ + uint32_t stat_ctx_id; +} cmdq_set_func_resources_t, *pcmdq_set_func_resources_t; + +/* creq_set_func_resources_resp (size:128b/16B) */ + +typedef struct creq_set_func_resources_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_LAST CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_SET_FUNC_RESOURCES_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Set function resources command response. */ + #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84) + #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_LAST CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES + uint8_t reserved48[6]; +} creq_set_func_resources_resp_t, *pcreq_set_func_resources_resp_t; + +/************* + * stop_func * + *************/ + + +/* cmdq_stop_func (size:128b/16B) */ + +typedef struct cmdq_stop_func { + /* Command opcode. */ + uint8_t opcode; + /* Stop the function */ + #define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC UINT32_C(0x82) + #define CMDQ_STOP_FUNC_OPCODE_LAST CMDQ_STOP_FUNC_OPCODE_STOP_FUNC + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; +} cmdq_stop_func_t, *pcmdq_stop_func_t; + +/* creq_stop_func_resp (size:128b/16B) */ + +typedef struct creq_stop_func_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_STOP_FUNC_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_STOP_FUNC_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_STOP_FUNC_RESP_TYPE_LAST CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_STOP_FUNC_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Stop PF command response. */ + #define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC UINT32_C(0x82) + #define CREQ_STOP_FUNC_RESP_EVENT_LAST CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC + uint8_t reserved48[6]; +} creq_stop_func_resp_t, *pcreq_stop_func_resp_t; + +/**************** + * read_context * + ****************/ + + +/* cmdq_read_context (size:192b/24B) */ + +typedef struct cmdq_read_context { + /* Command opcode. */ + uint8_t opcode; + /* + * Read the current state of any internal resource context. Can only + * be issued from a PF. + */ + #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT UINT32_C(0x85) + #define CMDQ_READ_CONTEXT_OPCODE_LAST CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Context ID */ + uint32_t xid; + /* Context type */ + uint8_t type; + /* + * Read QPC. The context (448 bytes) goes to resp_addr (as is, + * without a header), and resp_size should be set to 28 + * (448/16). + */ + #define CMDQ_READ_CONTEXT_TYPE_QPC UINT32_C(0x0) + /* + * Read CQ. The context (64 bytes) goes to resp_addr (as is, + * without a header), and resp_size should be set to 4 (64/16) + */ + #define CMDQ_READ_CONTEXT_TYPE_CQ UINT32_C(0x1) + /* + * Read MRW. The context (128 bytes) goes to resp_addr (as is, + * without a header), and resp_size should be set to 8 (128/16) + */ + #define CMDQ_READ_CONTEXT_TYPE_MRW UINT32_C(0x2) + /* + * Read SRQ. The context (64 bytes) goes to resp_addr (as is, + * without a header), and resp_size should be set to 4 (64/16) + */ + #define CMDQ_READ_CONTEXT_TYPE_SRQ UINT32_C(0x3) + #define CMDQ_READ_CONTEXT_TYPE_LAST CMDQ_READ_CONTEXT_TYPE_SRQ + uint8_t unused_0[3]; +} cmdq_read_context_t, *pcmdq_read_context_t; + +/* creq_read_context (size:128b/16B) */ + +typedef struct creq_read_context { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B records. + * records. + */ + #define CREQ_READ_CONTEXT_TYPE_MASK UINT32_C(0x3f) + #define CREQ_READ_CONTEXT_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_READ_CONTEXT_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_READ_CONTEXT_TYPE_LAST CREQ_READ_CONTEXT_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_READ_CONTEXT_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* + * Read the current state of any internal resource context. Can only + * be issued from a PF. + */ + #define CREQ_READ_CONTEXT_EVENT_READ_CONTEXT UINT32_C(0x85) + #define CREQ_READ_CONTEXT_EVENT_LAST CREQ_READ_CONTEXT_EVENT_READ_CONTEXT + uint16_t reserved16; + uint32_t reserved_32; +} creq_read_context_t, *pcreq_read_context_t; + +/***************** + * map_tc_to_cos * + *****************/ + + +/* cmdq_map_tc_to_cos (size:192b/24B) */ + +typedef struct cmdq_map_tc_to_cos { + /* Command opcode. */ + uint8_t opcode; + /* Map TC to COS. Can only be issued from a PF. */ + #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a) + #define CMDQ_MAP_TC_TO_COS_OPCODE_LAST CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* 1st COS index mapped to RoCE */ + uint16_t cos0; + /* Don't change this COS. */ + #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE UINT32_C(0xffff) + #define CMDQ_MAP_TC_TO_COS_COS0_LAST CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE + /* 2nd COS index mapped to RoCE */ + uint16_t cos1; + /* Disable this COS. */ + #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE UINT32_C(0x8000) + /* Don't change this COS. */ + #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE UINT32_C(0xffff) + #define CMDQ_MAP_TC_TO_COS_COS1_LAST CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE + uint32_t unused_0; +} cmdq_map_tc_to_cos_t, *pcmdq_map_tc_to_cos_t; + +/* creq_map_tc_to_cos_resp (size:128b/16B) */ + +typedef struct creq_map_tc_to_cos_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_MAP_TC_TO_COS_RESP_TYPE_LAST CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_MAP_TC_TO_COS_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Map TC to COS response. */ + #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS UINT32_C(0x8a) + #define CREQ_MAP_TC_TO_COS_RESP_EVENT_LAST CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS + uint8_t reserved48[6]; +} creq_map_tc_to_cos_resp_t, *pcreq_map_tc_to_cos_resp_t; + +/***************** + * query_roce_cc * + *****************/ + + +/* cmdq_query_roce_cc (size:128b/16B) */ + +typedef struct cmdq_query_roce_cc { + /* Command opcode. */ + uint8_t opcode; + /* Query congestion control. */ + #define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) + #define CMDQ_QUERY_ROCE_CC_OPCODE_LAST CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; +} cmdq_query_roce_cc_t, *pcmdq_query_roce_cc_t; + +/* creq_query_roce_cc_resp (size:128b/16B) */ + +typedef struct creq_query_roce_cc_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QUERY_ROCE_CC_RESP_TYPE_LAST CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Side buffer size in 16-byte units */ + uint32_t size; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QUERY_ROCE_CC_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Query congestion control response. */ + #define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC UINT32_C(0x8d) + #define CREQ_QUERY_ROCE_CC_RESP_EVENT_LAST CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC + uint8_t reserved48[6]; +} creq_query_roce_cc_resp_t, *pcreq_query_roce_cc_resp_t; + +/* Query congestion control command response side buffer structure. */ +/* creq_query_roce_cc_resp_sb (size:256b/32B) */ + +typedef struct creq_query_roce_cc_resp_sb { + /* Command opcode. */ + uint8_t opcode; + /* Query congestion control response. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) + #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + uint8_t enable_cc; + /* Enable. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC UINT32_C(0x1) + /* unused7 is 7 b */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK UINT32_C(0xfe) + #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_SFT 1 + uint8_t tos_dscp_tos_ecn; + /* IP TOS ECN. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK UINT32_C(0x3) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0 + /* IP TOS DSCP. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2 + /* Congestion Probability averaging factor. */ + uint8_t g; + /* Number of phases in Fast Recovery and Active Increase. */ + uint8_t num_phases_per_state; + /* The starting value of rate. */ + uint16_t init_cr; + /* The starting value of target rate. */ + uint16_t init_tr; + uint8_t alt_vlan_pcp; + /* Alternate vlan pcp value for CNP packets. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK UINT32_C(0x7) + #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0 + /* rsvd1 is 5 b */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK UINT32_C(0xf8) + #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3 + uint8_t alt_tos_dscp; + /* Alternate IP TOS DSCP. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK UINT32_C(0x3f) + #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0 + /* rsvd4 is 2 b */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK UINT32_C(0xc0) + #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6 + uint8_t cc_mode; + /* DCTCP CC algorithm. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP UINT32_C(0x0) + /* + * Probabilistic marking CC algorithm. On chips with CC Gen 0 + * support this will be TCP CC algorithm. + */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC UINT32_C(0x1) + #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC + /* Specifies the RoCE Tx Queue to use for sending CNP packets. */ + uint8_t tx_queue; + uint16_t rtt; + /* Round trip time in units of usecs */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK UINT32_C(0x3fff) + #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0 + /* rsvd5 is 2 b */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK UINT32_C(0xc000) + #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14 + uint16_t tcp_cp; + /* The value used as CP when cc_mode is 1(TCP) */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK UINT32_C(0x3ff) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0 + /* rsvd6 is 6 b */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK UINT32_C(0xfc00) + #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10 + /* Inactivity time after which QP CC parameters are initialized */ + uint16_t inactivity_th; + /* Number of packets per phase. Max is 255. */ + uint8_t pkts_per_phase; + /* Amount of time per phase in units of ms. Max is 15 */ + uint8_t time_per_phase; + uint32_t reserved32; +} creq_query_roce_cc_resp_sb_t, *pcreq_query_roce_cc_resp_sb_t; + +/* + * TLV encapsulated Query congestion control command response + * side buffer, with extended TLV record included for specifying + * the extended configuration for CC level 1. + */ +/* creq_query_roce_cc_resp_sb_tlv (size:384b/48B) */ + +typedef struct creq_query_roce_cc_resp_sb_tlv { + /* + * The command discriminator is used to differentiate between various + * types of HWRM messages. This includes legacy HWRM and RoCE slowpath + * command messages as well as newer TLV encapsulated HWRM commands. + * + * For TLV encapsulated messages this field must be 0x8000. + */ + uint16_t cmd_discr; + uint8_t reserved_8b; + uint8_t tlv_flags; + /* + * Indicates the presence of additional TLV encapsulated data + * follows this TLV. + */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1) + /* Last TLV in a sequence of TLVs. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) + /* More TLVs follow this TLV. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + /* + * When an HWRM receiver detects a TLV type that it does not + * support with the TLV required flag set, the receiver must + * reject the HWRM message with an error code indicating an + * unsupported TLV type. + */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) + /* No */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) + /* Yes */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES + /* + * This field defines the TLV type value which is divided into + * two ranges to differentiate between global and local TLV types. + * Global TLV types must be unique across all defined TLV types. + * Local TLV types are valid only for extensions to a given + * HWRM message and may be repeated across different HWRM message + * types. There is a direct correlation of each HWRM message type + * to a single global TLV type value. + * + * Global TLV range: `0 - (63k-1)` + * + * Local TLV range: `63k - (64k-1)` + */ + uint16_t tlv_type; + /* + * Length of the message data encapsulated by this TLV in bytes. + * This length does not include the size of the TLV header itself + * and it must be an integer multiple of 8B. + */ + uint16_t length; + /* + * Size of the tlv encapsulated response, + * including all tlvs and extension data in 16-byte units. + */ + uint8_t total_size; + uint8_t reserved56[7]; + /* Command opcode. */ + uint8_t opcode; + /* Query congestion control response. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + uint8_t enable_cc; + /* Enable. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC UINT32_C(0x1) + /* unused7 is 7 b */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK UINT32_C(0xfe) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_SFT 1 + uint8_t tos_dscp_tos_ecn; + /* IP TOS ECN. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK UINT32_C(0x3) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0 + /* IP TOS DSCP. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK UINT32_C(0xfc) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_SFT 2 + /* Congestion Probability averaging factor. */ + uint8_t g; + /* Number of phases in Fast Recovery and Active Increase. */ + uint8_t num_phases_per_state; + /* The starting value of rate. */ + uint16_t init_cr; + /* The starting value of target rate. */ + uint16_t init_tr; + uint8_t alt_vlan_pcp; + /* Alternate vlan pcp value for CNP packets. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK UINT32_C(0x7) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0 + /* rsvd1 is 5 b */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK UINT32_C(0xf8) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_SFT 3 + uint8_t alt_tos_dscp; + /* Alternate IP TOS DSCP. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK UINT32_C(0x3f) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0 + /* rsvd4 is 2 b */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK UINT32_C(0xc0) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_SFT 6 + uint8_t cc_mode; + /* DCTCP CC algorithm. */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP UINT32_C(0x0) + /* + * Probabilistic marking CC algorithm. On chips with CC Gen 0 + * support this will be TCP CC algorithm. + */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC UINT32_C(0x1) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC + /* Specifies the RoCE Tx Queue to use for sending CNP packets. */ + uint8_t tx_queue; + uint16_t rtt; + /* Round trip time in units of usecs */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK UINT32_C(0x3fff) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0 + /* rsvd5 is 2 b */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK UINT32_C(0xc000) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_SFT 14 + uint16_t tcp_cp; + /* The value used as CP when cc_mode is 1(TCP) */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK UINT32_C(0x3ff) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0 + /* rsvd6 is 6 b */ + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK UINT32_C(0xfc00) + #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_SFT 10 + /* Inactivity time after which QP CC parameters are initialized */ + uint16_t inactivity_th; + /* Number of packets per phase. Max is 255. */ + uint8_t pkts_per_phase; + /* Amount of time per phase in units of ms. Max is 15 */ + uint8_t time_per_phase; + uint32_t reserved32; +} creq_query_roce_cc_resp_sb_tlv_t, *pcreq_query_roce_cc_resp_sb_tlv_t; + +/* creq_query_roce_cc_gen1_resp_sb_tlv (size:704b/88B) */ + +typedef struct creq_query_roce_cc_gen1_resp_sb_tlv { + /* + * The command discriminator is used to differentiate between various + * types of HWRM messages. This includes legacy HWRM and RoCE slowpath + * command messages as well as newer TLV encapsulated HWRM commands. + * + * For TLV encapsulated messages this field must be 0x8000. + */ + uint16_t cmd_discr; + uint8_t reserved_8b; + uint8_t tlv_flags; + /* + * Indicates the presence of additional TLV encapsulated data + * follows this TLV. + */ + #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1) + /* Last TLV in a sequence of TLVs. */ + #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) + /* More TLVs follow this TLV. */ + #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + /* + * When an HWRM receiver detects a TLV type that it does not + * support with the TLV required flag set, the receiver must + * reject the HWRM message with an error code indicating an + * unsupported TLV type. + */ + #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) + /* No */ + #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) + /* Yes */ + #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) + #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES + /* + * This field defines the TLV type value which is divided into + * two ranges to differentiate between global and local TLV types. + * Global TLV types must be unique across all defined TLV types. + * Local TLV types are valid only for extensions to a given + * HWRM message and may be repeated across different HWRM message + * types. There is a direct correlation of each HWRM message type + * to a single global TLV type value. + * + * Global TLV range: `0 - (63k-1)` + * + * Local TLV range: `63k - (64k-1)` + */ + uint16_t tlv_type; + /* + * Length of the message data encapsulated by this TLV in bytes. + * This length does not include the size of the TLV header itself + * and it must be an integer multiple of 8B. + */ + uint16_t length; + uint64_t reserved64; + /* High order bits of inactivity threshold. */ + uint16_t inactivity_th_hi; + /* + * The number of uS between generation of CNPs when cc_mode is + * probabilistic marking. + */ + uint16_t min_time_between_cnps; + /* + * The starting value of congestion probability. Input range + * is 0 - 1023. + */ + uint16_t init_cp; + /* + * In tr_update_mode 0, Target Rate (TR) is updated to + * halfway between the Current Rate (CR) before and after reduction. + * In tr_update_mode 1, TR is updated to CR's value before reduction. + */ + uint8_t tr_update_mode; + /* + * Determine for how many RTTs with CNPs in a row, TR is being updated. + * 0: TR is updated when QPC. rtts_with_cnps == 0 + * 1-6: TR is updated if QPC. rtts_with_cnps <= tr_update_cycles + * 7: TR is updated on all reductions. + */ + uint8_t tr_update_cycles; + /* Number of RTTs in Fast Recovery stage. */ + uint8_t fr_num_rtts; + /* Time increment to increase TR in active increase phase. */ + uint8_t ai_rate_increase; + /* + * Indicates for how many RTTs with CNPs after the first one + * to not reduce rate even if CNPs are received. + */ + uint16_t reduction_relax_rtts_th; + /* + * For low rates, additional number of RTTS with CNPs + * for which no rate reduction is made. + * num_bits: 14 + */ + uint16_t additional_relax_cr_th; + /* + * If CR is less than or equal to this value, + * then the actual CR average is set to this value + * (shifted by bw_avg_weight). + */ + uint16_t cr_min_th; + /* Log based averaging weight for QPC variable actual_cr_avg. */ + uint8_t bw_avg_weight; + /* + * Used to compare CR to this factor times QPC.actual_cr_average + * as a reduction reference. Values between 0 and 6 represent factor of + * 1.125, 1.25, 1.5, 1.75, 2, 2.25, 2.5 respectively. + */ + uint8_t actual_cr_factor; + /* The level of CR above which CP is set to maximum level. */ + uint16_t max_cp_cr_th; + /* + * Enable adding fraction of CR to CP. + * 0 for disable, 1 for enable. + */ + uint8_t cp_bias_en; + /* Log based fraction of cr to add to CP when cp_bias_en is 1. */ + uint8_t cp_bias; + /* + * The value of ECN bits in a CNP packet generated by hardware. + * ECN-Capable Transport (ECT) codepoints supported include: + * 0 for not_ect, 1 for ect_0, 2 for ect_1 + */ + uint8_t cnp_ecn; + /* Not ECN capable Transport */ + #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT UINT32_C(0x0) + /* ECN Capable Transport-1 */ + #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 UINT32_C(0x1) + /* ECN Capable Transport-0 */ + #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 UINT32_C(0x2) + #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_LAST CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 + /* Enables jitter in RTT. */ + uint8_t rtt_jitter_en; + /* + * Number of bytes per usec, dependent on port speed. + * 200 Gbps: 25,000 + * 100 Gbps: 12,500 + * 50 Gbps: 6,250 + * 25 Gbps: 3125 + * 10 Gbps: 1250 + */ + uint16_t link_bytes_per_usec; + /* + * If CR is greater than or equal to this threshold, + * QPC's CC state is reset to its initial state. + */ + uint16_t reset_cc_cr_th; + /* + * The number of valid lsbits in CR and TR. + * Supported values include 10 through 14 to support 2^cr_width rate. + */ + uint8_t cr_width; + /* Lower end of random selection of quota_period. */ + uint8_t quota_period_min; + /* Upper end of random selection of quota_period. */ + uint8_t quota_period_max; + /* + * The absolute maximum possible quota_period, + * applicable when rate table for lower 24 levels is used. + */ + uint8_t quota_period_abs_max; + /* TR never goes below this level. */ + uint16_t tr_lower_bound; + /* Factor on probability threshold for adding 0.5 to CR randomly. */ + uint8_t cr_prob_factor; + /* Factor on probability threshold for adding 0.5 to TR randomly. */ + uint8_t tr_prob_factor; + /* + * Threshold to ensure fairness between requester and responder. + * If CR is less than the fairness threshold and a quota period has + * passed priority will be given to the path that did not last + * transfer data. + */ + uint16_t fairness_cr_th; + /* Log based rate reduction divider. */ + uint8_t red_div; + /* Threshold for rate reductions when CNPS received over last RTT. */ + uint8_t cnp_ratio_th; + /* + * Extended number of RTTS to wait, when there is no congestion, + * to start doubling the rate. + */ + uint16_t exp_ai_rtts; + /* Log based CR to CP ratio used in exponential increase. */ + uint8_t exp_ai_cr_cp_ratio; + /* Enable use of lowest 24 rate levels rate_table. */ + uint8_t use_rate_table; + /* + * Determines after how many congestion free RTTs to start + * updating CP to track CR. + */ + uint16_t cp_exp_update_th; + /* + * The threshold on congestion free RTTs above which AI can increase + * to 16. + */ + uint16_t high_exp_ai_rtts_th1; + /* + * The threshold on congestion free RTTs above which AI can increase + * to 32. + */ + uint16_t high_exp_ai_rtts_th2; + /* + * The number of congestion free RTTs above which + * reduction based on actual rate is enabled. + */ + uint16_t actual_cr_cong_free_rtts_th; + /* + * If rtts_with_cong is greater than 7 (severe congestion) and + * CR level post reduction is above this threshold, + * then TR is capped to 1.5 times CR.. + */ + uint16_t severe_cong_cr_th1; + /* + * If rtts_with_cong is greater than 7 (severe congestion) and + * CR level post reduction is above this threshold, + * then TR is capped to 1.25 times CR.. + */ + uint16_t severe_cong_cr_th2; + /* + * The maximum number of 64B that can be transmitted during RTT time, + * including all headers and Inter Packet Gap. + */ + uint32_t link64B_per_rtt; + /* + * The number of bytes to subtract from QPC.cc_bucket + * when an ack is scheduled. + */ + uint8_t cc_ack_bytes; + /* + * Enables reduction of CR, TR, and CP to init values when + * congestion free RTTs is greater than reduce2_init_cong_free_rtts_th. + */ + uint8_t reduce_init_en; + /* + * Minimum threshold value for number of congestion free RTTs before + * reducing to init values for CR, TR, and CP when reduce_init_en is + * enabled. + */ + uint16_t reduce_init_cong_free_rtts_th; + /* Enables random no reduction of CR. */ + uint8_t random_no_red_en; + /* + * Enables coarse correction to actual CR when actual RTT is longer + * than nominal. + */ + uint8_t actual_cr_shift_correction_en; + /* Enables adjustment to refill quota. */ + uint8_t quota_period_adjust_en; + uint8_t reserved[5]; +} creq_query_roce_cc_gen1_resp_sb_tlv_t, *pcreq_query_roce_cc_gen1_resp_sb_tlv_t; + +/* creq_query_roce_cc_gen2_resp_sb_tlv (size:512b/64B) */ + +typedef struct creq_query_roce_cc_gen2_resp_sb_tlv { + /* + * The command discriminator is used to differentiate between various + * types of HWRM messages. This includes legacy HWRM and RoCE slowpath + * command messages as well as newer TLV encapsulated HWRM commands. + * + * For TLV encapsulated messages this field must be 0x8000. + */ + uint16_t cmd_discr; + uint8_t reserved_8b; + uint8_t tlv_flags; + /* + * Indicates the presence of additional TLV encapsulated data + * follows this TLV. + */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1) + /* Last TLV in a sequence of TLVs. */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) + /* More TLVs follow this TLV. */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + /* + * When an HWRM receiver detects a TLV type that it does not + * support with the TLV required flag set, the receiver must + * reject the HWRM message with an error code indicating an + * unsupported TLV type. + */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) + /* No */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) + /* Yes */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES + /* + * This field defines the TLV type value which is divided into + * two ranges to differentiate between global and local TLV types. + * Global TLV types must be unique across all defined TLV types. + * Local TLV types are valid only for extensions to a given + * HWRM message and may be repeated across different HWRM message + * types. There is a direct correlation of each HWRM message type + * to a single global TLV type value. + * + * Global TLV range: `0 - (63k-1)` + * + * Local TLV range: `63k - (64k-1)` + */ + uint16_t tlv_type; + /* + * Length of the message data encapsulated by this TLV in bytes. + * This length does not include the size of the TLV header itself + * and it must be an integer multiple of 8B. + */ + uint16_t length; + uint64_t reserved64; + /* + * DCN queue level threshold values associated with DCN queue + * level table indices 0 to 7. + */ + uint16_t dcn_qlevel_tbl_thr[8]; + /* + * DCN queue level table action values. + * Returns CR, INC_CNP, UPD_IMM & TR fields associated with + * DCN queue level table indices 0 to 7. + */ + uint32_t dcn_qlevel_tbl_act[8]; + /* DCN queue level current rate. */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK UINT32_C(0x3fff) + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT 0 + /* DCN queue level increment CNP count. */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP UINT32_C(0x4000) + /* DCN queue level update CR and TR immediately. */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM UINT32_C(0x8000) + /* DCN queue level target rate */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK UINT32_C(0x3fff0000) + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_TR_SFT 16 +} creq_query_roce_cc_gen2_resp_sb_tlv_t, *pcreq_query_roce_cc_gen2_resp_sb_tlv_t; + +/*********************** + * cmdq_modify_roce_cc * + ***********************/ + + +/* cmdq_modify_roce_cc (size:448b/56B) */ + +typedef struct cmdq_modify_roce_cc { + /* Command opcode. */ + uint8_t opcode; + /* Modify congestion control. Can only be issued from a PF. */ + #define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c) + #define CMDQ_MODIFY_ROCE_CC_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Modify mask signifies the field that is requesting the change. */ + uint32_t modify_mask; + /* Enable change. */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC UINT32_C(0x1) + /* Running average weight change. */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G UINT32_C(0x2) + /* Number of phases in Fast Recovery. */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE UINT32_C(0x4) + /* The starting value of rate change. */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR UINT32_C(0x8) + /* The starting value of target rate change. */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR UINT32_C(0x10) + /* IP TOS ECN change */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN UINT32_C(0x20) + /* IP TOS DSCP change */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP UINT32_C(0x40) + /* Alternate IP TOS ECN change */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP UINT32_C(0x80) + /* Alternate IP TOS DSCP change */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP UINT32_C(0x100) + /* Round trip time in units of usecs */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT UINT32_C(0x200) + /* Congestion Control mode */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE UINT32_C(0x400) + /* The value used as CP when cc_mode is 1(TCP) */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP UINT32_C(0x800) + /* Specifies the RoCE Tx Queue to use for sending CNP packets */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE UINT32_C(0x1000) + /* Inactivity time after which QP CC parameters are initialized */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP UINT32_C(0x2000) + /* Amount of time per phase in units of ms. Max is 15. */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE UINT32_C(0x4000) + /* Number of packets per phase. Max is 255. */ + #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE UINT32_C(0x8000) + uint8_t enable_cc; + /* Enable. */ + #define CMDQ_MODIFY_ROCE_CC_ENABLE_CC UINT32_C(0x1) + /* rsvd1 is 7 b */ + #define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK UINT32_C(0xfe) + #define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1 + /* Congestion Probability averaging factor. */ + uint8_t g; + /* Number of phases in Fast Recovery. */ + uint8_t num_phases_per_state; + /* Number of packets per phase. Max is 255. */ + uint8_t pkts_per_phase; + /* + * The starting value of rate. + * The max value supported for CC support level 1 is 1024. + */ + uint16_t init_cr; + /* + * The starting value of target rate. + * The max value supported for CC support level 1 is 1024. + */ + uint16_t init_tr; + uint8_t tos_dscp_tos_ecn; + /* IP TOS ECN. Valid values are 1 or 2 when ECN is enabled. */ + #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK UINT32_C(0x3) + #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0 + /* IP TOS DSCP. */ + #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK UINT32_C(0xfc) + #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2 + uint8_t alt_vlan_pcp; + /* Alternate vlan pcp value for CNP packets. */ + #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK UINT32_C(0x7) + #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0 + /* rsvd3 is 5 b */ + #define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK UINT32_C(0xf8) + #define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3 + uint16_t alt_tos_dscp; + /* Alternate IP TOS DSCP. */ + #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK UINT32_C(0x3f) + #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0 + /* rsvd4 is 10 b */ + #define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK UINT32_C(0xffc0) + #define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6 + uint16_t rtt; + /* + * Round trip time in units of usecs. + * The max value supported for CC support level 1 is 2047. + */ + #define CMDQ_MODIFY_ROCE_CC_RTT_MASK UINT32_C(0x3fff) + #define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0 + /* rsvd5 is 2 b */ + #define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK UINT32_C(0xc000) + #define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14 + uint16_t tcp_cp; + /* The value used as CP when cc_mode is 1(TCP) */ + #define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK UINT32_C(0x3ff) + #define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0 + /* rsvd6 is 6 b */ + #define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK UINT32_C(0xfc00) + #define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10 + uint8_t cc_mode; + /* DCTCP */ + #define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE UINT32_C(0x0) + /* + * Probabilistic marking. On chips with CC Gen 0 support this + * will be TCP CC algorithm. + */ + #define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE UINT32_C(0x1) + #define CMDQ_MODIFY_ROCE_CC_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE + /* + * Specifies the RoCE Tx Queue to use for sending CNP packets. + * CC support level 0 support 0 to 3 Tx queues. + * CC support level 1 supports 0 to 7 Tx queues. + */ + uint8_t tx_queue; + /* Inactivity time after which QP CC parameters are initialized */ + uint16_t inactivity_th; + /* Amount of time per phase in units of ms. Max is 15 */ + uint8_t time_per_phase; + /* reserved8 is 8 b */ + uint8_t reserved8_1; + /* reserved16 is 16 b */ + uint16_t reserved16; + uint32_t reserved32; + uint64_t reserved64; +} cmdq_modify_roce_cc_t, *pcmdq_modify_roce_cc_t; + +/* + * TLV encapsulated modify CC command, with extended TLV record + * included for specifying the extended configuration for CC level 1. + */ +/* cmdq_modify_roce_cc_tlv (size:640b/80B) */ + +typedef struct cmdq_modify_roce_cc_tlv { + /* + * The command discriminator is used to differentiate between various + * types of HWRM messages. This includes legacy HWRM and RoCE slowpath + * command messages as well as newer TLV encapsulated HWRM commands. + * + * For TLV encapsulated messages this field must be 0x8000. + */ + uint16_t cmd_discr; + uint8_t reserved_8b; + uint8_t tlv_flags; + /* + * Indicates the presence of additional TLV encapsulated data + * follows this TLV. + */ + #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE UINT32_C(0x1) + /* Last TLV in a sequence of TLVs. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) + /* More TLVs follow this TLV. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + /* + * When an HWRM receiver detects a TLV type that it does not + * support with the TLV required flag set, the receiver must + * reject the HWRM message with an error code indicating an + * unsupported TLV type. + */ + #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) + /* No */ + #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) + /* Yes */ + #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) + #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES + /* + * This field defines the TLV type value which is divided into + * two ranges to differentiate between global and local TLV types. + * Global TLV types must be unique across all defined TLV types. + * Local TLV types are valid only for extensions to a given + * HWRM message and may be repeated across different HWRM message + * types. There is a direct correlation of each HWRM message type + * to a single global TLV type value. + * + * Global TLV range: `0 - (63k-1)` + * + * Local TLV range: `63k - (64k-1)` + */ + uint16_t tlv_type; + /* + * Length of the message data encapsulated by this TLV in bytes. + * This length does not include the size of the TLV header itself + * and it must be an integer multiple of 8B. + */ + uint16_t length; + /* + * Size of the tlv encapsulated command, including all tlvs and + * extension data in 16-byte units. + */ + uint8_t total_size; + uint8_t reserved56[7]; + /* Command opcode. */ + uint8_t opcode; + /* Modify congestion control. Can only be issued from a PF. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c) + #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Modify mask signifies the field that is requesting the change. */ + uint32_t modify_mask; + /* Enable change. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC UINT32_C(0x1) + /* Running average weight change. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G UINT32_C(0x2) + /* Number of phases in Fast Recovery. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE UINT32_C(0x4) + /* The starting value of rate change. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR UINT32_C(0x8) + /* The starting value of target rate change. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR UINT32_C(0x10) + /* IP TOS ECN change */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN UINT32_C(0x20) + /* IP TOS DSCP change */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP UINT32_C(0x40) + /* Alternate IP TOS ECN change */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP UINT32_C(0x80) + /* Alternate IP TOS DSCP change */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP UINT32_C(0x100) + /* Round trip time in units of usecs */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT UINT32_C(0x200) + /* Congestion Control mode */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE UINT32_C(0x400) + /* The value used as CP when cc_mode is 1(TCP) */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP UINT32_C(0x800) + /* Specifies the RoCE Tx Queue to use for sending CNP packets */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE UINT32_C(0x1000) + /* Inactivity time after which QP CC parameters are initialized */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP UINT32_C(0x2000) + /* Amount of time per phase in units of ms. Max is 15. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE UINT32_C(0x4000) + /* Number of packets per phase. Max is 255. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE UINT32_C(0x8000) + uint8_t enable_cc; + /* Enable. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC UINT32_C(0x1) + /* rsvd1 is 7 b */ + #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK UINT32_C(0xfe) + #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_SFT 1 + /* Congestion Probability averaging factor. */ + uint8_t g; + /* Number of phases in Fast Recovery. */ + uint8_t num_phases_per_state; + /* Number of packets per phase. Max is 255. */ + uint8_t pkts_per_phase; + /* + * The starting value of rate. + * The max value supported for CC support level 1 is 1024. + */ + uint16_t init_cr; + /* + * The starting value of target rate. + * The max value supported for CC support level 1 is 1024. + */ + uint16_t init_tr; + uint8_t tos_dscp_tos_ecn; + /* IP TOS ECN. Valid values are 1 or 2 when ECN is enabled. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK UINT32_C(0x3) + #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0 + /* IP TOS DSCP. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK UINT32_C(0xfc) + #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_SFT 2 + uint8_t alt_vlan_pcp; + /* Alternate vlan pcp value for CNP packets. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK UINT32_C(0x7) + #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0 + /* rsvd3 is 5 b */ + #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK UINT32_C(0xf8) + #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_SFT 3 + uint16_t alt_tos_dscp; + /* Alternate IP TOS DSCP. */ + #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK UINT32_C(0x3f) + #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0 + /* rsvd4 is 10 b */ + #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK UINT32_C(0xffc0) + #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_SFT 6 + uint16_t rtt; + /* + * Round trip time in units of usecs. + * The max value supported for CC support level 1 is 2047. + */ + #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK UINT32_C(0x3fff) + #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0 + /* rsvd5 is 2 b */ + #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK UINT32_C(0xc000) + #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_SFT 14 + uint16_t tcp_cp; + /* The value used as CP when cc_mode is 1(TCP) */ + #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK UINT32_C(0x3ff) + #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0 + /* rsvd6 is 6 b */ + #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK UINT32_C(0xfc00) + #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_SFT 10 + uint8_t cc_mode; + /* DCTCP */ + #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE UINT32_C(0x0) + /* + * Probabilistic marking. On chips with CC Gen 0 support this + * will be TCP CC algorithm. + */ + #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE UINT32_C(0x1) + #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE + /* + * Specifies the RoCE Tx Queue to use for sending CNP packets. + * CC support level 0 support 0 to 3 Tx queues. + * CC support level 1 supports 0 to 7 Tx queues. + */ + uint8_t tx_queue; + /* Inactivity time after which QP CC parameters are initialized */ + uint16_t inactivity_th; + /* Amount of time per phase in units of ms. Max is 15 */ + uint8_t time_per_phase; + /* reserved8 is 8 b */ + uint8_t reserved8_1; + /* reserved16 is 16 b */ + uint16_t reserved16; + uint32_t reserved32; + uint64_t reserved64; + uint64_t reservedtlvpad; +} cmdq_modify_roce_cc_tlv_t, *pcmdq_modify_roce_cc_tlv_t; + +/* cmdq_modify_roce_cc_gen1_tlv (size:768b/96B) */ + +typedef struct cmdq_modify_roce_cc_gen1_tlv { + /* + * The command discriminator is used to differentiate between various + * types of HWRM messages. This includes legacy HWRM and RoCE slowpath + * command messages as well as newer TLV encapsulated HWRM commands. + * + * For TLV encapsulated messages this field must be 0x8000. + */ + uint16_t cmd_discr; + uint8_t reserved_8b; + uint8_t tlv_flags; + /* + * Indicates the presence of additional TLV encapsulated data + * follows this TLV. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE UINT32_C(0x1) + /* Last TLV in a sequence of TLVs. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) + /* More TLVs follow this TLV. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + /* + * When an HWRM receiver detects a TLV type that it does not + * support with the TLV required flag set, the receiver must + * reject the HWRM message with an error code indicating an + * unsupported TLV type. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) + /* No */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) + /* Yes */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES + /* + * This field defines the TLV type value which is divided into + * two ranges to differentiate between global and local TLV types. + * Global TLV types must be unique across all defined TLV types. + * Local TLV types are valid only for extensions to a given + * HWRM message and may be repeated across different HWRM message + * types. There is a direct correlation of each HWRM message type + * to a single global TLV type value. + * + * Global TLV range: `0 - (63k-1)` + * + * Local TLV range: `63k - (64k-1)` + */ + uint16_t tlv_type; + /* + * Length of the message data encapsulated by this TLV in bytes. + * This length does not include the size of the TLV header itself + * and it must be an integer multiple of 8B. + */ + uint16_t length; + uint64_t reserved64; + /* Modify mask signifies the field that is requesting the change. */ + uint64_t modify_mask; + /* + * Update the number of uS between generation of CNPs for + * probabilistic marking mode. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS UINT32_C(0x1) + /* + * Update starting value of Congestion Probability (CP). + * Maximum value supported is 1023. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP UINT32_C(0x2) + /* Update Target Rate (TR) Update Mode. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE UINT32_C(0x4) + /* Update number of RTTs with CNPs in a row for TR update. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES UINT32_C(0x8) + /* Update number of RTTs in Fast Recovery stage. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS UINT32_C(0x10) + /* Update time increment to increase TR in active increase phase. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE UINT32_C(0x20) + /* + * Update count of RTTs with CNPs, received after + * the first one, to wait, before reducing rate. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH UINT32_C(0x40) + /* + * Update additional number of RTTS with CNPs, to wait, + * before further rate reduction, for low rates. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH UINT32_C(0x80) + /* Update threshold for update to Actual Current Rate (CR) */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH UINT32_C(0x100) + /* Update log based averaging weight for QPC variable actual_cr */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT UINT32_C(0x200) + /* Update factor used in the computation of rate reduction. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR UINT32_C(0x400) + /* Update the level of CR above which CP is set to maximum level. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH UINT32_C(0x800) + /* Enable adding fraction of CR to CP. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN UINT32_C(0x1000) + /* + * Update log based fraction of CR to add to CP + * when cp_bias_en is 1. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS UINT32_C(0x2000) + /* Update ECN bits in a CNP packet generated by hardware. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN UINT32_C(0x4000) + /* Update enable of jitter in RTT. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN UINT32_C(0x8000) + /* Update number of bytes per usec. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC UINT32_C(0x10000) + /* + * Update threshold used to reset QPC CC state to its initial + * state. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH UINT32_C(0x20000) + /* Update number of valid lsbits in CR and TR */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH UINT32_C(0x40000) + /* Update lower end of random selection of quota_period. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN UINT32_C(0x80000) + /* Update upper end of random selection of quota_period. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX UINT32_C(0x100000) + /* + * Update absolute maximum possible quota_period, + * when rate table for lower 24 levels is used. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX UINT32_C(0x200000) + /* Update lower bound of TR. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND UINT32_C(0x400000) + /* + * Update factor on probability threshold for adding + * 0.5 to CR randomly. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR UINT32_C(0x800000) + /* + * Update factor on probability threshold for adding + * 0.5 to TR randomly. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR UINT32_C(0x1000000) + /* + * Update threshold that ensures fairness between requester + * and responder + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH UINT32_C(0x2000000) + /* Update log based rate reduction divider. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV UINT32_C(0x4000000) + /* + * Update threshold for rate reductions when CNPS received + * over last RTT. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH UINT32_C(0x8000000) + /* + * Update extended number of RTTS to wait, + * when there is no congestion, to start doubling the rate. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS UINT32_C(0x10000000) + /* Update log based CR to CP ratio used in exponential increase. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO UINT32_C(0x20000000) + /* + * Update threshold, in congestion free RTTs, + * that triggers start of CP update to track CR. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH UINT32_C(0x40000000) + /* + * Update threshold on congestion free RTTs above + * which AI can increase to 16. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 UINT32_C(0x80000000) + /* + * Update threshold on congestion free RTTs above + * which AI can increase to 32. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 UINT32_C(0x100000000)L + /* Update use of lowest 24 rate levels rate_table. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE UINT32_C(0x200000000)L + /* + * Update the maximum number of 64B that can be transmitted + * during RTT time. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT UINT32_C(0x400000000)L + /* + * Update number of congestion free RTTs above which + * reduction based on actual rate is enabled. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH UINT32_C(0x800000000)L + /* + * Update threshold used in severe congestion for + * limiting TR to 1.5 times CR. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 UINT32_C(0x1000000000)L + /* + * Update threshold used in severe congestion for + * limiting TR to 1.25 times CR. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 UINT32_C(0x2000000000)L + /* + * Update number of bytes to subtract from QPC.cc_bucket + * when an ack is scheduled. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES UINT32_C(0x4000000000)L + /* Update enable of reduction of CR, TR, and CP to init values. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN UINT32_C(0x8000000000)L + /* + * Update threshold used for reduction of CR, TR, and CP to init + * values. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH UINT32_C(0x10000000000)L + /* Update enable of random no reduction of CR. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN UINT32_C(0x20000000000)L + /* Update enable of coarse correction to actual CR. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN UINT32_C(0x40000000000)L + /* Update enable of adjustment to refill quota. */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN UINT32_C(0x80000000000)L + /* High order bits of inactivity threshold. */ + uint16_t inactivity_th_hi; + /* + * The number of uS between generation of CNPs when cc_mode is + * probabilistic marking. + */ + uint16_t min_time_between_cnps; + /* + * The starting value of congestion probability. Input range + * is 0 - 1023. + */ + uint16_t init_cp; + /* + * In tr_update_mode 0, Target Rate (TR) is updated to + * halfway between the Current Rate (CR) before and after reduction. + * In tr_update_mode 1, TR is updated to CR's value before reduction. + */ + uint8_t tr_update_mode; + /* + * Determine for how many RTTs with CNPs in a row, TR is being updated. + * 0: TR is updated when QPC. rtts_with_cnps == 0 + * 1-6: TR is updated if QPC. rtts_with_cnps <= tr_update_cycles + * 7: TR is updated on all reductions. + */ + uint8_t tr_update_cycles; + /* Number of RTTs in Fast Recovery stage. */ + uint8_t fr_num_rtts; + /* Time increment to increase TR in active increase phase. */ + uint8_t ai_rate_increase; + /* + * Indicates for how many RTTs with CNPs after the first one + * to not reduce rate even if CNPs are received. + */ + uint16_t reduction_relax_rtts_th; + /* + * For low rates, additional number of RTTS with CNPs + * for which no rate reduction is made. + * num_bits: 14 + */ + uint16_t additional_relax_cr_th; + /* + * If CR is less than or equal to this value, + * then the actual CR average is set to this value + * (shifted by bw_avg_weight). + */ + uint16_t cr_min_th; + /* Log based averaging weight for QPC variable actual_cr_avg. */ + uint8_t bw_avg_weight; + /* + * Used to compare CR to this factor times QPC.actual_cr_average + * as a reduction reference. Values between 0 and 6 represent factor of + * 1.125, 1.25, 1.5, 1.75, 2, 2.25, 2.5 respectively. + */ + uint8_t actual_cr_factor; + /* The level of CR above which CP is set to maximum level. */ + uint16_t max_cp_cr_th; + /* + * Enable adding fraction of CR to CP. + * 0 for disable, 1 for enable. + */ + uint8_t cp_bias_en; + /* Log based fraction of cr to add to CP when cp_bias_en is 1. */ + uint8_t cp_bias; + /* + * The value of ECN bits in a CNP packet generated by hardware. + * ECN-Capable Transport (ECT) codepoints supported include: + * 0 for not_ect, 1 for ect_0, 2 for ect_1 + */ + uint8_t cnp_ecn; + /* Not ECN capable Transport */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT UINT32_C(0x0) + /* ECN Capable Transport-1 */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 UINT32_C(0x1) + /* ECN Capable Transport-0 */ + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 UINT32_C(0x2) + #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 + /* Enables jitter in RTT. */ + uint8_t rtt_jitter_en; + /* + * Number of bytes per usec, dependent on port speed. + * 200 Gbps: 25,000 + * 100 Gbps: 12,500 + * 50 Gbps: 6,250 + * 25 Gbps: 3125 + * 10 Gbps: 1250 + */ + uint16_t link_bytes_per_usec; + /* + * If CR is greater than or equal to this threshold, + * QPC's CC state is reset to its initial state. + */ + uint16_t reset_cc_cr_th; + /* + * The number of valid lsbits in CR and TR. + * Supported values include 10 through 14 to support 2^cr_width rate. + */ + uint8_t cr_width; + /* Lower end of random selection of quota_period. */ + uint8_t quota_period_min; + /* Upper end of random selection of quota_period. */ + uint8_t quota_period_max; + /* + * The absolute maximum possible quota_period, + * applicable when rate table for lower 24 levels is used. + */ + uint8_t quota_period_abs_max; + /* TR never goes below this level. */ + uint16_t tr_lower_bound; + /* Factor on probability threshold for adding 0.5 to CR randomly. */ + uint8_t cr_prob_factor; + /* Factor on probability threshold for adding 0.5 to TR randomly. */ + uint8_t tr_prob_factor; + /* + * Threshold to ensure fairness between requester and responder. + * If CR is less than the fairness threshold and a quota period has + * passed priority will be given to the path that did not last + * transfer data. + */ + uint16_t fairness_cr_th; + /* Log based rate reduction divider. */ + uint8_t red_div; + /* Threshold for rate reductions when CNPS received over last RTT. */ + uint8_t cnp_ratio_th; + /* + * Extended number of RTTS to wait, when there is no congestion, + * to start doubling the rate. + */ + uint16_t exp_ai_rtts; + /* Log based CR to CP ratio used in exponential increase. */ + uint8_t exp_ai_cr_cp_ratio; + /* Enable use of lowest 24 rate levels rate_table. */ + uint8_t use_rate_table; + /* + * Determines after how many congestion free RTTs to start + * updating CP to track CR. + */ + uint16_t cp_exp_update_th; + /* + * The threshold on congestion free RTTs above which AI can increase + * to 16. + */ + uint16_t high_exp_ai_rtts_th1; + /* + * The threshold on congestion free RTTs above which AI can increase + * to 32. + */ + uint16_t high_exp_ai_rtts_th2; + /* + * The number of congestion free RTTs above which + * reduction based on actual rate is enabled. + */ + uint16_t actual_cr_cong_free_rtts_th; + /* + * If rtts_with_cong is greater than 7 (severe congestion) and + * CR level post reduction is above this threshold, + * then TR is capped to 1.5 times CR.. + */ + uint16_t severe_cong_cr_th1; + /* + * If rtts_with_cong is greater than 7 (severe congestion) and + * CR level post reduction is above this threshold, + * then TR is capped to 1.25 times CR.. + */ + uint16_t severe_cong_cr_th2; + /* + * The maximum number of 64B that can be transmitted during RTT time, + * including all headers and Inter Packet Gap. + */ + uint32_t link64B_per_rtt; + /* + * The number of bytes to subtract from QPC.cc_bucket + * when an ack is scheduled. + */ + uint8_t cc_ack_bytes; + /* + * Enables reduction of CR, TR, and CP to init values when + * congestion free RTTs is greater than reduce2_init_cong_free_rtts_th. + */ + uint8_t reduce_init_en; + /* + * Minimum threshold value for number of congestion free RTTs before + * reducing to init values for CR, TR, and CP when reduce_init_en is + * enabled. + */ + uint16_t reduce_init_cong_free_rtts_th; + /* Enables random no reduction of CR. */ + uint8_t random_no_red_en; + /* + * Enables coarse correction to actual CR when actual RTT is longer + * than nominal. + */ + uint8_t actual_cr_shift_correction_en; + /* Enables adjustment to refill quota. */ + uint8_t quota_period_adjust_en; + uint8_t reserved[5]; +} cmdq_modify_roce_cc_gen1_tlv_t, *pcmdq_modify_roce_cc_gen1_tlv_t; + +/* cmdq_modify_roce_cc_gen2_tlv (size:256b/32B) */ + +typedef struct cmdq_modify_roce_cc_gen2_tlv { + /* + * The command discriminator is used to differentiate between various + * types of HWRM messages. This includes legacy HWRM and RoCE slowpath + * command messages as well as newer TLV encapsulated HWRM commands. + * + * For TLV encapsulated messages this field must be 0x8000. + */ + uint16_t cmd_discr; + uint8_t reserved_8b; + uint8_t tlv_flags; + /* + * Indicates the presence of additional TLV encapsulated data + * follows this TLV. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE UINT32_C(0x1) + /* Last TLV in a sequence of TLVs. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) + /* More TLVs follow this TLV. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + /* + * When an HWRM receiver detects a TLV type that it does not + * support with the TLV required flag set, the receiver must + * reject the HWRM message with an error code indicating an + * unsupported TLV type. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) + /* No */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) + /* Yes */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_YES + /* + * This field defines the TLV type value which is divided into + * two ranges to differentiate between global and local TLV types. + * Global TLV types must be unique across all defined TLV types. + * Local TLV types are valid only for extensions to a given + * HWRM message and may be repeated across different HWRM message + * types. There is a direct correlation of each HWRM message type + * to a single global TLV type value. + * + * Global TLV range: `0 - (63k-1)` + * + * Local TLV range: `63k - (64k-1)` + */ + uint16_t tlv_type; + /* + * Length of the message data encapsulated by this TLV in bytes. + * This length does not include the size of the TLV header itself + * and it must be an integer multiple of 8B. + */ + uint16_t length; + uint64_t reserved64; + /* Modify mask signifies the field that is requesting the change. */ + uint64_t modify_mask; + /* + * Modify the specific DCN queue level table index data. + * This must be set, to select the table index that needs an + * update. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_IDX UINT32_C(0x1) + /* Modify the DCN queue level threshold. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_THR UINT32_C(0x2) + /* Modify DCN queue level current rate. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_CR UINT32_C(0x4) + /* Modify DCN queue level increment CNP count. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_INC_CNP UINT32_C(0x8) + /* Modify DCN queue level update current & target rate immediately. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_UPD_IMM UINT32_C(0x10) + /* Modify DCN queue level target rate. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_TR UINT32_C(0x20) + /* DCN queue level table index. Valid values are from 0 to 7. */ + uint8_t dcn_qlevel_tbl_idx; + uint8_t reserved8; + /* + * DCN queue level threshold value associated with a DCN queue + * level table index. + */ + uint16_t dcn_qlevel_tbl_thr; + /* + * DCN queue level table action. + * Updates CR, INC_CNP, UPD_IMM & TR fields associated with the + * DCN queue level table index. + */ + uint32_t dcn_qlevel_tbl_act; + /* DCN queue level current rate. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK UINT32_C(0x3fff) + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT 0 + /* DCN queue level increment CNP count. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP UINT32_C(0x4000) + /* DCN queue level update CR and TR immediately. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM UINT32_C(0x8000) + /* DCN queue level target rate */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK UINT32_C(0x3fff0000) + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_TR_SFT 16 +} cmdq_modify_roce_cc_gen2_tlv_t, *pcmdq_modify_roce_cc_gen2_tlv_t; + +/* creq_modify_roce_cc_resp (size:128b/16B) */ + +typedef struct creq_modify_roce_cc_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_LAST CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_MODIFY_ROCE_CC_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Modify congestion control response. */ + #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC UINT32_C(0x8c) + #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_LAST CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC + uint8_t reserved48[6]; +} creq_modify_roce_cc_resp_t, *pcreq_modify_roce_cc_resp_t; + +/****************************** + * cmdq_set_link_aggr_mode_cc * + ******************************/ + + +/* cmdq_set_link_aggr_mode_cc (size:320b/40B) */ + +typedef struct cmdq_set_link_aggr_mode_cc { + /* Command opcode. */ + uint8_t opcode; + /* Set LAG mode. */ + #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE UINT32_C(0x8f) + #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_LAST CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Modify mask signifies the field that is requesting the change. */ + uint32_t modify_mask; + /* Enable Link aggregation. */ + #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN UINT32_C(0x1) + /* Bitmap of ports that are eligible to transmit RoCE traffic. */ + #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP UINT32_C(0x2) + /* Bitmap of ports that are members of the RoCE LAG. */ + #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP UINT32_C(0x4) + /* Link aggregation mode being used. */ + #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE UINT32_C(0x8) + /* Stat context ID for all the ports. */ + #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID UINT32_C(0x10) + uint8_t aggr_enable; + /* Enable Link aggregation. */ + #define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE UINT32_C(0x1) + /* rsvd1 is 7 b */ + #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK UINT32_C(0xfe) + #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_SFT 1 + uint8_t active_port_map; + /* Bitmap of ports that are eligible to transmit RoCE traffic. */ + #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK UINT32_C(0xf) + #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0 + /* rsvd2 is 4 b */ + #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK UINT32_C(0xf0) + #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_SFT 4 + /* Bitmap of ports that are members of the RoCE LAG. */ + uint8_t member_port_map; + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_LAST CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD + /* Stat context IDs for all 4 ports. */ + uint16_t stat_ctx_id[4]; + uint64_t rsvd1; +} cmdq_set_link_aggr_mode_cc_t, *pcmdq_set_link_aggr_mode_cc_t; + +/* creq_set_link_aggr_mode_resources_resp (size:128b/16B) */ + +typedef struct creq_set_link_aggr_mode_resources_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_LAST CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_SET_LINK_AGGR_MODE_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Set LAG mode. */ + #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE UINT32_C(0x8f) + #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_LAST CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE + uint8_t reserved48[6]; +} creq_set_link_aggr_mode_resources_resp_t, *pcreq_set_link_aggr_mode_resources_resp_t; + +/* Send a request from VF to pass a command to the PF. VF HSI is suspended. */ +/* cmdq_vf_backchannel_request (size:256b/32B) */ + +typedef struct cmdq_vf_backchannel_request { + /* Command opcode. */ + uint8_t opcode; + /* + * Send a request from VF to pass a command to the PF. VF HSI is + * suspended until the PF returns the response. + */ + #define CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86) + #define CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_LAST CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_VF_BACKCHANNEL_REQUEST + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Address of command request structure in VF space */ + uint64_t command_addr; + /* + * Command request length (up to 4K). An optional address of the extended + * response buffer should be provided in the request. + */ + uint16_t command_length; + uint8_t unused_0[6]; +} cmdq_vf_backchannel_request_t, *pcmdq_vf_backchannel_request_t; + +/* Read VF memory (primarily to get the backchannel request blob). */ +/* cmdq_read_vf_memory (size:256b/32B) */ + +typedef struct cmdq_read_vf_memory { + /* Command opcode. */ + uint8_t opcode; + /* + * Read VF memory (primarily to get the backchannel request blob). Can + * only be issued from a PF. + */ + #define CMDQ_READ_VF_MEMORY_OPCODE_READ_VF_MEMORY UINT32_C(0x87) + #define CMDQ_READ_VF_MEMORY_OPCODE_LAST CMDQ_READ_VF_MEMORY_OPCODE_READ_VF_MEMORY + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Address of memory in VF space to read */ + uint64_t addr; + /* VF id, as provided in 0xC0 VF request notification */ + uint16_t vf_id; + /* Length to read, up to 4K */ + uint16_t length; + uint32_t unused_0; +} cmdq_read_vf_memory_t, *pcmdq_read_vf_memory_t; + +/* Write VF memory (primarily to put the backchannel response blob). */ +/* cmdq_complete_vf_request (size:320b/40B) */ + +typedef struct cmdq_complete_vf_request { + /* Command opcode. */ + uint8_t opcode; + /* + * Write VF memory (primarily to put the backchannel response blob), + * and reenable VF HSI (post a CAG completion to it). Can only be + * issued from a PF. + */ + #define CMDQ_COMPLETE_VF_REQUEST_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88) + #define CMDQ_COMPLETE_VF_REQUEST_OPCODE_LAST CMDQ_COMPLETE_VF_REQUEST_OPCODE_COMPLETE_VF_REQUEST + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* + * Optional address of extended response in VF space to write. Length is + * in resp_size in 16 byte units. + */ + uint64_t addr; + /* Completion misc field to VF CREQ */ + uint32_t vf_misc; + /* VF id, as provided in 0xC0 VF request notification */ + uint16_t vf_id; + /* Completion cookie for the VF command, goes to VF CREQ */ + uint16_t vf_cookie; + /* Completion status for the VF command, goes to VF CREQ */ + uint8_t vf_status; + uint8_t unused_0[3]; + uint32_t unused_1; +} cmdq_complete_vf_request_t, *pcmdq_complete_vf_request_t; + +/***************************** + * orchestrate_qid_migration * + *****************************/ + + +/* cmdq_orchestrate_qid_migration (size:256b/32B) */ + +typedef struct cmdq_orchestrate_qid_migration { + /* Command opcode. */ + uint8_t opcode; + /* + * This command updates the QP context id ranges on the PF, + * to orchestrate QP context id range migration for devices that + * support the pseudo-static QP allocation feature. + */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_OPCODE_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93) + #define CMDQ_ORCHESTRATE_QID_MIGRATION_OPCODE_LAST CMDQ_ORCHESTRATE_QID_MIGRATION_OPCODE_ORCHESTRATE_QID_MIGRATION + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + uint8_t qid_migration_flags; + /* Flags to orchestrate QP context ID range migration amongst PFs. */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_MASK UINT32_C(0xf) + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_SFT 0 + /* Enable the PF's native QP context ID range. */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_ENABLE_NATIVE_QID_RANGE UINT32_C(0x0) + /* Enable the PF's extended QP context ID range. */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_ENABLE_EXTENDED_QID_RANGE UINT32_C(0x1) + /* Disable the PF's native QP context ID range. */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_NATIVE_QID_RANGE UINT32_C(0x2) + /* Disable the PF's extended QP context ID range. */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_EXTENDED_QID_RANGE UINT32_C(0x3) + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_LAST CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_EXTENDED_QID_RANGE + /* unused4 is 4 b */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_UNUSED4_MASK UINT32_C(0xf0) + #define CMDQ_ORCHESTRATE_QID_MIGRATION_UNUSED4_SFT 4 + uint8_t reserved56[7]; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_orchestrate_qid_migration_t, *pcmdq_orchestrate_qid_migration_t; + +/* creq_orchestrate_qid_migration_resp (size:128b/16B) */ + +typedef struct creq_orchestrate_qid_migration_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_LAST CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Orchestrate QPID migration command response. */ + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_EVENT_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93) + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_EVENT_LAST CREQ_ORCHESTRATE_QID_MIGRATION_RESP_EVENT_ORCHESTRATE_QID_MIGRATION + uint8_t reserved48[6]; +} creq_orchestrate_qid_migration_resp_t, *pcreq_orchestrate_qid_migration_resp_t; + +/******************* + * create_qp_batch * + *******************/ + + +/* cmdq_create_qp_batch (size:384b/48B) */ + +typedef struct cmdq_create_qp_batch { + /* Command opcode. */ + uint8_t opcode; + /* This command allocates a batch of QPs in a sequential range. */ + #define CMDQ_CREATE_QP_BATCH_OPCODE_CREATE_QP_BATCH UINT32_C(0x94) + #define CMDQ_CREATE_QP_BATCH_OPCODE_LAST CMDQ_CREATE_QP_BATCH_OPCODE_CREATE_QP_BATCH + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Starting QP context id to be used for the sequential range. */ + uint32_t start_xid; + /* Count of QPs to be allocated */ + uint32_t count; + /* Size of an individual element of the qp_params_array. */ + uint32_t per_qp_param_size; + uint32_t reserved32; + /* + * Host DMA address of the array of per-QP parameters. + * Per-QP parameters are identical to those of the + * `create_qp` command and specified by the + * `create_qp_batch_data` structure. + */ + uint64_t qp_params_array; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_create_qp_batch_t, *pcmdq_create_qp_batch_t; + +/* creq_create_qp_batch_resp (size:128b/16B) */ + +typedef struct creq_create_qp_batch_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_CREATE_QP_BATCH_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_CREATE_QP_BATCH_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_CREATE_QP_BATCH_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_CREATE_QP_BATCH_RESP_TYPE_LAST CREQ_CREATE_QP_BATCH_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_CREATE_QP_BATCH_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Create batch QPs command response. */ + #define CREQ_CREATE_QP_BATCH_RESP_EVENT_CREATE_QP_BATCH UINT32_C(0x94) + #define CREQ_CREATE_QP_BATCH_RESP_EVENT_LAST CREQ_CREATE_QP_BATCH_RESP_EVENT_CREATE_QP_BATCH + uint16_t reserved16; + /* Count of QPs successfully created. */ + uint32_t count; +} creq_create_qp_batch_resp_t, *pcreq_create_qp_batch_resp_t; + +/******************** + * destroy_qp_batch * + ********************/ + + +/* cmdq_destroy_qp_batch (size:256b/32B) */ + +typedef struct cmdq_destroy_qp_batch { + /* Command opcode. */ + uint8_t opcode; + /* + * This command deletes the batch of requested count of QPs. + * The starting QP ID can be specified to request a batch deletion + * of a sequential range. + */ + #define CMDQ_DESTROY_QP_BATCH_OPCODE_DESTROY_QP_BATCH UINT32_C(0x95) + #define CMDQ_DESTROY_QP_BATCH_OPCODE_LAST CMDQ_DESTROY_QP_BATCH_OPCODE_DESTROY_QP_BATCH + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Starting QP context id to be used for the sequential range. */ + uint32_t start_xid; + /* + * Count of QPs to be deleted. A value of zero implies all QPs + * are to be deleted. + */ + uint32_t count; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_destroy_qp_batch_t, *pcmdq_destroy_qp_batch_t; + +/* creq_destroy_qp_batch_resp (size:128b/16B) */ + +typedef struct creq_destroy_qp_batch_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DESTROY_QP_BATCH_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DESTROY_QP_BATCH_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DESTROY_QP_BATCH_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DESTROY_QP_BATCH_RESP_TYPE_LAST CREQ_DESTROY_QP_BATCH_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DESTROY_QP_BATCH_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Destroy batch QPs command response. */ + #define CREQ_DESTROY_QP_BATCH_RESP_EVENT_DESTROY_QP_BATCH UINT32_C(0x95) + #define CREQ_DESTROY_QP_BATCH_RESP_EVENT_LAST CREQ_DESTROY_QP_BATCH_RESP_EVENT_DESTROY_QP_BATCH + uint16_t reserved16; + /* Count of QPs successfully destroyed. */ + uint32_t count; +} creq_destroy_qp_batch_resp_t, *pcreq_destroy_qp_batch_resp_t; + +/******************************* + * allocate_roce_stats_ext_ctx * + *******************************/ + + +/* cmdq_allocate_roce_stats_ext_ctx (size:256b/32B) */ + +typedef struct cmdq_allocate_roce_stats_ext_ctx { + /* Command opcode. */ + uint8_t opcode; + /* + * This command allocates an extended RoCE statistics context + * that supports periodic DMA to a host address. The extended + * statistics context id can be assigned by the driver, + * via `create_qp`, `create_qp_batch` or `modify_qp` to a + * specific QP, a subset of QPs or to all QPs of a specific function. + * These statistics can be queried via `query_roce_stats_ext_v2`. + */ + #define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96) + #define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_LAST CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* + * This is the address to be programmed in the statistic block + * by the firmware to support periodic DMA of the statistics. + */ + uint64_t stats_dma_addr; + /* + * The statistic block update period in ms. + * e.g. 250ms, 500ms, 750ms, 1000ms. + * If update_period_ms is 0, then the stats update + * shall be never done and the DMA address shall not be used. + * In this case, the statistics can only be read by + * `query_roce_stats_ext_v2` command. + */ + uint32_t update_period_ms; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + uint16_t reserved16; +} cmdq_allocate_roce_stats_ext_ctx_t, *pcmdq_allocate_roce_stats_ext_ctx_t; + +/* creq_allocate_roce_stats_ext_ctx_resp (size:128b/16B) */ + +typedef struct creq_allocate_roce_stats_ext_ctx_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_LAST CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Extended RoCE statistics context id. */ + uint32_t roce_stats_ext_xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Allocate extended RoCE statistics context command response. */ + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96) + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_LAST CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_ALLOCATE_ROCE_STATS_EXT_CTX + uint8_t reserved48[6]; +} creq_allocate_roce_stats_ext_ctx_resp_t, *pcreq_allocate_roce_stats_ext_ctx_resp_t; + +/********************************* + * deallocate_roce_stats_ext_ctx * + *********************************/ + + +/* cmdq_deallocate_roce_stats_ext_ctx (size:256b/32B) */ + +typedef struct cmdq_deallocate_roce_stats_ext_ctx { + /* Command opcode. */ + uint8_t opcode; + /* This command deallocates an extended RoCE statistics context. */ + #define CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97) + #define CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_LAST CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Extended RoCE statistics context id. */ + uint32_t roce_stats_ext_xid; + uint32_t reserved32; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_deallocate_roce_stats_ext_ctx_t, *pcmdq_deallocate_roce_stats_ext_ctx_t; + +/* creq_deallocate_roce_stats_ext_ctx_resp (size:128b/16B) */ + +typedef struct creq_deallocate_roce_stats_ext_ctx_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_LAST CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Extended RoCE statistics context id. */ + uint32_t roce_stats_ext_xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Deallocate extended RoCE statistics context command response. */ + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97) + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_LAST CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_DEALLOCATE_ROCE_STATS_EXT_CTX + uint8_t reserved48[6]; +} creq_deallocate_roce_stats_ext_ctx_resp_t, *pcreq_deallocate_roce_stats_ext_ctx_resp_t; + +/*************************** + * query_roce_stats_ext_v2 * + ***************************/ + + +/* cmdq_query_roce_stats_ext_v2 (size:256b/32B) */ + +typedef struct cmdq_query_roce_stats_ext_v2 { + /* Command opcode. */ + uint8_t opcode; + /* + * Query extended RoCE statistics for devices that support + * `roce_stats_ext_ctx_supported` feature. + */ + #define CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98) + #define CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_QUERY_ROCE_STATS_EXT_V2 + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Extended RoCE statistics context id. */ + uint32_t roce_stats_ext_xid; + uint32_t reserved32; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_query_roce_stats_ext_v2_t, *pcmdq_query_roce_stats_ext_v2_t; + +/* creq_query_roce_stats_ext_v2_resp (size:128b/16B) */ + +typedef struct creq_query_roce_stats_ext_v2_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Side buffer size in 16-byte units */ + uint32_t size; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Query extended RoCE statistics v2. */ + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98) + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_QUERY_ROCE_STATS_EXT_V2 + uint8_t reserved48[6]; +} creq_query_roce_stats_ext_v2_resp_t, *pcreq_query_roce_stats_ext_v2_resp_t; + +/* Query extended RoCE Stats command response side buffer structure. */ +/* creq_query_roce_stats_ext_v2_resp_sb (size:1920b/240B) */ + +typedef struct creq_query_roce_stats_ext_v2_resp_sb { + /* Command opcode. */ + uint8_t opcode; + /* Query extended RoCE statistics v2. */ + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98) + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT_V2 + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t rsvd; + /* Number of transmitted Atomic request packets without errors. */ + uint64_t tx_atomic_req_pkts; + /* Number of transmitted Read request packets without errors. */ + uint64_t tx_read_req_pkts; + /* Number of transmitted Read response packets without errors. */ + uint64_t tx_read_res_pkts; + /* Number of transmitted Write request packets without errors. */ + uint64_t tx_write_req_pkts; + /* Number of transmitted RC Send packets without errors. */ + uint64_t tx_rc_send_req_pkts; + /* + * Number of transmitted UD Send (including QP1) packets + * without errors. + */ + uint64_t tx_ud_send_req_pkts; + /* Number of transmitted CNPs. Includes DCN_CNPs. */ + uint64_t tx_cnp_pkts; + /* + * Number of transmitted RoCE packets. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t tx_roce_pkts; + /* + * Number of transmitted RoCE header and payload bytes. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t tx_roce_bytes; + /* + * Number of drops that occurred to lack of buffers. + * This count includes RC sends, RC writes with immediate, + * UD sends, RawEth, and QP1 packets dropped due to lack of buffers. + */ + uint64_t rx_out_of_buffer_pkts; + /* Number of packets that were received out of sequence. */ + uint64_t rx_out_of_sequence_pkts; + /* + * Number of duplicate read/atomic requests resulting in responder + * hardware retransmission. + */ + uint64_t dup_req; + /* + * Number of missing response packets resulting in hardware + * retransmission. + */ + uint64_t missing_resp; + /* + * Number of sequence error NAKs received resulting in hardware + * retransmission. + */ + uint64_t seq_err_naks_rcvd; + /* Number of RNR NAKs received resulting in hardware retransmission. */ + uint64_t rnr_naks_rcvd; + /* Number of timeouts resulting in hardware retransmission. */ + uint64_t to_retransmits; + /* Number of received Atomic request packets without errors. */ + uint64_t rx_atomic_req_pkts; + /* Number of received Read request packets without errors. */ + uint64_t rx_read_req_pkts; + /* Number of received Read response packets without errors. */ + uint64_t rx_read_res_pkts; + /* Number of received Write request packets without errors. */ + uint64_t rx_write_req_pkts; + /* Number of received RC Send packets without errors. */ + uint64_t rx_rc_send_pkts; + /* Number of received UD Send packets without errors. */ + uint64_t rx_ud_send_pkts; + /* Number of received DCN payload cut packets. */ + uint64_t rx_dcn_payload_cut; + /* Number of received ECN-marked packets. */ + uint64_t rx_ecn_marked_pkts; + /* Number of received CNP packets. Includes DCN_CNPs. */ + uint64_t rx_cnp_pkts; + /* + * Number of received RoCE packets including RoCE packets with errors. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t rx_roce_pkts; + /* + * Number of received RoCE header and payload bytes including RoCE + * packets with errors. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t rx_roce_bytes; + /* + * Number of received RoCE packets without errors. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t rx_roce_good_pkts; + /* + * Number of received RoCE header and payload bytes without errors. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t rx_roce_good_bytes; +} creq_query_roce_stats_ext_v2_resp_sb_t, *pcreq_query_roce_stats_ext_v2_resp_sb_t; + +/* RoCE function async event notifications. */ +/* creq_func_event (size:128b/16B) */ + +typedef struct creq_func_event { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_FUNC_EVENT_TYPE_MASK UINT32_C(0x3f) + #define CREQ_FUNC_EVENT_TYPE_SFT 0 + /* Function Async Notification */ + #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT UINT32_C(0x3a) + #define CREQ_FUNC_EVENT_TYPE_LAST CREQ_FUNC_EVENT_TYPE_FUNC_EVENT + uint8_t reserved56[7]; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_FUNC_EVENT_V UINT32_C(0x1) + /* + * This value defines what type of async event has occurred + * on the function. + */ + uint8_t event; + /* + * Invalid PBL or PCIE UR response occurred + * in SQ WQE or IRRQ read access. + */ + #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR UINT32_C(0x1) + /* + * Invalid PBL or PCIE UR response occurred + * during data read access. + */ + #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR UINT32_C(0x2) + /* + * Invalid PBL or PCIE UR response occurred + * in RQ/SRQ WQE or ORRQ read access. + */ + #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR UINT32_C(0x3) + /* Invalid PBL occurred during data write access. */ + #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR UINT32_C(0x4) + /* Invalid PBL occurred during CQ write access. */ + #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR UINT32_C(0x5) + /* + * Invalid PBL or PCIE UR response occurred in TQM + * read access. + */ + #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR UINT32_C(0x6) + /* PCIE UR response occurred in CFC read access. */ + #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR UINT32_C(0x7) + /* PCIE UR response occurred in CFC read access. */ + #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR UINT32_C(0x8) + /* PCIE UR response occurred in CFC read access. */ + #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR UINT32_C(0x9) + /* PCIE UR response occurred in CFC read access. */ + #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR UINT32_C(0xa) + /* + * Invalid PBL or + * PCIE UR response + * occurred on timer read access. + */ + #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR UINT32_C(0xb) + /* A VF sent a backchannel command request */ + #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST UINT32_C(0x80) + /* + * Communication resource (QPC, CQ, SRQ, MRW) exhausted, and resource + * array extension is enabled. + */ + #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED UINT32_C(0x81) + #define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED + uint8_t reserved48[6]; +} creq_func_event_t, *pcreq_func_event_t; + +/* RoCE slowpath command completion events. */ +/* creq_qp_event (size:128b/16B) */ + +typedef struct creq_qp_event { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QP_EVENT_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QP_EVENT_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QP_EVENT_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QP_EVENT_TYPE_LAST CREQ_QP_EVENT_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Success. */ + #define CREQ_QP_EVENT_STATUS_SUCCESS UINT32_C(0x0) + /* Fail. */ + #define CREQ_QP_EVENT_STATUS_FAIL UINT32_C(0x1) + /* Resources. */ + #define CREQ_QP_EVENT_STATUS_RESOURCES UINT32_C(0x2) + /* Invalid command. */ + #define CREQ_QP_EVENT_STATUS_INVALID_CMD UINT32_C(0x3) + /* Not implemented. */ + #define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED UINT32_C(0x4) + /* Invalid parameter. */ + #define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER UINT32_C(0x5) + /* Hardware operation failed. */ + #define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR UINT32_C(0x6) + /* Firmware operation failed due to internal error. */ + #define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR UINT32_C(0x7) + #define CREQ_QP_EVENT_STATUS_LAST CREQ_QP_EVENT_STATUS_INTERNAL_ERROR + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QP_EVENT_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Create QP command response. */ + #define CREQ_QP_EVENT_EVENT_CREATE_QP UINT32_C(0x1) + /* Destroy QP command response. */ + #define CREQ_QP_EVENT_EVENT_DESTROY_QP UINT32_C(0x2) + /* Modify QP command response. */ + #define CREQ_QP_EVENT_EVENT_MODIFY_QP UINT32_C(0x3) + /* Query QP command response. */ + #define CREQ_QP_EVENT_EVENT_QUERY_QP UINT32_C(0x4) + /* Create SRQ command response. */ + #define CREQ_QP_EVENT_EVENT_CREATE_SRQ UINT32_C(0x5) + /* Destroy SRQ command response. */ + #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ UINT32_C(0x6) + /* Query SRQ command response. */ + #define CREQ_QP_EVENT_EVENT_QUERY_SRQ UINT32_C(0x8) + /* Create CQ command response. */ + #define CREQ_QP_EVENT_EVENT_CREATE_CQ UINT32_C(0x9) + /* Destroy CQ command response. */ + #define CREQ_QP_EVENT_EVENT_DESTROY_CQ UINT32_C(0xa) + /* Resize CQ command response. */ + #define CREQ_QP_EVENT_EVENT_RESIZE_CQ UINT32_C(0xc) + /* Allocate MRW command response. */ + #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW UINT32_C(0xd) + /* De-allocate key command response. */ + #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY UINT32_C(0xe) + /* Register MR command response. */ + #define CREQ_QP_EVENT_EVENT_REGISTER_MR UINT32_C(0xf) + /* Deregister MR command response. */ + #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR UINT32_C(0x10) + /* Add GID command response. */ + #define CREQ_QP_EVENT_EVENT_ADD_GID UINT32_C(0x11) + /* Delete GID command response. */ + #define CREQ_QP_EVENT_EVENT_DELETE_GID UINT32_C(0x12) + /* Modify GID command response. */ + #define CREQ_QP_EVENT_EVENT_MODIFY_GID UINT32_C(0x17) + /* Query GID command response. */ + #define CREQ_QP_EVENT_EVENT_QUERY_GID UINT32_C(0x18) + /* Create QP1 command response. */ + #define CREQ_QP_EVENT_EVENT_CREATE_QP1 UINT32_C(0x13) + /* Destroy QP1 command response. */ + #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 UINT32_C(0x14) + /* Create AH command response. */ + #define CREQ_QP_EVENT_EVENT_CREATE_AH UINT32_C(0x15) + /* Destroy AH command response. */ + #define CREQ_QP_EVENT_EVENT_DESTROY_AH UINT32_C(0x16) + /* Initialize firmware command response. */ + #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW UINT32_C(0x80) + /* De-initialize firmware command response. */ + #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW UINT32_C(0x81) + /* Stop PF command response. */ + #define CREQ_QP_EVENT_EVENT_STOP_FUNC UINT32_C(0x82) + /* Query info PF command response. */ + #define CREQ_QP_EVENT_EVENT_QUERY_FUNC UINT32_C(0x83) + /* Set function resources command response. */ + #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84) + /* + * Read the current state of any internal resource context. Can only be + * issued from a PF. + */ + #define CREQ_QP_EVENT_EVENT_READ_CONTEXT UINT32_C(0x85) + /* Map TC to COS response. */ + #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS UINT32_C(0x8a) + /* Query firmware and interface version response. */ + #define CREQ_QP_EVENT_EVENT_QUERY_VERSION UINT32_C(0x8b) + /* Modify congestion control response. */ + #define CREQ_QP_EVENT_EVENT_MODIFY_CC UINT32_C(0x8c) + /* Query congestion control response. */ + #define CREQ_QP_EVENT_EVENT_QUERY_CC UINT32_C(0x8d) + /* Query RoCE statistics. */ + #define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS UINT32_C(0x8e) + /* Set LAG mode. */ + #define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE UINT32_C(0x8f) + /* + * Query QP for a PF other than the requesting PF. Also can query for + * more than one QP. + */ + #define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND UINT32_C(0x91) + /* QP error notification event. */ + #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0) + /* CQ error notification event. */ + #define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION UINT32_C(0xc1) + #define CREQ_QP_EVENT_EVENT_LAST CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION + uint8_t reserved48[6]; +} creq_qp_event_t, *pcreq_qp_event_t; + +/* QP error notification event. */ +/* creq_qp_error_notification (size:128b/16B) */ + +typedef struct creq_qp_error_notification { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QP_ERROR_NOTIFICATION_TYPE_LAST CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* requestor slow path state */ + uint8_t req_slow_path_state; + /* requestor error reason */ + uint8_t req_err_state_reason; + /* No error. */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR UINT32_C(0x0) + /* + * Requester detected opcode error. + * * First, only, middle, last for incoming RDMA read + * responses are improperly ordered with respect to previous + * (PSN) packet. + * * First or middle packet is not full MTU size. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR UINT32_C(0x1) + /* + * Transport timeout retry limit exceeded. + * The requestor retried the same unacked PSN request packet + * too many times. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT UINT32_C(0x2) + /* + * RNR NAK retry limit exceeded. + * The requestor received an RNR NAK with the same NAK PSN + * too many times. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT UINT32_C(0x3) + /* + * NAK arrival, When NAK code is 1, Invalid Request. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 UINT32_C(0x4) + /* + * NAK arrival, When NAK code is 2, Remote Access Error. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 UINT32_C(0x5) + /* + * NAK arrival, When NAK code is 3, Remote Operational Error. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 UINT32_C(0x6) + /* + * NAK arrival. When NAK code is 4, Invalid RD Request. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 UINT32_C(0x7) + /* + * Local memory error. + * An SGE described an inaccessible memory. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR UINT32_C(0x8) + /* + * Local memory error. + * An SGE described an inaccessible memory. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR UINT32_C(0x9) + /* + * Read response length error. + * The read response payload size does not match the read + * length of the request. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH UINT32_C(0xa) + /* + * Invalid read response. + * A read response arrived and had a PSN that was not in the + * reply range of any outstanding read request on the ORRQ. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP UINT32_C(0xb) + /* + * Illegal bind. + * * No MW with the specified R_Key exists. + * * No MR with the specified L_Key exists. + * * A bind request was performed on a window that was already + * bound. + * * A bind request was performed for an underlying MR that + * is not registered. + * * A bind request was performed for a memory area that exceeds + * the range of the underlying MR. + * * A bind request was performed with a set of permissions + * that are looser than the permissions of the underlying MR. + * * Domain error MW - When QP's PD does not match MW PD. + * * Domain error MR - When QP's PD does not match parent MR's + * PD. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND UINT32_C(0xc) + /* + * Illegal fast register. + * * No MR with the specified L_Key exists. + * * A fast register request was performed on a non- + * physical MR. + * * A fast register request was performed on a physical MR + * that is already registered. + * * A fast register request was performed on a physical MR + * that does not have a page list allocated (has not been + * initialized). + * * The number of pages being registered exceeds the capacity + * of the physical MR. + * * The length of the registration is not possible with the + * actual number of pages provided. + * * Domain error - when QP's PD does not match PMR PD. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG UINT32_C(0xd) + /* + * Illegal invalidate. + * * No MR with the specified L_Key exists. + * * No MW with the specified R_Key exists. + * * An invalidate was performed against a non-physical MR. + * * An invalidate was performed against a physical MR that + * is not registered. + * * An invalidate was performed against a MW that is not + * bound. + * * The PD of the MR/MW being invalidated does not match the PD + * of the QP. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE UINT32_C(0xe) + /* + * Completion Error. + * No CQE space available on queue, or CQ not in VALID state. + * This is a Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR UINT32_C(0xf) + /* + * Local memory error while retransmitting WQE. + * An SQ SGE described an inaccessible memory. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR UINT32_C(0x10) + /* + * Problem found in the format of a WQE in the SQ. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR UINT32_C(0x11) + /* + * Problem was found in the format of an ORRQ entry. + * This is a RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR UINT32_C(0x12) + /* + * A UD send attempted to use an invalid AVID. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR UINT32_C(0x13) + /* + * A UD send attempted to use an AVID that is outside of its + * QP's protection domain. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR UINT32_C(0x14) + /* + * A load error occurred on an attempt to load the CQ Context. + * This is a Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR UINT32_C(0x15) + /* + * There was an attempt to process a WQE from the SQ that + * corresponds to an operation that is unsupported for the + * corresponding QP. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR UINT32_C(0x16) + /* + * There was an attempt to process a WQE from the SQ that + * corresponds to an operation that is unsupported for the + * corresponding QP, according to the supported_operations QPC + * field. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR UINT32_C(0x17) + /* + * A fatal error was detected on an attempt to read from + * or write to PCIe on the transmit side. This error is + * detected by the TX side (or CAGR), but has the priority + * of a Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR UINT32_C(0x18) + /* + * A fatal error was detected on an attempt to read from + * or write to PCIe on the receive side. This error is detected + * by the RX side (or CAGR), but has the priority of a + * Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR UINT32_C(0x19) + /* + * When processing a WQE from the SQ, TWE detected an error + * such that the wqe_size given in the header is larger than + * the delta between sq_work_idx and sq_prod_idx. This error + * has priority over the non-error case that occurs when TWE + * detects that it simply doesn't have enough slots fetched + * to execute the WQE during the current residency. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR UINT32_C(0x1a) + /* + * When reading the MSN table to initiate HW retransmit, RWE + * found that to_retransmit_psn was not within the range defined + * by start_psn and next_psn in the corresponding MSN table + * entry. To_retransmit_psn must be greater than or equal to + * start_psn and less than next_psn in order for the range check + * to succeed. + * This is a RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR UINT32_C(0x1b) + /* + * While retransmitting, TWE detected one of several possible + * error detection scenarios related to the improper setup of + * retransmission. These include a category or errors known as + * retx_end_error where the retransmission end does not line up + * sequentially with the WQE index and PSN upon continuing on + * with the regular transmission that follows the + * retransmission. It also includes the error condition in which + * the retransmission Work Request has gen_dup_read_request set + * and the WQE fetched by TWE is not an RDMA Read or Atomic WQE. + * Please see TWE requirements for a full list of the various + * possible retransmit setup error cases. These error cases + * apply to H/W and F/W retransmission, alike. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR UINT32_C(0x1c) + /* + * An express doorbell was posted that overflowed the SQ. The + * doorbell is dropped, along with all subsequent doorbells for + * this SQ. This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SQ_OVERFLOW UINT32_C(0x1d) + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_LAST CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SQ_OVERFLOW + /* QP context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QP_ERROR_NOTIFICATION_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* QP error notification event. */ + #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0) + #define CREQ_QP_ERROR_NOTIFICATION_EVENT_LAST CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION + /* responder slow path state */ + uint8_t res_slow_path_state; + uint8_t res_err_state_reason; + /* No error. */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR UINT32_C(0x0) + /* + * Incoming Send, RDMA write, or RDMA read exceeds the maximum + * transfer length. Detected on RX first and only packets for + * write. Detected on RX request for read. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX UINT32_C(0x1) + /* + * RDMA write payload size does not match write length. Detected + * when total write payload is not equal to the RDMA write + * length that was given in the first or only packet of the + * request. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH UINT32_C(0x2) + /* + * Send payload exceeds RQ/SRQ WQE buffer capacity. The total + * send payload that arrived is more than the size of the WQE + * buffer that was fetched from the RQ/SRQ. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE UINT32_C(0x3) + /* + * Responder detected opcode error. + * * First, only, middle, last or incoming requests are + * improperly ordered with respect to previous (PSN) packet. + * * First or middle packet is not full MTU size. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR UINT32_C(0x4) + /* + * PSN sequence error retry limit exceeded. + * The responder encountered a PSN sequence error for the + * same PSN too many times. This can occur via implicit or + * explicit NAK. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT UINT32_C(0x5) + /* + * Invalid R_Key. + * An incoming request contained an R_Key that did not reference + * a valid MR/MW. This error may be detected by the RX engine + * for RDMA write or by the TX engine for RDMA read + * (detected while servicing IRRQ). + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY UINT32_C(0x6) + /* + * Domain error. + * An incoming request specified an R_Key which + * referenced a MR/MW that was not in the same PD as the QP on + * which the request arrived. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR UINT32_C(0x7) + /* + * No permission. + * An incoming request contained an R_Key that referenced a + * MR/MW which did not have the access permission needed for + * the operation. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION UINT32_C(0x8) + /* + * Range error. + * An incoming request had a combination of R_Key,VA, and + * length that was out of bounds of the associated MR/MW. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR UINT32_C(0x9) + /* + * Invalid R_Key. + * An incoming request contained an R_Key that did not + * reference a valid MR/MW. This error may be detected + * by the RX engine for RDMA write or by the TX engine + * for RDMA read (detected while servicing IRRQ). + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY UINT32_C(0xa) + /* + * Domain error. + * An incoming request specified an R_Key which referenced + * a MR/MW that was not in the same PD as the QP on + * which the request arrived. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR UINT32_C(0xb) + /* + * No permission. + * An incoming request contained an R_Key that referenced a + * MR/MW which did not have the access permission needed for + * the operation. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION UINT32_C(0xc) + /* + * Range error. + * An incoming request had a combination of R_Key, VA, and + * length that was out of bounds of the associated MR/MW. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR UINT32_C(0xd) + /* + * IRRQ overflow. + * The peer sent us more RDMA read or atomic requests than + * the negotiated maximum. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW UINT32_C(0xe) + /* + * Unsupported opcode. + * The peer sent us a request with an opcode for a request + * type that is not supported on this QP. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE UINT32_C(0xf) + /* + * Unaligned atomic operation. The VA of an atomic request + * is on a memory boundary that prevents atomic execution. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC UINT32_C(0x10) + /* + * Remote invalidate error. + * A send with invalidate request arrived in which the + * R_Key to invalidate did not describe a MR/MW which could + * be invalidated. RQ WQE completes with error status. + * This error is only reported if the send operation did + * not fail. If the send operation failed then the remote + * invalidate error is not reported. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE UINT32_C(0x11) + /* + * Local memory error. An RQ/SRQ SGE described an inaccessible + * memory. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR UINT32_C(0x12) + /* + * SRQ in error. The QP is moving to error state because it + * found SRQ it uses in error. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR UINT32_C(0x13) + /* + * Completion error. No CQE space available on queue or CQ not + * in VALID state. + * This is a Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR UINT32_C(0x14) + /* + * Invalid R_Key while resending responses to duplicate request. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY UINT32_C(0x15) + /* + * Problem was found in the format of a WQE in the RQ/SRQ. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR UINT32_C(0x16) + /* + * Problem was found in the format of an IRRQ entry. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR UINT32_C(0x17) + /* + * A load error occurred on an attempt to load the CQ Context. + * This is a Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR UINT32_C(0x18) + /* + * A load error occurred on an attempt to load the SRQ Context. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR UINT32_C(0x19) + /* + * A fatal error was detected on an attempt to read from or + * write to PCIe on the transmit side. This error is detected + * by the TX side, but has the priority of a Completion + * Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR UINT32_C(0x1b) + /* + * A fatal error was detected on an attempt to read from or + * write to PCIe on the receive side. This error is detected + * by the RX side (or CAGR), but has the priority of a Completion + * Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR UINT32_C(0x1c) + /* + * When searching the IRRQ to respond to a duplicate request, + * RWE could not find the duplicate request in the entire IRRQ. + * This is a RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND UINT32_C(0x1d) + /* + * An express doorbell was posted that overflowed the RQ. The + * doorbell is dropped, along with all subsequent doorbells for + * this RQ. This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RQ_OVERFLOW UINT32_C(0x1e) + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_LAST CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RQ_OVERFLOW + /* + * Final SQ Consumer Index value. Any additional SQ WQEs will + * have to be completed by the user provider. + */ + uint16_t sq_cons_idx; + /* + * Final RQ Consumer Index value. Any additional RQ WQEs will + * have to be completed by the user provider. + */ + uint16_t rq_cons_idx; +} creq_qp_error_notification_t, *pcreq_qp_error_notification_t; + +/* CQ error notification event. */ +/* creq_cq_error_notification (size:128b/16B) */ + +typedef struct creq_cq_error_notification { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK UINT32_C(0x3f) + #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0 + /* CQ Async Notification */ + #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT UINT32_C(0x38) + #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_LAST CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT + /* Status of the response. */ + uint8_t status; + /* CQ error reason code. */ + uint8_t cq_err_reason; + /* Requester completion error for invalid CQ state. */ + #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR UINT32_C(0x1) + /* Requester completion error for CQ overflow. */ + #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR UINT32_C(0x2) + /* Attempt to load CQ context resulted in error. */ + #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR UINT32_C(0x3) + /* Responder completion error for invalid CQ state. */ + #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR UINT32_C(0x4) + /* Responder completion error for CQ overflow. */ + #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR UINT32_C(0x5) + /* Attempt to load CQ context resulted in error. */ + #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR UINT32_C(0x6) + #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_LAST CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR + uint8_t reserved8; + /* CQ context id */ + uint32_t xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_CQ_ERROR_NOTIFICATION_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* CQ error notification event. */ + #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION UINT32_C(0xc1) + #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_LAST CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION + uint8_t reserved48[6]; +} creq_cq_error_notification_t, *pcreq_cq_error_notification_t; + +/* sq_base (size:64b/8B) */ + +typedef struct sq_base { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Send */ + #define SQ_BASE_WQE_TYPE_SEND UINT32_C(0x0) + /* + * Send with Immediate + * + * Allowed only on reliable connection (RC) and + * unreliable datagram (UD) SQs. + */ + #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1) + /* + * Send with Invalidate. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2) + /* + * RDMA Write. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_WRITE_WQE UINT32_C(0x4) + /* + * RDMA Write with Immediate. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5) + /* + * RDMA Read. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_READ_WQE UINT32_C(0x6) + /* + * Atomic Compare/Swap. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_ATOMIC_CS UINT32_C(0x8) + /* + * Atomic Fetch/Add. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_ATOMIC_FA UINT32_C(0xb) + /* + * Local Invalidate. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc) + /* + * FR-PMR (Fast Register Physical Memory Region) + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_FR_PMR UINT32_C(0xd) + /* + * Memory Bind + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_BIND UINT32_C(0xe) + /* + * FR-PPMR (Fast Register Proxy Physical Memory Region) + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_FR_PPMR UINT32_C(0xf) + /* Send V3 */ + #define SQ_BASE_WQE_TYPE_SEND_V3 UINT32_C(0x10) + /* + * Send with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11) + /* + * Send with Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12) + /* + * UD Send V3 + * + * Allowed only on unreliable datagram (UD) SQs. + */ + #define SQ_BASE_WQE_TYPE_UDSEND_V3 UINT32_C(0x13) + /* + * UD Send with Immediate V3 + * + * Allowed only on unreliable datagram (UD) SQs. + */ + #define SQ_BASE_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14) + /* + * RDMA Write V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15) + /* + * RDMA Write with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16) + /* + * RDMA Read V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17) + /* + * Atomic Compare/Swap V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18) + /* + * Atomic Fetch/Add V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19) + /* + * Local Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a) + /* + * FR-PMR (Fast Register Physical Memory Region) V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b) + /* + * Memory Bind V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_BIND_V3 UINT32_C(0x1c) + /* RawEth/QP1 Send V3 */ + #define SQ_BASE_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d) + /* Change UDP Source Port V3 */ + #define SQ_BASE_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e) + #define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_CHANGE_UDPSRCPORT_V3 + uint8_t unused_0[7]; +} sq_base_t, *psq_base_t; + +/* + * Most SQ WQEs contain SGEs used to define the SGL used to map payload + * data in host memory. The number of SGE structures is defined by the + * wqe_size field. SGE structures are aligned to 16B boundaries. + * + * In backward-compatible modes there can be 2, 4 or 6 SGEs (based on + * the mode). In variable-sized WQE mode there can be 0-30 SGE + * structures. + */ +/* sq_sge (size:128b/16B) */ + +typedef struct sq_sge { + /* + * The virtual address in local memory or a physical address + * when l_key value is a reserved value of a physical address. + * Driver configures this value in the chip and the chip compares + * l_key in SGEs with that reserved value, if equal it access + * the physical address specified. The chip however MUST verify + * that the QP allows the use reserved key. + */ + uint64_t va_or_pa; + /* + * Local Key associated with this registered MR; The 24 msb of + * the key used to index the MRW Table and the 8 lsb are compared + * with the 8 bits key part stored in the MRWC. The PBL in the + * MRW Context is used to translate the above VA to physical + * address. + */ + uint32_t l_key; + /* + * Size of SGE in bytes; Based on page size of the system the + * chip knows how many entries are in the PBL + */ + uint32_t size; +} sq_sge_t, *psq_sge_t; + +/* sq_psn_search (size:64b/8B) */ + +typedef struct sq_psn_search { + /* Start PSN. */ + uint32_t opcode_start_psn; + /* Start PSN. */ + #define SQ_PSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff) + #define SQ_PSN_SEARCH_START_PSN_SFT 0 + /* The opcodes are software defined. */ + #define SQ_PSN_SEARCH_OPCODE_MASK UINT32_C(0xff000000) + #define SQ_PSN_SEARCH_OPCODE_SFT 24 + uint32_t flags_next_psn; + /* Next PSN. Equal to the start PSN of the next WQE. */ + #define SQ_PSN_SEARCH_NEXT_PSN_MASK UINT32_C(0xffffff) + #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0 + /* Opcode specific flags. */ + #define SQ_PSN_SEARCH_FLAGS_MASK UINT32_C(0xff000000) + #define SQ_PSN_SEARCH_FLAGS_SFT 24 +} sq_psn_search_t, *psq_psn_search_t; + +/* This PSN table structure is used only on devices where variable size WQEs are supported. */ +/* sq_psn_search_ext (size:128b/16B) */ + +typedef struct sq_psn_search_ext { + /* Start PSN. */ + uint32_t opcode_start_psn; + /* Start PSN. */ + #define SQ_PSN_SEARCH_EXT_START_PSN_MASK UINT32_C(0xffffff) + #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0 + /* The opcodes are software defined. */ + #define SQ_PSN_SEARCH_EXT_OPCODE_MASK UINT32_C(0xff000000) + #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24 + uint32_t flags_next_psn; + /* Next PSN. Equal to the start PSN of the next WQE. */ + #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK UINT32_C(0xffffff) + #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0 + /* Opcode specific flags. */ + #define SQ_PSN_SEARCH_EXT_FLAGS_MASK UINT32_C(0xff000000) + #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24 + /* + * This field is used only when variable sized WQEs are being used. + * This indicates the starting slot index of the corresponding WQE. + */ + uint16_t start_slot_idx; + /* reserved16 is 16 b */ + uint16_t reserved16; + /* reserved32 is 32 b */ + uint32_t reserved32; +} sq_psn_search_ext_t, *psq_psn_search_ext_t; + +/* This MSN table structure is used only on devices where Hardware based Requester retransmission is used. */ +/* sq_msn_search (size:64b/8B) */ + +typedef struct sq_msn_search { + /* MSN search entry. */ + uint64_t start_idx_next_psn_start_psn; + /* Start PSN. */ + #define SQ_MSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff) + #define SQ_MSN_SEARCH_START_PSN_SFT 0 + /* Next PSN. Equal to the start PSN of the next WQE. */ + #define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL + #define SQ_MSN_SEARCH_NEXT_PSN_SFT 24 + /* + * For variable-size WQEs, this field indicates the starting + * slot index that corresponds to the WQE. + * In backward-compatible mode, this is the starting WQE index. + */ + #define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL + #define SQ_MSN_SEARCH_START_IDX_SFT 48 +} sq_msn_search_t, *psq_msn_search_t; + +/* Send SQ WQE */ +/* sq_send (size:1024b/128B) */ + +typedef struct sq_send { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Send */ + #define SQ_SEND_WQE_TYPE_SEND UINT32_C(0x0) + /* + * Send with Immediate + * + * Allowed only on reliable connection (RC) and + * unreliable datagram (UD) SQs. + */ + #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1) + /* + * Send with Invalidate. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_SEND_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2) + #define SQ_SEND_WQE_TYPE_LAST SQ_SEND_WQE_TYPE_SEND_W_INVALID + uint8_t flags; + #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_SEND_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * For local invalidate request. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. This bit should be set only in the last (or only) packet + * of the message. + */ + #define SQ_SEND_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_SEND_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_SEND_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_SEND_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * While this field defines the valid WQE size. The actual + * total WQE size is always 128B. + */ + uint8_t wqe_size; + uint8_t reserved8_1; + /* + * Either invalidate key (R_Key of the remote host) that will + * be send with IETH (Invalidate ETH) if wqe_type is of Send + * with Invalidate, or immediate value that will be sent with + * ImmDt header if wqe_type is Send with Immediate. + */ + uint32_t inv_key_or_imm_data; + /* This field represents a 32-bit total data length, in bytes. */ + uint32_t length; + /* + * When in the SQ of a UD QP, indicates the q_key to be used in + * the transmitted packet. However, if the most significant bit + * of this field is set, then the q_key will be taken from QP + * context, rather than from this field. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. + */ + uint32_t q_key; + /* + * When in the SQ of a UD QP, indicates the destination QP to be + * used in the transmitted packet. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. + */ + uint32_t dst_qp; + #define SQ_SEND_DST_QP_MASK UINT32_C(0xffffff) + #define SQ_SEND_DST_QP_SFT 0 + uint32_t avid; + /* + * If the serv_type is 'UD', then this field supplies the AVID + * (Address Vector ID). + */ + #define SQ_SEND_AVID_MASK UINT32_C(0xfffff) + #define SQ_SEND_AVID_SFT 0 + uint32_t reserved32; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_SEND_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_SEND_TIMESTAMP_SFT 0 + /* + * When inline=0, then this area is filled with from 1 to 6 + * SGEs based on the wqe_size field. + * + * When inline=1, this area is filled with payload data for the + * send based on the length_or_AVID field. Bits [7:0] of word 0 + * hold the first byte to go out on the wire. + */ + uint32_t data[24]; +} sq_send_t, *psq_send_t; + +/* Send SQ WQE header. */ +/* sq_send_hdr (size:256b/32B) */ + +typedef struct sq_send_hdr { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Send */ + #define SQ_SEND_HDR_WQE_TYPE_SEND UINT32_C(0x0) + /* + * Send with Immediate + * + * Allowed only on reliable connection (RC) and + * unreliable datagram (UD) SQs. + */ + #define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1) + /* + * Send with Invalidate. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2) + #define SQ_SEND_HDR_WQE_TYPE_LAST SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID + uint8_t flags; + #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_SEND_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * For local invalidate request. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. This bit should be set only in the last (or only) packet + * of the message. + */ + #define SQ_SEND_HDR_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_SEND_HDR_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_SEND_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_SEND_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * While this field defines the valid WQE size. The actual + * total WQE size is always 128B. + */ + uint8_t wqe_size; + uint8_t reserved8_1; + /* + * Either invalidate key (R_Key of the remote host) that will + * be send with IETH (Invalidate ETH) if wqe_type is of Send + * with Invalidate, or immediate value that will be sent with + * ImmDt header if wqe_type is Send with Immediate. + */ + uint32_t inv_key_or_imm_data; + /* This field represents a 32-bit total data length, in bytes. */ + uint32_t length; + /* + * When in the SQ of a UD QP, indicates the q_key to be used in + * the transmitted packet. However, if the most significant bit + * of this field is set, then the q_key will be taken from QP + * context, rather than from this field. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. + */ + uint32_t q_key; + /* + * When in the SQ of a UD QP, indicates the destination QP to be + * used in the transmitted packet. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. + */ + uint32_t dst_qp; + #define SQ_SEND_HDR_DST_QP_MASK UINT32_C(0xffffff) + #define SQ_SEND_HDR_DST_QP_SFT 0 + uint32_t avid; + /* + * If the serv_type is 'UD', then this field supplies the AVID + * (Address Vector ID). + */ + #define SQ_SEND_HDR_AVID_MASK UINT32_C(0xfffff) + #define SQ_SEND_HDR_AVID_SFT 0 + uint32_t reserved32; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_SEND_HDR_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_SEND_HDR_TIMESTAMP_SFT 0 +} sq_send_hdr_t, *psq_send_hdr_t; + +/* Send Raw Ethernet and QP1 SQ WQE */ +/* sq_send_raweth_qp1 (size:1024b/128B) */ + +typedef struct sq_send_raweth_qp1 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Send */ + #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND UINT32_C(0x0) + #define SQ_SEND_RAWETH_QP1_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND + uint8_t flags; + #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* This flag must be zero for a Raweth or QP1 send. */ + #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* This flag must be zero for a Raweth or QP1 send. */ + #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE UINT32_C(0x4) + /* This flag must be zero for a Raweth or QP1 send. */ + #define SQ_SEND_RAWETH_QP1_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * While this field defines the valid WQE size. The actual + * total WQE size is always 128B. + */ + uint8_t wqe_size; + uint8_t reserved8; + /* + * All bits in this field must be valid on the first BD of a packet. + * Their value on other BDs of the packet will be ignored. + */ + uint16_t lflags; + /* + * If set to 1, the controller replaces the TCP/UPD checksum + * fields of normal TCP/UPD checksum, or the inner TCP/UDP + * checksum field of the encapsulated TCP/UDP packets with the + * hardware calculated TCP/UDP checksum for the packet associated + * with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) + /* + * If set to 1, the controller replaces the IP checksum of the + * normal packets, or the inner IP checksum of the encapsulated + * packets with the hardware calculated IP checksum for the + * packet associated with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM UINT32_C(0x2) + /* + * If set to 1, the controller will not append an Ethernet CRC + * to the end of the frame. + * + * This bit must be valid on the first BD of a packet. + * + * Packet must be 64B or longer when this flag is set. It is not + * useful to use this bit with any form of TX offload such as + * CSO or LSO. The intent is that the packet from the host already + * has a valid Ethernet CRC on the packet. + */ + #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC UINT32_C(0x4) + /* + * If set to 1, the device will record the time at which the packet + * was actually transmitted at the TX MAC. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP UINT32_C(0x8) + /* + * If set to 1, The controller replaces the tunnel IP checksum + * field with hardware calculated IP checksum for the IP header + * of the packet associated with this descriptor. In case of + * VXLAN, the controller also replaces the outer header UDP + * checksum with hardware calculated UDP checksum for the packet + * associated with this descriptor. + */ + #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) + /* + * If set to '1', then the RoCE ICRC will be appended to the + * packet. Packet must be a valid RoCE format packet. + */ + #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC UINT32_C(0x100) + /* + * If set to '1', then the FCoE CRC will be appended to the + * packet. Packet must be a valid FCoE format packet. + */ + #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC UINT32_C(0x200) + /* + * This value selects a CFA action to perform on the packet. + * Set this value to zero if no CFA action is desired. + * + * This value must be valid on the first BD of a packet. + */ + uint16_t cfa_action; + /* + * This field represents a 32-bit total data length, in bytes. + * Note, however, that the length cannot exceed the MTU. + */ + uint32_t length; + uint32_t reserved32_1; + /* + * This value is action meta-data that defines CFA edit operations + * that are done in addition to any action editing. + */ + uint32_t cfa_meta; + /* When key=1, This is the VLAN tag VID value. */ + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0 + /* When key=1, This is the VLAN tag DE value. */ + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE UINT32_C(0x1000) + /* When key=1, This is the VLAN tag PRI value. */ + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13 + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16 + /* 0x88a8 */ + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) + /* 0x8100 */ + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) + /* 0x9100 */ + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) + /* 0x9200 */ + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) + /* 0x9300 */ + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) + /* Value programmed in CFA VLANTPID register. */ + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) + #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19 + /* + * This field identifies the type of edit to be performed + * on the packet. + * + * This value must be valid on the first BD of a packet. + */ + #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK UINT32_C(0xf0000000) + #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28 + /* No editing */ + #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + /* + * - meta[17:16] - TPID select value (0 = 0x8100). + * - meta[15:12] - PRI/DE value. + * - meta[11:0] - VID value. + */ + #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) + #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG + uint32_t reserved32_2; + uint32_t reserved32_3; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0 + /* + * When inline=0, then this area is filled with from 1 to 6 + * SGEs based on the wqe_size field. + * + * When inline=1, this area is filled with payload data for the + * send based on the length_or_AVID field. Bits [7:0] of word 0 + * hold the first byte to go out on the wire. + */ + uint32_t data[24]; +} sq_send_raweth_qp1_t, *psq_send_raweth_qp1_t; + +/* Send Raw Ethernet and QP1 SQ WQE header. */ +/* sq_send_raweth_qp1_hdr (size:256b/32B) */ + +typedef struct sq_send_raweth_qp1_hdr { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Send */ + #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND UINT32_C(0x0) + #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND + uint8_t flags; + #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* This flag must be zero for a Raweth or QP1 send. */ + #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* This flag must be zero for a Raweth or QP1 send. */ + #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + /* This flag must be zero for a Raweth or QP1 send. */ + #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * While this field defines the valid WQE size. The actual + * total WQE size is always 128B. + */ + uint8_t wqe_size; + uint8_t reserved8; + /* + * All bits in this field must be valid on the first BD of a packet. + * Their value on other BDs of the packet will be ignored. + */ + uint16_t lflags; + /* + * If set to 1, the controller replaces the TCP/UPD checksum + * fields of normal TCP/UPD checksum, or the inner TCP/UDP + * checksum field of the encapsulated TCP/UDP packets with the + * hardware calculated TCP/UDP checksum for the packet associated + * with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) + /* + * If set to 1, the controller replaces the IP checksum of the + * normal packets, or the inner IP checksum of the encapsulated + * packets with the hardware calculated IP checksum for the + * packet associated with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM UINT32_C(0x2) + /* + * If set to 1, the controller will not append an Ethernet CRC + * to the end of the frame. + * + * This bit must be valid on the first BD of a packet. + * + * Packet must be 64B or longer when this flag is set. It is not + * useful to use this bit with any form of TX offload such as + * CSO or LSO. The intent is that the packet from the host already + * has a valid Ethernet CRC on the packet. + */ + #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC UINT32_C(0x4) + /* + * If set to 1, the device will record the time at which the packet + * was actually transmitted at the TX MAC. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP UINT32_C(0x8) + /* + * If set to 1, The controller replaces the tunnel IP checksum + * field with hardware calculated IP checksum for the IP header + * of the packet associated with this descriptor. In case of + * VXLAN, the controller also replaces the outer header UDP + * checksum with hardware calculated UDP checksum for the packet + * associated with this descriptor. + */ + #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) + /* + * If set to '1', then the RoCE ICRC will be appended to the + * packet. Packet must be a valid RoCE format packet. + */ + #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC UINT32_C(0x100) + /* + * If set to '1', then the FCoE CRC will be appended to the + * packet. Packet must be a valid FCoE format packet. + */ + #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC UINT32_C(0x200) + /* + * This value selects a CFA action to perform on the packet. + * Set this value to zero if no CFA action is desired. + * + * This value must be valid on the first BD of a packet. + */ + uint16_t cfa_action; + /* + * This field represents a 32-bit total data length, in bytes. + * Note, however, that the length cannot exceed the MTU. + */ + uint32_t length; + uint32_t reserved32_1; + /* + * This value is action meta-data that defines CFA edit operations + * that are done in addition to any action editing. + */ + uint32_t cfa_meta; + /* When key=1, This is the VLAN tag VID value. */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0 + /* When key=1, This is the VLAN tag DE value. */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE UINT32_C(0x1000) + /* When key=1, This is the VLAN tag PRI value. */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_SFT 13 + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_SFT 16 + /* 0x88a8 */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) + /* 0x8100 */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) + /* 0x9100 */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) + /* 0x9200 */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) + /* 0x9300 */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) + /* Value programmed in CFA VLANTPID register. */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_LAST SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_SFT 19 + /* + * This field identifies the type of edit to be performed + * on the packet. + * + * This value must be valid on the first BD of a packet. + */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK UINT32_C(0xf0000000) + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_SFT 28 + /* No editing */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + /* + * - meta[17:16] - TPID select value (0 = 0x8100). + * - meta[15:12] - PRI/DE value. + * - meta[11:0] - VID value. + */ + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) + #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG + uint32_t reserved32_2; + uint32_t reserved32_3; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0 +} sq_send_raweth_qp1_hdr_t, *psq_send_raweth_qp1_hdr_t; + +/* RDMA SQ WQE */ +/* sq_rdma (size:1024b/128B) */ + +typedef struct sq_rdma { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * RDMA Write. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_WQE_TYPE_WRITE_WQE UINT32_C(0x4) + /* + * RDMA Write with Immediate. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5) + /* + * RDMA Read. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_WQE_TYPE_READ_WQE UINT32_C(0x6) + #define SQ_RDMA_WQE_TYPE_LAST SQ_RDMA_WQE_TYPE_READ_WQE + uint8_t flags; + #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_RDMA_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_RDMA_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. This bit should be set only in the last (or + * only) packet of the message. + */ + #define SQ_RDMA_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ following + * this WQE. This bit may be 1 only for write operations. + */ + #define SQ_RDMA_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_RDMA_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_RDMA_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * The number of 16 bytes chunks of data including this first + * wqe of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * While this field defines the valid WQE size. The actual + * total WQE size is always 128B. + */ + uint8_t wqe_size; + uint8_t reserved8; + /* + * Immediate data - valid for RDMA Write with immediate and + * causes the controller to add immDt header with this value + */ + uint32_t imm_data; + /* Total data length in bytes */ + uint32_t length; + uint32_t reserved32_1; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; + /* + * R_Key provided by remote node when the connection was + * established and placed in the RETH header. It identify the + * MRW on the remote host + */ + uint32_t remote_key; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_RDMA_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_RDMA_TIMESTAMP_SFT 0 + /* + * When inline=0, then this area is filled with from 1 to 6 + * SGEs based on the wqe_size field. + * + * When inline=1, this area is filled with payload data for the + * write based on the length field. Bits [7:0] of word 0 + * hold the first byte to go out on the wire. + */ + uint32_t data[24]; +} sq_rdma_t, *psq_rdma_t; + +/* RDMA SQ WQE header. */ +/* sq_rdma_hdr (size:256b/32B) */ + +typedef struct sq_rdma_hdr { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * RDMA Write. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE UINT32_C(0x4) + /* + * RDMA Write with Immediate. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5) + /* + * RDMA Read. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_HDR_WQE_TYPE_READ_WQE UINT32_C(0x6) + #define SQ_RDMA_HDR_WQE_TYPE_LAST SQ_RDMA_HDR_WQE_TYPE_READ_WQE + uint8_t flags; + #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_RDMA_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. This bit should be set only in the last (or + * only) packet of the message. + */ + #define SQ_RDMA_HDR_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ following + * this WQE. This bit may be 1 only for write operations. + */ + #define SQ_RDMA_HDR_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_RDMA_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * The number of 16 bytes chunks of data including this first + * wqe of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * While this field defines the valid WQE size. The actual + * total WQE size is always 128B. + */ + uint8_t wqe_size; + uint8_t reserved8; + /* + * Immediate data - valid for RDMA Write with immediate and + * causes the controller to add immDt header with this value + */ + uint32_t imm_data; + /* Total data length in bytes */ + uint32_t length; + uint32_t reserved32_1; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; + /* + * R_Key provided by remote node when the connection was + * established and placed in the RETH header. It identify the + * MRW on the remote host + */ + uint32_t remote_key; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_RDMA_HDR_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_RDMA_HDR_TIMESTAMP_SFT 0 +} sq_rdma_hdr_t, *psq_rdma_hdr_t; + +/* Atomic SQ WQE */ +/* sq_atomic (size:1024b/128B) */ + +typedef struct sq_atomic { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Atomic Compare/Swap. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS UINT32_C(0x8) + /* + * Atomic Fetch/Add. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA UINT32_C(0xb) + #define SQ_ATOMIC_WQE_TYPE_LAST SQ_ATOMIC_WQE_TYPE_ATOMIC_FA + uint8_t flags; + #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_ATOMIC_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_ATOMIC_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. This bit should be set only in the last (or + * only) packet of the message. + */ + #define SQ_ATOMIC_FLAGS_SE UINT32_C(0x8) + /* NA for this WQE */ + #define SQ_ATOMIC_FLAGS_INLINE UINT32_C(0x10) + /* + * The atomic WQE does not have a timestamp field, so this field is + * ignored and should be zero. + */ + #define SQ_ATOMIC_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_ATOMIC_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint16_t reserved16; + /* + * R_Key provided by remote node when the connection was + * established and placed in the AETH header. It identify the + * MRW on the remote host + */ + uint32_t remote_key; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; + /* Data value to be placed in remote host specified address */ + uint64_t swap_data; + /* + * Data value to be compared with the value in the remote host + * specified address + */ + uint64_t cmp_data; + /* + * The first 16B of the data field must be filled with a single + * SGE. This will be used to store the return value from the + * Atomic Ack response. The size of the single SGE must be 8B. + */ + uint32_t data[24]; +} sq_atomic_t, *psq_atomic_t; + +/* Atomic SQ WQE header. */ +/* sq_atomic_hdr (size:256b/32B) */ + +typedef struct sq_atomic_hdr { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Atomic Compare/Swap. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS UINT32_C(0x8) + /* + * Atomic Fetch/Add. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA UINT32_C(0xb) + #define SQ_ATOMIC_HDR_WQE_TYPE_LAST SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA + uint8_t flags; + #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_ATOMIC_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. This bit should be set only in the last (or + * only) packet of the message. + */ + #define SQ_ATOMIC_HDR_FLAGS_SE UINT32_C(0x8) + /* NA for this WQE */ + #define SQ_ATOMIC_HDR_FLAGS_INLINE UINT32_C(0x10) + /* + * The atomic WQE does not have a timestamp field, so this field is + * ignored and should be zero. + */ + #define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint16_t reserved16; + /* + * R_Key provided by remote node when the connection was + * established and placed in the AETH header. It identify the + * MRW on the remote host + */ + uint32_t remote_key; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; + /* Data value to be placed in remote host specified address */ + uint64_t swap_data; + /* + * Data value to be compared with the value in the remote host + * specified address + */ + uint64_t cmp_data; +} sq_atomic_hdr_t, *psq_atomic_hdr_t; + +/* Local Invalidate SQ WQE */ +/* sq_localinvalidate (size:1024b/128B) */ + +typedef struct sq_localinvalidate { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Local Invalidate. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc) + #define SQ_LOCALINVALIDATE_WQE_TYPE_LAST SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID + uint8_t flags; + #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. This bit should be set only in the last (or + * only) packet of the message. + */ + #define SQ_LOCALINVALIDATE_FLAGS_SE UINT32_C(0x8) + /* NA for this WQE */ + #define SQ_LOCALINVALIDATE_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint16_t reserved16; + /* + * The local key for the MR/W to invalidate; 24 msb of the key + * are used to index the MRW table, 8 lsb are compared with the + * 8 bit key in the MRWC + */ + uint32_t inv_l_key; + uint64_t reserved64; + uint8_t reserved128[16]; + /* The data field for local invalidate is not used. */ + uint32_t data[24]; +} sq_localinvalidate_t, *psq_localinvalidate_t; + +/* Local Invalidate SQ WQE header. */ +/* sq_localinvalidate_hdr (size:256b/32B) */ + +typedef struct sq_localinvalidate_hdr { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Local Invalidate. + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc) + #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID + uint8_t flags; + #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. This bit should be set only in the last (or + * only) packet of the message. + */ + #define SQ_LOCALINVALIDATE_HDR_FLAGS_SE UINT32_C(0x8) + /* NA for this WQE */ + #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint16_t reserved16; + /* + * The local key for the MR/W to invalidate; 24 msb of the key + * are used to index the MRW table, 8 lsb are compared with the + * 8 bit key in the MRWC + */ + uint32_t inv_l_key; + uint64_t reserved64; + uint8_t reserved128[16]; +} sq_localinvalidate_hdr_t, *psq_localinvalidate_hdr_t; + +/* FR-PMR SQ WQE */ +/* sq_fr_pmr (size:1024b/128B) */ + +typedef struct sq_fr_pmr { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * FR-PMR (Fast Register Physical Memory Region) + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_FR_PMR_WQE_TYPE_FR_PMR UINT32_C(0xd) + #define SQ_FR_PMR_WQE_TYPE_LAST SQ_FR_PMR_WQE_TYPE_FR_PMR + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_FR_PMR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_FR_PMR_FLAGS_UC_FENCE UINT32_C(0x4) + /* Not Applicable for FR_PMR. Nothing is sent */ + #define SQ_FR_PMR_FLAGS_SE UINT32_C(0x8) + /* NA */ + #define SQ_FR_PMR_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_FR_PMR_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_FR_PMR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. + */ + uint8_t access_cntl; + /* Local Write Access */ + #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* Remote Write Access */ + #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* Remote Atomic Access */ + #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* Window Binding Allowed */ + #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) + uint8_t zero_based_page_size_log; + /* Page size. 0 for 4KB page size, ... to 8TB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PMR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T + /* Indicate the MR is ZBVA (Zero Base VA) */ + #define SQ_FR_PMR_ZERO_BASED UINT32_C(0x20) + /* + * Local Key; 24 msb of the key are used to index the MRW + * table, 8 lsb are assigned to the 8 bit key_lsb field in + * the MRWC. + */ + uint32_t l_key; + /* Length in bytes of registered MR */ + uint8_t length[5]; + uint8_t reserved8_1; + uint8_t reserved8_2; + uint8_t numlevels_pbl_page_size_log; + /* PBL page size. 0 for 4KB page size, ... to 8TB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T + /* Number of levels of PBL for translation */ + #define SQ_FR_PMR_NUMLEVELS_MASK UINT32_C(0xc0) + #define SQ_FR_PMR_NUMLEVELS_SFT 6 + /* + * A zero level PBL means that the VA is the physical address used + * for the operation. No translation is done by the PTU. + */ + #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) + /* + * A one layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical pages. + */ + #define SQ_FR_PMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) + /* + * A two layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size physical + * pages that contain PBE values that point to actual physical + * pages. + */ + #define SQ_FR_PMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) + #define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2 + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t pblptr; + /* Local Virtual Address */ + uint64_t va; + /* The data field for FR-PMR is not used. */ + uint32_t data[24]; +} sq_fr_pmr_t, *psq_fr_pmr_t; + +/* FR-PMR SQ WQE header. */ +/* sq_fr_pmr_hdr (size:256b/32B) */ + +typedef struct sq_fr_pmr_hdr { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * FR-PMR (Fast Register Physical Memory Region) + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR UINT32_C(0xd) + #define SQ_FR_PMR_HDR_WQE_TYPE_LAST SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_FR_PMR_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + /* Not Applicable for FR_PMR. Nothing is sent */ + #define SQ_FR_PMR_HDR_FLAGS_SE UINT32_C(0x8) + /* NA */ + #define SQ_FR_PMR_HDR_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. + */ + uint8_t access_cntl; + /* Local Write Access */ + #define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* Remote Write Access */ + #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* Remote Atomic Access */ + #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* Window Binding Allowed */ + #define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) + uint8_t zero_based_page_size_log; + /* Page size. 0 for 4KB page size, ... to 8TB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T + /* Indicate the MR is ZBVA (Zero Base VA) */ + #define SQ_FR_PMR_HDR_ZERO_BASED UINT32_C(0x20) + /* + * Local Key; 24 msb of the key are used to index the MRW + * table, 8 lsb are assigned to the 8 bit key_lsb field in + * the MRWC. + */ + uint32_t l_key; + /* Length in bytes of registered MR */ + uint8_t length[5]; + uint8_t reserved8_1; + uint8_t reserved8_2; + uint8_t numlevels_pbl_page_size_log; + /* PBL page size. 0 for 4KB page size, ... to 8TB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T + /* Number of levels of PBL for translation */ + #define SQ_FR_PMR_HDR_NUMLEVELS_MASK UINT32_C(0xc0) + #define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6 + /* + * A zero level PBL means that the VA is the physical address used + * for the operation. No translation is done by the PTU. + */ + #define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) + /* + * A one layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical pages. + */ + #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) + /* + * A two layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size physical + * pages that contain PBE values that point to actual physical + * pages. + */ + #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) + #define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t pblptr; + /* Local Virtual Address */ + uint64_t va; +} sq_fr_pmr_hdr_t, *psq_fr_pmr_hdr_t; + +/* FR-PPMR SQ WQE */ +/* sq_fr_ppmr (size:1024b/128B) */ + +typedef struct sq_fr_ppmr { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * FR-PPMR (Fast Register Proxy Physical Memory Region) + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_FR_PPMR_WQE_TYPE_FR_PPMR UINT32_C(0xf) + #define SQ_FR_PPMR_WQE_TYPE_LAST SQ_FR_PPMR_WQE_TYPE_FR_PPMR + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_FR_PPMR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_FR_PPMR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_FR_PPMR_FLAGS_UC_FENCE UINT32_C(0x4) + /* Not Applicable for FR_PPMR. Nothing is sent */ + #define SQ_FR_PPMR_FLAGS_SE UINT32_C(0x8) + /* NA */ + #define SQ_FR_PPMR_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_FR_PPMR_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_FR_PPMR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. + */ + uint8_t access_cntl; + /* Local Write Access */ + #define SQ_FR_PPMR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* Remote Write Access */ + #define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* Remote Atomic Access */ + #define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* Window Binding Allowed */ + #define SQ_FR_PPMR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) + uint8_t zero_based_page_size_log; + /* Page size. 0 for 4KB page size, ... to 8TB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PPMR_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PPMR_PAGE_SIZE_LOG_LAST SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8T + /* Indicate the MR is ZBVA (Zero Base VA) */ + #define SQ_FR_PPMR_ZERO_BASED UINT32_C(0x20) + /* + * Local Key; 24 msb of the key are used to index the MRW + * table, 8 lsb are assigned to the 8 bit key_lsb field in + * the MRWC. + */ + uint32_t l_key; + /* Length in bytes of registered MR */ + uint32_t length; + /* Sets the proxy_vfid field of the physical memory region. */ + uint16_t proxy_vfid; + /* Sets the proxy_pfid field of the physical memory region. */ + uint8_t proxy_pfid; + uint8_t numlevels_pbl_page_size_log; + /* PBL page size. 0 for 4KB page size, ... to 8TB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8T + /* Sets the proxy_vf_valid field of the physical memory region. */ + #define SQ_FR_PPMR_PROXY_VF_VALID UINT32_C(0x20) + /* Number of levels of PBL for translation */ + #define SQ_FR_PPMR_NUMLEVELS_MASK UINT32_C(0xc0) + #define SQ_FR_PPMR_NUMLEVELS_SFT 6 + /* + * A zero level PBL means that the VA is the physical address used + * for the operation. No translation is done by the PTU. + */ + #define SQ_FR_PPMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) + /* + * A one layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical pages. + */ + #define SQ_FR_PPMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) + /* + * A two layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size physical + * pages that contain PBE values that point to actual physical + * pages. + */ + #define SQ_FR_PPMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) + #define SQ_FR_PPMR_NUMLEVELS_LAST SQ_FR_PPMR_NUMLEVELS_LAYER2 + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t pblptr; + /* Local Virtual Address */ + uint64_t va; + /* The data field for FR-PPMR is not used. */ + uint32_t data[24]; +} sq_fr_ppmr_t, *psq_fr_ppmr_t; + +/* FR-PPMR SQ WQE header. */ +/* sq_fr_ppmr_hdr (size:256b/32B) */ + +typedef struct sq_fr_ppmr_hdr { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * FR-PPMR (Fast Register Proxy Physical Memory Region) + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_FR_PPMR_HDR_WQE_TYPE_FR_PPMR UINT32_C(0xf) + #define SQ_FR_PPMR_HDR_WQE_TYPE_LAST SQ_FR_PPMR_HDR_WQE_TYPE_FR_PPMR + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_FR_PPMR_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_FR_PPMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_FR_PPMR_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + /* Not Applicable for FR_PPMR. Nothing is sent */ + #define SQ_FR_PPMR_HDR_FLAGS_SE UINT32_C(0x8) + /* NA */ + #define SQ_FR_PPMR_HDR_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_FR_PPMR_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_FR_PPMR_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. + */ + uint8_t access_cntl; + /* Local Write Access */ + #define SQ_FR_PPMR_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* Remote Write Access */ + #define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* Remote Atomic Access */ + #define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* Window Binding Allowed */ + #define SQ_FR_PPMR_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) + uint8_t zero_based_page_size_log; + /* Page size. 0 for 4KB page size, ... to 8TB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8T + /* Indicate the MR is ZBVA (Zero Base VA) */ + #define SQ_FR_PPMR_HDR_ZERO_BASED UINT32_C(0x20) + /* + * Local Key; 24 msb of the key are used to index the MRW + * table, 8 lsb are assigned to the 8 bit key_lsb field in + * the MRWC. + */ + uint32_t l_key; + /* Length in bytes of registered MR */ + uint32_t length; + /* Sets the proxy_vfid field of the physical memory region. */ + uint16_t proxy_vfid; + /* Sets the proxy_pfid field of the physical memory region. */ + uint8_t proxy_pfid; + uint8_t numlevels_pbl_page_size_log; + /* PBL page size. 0 for 4KB page size, ... to 8TB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T + /* Sets the proxy_vf_valid field of the physical memory region. */ + #define SQ_FR_PPMR_HDR_PROXY_VF_VALID UINT32_C(0x20) + /* Number of levels of PBL for translation */ + #define SQ_FR_PPMR_HDR_NUMLEVELS_MASK UINT32_C(0xc0) + #define SQ_FR_PPMR_HDR_NUMLEVELS_SFT 6 + /* + * A zero level PBL means that the VA is the physical address used + * for the operation. No translation is done by the PTU. + */ + #define SQ_FR_PPMR_HDR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) + /* + * A one layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical pages. + */ + #define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) + /* + * A two layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size physical + * pages that contain PBE values that point to actual physical + * pages. + */ + #define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) + #define SQ_FR_PPMR_HDR_NUMLEVELS_LAST SQ_FR_PPMR_HDR_NUMLEVELS_LAYER2 + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t pblptr; + /* Local Virtual Address */ + uint64_t va; +} sq_fr_ppmr_hdr_t, *psq_fr_ppmr_hdr_t; + +/* + * Bind SQ WQE. This WQE can perform either: + * * type1 "bind memory window", if mw_type==Type1 + * * type2 "post send bind memory window", if mw_type==Type2 + */ +/* sq_bind (size:1024b/128B) */ + +typedef struct sq_bind { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Memory Bind + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BIND_WQE_TYPE_BIND UINT32_C(0xe) + #define SQ_BIND_WQE_TYPE_LAST SQ_BIND_WQE_TYPE_BIND + uint8_t flags; + #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_BIND_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_BIND_FLAGS_UC_FENCE UINT32_C(0x4) + /* NA, nothing is sent. */ + #define SQ_BIND_FLAGS_SE UINT32_C(0x8) + /* NA */ + #define SQ_BIND_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_BIND_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_BIND_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. + */ + uint8_t access_cntl; + #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK UINT32_C(0xff) + #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0 + /* + * Local Write Access. + * + * Local accesses are never allowed for memory windows, so this + * bit must always be zero in a bind WQE. If this bit is ever + * set, the bind will fail with an errored completion. + */ + #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_BIND_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* + * Remote Write Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is + * not the case, then the bind will fail with an errored + * completion. + */ + #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* + * Remote Atomic Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is + * not the case, then the bind will fail with an errored + * completion. + */ + #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* + * Window Binding Allowed. + * + * It is never allowed to bind windows to windows, so this bit + * must always be zero in a bind WQE. If this bit is ever set, + * the bind will fail with an errored completion. + */ + #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) + /* reserved8_1 is 8 b */ + uint8_t reserved8_1; + uint8_t mw_type_zero_based; + /* + * If this bit is set, then the newly-bound memory window will be + * zero-based. If clear, then the newly-bound memory window will be + * non-zero-based. + */ + #define SQ_BIND_ZERO_BASED UINT32_C(0x1) + /* + * If type1 is specified, then this WQE performs a "bind memory + * window" operation on a type1 window. If type2 is specified, then + * this WQE performs a "post send bind memory window" operation on a + * type2 window. + * + * Note that the bind WQE cannot change the type of the memory + * window. + * + * If a "bind memory window" operation is attempted on a memory + * window that was allocated as type2, then the bind will fail with + * an errored completion, as "bind memory window" is allowed only on + * type1 memory windows. + * + * Similarly, if a "post send bind memory window" operation is + * attempted on a memory window that was allocated as type1, then the + * bind will fail with an errored completions, as "post send bind + * memory window" is allowed only on type2 memory windows. + */ + #define SQ_BIND_MW_TYPE UINT32_C(0x2) + /* Type 1 Bind Memory Window */ + #define SQ_BIND_MW_TYPE_TYPE1 (UINT32_C(0x0) << 1) + /* Type 2 Post Send Bind Memory Window */ + #define SQ_BIND_MW_TYPE_TYPE2 (UINT32_C(0x1) << 1) + #define SQ_BIND_MW_TYPE_LAST SQ_BIND_MW_TYPE_TYPE2 + uint8_t reserved8_2; + uint16_t reserved16; + /* + * The L_Key of the parent MR; 24 msb of the key are used to + * index the MRW table, 8 lsb are compared with the 8 bit key + * in the MRWC. + */ + uint32_t parent_l_key; + /* + * Local Key; 24 msb of the key are used to index the memory + * window being bound in the MRW table, 8 lsb are assign to the + * 8 bit key_lsb field in the MRWC. + */ + uint32_t l_key; + /* Local Virtual Address */ + uint64_t va; + /* + * Length in bytes of registered MW; 40 bits as this is the max + * size of an MR/W + */ + uint8_t length[5]; + uint8_t reserved24[3]; + /* The data field for Bind is not used. */ + uint32_t data[24]; +} sq_bind_t, *psq_bind_t; + +/* + * Bind SQ WQE header. This WQE can perform either: + * * type1 "bind memory window", if mw_type==Type1 + * * type2 "post send bind memory window", if mw_type==Type2 + */ +/* sq_bind_hdr (size:256b/32B) */ + +typedef struct sq_bind_hdr { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Memory Bind + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BIND_HDR_WQE_TYPE_BIND UINT32_C(0xe) + #define SQ_BIND_HDR_WQE_TYPE_LAST SQ_BIND_HDR_WQE_TYPE_BIND + uint8_t flags; + #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) + #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (se_flag refers to the receiver side) + */ + #define SQ_BIND_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_BIND_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + /* NA, nothing is sent. */ + #define SQ_BIND_HDR_FLAGS_SE UINT32_C(0x8) + /* NA */ + #define SQ_BIND_HDR_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_BIND_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_BIND_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. + */ + uint8_t access_cntl; + #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK UINT32_C(0xff) + #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0 + /* + * Local Write Access. + * + * Local accesses are never allowed for memory windows, so this + * bit must always be zero in a bind WQE. If this bit is ever + * set, the bind will fail with an errored completion. + */ + #define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* + * Remote Write Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is + * not the case, then the bind will fail with an errored + * completion. + */ + #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* + * Remote Atomic Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is + * not the case, then the bind will fail with an errored + * completion. + */ + #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* + * Window Binding Allowed. + * + * It is never allowed to bind windows to windows, so this bit + * must always be zero in a bind WQE. If this bit is ever set, + * the bind will fail with an errored completion. + */ + #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) + /* reserved8_1 is 8 b */ + uint8_t reserved8_1; + uint8_t mw_type_zero_based; + /* + * If this bit is set, then the newly-bound memory window will be + * zero-based. If clear, then the newly-bound memory window will be + * non-zero-based. + */ + #define SQ_BIND_HDR_ZERO_BASED UINT32_C(0x1) + /* + * If type1 is specified, then this WQE performs a "bind memory + * window" operation on a type1 window. If type2 is specified, then + * this WQE performs a "post send bind memory window" operation on a + * type2 window. + * + * Note that the bind WQE cannot change the type of the memory + * window. + * + * If a "bind memory window" operation is attempted on a memory + * window that was allocated as type2, then the bind will fail with + * an errored completion, as "bind memory window" is allowed only on + * type1 memory windows. + * + * Similarly, if a "post send bind memory window" operation is + * attempted on a memory window that was allocated as type1, then the + * bind will fail with an errored completions, as "post send bind + * memory window" is allowed only on type2 memory windows. + */ + #define SQ_BIND_HDR_MW_TYPE UINT32_C(0x2) + /* Type 1 Bind Memory Window */ + #define SQ_BIND_HDR_MW_TYPE_TYPE1 (UINT32_C(0x0) << 1) + /* Type 2 Post Send Bind Memory Window */ + #define SQ_BIND_HDR_MW_TYPE_TYPE2 (UINT32_C(0x1) << 1) + #define SQ_BIND_HDR_MW_TYPE_LAST SQ_BIND_HDR_MW_TYPE_TYPE2 + uint8_t reserved8_2; + uint16_t reserved16; + /* + * The L_Key of the parent MR; 24 msb of the key are used to + * index the MRW table, 8 lsb are compared with the 8 bit key + * in the MRWC. + */ + uint32_t parent_l_key; + /* + * Local Key; 24 msb of the key are used to index the memory + * window being bound in the MRW table, 8 lsb are assign to the + * 8 bit key_lsb field in the MRWC. + */ + uint32_t l_key; + /* Local Virtual Address */ + uint64_t va; + /* + * Length in bytes of registered MW; 40 bits as this is the max + * size of an MR/W + */ + uint8_t length[5]; + uint8_t reserved24[3]; +} sq_bind_hdr_t, *psq_bind_hdr_t; + +/* + * This V3 version of structure is not accessible from host software, but is documented here (in the SW section) anyway. + * This is the MSN Table (located in IQM). The table is written by the RoCE transmitter when sending wire operation WQEs. It is used to provide the RoCE receiver with information about the SQ WQEs in order to make requester completions and to perform requester HW retransmission. The number of entries in the table is configured in the QPC and must be equal to the maximum number of WQEs that can be present in the SQ at one time, rounded up to the nearest power of two. + */ +/* sq_msn_search_v3 (size:128b/16B) */ + +typedef struct sq_msn_search_v3 { + uint64_t idx_psn; + /* Start PSN of the WQE. */ + #define SQ_MSN_SEARCH_V3_START_PSN_MASK UINT32_C(0xffffff) + #define SQ_MSN_SEARCH_V3_START_PSN_SFT 0 + /* Next PSN. Equal to the start PSN of the next WQE. */ + #define SQ_MSN_SEARCH_V3_NEXT_PSN_MASK UINT32_C(0xffffff000000)L + #define SQ_MSN_SEARCH_V3_NEXT_PSN_SFT 24 + /* + * Start index. For variable-size WQEs, this field indicates the + * starting slot index that corresponds to the WQE. In + * backward-compatible mode, this is the starting WQE index. + */ + #define SQ_MSN_SEARCH_V3_START_IDX_MASK UINT32_C(0xffff000000000000)L + #define SQ_MSN_SEARCH_V3_START_IDX_SFT 48 + /* + * This value will be returned in the completion if the completion + * is signaled. + */ + uint32_t wqe_opaque; + /* The size of the WQE in units of 16B chunks. */ + uint8_t wqe_size; + uint8_t signal; + /* Set if completion signaling is requested. */ + #define SQ_MSN_SEARCH_V3_SGNLD UINT32_C(0x1) + /* + * Set if at least one signaled local memory operation WQE is + * present in the SQ between the previous wire-operation WQE + * and this WQE. + */ + #define SQ_MSN_SEARCH_V3_PREV_SGNLD_LOCAL_MEM_WQE UINT32_C(0x2) + uint16_t reserved; +} sq_msn_search_v3_t, *psq_msn_search_v3_t; + +/* SQ Send WQE V3 for RC SQs. */ +/* sq_send_v3 (size:1024b/128B) */ + +typedef struct sq_send_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Send V3 */ + #define SQ_SEND_V3_WQE_TYPE_SEND_V3 UINT32_C(0x10) + /* + * Send with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_SEND_V3_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11) + /* + * Send with Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_SEND_V3_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12) + #define SQ_SEND_V3_WQE_TYPE_LAST SQ_SEND_V3_WQE_TYPE_SEND_W_INVALID_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_SEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. + */ + #define SQ_SEND_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_SEND_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_SEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_SEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * Note: Since the WQE header consumes only one slot (16 bytes) + * for this type of WQE, and the maximum number of SGEs supported + * by the device is 30, this field must never exceed 31. + */ + #define SQ_SEND_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_SEND_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_SEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_SEND_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * Either invalidate key (R_Key of the remote host) that will + * be send with IETH (Invalidate ETH) if wqe_type is of Send + * with Invalidate, or immediate value that will be sent with + * ImmDt header if wqe_type is Send with Immediate. + */ + uint32_t inv_key_or_imm_data; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_SEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_SEND_V3_TIMESTAMP_SFT 0 + /* + * When inline=0, then this area is filled with from 1 to 30 SGEs + * based on the wqe_size field. + * + * When inline=1, this area is filled with payload data for the + * send. Length of data is described in the inline_length field. + * Bits [7:0] of word 0 hold the first byte to go out on the wire. + */ + uint32_t data[28]; +} sq_send_v3_t, *psq_send_v3_t; + +/* Send SQ WQE V3 header. */ +/* sq_send_hdr_v3 (size:128b/16B) */ + +typedef struct sq_send_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Send V3 */ + #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_V3 UINT32_C(0x10) + /* + * Send with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11) + /* + * Send with Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12) + #define SQ_SEND_HDR_V3_WQE_TYPE_LAST SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_INVALID_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_SEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. + */ + #define SQ_SEND_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_SEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_SEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_SEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * Note: Since the WQE header consumes only one slot (16 bytes) + * for this type of WQE, and the maximum number of SGEs supported + * by the device is 30, this field must never exceed 31. + */ + #define SQ_SEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_SEND_HDR_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_SEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_SEND_HDR_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * Either invalidate key (R_Key of the remote host) that will + * be send with IETH (Invalidate ETH) if wqe_type is of Send + * with Invalidate, or immediate value that will be sent with + * ImmDt header if wqe_type is Send with Immediate. + */ + uint32_t inv_key_or_imm_data; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_SEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_SEND_HDR_V3_TIMESTAMP_SFT 0 +} sq_send_hdr_v3_t, *psq_send_hdr_v3_t; + +/* SQ WQE V3 for Raw Ethernet and QP1 */ +/* sq_rawqp1send_v3 (size:1024b/128B) */ + +typedef struct sq_rawqp1send_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* RawEth/QP1 Send V3 */ + #define SQ_RAWQP1SEND_V3_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d) + #define SQ_RAWQP1SEND_V3_WQE_TYPE_LAST SQ_RAWQP1SEND_V3_WQE_TYPE_RAWQP1SEND_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_RAWQP1SEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_RAWQP1SEND_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_RAWQP1SEND_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_RAWQP1SEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_RAWQP1SEND_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * All bits in this field must be valid on the first BD of a packet. + * Their value on other BDs of the packet will be ignored. + */ + uint16_t lflags; + /* + * If set to 1, the controller replaces the TCP/UPD checksum + * fields of normal TCP/UPD checksum, or the inner TCP/UDP + * checksum field of the encapsulated TCP/UDP packets with the + * hardware calculated TCP/UDP checksum for the packet associated + * with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) + /* + * If set to 1, the controller replaces the IP checksum of the + * normal packets, or the inner IP checksum of the encapsulated + * packets with the hardware calculated IP checksum for the + * packet associated with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_IP_CHKSUM UINT32_C(0x2) + /* + * If set to 1, the controller will not append an Ethernet CRC + * to the end of the frame. + * + * This bit must be valid on the first BD of a packet. + * + * Packet must be 64B or longer when this flag is set. It is not + * useful to use this bit with any form of TX offload such as + * CSO or LSO. The intent is that the packet from the host already + * has a valid Ethernet CRC on the packet. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_NOCRC UINT32_C(0x4) + /* + * If set to 1, The controller replaces the tunnel IP checksum + * field with hardware calculated IP checksum for the IP header + * of the packet associated with this descriptor. In case of + * VXLAN, the controller also replaces the outer header UDP + * checksum with hardware calculated UDP checksum for the packet + * associated with this descriptor. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) + /* + * If set to 1, The controller replaces the Outer-tunnel IP + * checksum field with hardware calculated IP checksum for the IP + * header of the packet associated with this descriptor. + * + * For outer UDP checksum, it will be the following behavior for + * all cases independent of settings of inner LSO and checksum + * offload BD flags: + * + * - If outer UDP checksum is 0, then do not update it. + * - If outer UDP checksum is non zero, then the hardware should + * compute and update it. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_OT_IP_CHKSUM UINT32_C(0x20) + /* + * If set to '1', then the RoCE ICRC will be appended to the + * packet. Packet must be a valid RoCE format packet. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_ROCE_CRC UINT32_C(0x100) + /* + * If set to '1', then the FCoE CRC will be appended to the + * packet. Packet must be a valid FCoE format packet. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_FCOE_CRC UINT32_C(0x200) + /* + * This value selects a CFA action to perform on the packet. + * Set this value to zero if no CFA action is desired. + * + * This value must be valid on the first BD of a packet. + */ + uint16_t cfa_action; + /* + * This value selects a CFA action to perform on the packet. + * Set this value to zero if no CFA action is desired. + * + * This value must be valid on the first BD of a packet. + */ + uint16_t cfa_action_high; + /* + * This value selects bits 25:16 of the CFA action to perform on + * the packet. See the cfa_action field for more information. + */ + #define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff) + #define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_SFT 0 + uint16_t reserved_2; + /* + * This value is action meta-data that defines CFA edit operations + * that are done in addition to any action editing. + */ + uint32_t cfa_meta; + /* When key=1, This is the VLAN tag VID value. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_SFT 0 + /* When key=1, This is the VLAN tag DE value. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_DE UINT32_C(0x1000) + /* When key=1, This is the VLAN tag PRI value. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_PRI_SFT 13 + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_SFT 16 + /* 0x88a8 */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) + /* 0x8100 */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) + /* 0x9100 */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) + /* 0x9200 */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) + /* 0x9300 */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) + /* Value programmed in CFA VLANTPID register. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_LAST SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPIDCFG + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_RESERVED_SFT 19 + /* + * This field identifies the type of edit to be performed + * on the packet. + * + * This value must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_V3_CFA_META_KEY_MASK UINT32_C(0xf0000000) + #define SQ_RAWQP1SEND_V3_CFA_META_KEY_SFT 28 + /* No editing */ + #define SQ_RAWQP1SEND_V3_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + /* + * - meta[17:16] - TPID select value (0 = 0x8100). + * - meta[15:12] - PRI/DE value. + * - meta[11:0] - VID value. + */ + #define SQ_RAWQP1SEND_V3_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) + #define SQ_RAWQP1SEND_V3_CFA_META_KEY_LAST SQ_RAWQP1SEND_V3_CFA_META_KEY_VLAN_TAG + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_RAWQP1SEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_RAWQP1SEND_V3_TIMESTAMP_SFT 0 + uint64_t reserved_3; + /* + * When inline=0, then this area is filled with from 1 to 6 SGEs + * based on the wqe_size field. + * + * When inline=1, this area is filled with payload data for the + * send. Length of data is described in the inline_length field. + * Bits [7:0] of word 0 hold the first byte to go out on the wire. + */ + uint32_t data[24]; +} sq_rawqp1send_v3_t, *psq_rawqp1send_v3_t; + +/* SQ WQE V3 structure for Raw Ethernet and QP1 SQs. */ +/* sq_rawqp1send_hdr_v3 (size:256b/32B) */ + +typedef struct sq_rawqp1send_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* RawEth/QP1 Send V3 */ + #define SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d) + #define SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_LAST SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_RAWQP1SEND_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * All bits in this field must be valid on the first BD of a packet. + * Their value on other BDs of the packet will be ignored. + */ + uint16_t lflags; + /* + * If set to 1, the controller replaces the TCP/UPD checksum + * fields of normal TCP/UPD checksum, or the inner TCP/UDP + * checksum field of the encapsulated TCP/UDP packets with the + * hardware calculated TCP/UDP checksum for the packet associated + * with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) + /* + * If set to 1, the controller replaces the IP checksum of the + * normal packets, or the inner IP checksum of the encapsulated + * packets with the hardware calculated IP checksum for the + * packet associated with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_IP_CHKSUM UINT32_C(0x2) + /* + * If set to 1, the controller will not append an Ethernet CRC + * to the end of the frame. + * + * This bit must be valid on the first BD of a packet. + * + * Packet must be 64B or longer when this flag is set. It is not + * useful to use this bit with any form of TX offload such as + * CSO or LSO. The intent is that the packet from the host already + * has a valid Ethernet CRC on the packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_NOCRC UINT32_C(0x4) + /* + * If set to 1, The controller replaces the tunnel IP checksum + * field with hardware calculated IP checksum for the IP header + * of the packet associated with this descriptor. In case of + * VXLAN, the controller also replaces the outer header UDP + * checksum with hardware calculated UDP checksum for the packet + * associated with this descriptor. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) + /* + * If set to 1, The controller replaces the Outer-tunnel IP + * checksum field with hardware calculated IP checksum for the IP + * header of the packet associated with this descriptor. + * + * For outer UDP checksum, it will be the following behavior for + * all cases independent of settings of inner LSO and checksum + * offload BD flags: + * + * - If outer UDP checksum is 0, then do not update it. + * - If outer UDP checksum is non zero, then the hardware should + * compute and update it. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_OT_IP_CHKSUM UINT32_C(0x20) + /* + * If set to '1', then the RoCE ICRC will be appended to the + * packet. Packet must be a valid RoCE format packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_ROCE_CRC UINT32_C(0x100) + /* + * If set to '1', then the FCoE CRC will be appended to the + * packet. Packet must be a valid FCoE format packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_FCOE_CRC UINT32_C(0x200) + /* + * This value selects a CFA action to perform on the packet. + * Set this value to zero if no CFA action is desired. + * + * This value must be valid on the first BD of a packet. + */ + uint16_t cfa_action; + /* + * This value selects a CFA action to perform on the packet. + * Set this value to zero if no CFA action is desired. + * + * This value must be valid on the first BD of a packet. + */ + uint16_t cfa_action_high; + /* + * This value selects bits 25:16 of the CFA action to perform on + * the packet. See the cfa_action field for more information. + */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff) + #define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_SFT 0 + uint16_t reserved_2; + /* + * This value is action meta-data that defines CFA edit operations + * that are done in addition to any action editing. + */ + uint32_t cfa_meta; + /* When key=1, This is the VLAN tag VID value. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_SFT 0 + /* When key=1, This is the VLAN tag DE value. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_DE UINT32_C(0x1000) + /* When key=1, This is the VLAN tag PRI value. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_PRI_SFT 13 + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_SFT 16 + /* 0x88a8 */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) + /* 0x8100 */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) + /* 0x9100 */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) + /* 0x9200 */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) + /* 0x9300 */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) + /* Value programmed in CFA VLANTPID register. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_LAST SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPIDCFG + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_RESERVED_SFT 19 + /* + * This field identifies the type of edit to be performed + * on the packet. + * + * This value must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_MASK UINT32_C(0xf0000000) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_SFT 28 + /* No editing */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + /* + * - meta[17:16] - TPID select value (0 = 0x8100). + * - meta[15:12] - PRI/DE value. + * - meta[11:0] - VID value. + */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_LAST SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_VLAN_TAG + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_SFT 0 + uint64_t reserved_3; +} sq_rawqp1send_hdr_v3_t, *psq_rawqp1send_hdr_v3_t; + +/* SQ Send WQE V3 for UD SQs. */ +/* sq_udsend_v3 (size:1024b/128B) */ + +typedef struct sq_udsend_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * UD Send V3 + * + * Allowed only on unreliable datagram (UD) SQs. + */ + #define SQ_UDSEND_V3_WQE_TYPE_UDSEND_V3 UINT32_C(0x13) + /* + * UD Send with Immediate V3 + * + * Allowed only on unreliable datagram (UD) SQs. + */ + #define SQ_UDSEND_V3_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14) + #define SQ_UDSEND_V3_WQE_TYPE_LAST SQ_UDSEND_V3_WQE_TYPE_UDSEND_W_IMMED_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_UDSEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_UDSEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_UDSEND_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. + */ + #define SQ_UDSEND_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_UDSEND_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_UDSEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_UDSEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_UDSEND_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_UDSEND_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. */ - #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID UINT32_C(0x1) + #define SQ_UDSEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_UDSEND_V3_INLINE_LENGTH_SFT 0 /* - * When this bit is set FW will use the function_id to extract RoCE statistics. - * When collection is specified then FW will return the specific collection - * stats and if the collection is not specified then FW will return the default - * stats which will be for all QPs. + * This value will be returned in the completion if the completion is + * signaled. */ - #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID UINT32_C(0x2) - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - /* The specific statistics group being queried. */ - uint8_t collection_id; - /* Host address of the response. */ - uint64_t resp_addr; - /* Unique identifier for a function */ - uint32_t function_id; - /* PF number */ - #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK UINT32_C(0xff) - #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0 - /* VF number */ - #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK UINT32_C(0xffff00) - #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8 - /* When set the vf_num is valid. */ - #define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID UINT32_C(0x1000000) - uint32_t reserved32; -} cmdq_query_roce_stats_ext_t, *pcmdq_query_roce_stats_ext_t; - -/* creq_query_roce_stats_ext_resp (size:128b/16B) */ - -typedef struct creq_query_roce_stats_ext_resp { - uint8_t type; + uint32_t opaque; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Immediate value that will be sent with ImmDt header if wqe_type is + * UD Send with Immediate. */ - #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Side buffer size in 16-byte units */ - uint32_t size; - uint8_t v; + uint32_t imm_data; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * When in the SQ of a UD QP, indicates the q_key to be used in + * the transmitted packet. However, if the most significant bit + * of this field is set, then the q_key will be taken from QP + * context, rather than from this field. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. */ - #define CREQ_QUERY_ROCE_STATS_EXT_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Query extended RoCE statistics. */ - #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT UINT32_C(0x92) - #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT - uint8_t reserved48[6]; -} creq_query_roce_stats_ext_resp_t, *pcreq_query_roce_stats_ext_resp_t; + uint32_t q_key; + /* + * When in the SQ of a UD QP, indicates the destination QP to be + * used in the transmitted packet. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. + */ + uint32_t dst_qp; + #define SQ_UDSEND_V3_DST_QP_MASK UINT32_C(0xffffff) + #define SQ_UDSEND_V3_DST_QP_SFT 0 + uint32_t avid; + /* + * If the serv_type is 'UD', then this field supplies the AVID + * (Address Vector ID). + */ + #define SQ_UDSEND_V3_AVID_MASK UINT32_C(0x3ff) + #define SQ_UDSEND_V3_AVID_SFT 0 + uint32_t reserved2; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_UDSEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_UDSEND_V3_TIMESTAMP_SFT 0 + /* + * When inline=0, then this area is filled with from 1 to 30 SGEs + * based on the wqe_size field. + * + * When inline=1, this area is filled with payload data for the + * send. Length of data is described in the inline_length field. + * Bits [7:0] of word 0 hold the first byte to go out on the wire. + */ + uint32_t data[24]; +} sq_udsend_v3_t, *psq_udsend_v3_t; -/* Query extended RoCE Stats command response side buffer structure. */ -/* creq_query_roce_stats_ext_resp_sb (size:1984b/248B) */ +/* SQ WQE V3 header for UD SQs. */ +/* sq_udsend_hdr_v3 (size:256b/32B) */ -typedef struct creq_query_roce_stats_ext_resp_sb { - /* Command opcode. */ - uint8_t opcode; - /* Query extended RoCE statistics. */ - #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92) - #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t rsvd; - /* Number of transmitted Atomic request packets. */ - uint64_t tx_atomic_req_pkts; - /* Number of transmitted Read request packets. */ - uint64_t tx_read_req_pkts; - /* Number of transmitted Read response packets. */ - uint64_t tx_read_res_pkts; - /* Number of transmitted Write request packets. */ - uint64_t tx_write_req_pkts; +typedef struct sq_udsend_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; /* - * Number of transmitted Send request packets. - * This is for RC QPs only. + * UD Send V3 + * + * Allowed only on unreliable datagram (UD) SQs. */ - uint64_t tx_send_req_pkts; + #define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_V3 UINT32_C(0x13) /* - * Number of transmitted RoCE packets. - * This includes RC, UD, RawEth, and QP1 packets + * UD Send with Immediate V3 + * + * Allowed only on unreliable datagram (UD) SQs. */ - uint64_t tx_roce_pkts; + #define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14) + #define SQ_UDSEND_HDR_V3_WQE_TYPE_LAST SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_W_IMMED_V3 + uint8_t flags; /* - * Number of transmitted RoCE header and payload bytes. - * This includes RC, UD, RawEth, and QP1 packets. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). */ - uint64_t tx_roce_bytes; - /* Number of received Atomic request packets. */ - uint64_t rx_atomic_req_pkts; - /* Number of received Read request packets. */ - uint64_t rx_read_req_pkts; - /* Number of received Read response packets. */ - uint64_t rx_read_res_pkts; - /* Number of received Write request packets. */ - uint64_t rx_write_req_pkts; + #define SQ_UDSEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) /* - * Number of received Send request packets. - * This is for RC QPs only. + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a UD send. */ - uint64_t rx_send_req_pkts; + #define SQ_UDSEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) /* - * Number of received RoCE packets including RoCE packets with errors. - * This includes RC, UD, RawEth, and QP1 packets + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a UD send. */ - uint64_t rx_roce_pkts; + #define SQ_UDSEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) /* - * Number of received RoCE header and payload bytes including RoCE - * packets with errors. - * This includes RC, UD, RawEth, and QP1 packets. + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. */ - uint64_t rx_roce_bytes; + #define SQ_UDSEND_HDR_V3_FLAGS_SE UINT32_C(0x8) /* - * Number of received RoCE packets. - * This includes RC, UD, RawEth, and QP1 packets + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. */ - uint64_t rx_roce_good_pkts; + #define SQ_UDSEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10) /* - * Number of received RoCE header and payload bytes. - * This includes RC, UD, RawEth, and QP1 packets. + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. */ - uint64_t rx_roce_good_bytes; + #define SQ_UDSEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) /* - * Number of drops that occurred to lack of buffers. - * This is for RC QPs only. + * When set to '1', this operation will cause a trace capture in + * each block it passes through. */ - uint64_t rx_out_of_buffer_pkts; - /* Number of packets that were received out of sequence. */ - uint64_t rx_out_of_sequence_pkts; - /* Number of transmitted CNP packets. The counter is per port. */ - uint64_t tx_cnp_pkts; - /* Number of received CNP packets. The counter is per port. */ - uint64_t rx_cnp_pkts; - /* Number of received ECN-marked RoCE packets. The counter is per port. */ - uint64_t rx_ecn_marked_pkts; - /* Number of transmitted CNP bytes. */ - uint64_t tx_cnp_bytes; - /* Number of received CNP bytes. */ - uint64_t rx_cnp_bytes; + #define SQ_UDSEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; /* - * Number of sequence error NAKs received. - * This counter is only applicable for devices that support - * hardware based retransmission. + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_UDSEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_UDSEND_HDR_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. */ - uint64_t seq_err_naks_rcvd; + #define SQ_UDSEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_UDSEND_HDR_V3_INLINE_LENGTH_SFT 0 /* - * Number of RNR NAKs received. - * This counter is only applicable for devices that support - * hardware based retransmission. + * This value will be returned in the completion if the completion is + * signaled. */ - uint64_t rnr_naks_rcvd; + uint32_t opaque; /* - * Number of missing response resulting in HW retransmission. - * This counter is only applicable for devices that support - * hardware based retransmission. + * Immediate value that will be sent with ImmDt header if wqe_type is + * UD Send with Immediate. */ - uint64_t missing_resp; + uint32_t imm_data; /* - * Number of timeouts resulting in HW retransmission. - * This counter is only applicable for devices that support - * hardware based retransmission. + * When in the SQ of a UD QP, indicates the q_key to be used in + * the transmitted packet. However, if the most significant bit + * of this field is set, then the q_key will be taken from QP + * context, rather than from this field. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. */ - uint64_t to_retransmit; + uint32_t q_key; /* - * Number of duplicate read requests resulting in HW retransmission. - * This counter is only applicable for devices that support - * hardware based retransmission. + * When in the SQ of a UD QP, indicates the destination QP to be + * used in the transmitted packet. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. */ - uint64_t dup_req; + uint32_t dst_qp; + #define SQ_UDSEND_HDR_V3_DST_QP_MASK UINT32_C(0xffffff) + #define SQ_UDSEND_HDR_V3_DST_QP_SFT 0 + uint32_t avid; /* - * Number of received DCN payload cut packets. - * This counter is only applicable for devices that support - * the DCN Payload Cut feature. + * If the serv_type is 'UD', then this field supplies the AVID + * (Address Vector ID). */ - uint64_t rx_dcn_payload_cut; - /* Number of transmitted packets that bypassed the transmit engine. */ - uint64_t te_bypassed; -} creq_query_roce_stats_ext_resp_sb_t, *pcreq_query_roce_stats_ext_resp_sb_t; - -/************** - * query_func * - **************/ - - -/* cmdq_query_func (size:128b/16B) */ - -typedef struct cmdq_query_func { - /* Command opcode. */ - uint8_t opcode; - /* Query the HW capabilities for the function. */ - #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC UINT32_C(0x83) - #define CMDQ_QUERY_FUNC_OPCODE_LAST CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; -} cmdq_query_func_t, *pcmdq_query_func_t; + #define SQ_UDSEND_HDR_V3_AVID_MASK UINT32_C(0x3ff) + #define SQ_UDSEND_HDR_V3_AVID_SFT 0 + uint32_t reserved2; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_UDSEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_UDSEND_HDR_V3_TIMESTAMP_SFT 0 +} sq_udsend_hdr_v3_t, *psq_udsend_hdr_v3_t; -/* creq_query_func_resp (size:128b/16B) */ +/* SQ RDMA WQE V3 for RC SQs. */ +/* sq_rdma_v3 (size:1024b/128B) */ -typedef struct creq_query_func_resp { - uint8_t type; +typedef struct sq_rdma_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * RDMA Write V3 + * + * Allowed only on reliable connection (RC) SQs. */ - #define CREQ_QUERY_FUNC_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_QUERY_FUNC_RESP_TYPE_LAST CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Side buffer size in 16-byte units */ - uint32_t size; - uint8_t v; + #define SQ_RDMA_V3_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * RDMA Write with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. */ - #define CREQ_QUERY_FUNC_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Query info PF command response. */ - #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC UINT32_C(0x83) - #define CREQ_QUERY_FUNC_RESP_EVENT_LAST CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC - uint8_t reserved48[6]; -} creq_query_func_resp_t, *pcreq_query_func_resp_t; + #define SQ_RDMA_V3_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16) + /* + * RDMA Read V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_V3_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17) + #define SQ_RDMA_V3_WQE_TYPE_LAST SQ_RDMA_V3_WQE_TYPE_READ_WQE_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_RDMA_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_RDMA_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_RDMA_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. + */ + #define SQ_RDMA_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ following + * this WQE. This bit may be 1 only for write operations. + */ + #define SQ_RDMA_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_RDMA_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_RDMA_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_RDMA_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_RDMA_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_RDMA_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_RDMA_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * Immediate data - valid for RDMA Write with immediate and + * causes the controller to add immDt header with this value + */ + uint32_t imm_data; + uint32_t reserved2; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; + /* + * R_Key provided by remote node when the connection was + * established and placed in the RETH header. It identify the + * MRW on the remote host + */ + uint32_t remote_key; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_RDMA_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_RDMA_V3_TIMESTAMP_SFT 0 + /* + * When inline=0, then this area is filled with from 1 to 30 SGEs + * based on the wqe_size field. + * + * When inline=1, this area is filled with payload data for the send. + * Length of data is described in the inline_length field. Bits [7:0] + * of word 0 hold the first byte to go out on the wire. + */ + uint32_t data[24]; +} sq_rdma_v3_t, *psq_rdma_v3_t; -/* Query function command response side buffer structure. */ -/* creq_query_func_resp_sb (size:1088b/136B) */ +/* SQ RDMA WQE V3 header for RC SQs. */ +/* sq_rdma_hdr_v3 (size:256b/32B) */ -typedef struct creq_query_func_resp_sb { - /* Command opcode. */ - uint8_t opcode; - /* Query info PF command response. */ - #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC UINT32_C(0x83) - #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_LAST CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Max MR size supported. */ - uint64_t max_mr_size; - /* Max QP supported. */ - uint32_t max_qp; - /* Max WQEs per QP. */ - uint16_t max_qp_wr; - /* Device capability flags. */ - uint16_t dev_cap_flags; - /* Allow QP resizing. */ - #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP UINT32_C(0x1) - /* Specifies Congestion Control (CC) generation. */ - #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK UINT32_C(0xe) - #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1 +typedef struct sq_rdma_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; /* - * Includes support for DCTCP and TCP CC algorithms, - * enabling operation in networks where PFC is enabled. + * RDMA Write V3 + * + * Allowed only on reliable connection (RC) SQs. */ - #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (UINT32_C(0x0) << 1) + #define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15) /* - * Enhances cc_gen0 support with probabilistic marking algorithm, - * enabling fast ramp up and convergence, - * as well as operation in networks where PFC is not enabled. - * Includes a number of parameters that are different from cc_gen0 - * chips as well as new parameters. TCP CC algorithm is not supported. + * RDMA Write with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. */ - #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (UINT32_C(0x1) << 1) + #define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16) /* - * Enhances cc_gen1 support for additional CC parameters: - * reduce_init_en, reduce_init_cong_free_rtts_th, random_no_red_en, - * actual_cr_shift_correction_en, quota_period_adjust_en + * RDMA Read V3 + * + * Allowed only on reliable connection (RC) SQs. */ - #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (UINT32_C(0x2) << 1) - #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT + #define SQ_RDMA_HDR_V3_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17) + #define SQ_RDMA_HDR_V3_WQE_TYPE_LAST SQ_RDMA_HDR_V3_WQE_TYPE_READ_WQE_V3 + uint8_t flags; /* - * Support for the extended RoCE statistics is available. These - * statistics are queried via the `query_roce_stats_ext` command - * and are enabled on a per-QP basis via `create_qp`. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). */ - #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS UINT32_C(0x10) + #define SQ_RDMA_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) /* - * Support for both allocating and registering a new MR via the - * `register_mr` command is available. With this feature the - * `allocate_mrw` command does not have to be called before - * registering. + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE */ - #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC UINT32_C(0x20) + #define SQ_RDMA_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) /* - * Support for optimized transmit path to lower latency for WQEs - * with inline data. + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. */ - #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x40) + #define SQ_RDMA_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) /* - * The underlying HW uses the version 2 of the CQEs definitions for - * the following CQE types: - * RES_UD, RES_RAWETH_QP1, RES_UD_CFA + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. */ - #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 UINT32_C(0x80) - /* Support for ping pong push mode is available. */ - #define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE UINT32_C(0x100) - /* Support for hardware requester retransmission is enabled. */ - #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED UINT32_C(0x200) - /* Support for hardware responder retransmission is enabled. */ - #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED UINT32_C(0x400) - /* Max CQs supported. */ - uint32_t max_cq; - /* Max CQEs per CQ supported. */ - uint32_t max_cqe; - /* Max PDs supported. */ - uint32_t max_pd; + #define SQ_RDMA_HDR_V3_FLAGS_SE UINT32_C(0x8) /* - * Max SGEs per QP WQE supported. On chips with variable-size WQE support, - * this field is applicable only for the backward compatible mode. + * Indicate that inline data is posted to the SQ following + * this WQE. This bit may be 1 only for write operations. */ - uint8_t max_sge; - /* Max SGEs per SRQ WQE supported. */ - uint8_t max_srq_sge; - /* Max outstanding RDMA read & atomic supported. */ - uint8_t max_qp_rd_atom; - /* Max outstanding RDMA read & atomic that can be sent from an initiator. */ - uint8_t max_qp_init_rd_atom; - /* Max MRs supported. */ - uint32_t max_mr; - /* Max MWs supported. */ - uint32_t max_mw; - /* Max Raw Ethertype QPs supported. */ - uint32_t max_raw_eth_qp; - /* Max AHs supported. */ - uint32_t max_ah; - /* Max FMRs supported. */ - uint32_t max_fmr; - /* Max WQEs per SRQ supported. */ - uint32_t max_srq_wr; - /* Max PKEYs supported. */ - uint32_t max_pkeys; + #define SQ_RDMA_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_RDMA_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_RDMA_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_RDMA_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_RDMA_HDR_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_RDMA_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_RDMA_HDR_V3_INLINE_LENGTH_SFT 0 /* - * Max inline data supported. On chips with variable-size WQE support, - * this field is applicable only for the backward compatible mode. + * This value will be returned in the completion if the completion is + * signaled. */ - uint32_t max_inline_data; - /* Max mappings per FMR supported. */ - uint8_t max_map_per_fmr; - /* L2 DB space size in pages. */ - uint8_t l2_db_space_size; - /* Max SRQs supported. */ - uint16_t max_srq; - /* Max GIDs supported. */ - uint32_t max_gid; + uint32_t opaque; /* - * An array of 48 8-bit values to specify allocation multiplier for TQM host buffer regions. - * Each region occupies 16 MB of TQM PBL address space: 0x00000000, 0x01000000, 0x02000000, etc. - * The host needs to allocate (*multiplier, rounded up to page size) of physical memory for non-zero slots - * and map the pages to the corresponding 16MB regions. - * Typically there are total 3 non-zero values in this array, their values are 16, 16, 12. - * Cu+ will only populate up to index 11. SR may populate up to index 47. + * Immediate data - valid for RDMA Write with immediate and + * causes the controller to add immDt header with this value */ - uint32_t tqm_alloc_reqs[12]; - /* Max Doorbell page indices supported. */ - uint32_t max_dpi; - /* Max SGEs per QP WQE supported in the variable-size WQE mode. */ - uint8_t max_sge_var_wqe; - uint8_t reserved_8; - /* Max inline data supported in the variable-size WQE mode. */ - uint16_t max_inline_data_var_wqe; -} creq_query_func_resp_sb_t, *pcreq_query_func_resp_sb_t; - -/********************** - * set_func_resources * - **********************/ - + uint32_t imm_data; + uint32_t reserved2; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; + /* + * R_Key provided by remote node when the connection was + * established and placed in the RETH header. It identify the + * MRW on the remote host + */ + uint32_t remote_key; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_RDMA_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_RDMA_HDR_V3_TIMESTAMP_SFT 0 +} sq_rdma_hdr_v3_t, *psq_rdma_hdr_v3_t; -/* cmdq_set_func_resources (size:448b/56B) */ +/* SQ Atomic V3 WQE for RC SQs. */ +/* sq_atomic_v3 (size:448b/56B) */ -typedef struct cmdq_set_func_resources { - /* Command opcode. */ - uint8_t opcode; +typedef struct sq_atomic_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; /* - * Set the following resources for the function: - * - Max QP, CQ, MR+MW, SRQ per PF - * - Max QP, CQ, MR+MW, SRQ per VF + * Atomic Compare/Swap V3 + * + * Allowed only on reliable connection (RC) SQs. */ - #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84) - #define CMDQ_SET_FUNC_RESOURCES_OPCODE_LAST CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; + #define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18) /* - * When set, the 32b `max_mrw_per_vf` field is logically divided - * into two 16b fields, `max_mr_per_vf` and `max_av_per_vf`. + * Atomic Fetch/Add V3 + * + * Allowed only on reliable connection (RC) SQs. */ - #define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x1) - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* Number of QPs. It is the responsibility of the host to first extend the existing PBL with new addresses to pages to handle the adjustment. Must be greater or equal to current. */ - uint32_t number_of_qp; - /* Number of MRWs. It is the responsibility of the host to first extend the existing PBL with new addresses to pages to handle the adjustment. Must be greater or equal to current. */ - uint32_t number_of_mrw; - /* Number of SRQs. It is the responsibility of the host to first extend the existing PBL with new addresses to pages to handle the adjustment. Must be greater or equal to current. */ - uint32_t number_of_srq; - /* Number of CQs. It is the responsibility of the host to first extend the existing PBL with new addresses to pages to handle the adjustment. Must be greater or equal to current. */ - uint32_t number_of_cq; - /* Number of QPs per VF. */ - uint32_t max_qp_per_vf; + #define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19) + #define SQ_ATOMIC_V3_WQE_TYPE_LAST SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_FA_V3 + uint8_t flags; /* - * If the MR/AV split reservation flag is not set, then this field - * represents the total number of MR plus AV entries allowed per - * VF. For versions of firmware that support the split reservation, - * when it is not specified half of the entries will be reserved - * for MRs and the other half for AVs. - * - * If the MR/AV split reservation flag is set, then this - * field is logically divided into two 16b fields. Bits `[31:16]` - * represents the `max_mr_per_vf` and bits `[15:0]` represents - * `max_av_per_vf`. The granularity of these values is defined by - * the `mrav_num_entries_unit` field returned by the - * `backing_store_qcaps` command. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). */ - uint32_t max_mrw_per_vf; - /* Number of SRQs per VF. */ - uint32_t max_srq_per_vf; - /* Number of CQs per VF. */ - uint32_t max_cq_per_vf; - /* Number of GIDs per VF. */ - uint32_t max_gid_per_vf; - /* Statistics context index for this function. */ - uint32_t stat_ctx_id; -} cmdq_set_func_resources_t, *pcmdq_set_func_resources_t; - -/* creq_set_func_resources_resp (size:128b/16B) */ - -typedef struct creq_set_func_resources_resp { - uint8_t type; + #define SQ_ATOMIC_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE */ - #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_LAST CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - uint32_t reserved32; - uint8_t v; + #define SQ_ATOMIC_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. */ - #define CREQ_SET_FUNC_RESOURCES_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Set function resources command response. */ - #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84) - #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_LAST CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES - uint8_t reserved48[6]; -} creq_set_func_resources_resp_t, *pcreq_set_func_resources_resp_t; - -/************* - * stop_func * - *************/ - - -/* cmdq_stop_func (size:128b/16B) */ - -typedef struct cmdq_stop_func { - /* Command opcode. */ - uint8_t opcode; - /* Stop the function */ - #define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC UINT32_C(0x82) - #define CMDQ_STOP_FUNC_OPCODE_LAST CMDQ_STOP_FUNC_OPCODE_STOP_FUNC - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; -} cmdq_stop_func_t, *pcmdq_stop_func_t; - -/* creq_stop_func_resp (size:128b/16B) */ - -typedef struct creq_stop_func_resp { - uint8_t type; + #define SQ_ATOMIC_V3_FLAGS_UC_FENCE UINT32_C(0x4) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. */ - #define CREQ_STOP_FUNC_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_STOP_FUNC_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_STOP_FUNC_RESP_TYPE_LAST CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - uint32_t reserved32; - uint8_t v; + #define SQ_ATOMIC_V3_FLAGS_SE UINT32_C(0x8) + /* NA for this WQE */ + #define SQ_ATOMIC_V3_FLAGS_INLINE UINT32_C(0x10) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * The atomic WQE does not have a timestamp field, so this field is + * ignored and should be zero. */ - #define CREQ_STOP_FUNC_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Stop PF command response. */ - #define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC UINT32_C(0x82) - #define CREQ_STOP_FUNC_RESP_EVENT_LAST CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC - uint8_t reserved48[6]; -} creq_stop_func_resp_t, *pcreq_stop_func_resp_t; - -/**************** - * read_context * - ****************/ - - -/* cmdq_read_context (size:192b/24B) */ - -typedef struct cmdq_read_context { - /* Command opcode. */ - uint8_t opcode; - /* Read the current state of any internal resource context. Can only be issued from a PF. */ - #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT UINT32_C(0x85) - #define CMDQ_READ_CONTEXT_OPCODE_LAST CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - uint32_t type_xid; - /* Context ID */ - #define CMDQ_READ_CONTEXT_XID_MASK UINT32_C(0xffffff) - #define CMDQ_READ_CONTEXT_XID_SFT 0 - /* Context type */ - #define CMDQ_READ_CONTEXT_TYPE_MASK UINT32_C(0xff000000) - #define CMDQ_READ_CONTEXT_TYPE_SFT 24 - /* Read QPC. The context (448 bytes) goes to resp_addr (as is, without a header), and resp_size should be set to 28 (448/16) */ - #define CMDQ_READ_CONTEXT_TYPE_QPC (UINT32_C(0x0) << 24) - /* Read CQ. The context (64 bytes) goes to resp_addr (as is, without a header), and resp_size should be set to 4 (64/16) */ - #define CMDQ_READ_CONTEXT_TYPE_CQ (UINT32_C(0x1) << 24) - /* Read MRW. The context (128 bytes) goes to resp_addr (as is, without a header), and resp_size should be set to 8 (128/16) */ - #define CMDQ_READ_CONTEXT_TYPE_MRW (UINT32_C(0x2) << 24) - /* Read SRQ. The context (64 bytes) goes to resp_addr (as is, without a header), and resp_size should be set to 4 (64/16) */ - #define CMDQ_READ_CONTEXT_TYPE_SRQ (UINT32_C(0x3) << 24) - #define CMDQ_READ_CONTEXT_TYPE_LAST CMDQ_READ_CONTEXT_TYPE_SRQ - uint32_t unused_0; -} cmdq_read_context_t, *pcmdq_read_context_t; - -/* creq_read_context (size:128b/16B) */ - -typedef struct creq_read_context { - uint8_t type; + #define SQ_ATOMIC_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B records. - * records. + * When set to '1', this operation will cause a trace capture in + * each block it passes through. */ - #define CREQ_READ_CONTEXT_TYPE_MASK UINT32_C(0x3f) - #define CREQ_READ_CONTEXT_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_READ_CONTEXT_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_READ_CONTEXT_TYPE_LAST CREQ_READ_CONTEXT_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - uint32_t reserved32; - uint8_t v; + #define SQ_ATOMIC_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * The size of the WQE in units of 16B chunks. + * + * For the Atomic WQE, this field will always have a value of 4. */ - #define CREQ_READ_CONTEXT_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Read the current state of any internal resource context. Can only be issued from a PF. */ - #define CREQ_READ_CONTEXT_EVENT_READ_CONTEXT UINT32_C(0x85) - #define CREQ_READ_CONTEXT_EVENT_LAST CREQ_READ_CONTEXT_EVENT_READ_CONTEXT - uint16_t reserved16; - uint32_t reserved_32; -} creq_read_context_t, *pcreq_read_context_t; - -/***************** - * map_tc_to_cos * - *****************/ - - -/* cmdq_map_tc_to_cos (size:192b/24B) */ - -typedef struct cmdq_map_tc_to_cos { - /* Command opcode. */ - uint8_t opcode; - /* Map TC to COS. Can only be issued from a PF. */ - #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a) - #define CMDQ_MAP_TC_TO_COS_OPCODE_LAST CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* 1st COS index mapped to RoCE */ - uint16_t cos0; - /* Don't change this COS. */ - #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE UINT32_C(0xffff) - #define CMDQ_MAP_TC_TO_COS_COS0_LAST CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE - /* 2nd COS index mapped to RoCE */ - uint16_t cos1; - /* Disable this COS. */ - #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE UINT32_C(0x8000) - /* Don't change this COS. */ - #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE UINT32_C(0xffff) - #define CMDQ_MAP_TC_TO_COS_COS1_LAST CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE - uint32_t unused_0; -} cmdq_map_tc_to_cos_t, *pcmdq_map_tc_to_cos_t; - -/* creq_map_tc_to_cos_resp (size:128b/16B) */ - -typedef struct creq_map_tc_to_cos_resp { - uint8_t type; + #define SQ_ATOMIC_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_ATOMIC_V3_WQE_SIZE_SFT 0 + uint8_t reserved1; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This value will be returned in the completion if the completion is + * signaled. */ - #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_MAP_TC_TO_COS_RESP_TYPE_LAST CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - uint32_t reserved32; - uint8_t v; + uint32_t opaque; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * R_Key provided by remote node when the connection was + * established and placed in the AETH header. It identifies the + * MRW on the remote host. */ - #define CREQ_MAP_TC_TO_COS_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Map TC to COS response. */ - #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS UINT32_C(0x8a) - #define CREQ_MAP_TC_TO_COS_RESP_EVENT_LAST CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS - uint8_t reserved48[6]; -} creq_map_tc_to_cos_resp_t, *pcreq_map_tc_to_cos_resp_t; - -/***************** - * query_roce_cc * - *****************/ - - -/* cmdq_query_roce_cc (size:128b/16B) */ - -typedef struct cmdq_query_roce_cc { - /* Command opcode. */ - uint8_t opcode; - /* Query congestion control. */ - #define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) - #define CMDQ_QUERY_ROCE_CC_OPCODE_LAST CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; -} cmdq_query_roce_cc_t, *pcmdq_query_roce_cc_t; - -/* creq_query_roce_cc_resp (size:128b/16B) */ - -typedef struct creq_query_roce_cc_resp { - uint8_t type; + uint32_t remote_key; + uint32_t reserved2; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * For compare/swap, this is the data value to be placed in the + * remote host at the specified remote_VA if the comparison succeeds. + * + * For fetch/add, this is the value to be added to the data in the + * remote host at the specified remote_VA. */ - #define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_QUERY_ROCE_CC_RESP_TYPE_LAST CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Side buffer size in 16-byte units */ - uint32_t size; - uint8_t v; + uint64_t swap_data; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * For compare/swap, this is the data value to be compared with the + * value in the remote host at the specified remote_VA. + * + * This field is not used for fetch/add. */ - #define CREQ_QUERY_ROCE_CC_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Query congestion control response. */ - #define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC UINT32_C(0x8d) - #define CREQ_QUERY_ROCE_CC_RESP_EVENT_LAST CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC - uint8_t reserved48[6]; -} creq_query_roce_cc_resp_t, *pcreq_query_roce_cc_resp_t; - -/* Query congestion control command response side buffer structure. */ -/* creq_query_roce_cc_resp_sb (size:256b/32B) */ - -typedef struct creq_query_roce_cc_resp_sb { - /* Command opcode. */ - uint8_t opcode; - /* Query congestion control response. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) - #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - uint8_t enable_cc; - /* Enable. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC UINT32_C(0x1) - /* unused7 is 7 b */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK UINT32_C(0xfe) - #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_SFT 1 - uint8_t tos_dscp_tos_ecn; - /* IP TOS ECN. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK UINT32_C(0x3) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0 - /* IP TOS DSCP. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2 - /* Congestion Probability averaging factor. */ - uint8_t g; - /* Number of phases in Fast Recovery and Active Increase. */ - uint8_t num_phases_per_state; - /* The starting value of rate. */ - uint16_t init_cr; - /* The starting value of target rate. */ - uint16_t init_tr; - uint8_t alt_vlan_pcp; - /* Alternate vlan pcp value for CNP packets. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK UINT32_C(0x7) - #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0 - /* rsvd1 is 5 b */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK UINT32_C(0xf8) - #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3 - uint8_t alt_tos_dscp; - /* Alternate IP TOS DSCP. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK UINT32_C(0x3f) - #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0 - /* rsvd4 is 2 b */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK UINT32_C(0xc0) - #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6 - uint8_t cc_mode; - /* DCTCP CC algorithm. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP UINT32_C(0x0) + uint64_t cmp_data; /* - * Probabilistic marking CC algorithm. On chips with CC Gen 0 - * support this will be TCP CC algorithm. + * The virtual address in local memory or a physical address when + * l_key value is a reserved value of a physical address. Driver + * configures this value in the chip and the chip compares l_key in + * SGEs with that reserved value, if equal it access the physical + * address specified. The chip however MUST verify that the QP allows + * the use reserved key. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC UINT32_C(0x1) - #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC - /* Specifies the RoCE Tx Queue to use for sending CNP packets. */ - uint8_t tx_queue; - uint16_t rtt; - /* Round trip time in units of usecs */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK UINT32_C(0x3fff) - #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0 - /* rsvd5 is 2 b */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK UINT32_C(0xc000) - #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14 - uint16_t tcp_cp; - /* The value used as CP when cc_mode is 1(TCP) */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK UINT32_C(0x3ff) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0 - /* rsvd6 is 6 b */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK UINT32_C(0xfc00) - #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10 - /* Inactivity time after which QP CC parameters are initialized */ - uint16_t inactivity_th; - /* Number of packets per phase. Max is 255. */ - uint8_t pkts_per_phase; - /* Amount of time per phase in units of ms. Max is 15 */ - uint8_t time_per_phase; - uint32_t reserved32; -} creq_query_roce_cc_resp_sb_t, *pcreq_query_roce_cc_resp_sb_t; + uint64_t va_or_pa; + /* + * Local Key associated with this registered MR; The 24 msb of the + * key used to index the MRW Table and the 8 lsb are compared with + * the 8 bits key part stored in the MRWC. The PBL in the MRW Context + * is used to translate the above VA to physical address. + */ + uint32_t l_key; + /* + * Size of SGE in bytes; Based on page size of the system the chip + * knows how many entries are in the PBL + * + * This field must have a value of 8 for an Atomic WQE. + */ + uint32_t size; +} sq_atomic_v3_t, *psq_atomic_v3_t; -/* - * TLV encapsulated Query congestion control command response - * side buffer, with extended TLV record included for specifying - * the extended configuration for CC level 1. - */ -/* creq_query_roce_cc_resp_sb_tlv (size:384b/48B) */ +/* SQ Atomic WQE V3 header for RC SQs. */ +/* sq_atomic_hdr_v3 (size:320b/40B) */ -typedef struct creq_query_roce_cc_resp_sb_tlv { +typedef struct sq_atomic_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; /* - * The command discriminator is used to differentiate between various - * types of HWRM messages. This includes legacy HWRM and RoCE slowpath - * command messages as well as newer TLV encapsulated HWRM commands. + * Atomic Compare/Swap V3 * - * For TLV encapsulated messages this field must be 0x8000. + * Allowed only on reliable connection (RC) SQs. */ - uint16_t cmd_discr; - uint8_t reserved_8b; - uint8_t tlv_flags; + #define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18) /* - * Indicates the presence of additional TLV encapsulated data - * follows this TLV. + * Atomic Fetch/Add V3 + * + * Allowed only on reliable connection (RC) SQs. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1) - /* Last TLV in a sequence of TLVs. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) - /* More TLVs follow this TLV. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + #define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19) + #define SQ_ATOMIC_HDR_V3_WQE_TYPE_LAST SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_FA_V3 + uint8_t flags; /* - * When an HWRM receiver detects a TLV type that it does not - * support with the TLV required flag set, the receiver must - * reject the HWRM message with an error code indicating an - * unsupported TLV type. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) - /* No */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) - /* Yes */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES + #define SQ_ATOMIC_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) /* - * This field defines the TLV type value which is divided into - * two ranges to differentiate between global and local TLV types. - * Global TLV types must be unique across all defined TLV types. - * Local TLV types are valid only for extensions to a given - * HWRM message and may be repeated across different HWRM message - * types. There is a direct correlation of each HWRM message type - * to a single global TLV type value. - * - * Global TLV range: `0 - (63k-1)` - * - * Local TLV range: `63k - (64k-1)` + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE */ - uint16_t tlv_type; + #define SQ_ATOMIC_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) /* - * Length of the message data encapsulated by this TLV in bytes. - * This length does not include the size of the TLV header itself - * and it must be an integer multiple of 8B. + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. */ - uint16_t length; + #define SQ_ATOMIC_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) /* - * Size of the tlv encapsulated response, - * including all tlvs and extension data in 16-byte units. + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. */ - uint8_t total_size; - uint8_t reserved56[7]; - /* Command opcode. */ - uint8_t opcode; - /* Query congestion control response. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - uint8_t enable_cc; - /* Enable. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC UINT32_C(0x1) - /* unused7 is 7 b */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK UINT32_C(0xfe) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_SFT 1 - uint8_t tos_dscp_tos_ecn; - /* IP TOS ECN. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK UINT32_C(0x3) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0 - /* IP TOS DSCP. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK UINT32_C(0xfc) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_SFT 2 - /* Congestion Probability averaging factor. */ - uint8_t g; - /* Number of phases in Fast Recovery and Active Increase. */ - uint8_t num_phases_per_state; - /* The starting value of rate. */ - uint16_t init_cr; - /* The starting value of target rate. */ - uint16_t init_tr; - uint8_t alt_vlan_pcp; - /* Alternate vlan pcp value for CNP packets. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK UINT32_C(0x7) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0 - /* rsvd1 is 5 b */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK UINT32_C(0xf8) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_SFT 3 - uint8_t alt_tos_dscp; - /* Alternate IP TOS DSCP. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK UINT32_C(0x3f) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0 - /* rsvd4 is 2 b */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK UINT32_C(0xc0) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_SFT 6 - uint8_t cc_mode; - /* DCTCP CC algorithm. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP UINT32_C(0x0) + #define SQ_ATOMIC_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* NA for this WQE */ + #define SQ_ATOMIC_HDR_V3_FLAGS_INLINE UINT32_C(0x10) /* - * Probabilistic marking CC algorithm. On chips with CC Gen 0 - * support this will be TCP CC algorithm. + * The atomic WQE does not have a timestamp field, so this field is + * ignored and should be zero. */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC UINT32_C(0x1) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_LAST CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC - /* Specifies the RoCE Tx Queue to use for sending CNP packets. */ - uint8_t tx_queue; - uint16_t rtt; - /* Round trip time in units of usecs */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK UINT32_C(0x3fff) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0 - /* rsvd5 is 2 b */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK UINT32_C(0xc000) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_SFT 14 - uint16_t tcp_cp; - /* The value used as CP when cc_mode is 1(TCP) */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK UINT32_C(0x3ff) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0 - /* rsvd6 is 6 b */ - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK UINT32_C(0xfc00) - #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_SFT 10 - /* Inactivity time after which QP CC parameters are initialized */ - uint16_t inactivity_th; - /* Number of packets per phase. Max is 255. */ - uint8_t pkts_per_phase; - /* Amount of time per phase in units of ms. Max is 15 */ - uint8_t time_per_phase; - uint32_t reserved32; -} creq_query_roce_cc_resp_sb_tlv_t, *pcreq_query_roce_cc_resp_sb_tlv_t; - -/* creq_query_roce_cc_gen1_resp_sb_tlv (size:704b/88B) */ - -typedef struct creq_query_roce_cc_gen1_resp_sb_tlv { + #define SQ_ATOMIC_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) /* - * The command discriminator is used to differentiate between various - * types of HWRM messages. This includes legacy HWRM and RoCE slowpath - * command messages as well as newer TLV encapsulated HWRM commands. + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_ATOMIC_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The size of the WQE in units of 16B chunks. * - * For TLV encapsulated messages this field must be 0x8000. + * For the Atomic WQE, this field will always have a value of 4. */ - uint16_t cmd_discr; - uint8_t reserved_8b; - uint8_t tlv_flags; + #define SQ_ATOMIC_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_ATOMIC_HDR_V3_WQE_SIZE_SFT 0 + uint8_t reserved1; /* - * Indicates the presence of additional TLV encapsulated data - * follows this TLV. + * This value will be returned in the completion if the completion is + * signaled. */ - #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1) - /* Last TLV in a sequence of TLVs. */ - #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) - /* More TLVs follow this TLV. */ - #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + uint32_t opaque; /* - * When an HWRM receiver detects a TLV type that it does not - * support with the TLV required flag set, the receiver must - * reject the HWRM message with an error code indicating an - * unsupported TLV type. + * R_Key provided by remote node when the connection was + * established and placed in the AETH header. It identifies the + * MRW on the remote host. */ - #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) - /* No */ - #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) - /* Yes */ - #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) - #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES + uint32_t remote_key; + uint32_t reserved2; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; /* - * This field defines the TLV type value which is divided into - * two ranges to differentiate between global and local TLV types. - * Global TLV types must be unique across all defined TLV types. - * Local TLV types are valid only for extensions to a given - * HWRM message and may be repeated across different HWRM message - * types. There is a direct correlation of each HWRM message type - * to a single global TLV type value. - * - * Global TLV range: `0 - (63k-1)` + * For compare/swap, this is the data value to be placed in the + * remote host at the specified remote_VA if the comparison succeeds. * - * Local TLV range: `63k - (64k-1)` + * For fetch/add, this is the value to be added to the data in the + * remote host at the specified remote_VA. */ - uint16_t tlv_type; + uint64_t swap_data; /* - * Length of the message data encapsulated by this TLV in bytes. - * This length does not include the size of the TLV header itself - * and it must be an integer multiple of 8B. + * For compare/swap, this is the data value to be compared with the + * value in the remote host at the specified remote_VA. + * + * This field is not used for fetch/add. */ - uint16_t length; - uint64_t reserved64; - /* High order bits of inactivity threshold. */ - uint16_t inactivity_th_hi; - /* The number of uS between generation of CNPs when cc_mode is probabilistic marking. */ - uint16_t min_time_between_cnps; - /* The starting value of congestion probability. Input range is 0 - 1023. */ - uint16_t init_cp; + uint64_t cmp_data; +} sq_atomic_hdr_v3_t, *psq_atomic_hdr_v3_t; + +/* SQ Local Invalidate WQE V3 for RC SQs. */ +/* sq_localinvalidate_v3 (size:128b/16B) */ + +typedef struct sq_localinvalidate_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; /* - * In tr_update_mode 0, Target Rate (TR) is updated to - * halfway between the Current Rate (CR) before and after reduction. - * In tr_update_mode 1, TR is updated to CR's value before reduction. + * Local Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. */ - uint8_t tr_update_mode; + #define SQ_LOCALINVALIDATE_V3_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a) + #define SQ_LOCALINVALIDATE_V3_WQE_TYPE_LAST SQ_LOCALINVALIDATE_V3_WQE_TYPE_LOCAL_INVALID_V3 + uint8_t flags; /* - * Determine for how many RTTs with CNPs in a row, TR is being updated. - * 0: TR is updated when QPC. rtts_with_cnps == 0 - * 1-6: TR is updated if QPC. rtts_with_cnps <= tr_update_cycles - * 7: TR is updated on all reductions. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). */ - uint8_t tr_update_cycles; - /* Number of RTTs in Fast Recovery stage. */ - uint8_t fr_num_rtts; - /* Time increment to increase TR in active increase phase. */ - uint8_t ai_rate_increase; + #define SQ_LOCALINVALIDATE_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) /* - * Indicates for how many RTTs with CNPs after the first one - * to not reduce rate even if CNPs are received. + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE */ - uint16_t reduction_relax_rtts_th; + #define SQ_LOCALINVALIDATE_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) /* - * For low rates, additional number of RTTS with CNPs - * for which no rate reduction is made. - * num_bits: 14 + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. */ - uint16_t additional_relax_cr_th; + #define SQ_LOCALINVALIDATE_V3_FLAGS_UC_FENCE UINT32_C(0x4) /* - * If CR is less than or equal to this value, - * then the actual CR average is set to this value - * (shifted by bw_avg_weight). + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint16_t cr_min_th; - /* Log based averaging weight for QPC variable actual_cr_avg. */ - uint8_t bw_avg_weight; + #define SQ_LOCALINVALIDATE_V3_FLAGS_SE UINT32_C(0x8) /* - * Used to compare CR to this factor times QPC.actual_cr_average - * as a reduction reference. Values between 0 and 6 represent factor of - * 1.125, 1.25, 1.5, 1.75, 2, 2.25, 2.5 respectively. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint8_t actual_cr_factor; - /* The level of CR above which CP is set to maximum level. */ - uint16_t max_cp_cr_th; + #define SQ_LOCALINVALIDATE_V3_FLAGS_INLINE UINT32_C(0x10) /* - * Enable adding fraction of CR to CP. - * 0 for disable, 1 for enable. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint8_t cp_bias_en; - /* Log based fraction of cr to add to CP when cp_bias_en is 1. */ - uint8_t cp_bias; + #define SQ_LOCALINVALIDATE_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) /* - * The value of ECN bits in a CNP packet generated by hardware. - * ECN-Capable Transport (ECT) codepoints supported include: - * 0 for not_ect, 1 for ect_0, 2 for ect_1 + * When set to '1', this operation will cause a trace capture in + * each block it passes through. */ - uint8_t cnp_ecn; - /* Not ECN capable Transport */ - #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT UINT32_C(0x0) - /* ECN Capable Transport-1 */ - #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 UINT32_C(0x1) - /* ECN Capable Transport-0 */ - #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 UINT32_C(0x2) - #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_LAST CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 - /* Enables jitter in RTT. */ - uint8_t rtt_jitter_en; + #define SQ_LOCALINVALIDATE_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; /* - * Number of bytes per usec, dependent on port speed. - * 200 Gbps: 25,000 - * 100 Gbps: 12,500 - * 50 Gbps: 6,250 - * 25 Gbps: 3125 - * 10 Gbps: 1250 + * The size of the WQE in units of 16B chunks. + * + * For the Local Invalidate WQE, this field will always have + * a value of 1. */ - uint16_t link_bytes_per_usec; + #define SQ_LOCALINVALIDATE_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_LOCALINVALIDATE_V3_WQE_SIZE_SFT 0 + uint8_t reserved1; /* - * If CR is greater than or equal to this threshold, - * QPC's CC state is reset to its initial state. + * This value will be returned in the completion if the completion is + * signaled. */ - uint16_t reset_cc_cr_th; + uint32_t opaque; /* - * The number of valid lsbits in CR and TR. - * Supported values include 10 through 14 to support 2^cr_width rate. + * The local key for the MR/W to invalidate; 24 msb of the key + * are used to index the MRW table, 8 lsb are compared with the + * 8 bit key in the MRWC */ - uint8_t cr_width; - /* Lower end of random selection of quota_period. */ - uint8_t quota_period_min; - /* Upper end of random selection of quota_period. */ - uint8_t quota_period_max; + uint32_t inv_l_key; + uint32_t reserved2; +} sq_localinvalidate_v3_t, *psq_localinvalidate_v3_t; + +/* SQ Local Invalidate WQE V3 header for RC SQs. */ +/* sq_localinvalidate_hdr_v3 (size:128b/16B) */ + +typedef struct sq_localinvalidate_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; /* - * The absolute maximum possible quota_period, - * applicable when rate table for lower 24 levels is used. + * Local Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. */ - uint8_t quota_period_abs_max; - /* TR never goes below this level. */ - uint16_t tr_lower_bound; - /* Factor on probability threshold for adding 0.5 to CR randomly. */ - uint8_t cr_prob_factor; - /* Factor on probability threshold for adding 0.5 to TR randomly. */ - uint8_t tr_prob_factor; + #define SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a) + #define SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LOCAL_INVALID_V3 + uint8_t flags; /* - * Threshold to ensure fairness between requester and responder. - * If CR is less than the fairness threshold and a quota period has passed - * priority will be given to the path that did not last transfer data. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). */ - uint16_t fairness_cr_th; - /* Log based rate reduction divider. */ - uint8_t red_div; - /* Threshold for rate reductions when CNPS received over last RTT. */ - uint8_t cnp_ratio_th; + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) /* - * Extended number of RTTS to wait, when there is no congestion, - * to start doubling the rate. + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE */ - uint16_t exp_ai_rtts; - /* Log based CR to CP ratio used in exponential increase. */ - uint8_t exp_ai_cr_cp_ratio; - /* Enable use of lowest 24 rate levels rate_table. */ - uint8_t use_rate_table; + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) /* - * Determines after how many congestion free RTTs to start - * updating CP to track CR. + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. */ - uint16_t cp_exp_update_th; - /* The threshold on congestion free RTTs above which AI can increase to 16. */ - uint16_t high_exp_ai_rtts_th1; - /* The threshold on congestion free RTTs above which AI can increase to 32. */ - uint16_t high_exp_ai_rtts_th2; + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) /* - * The number of congestion free RTTs above which - * reduction based on actual rate is enabled. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint16_t actual_cr_cong_free_rtts_th; + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SE UINT32_C(0x8) /* - * If rtts_with_cong is greater than 7 (severe congestion) and - * CR level post reduction is above this threshold, - * then TR is capped to 1.5 times CR.. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint16_t severe_cong_cr_th1; + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_INLINE UINT32_C(0x10) /* - * If rtts_with_cong is greater than 7 (severe congestion) and - * CR level post reduction is above this threshold, - * then TR is capped to 1.25 times CR.. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint16_t severe_cong_cr_th2; + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) /* - * The maximum number of 64B that can be transmitted during RTT time, - * including all headers and Inter Packet Gap. + * When set to '1', this operation will cause a trace capture in + * each block it passes through. */ - uint32_t link64B_per_rtt; + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; /* - * The number of bytes to subtract from QPC.cc_bucket - * when an ack is scheduled. + * The size of the WQE in units of 16B chunks. + * + * For the Local Invalidate WQE, this field will always have + * a value of 1. */ - uint8_t cc_ack_bytes; + #define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_SFT 0 + uint8_t reserved1; /* - * Enables reduction of CR, TR, and CP to init values when - * congestion free RTTs is greater than reduce2_init_cong_free_rtts_th. + * This value will be returned in the completion if the completion is + * signaled. */ - uint8_t reduce_init_en; + uint32_t opaque; /* - * Minimum threshold value for number of congestion free RTTs before reducing - * to init values for CR, TR, and CP when reduce_init_en is enabled. + * The local key for the MR/W to invalidate; 24 msb of the key + * are used to index the MRW table, 8 lsb are compared with the + * 8 bit key in the MRWC */ - uint16_t reduce_init_cong_free_rtts_th; - /* Enables random no reduction of CR. */ - uint8_t random_no_red_en; - /* Enables coarse correction to actual CR when actual RTT is longer than nominal. */ - uint8_t actual_cr_shift_correction_en; - /* Enables adjustment to refill quota. */ - uint8_t quota_period_adjust_en; - uint8_t reserved[5]; -} creq_query_roce_cc_gen1_resp_sb_tlv_t, *pcreq_query_roce_cc_gen1_resp_sb_tlv_t; - -/*********************** - * cmdq_modify_roce_cc * - ***********************/ - + uint32_t inv_l_key; + uint32_t reserved2; +} sq_localinvalidate_hdr_v3_t, *psq_localinvalidate_hdr_v3_t; -/* cmdq_modify_roce_cc (size:448b/56B) */ +/* + * SQ FR-PMR WQE V3 for RC SQs. + * + * The FR-PMR WQE must be padded to 3 slots (48 bytes) in the SQ, even + * though the final 8 bytes are not shown here. + */ +/* sq_fr_pmr_v3 (size:320b/40B) */ -typedef struct cmdq_modify_roce_cc { - /* Command opcode. */ - uint8_t opcode; - /* Modify congestion control. Can only be issued from a PF. */ - #define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c) - #define CMDQ_MODIFY_ROCE_CC_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* Modify mask signifies the field that is requesting the change. */ - uint32_t modify_mask; - /* Enable change. */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC UINT32_C(0x1) - /* Running average weight change. */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G UINT32_C(0x2) - /* Number of phases in Fast Recovery. */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE UINT32_C(0x4) - /* The starting value of rate change. */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR UINT32_C(0x8) - /* The starting value of target rate change. */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR UINT32_C(0x10) - /* IP TOS ECN change */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN UINT32_C(0x20) - /* IP TOS DSCP change */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP UINT32_C(0x40) - /* Alternate IP TOS ECN change */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP UINT32_C(0x80) - /* Alternate IP TOS DSCP change */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP UINT32_C(0x100) - /* Round trip time in units of usecs */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT UINT32_C(0x200) - /* Congestion Control mode */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE UINT32_C(0x400) - /* The value used as CP when cc_mode is 1(TCP) */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP UINT32_C(0x800) - /* Specifies the RoCE Tx Queue to use for sending CNP packets */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE UINT32_C(0x1000) - /* Inactivity time after which QP CC parameters are initialized */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP UINT32_C(0x2000) - /* Amount of time per phase in units of ms. Max is 15. */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE UINT32_C(0x4000) - /* Number of packets per phase. Max is 255. */ - #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE UINT32_C(0x8000) - uint8_t enable_cc; - /* Enable. */ - #define CMDQ_MODIFY_ROCE_CC_ENABLE_CC UINT32_C(0x1) - /* rsvd1 is 7 b */ - #define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK UINT32_C(0xfe) - #define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1 - /* Congestion Probability averaging factor. */ - uint8_t g; - /* Number of phases in Fast Recovery. */ - uint8_t num_phases_per_state; - /* Number of packets per phase. Max is 255. */ - uint8_t pkts_per_phase; +typedef struct sq_fr_pmr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; /* - * The starting value of rate. - * The max value supported for CC support level 1 is 1024. + * FR-PMR (Fast Register Physical Memory Region) V3 + * + * Allowed only on reliable connection (RC) SQs. */ - uint16_t init_cr; + #define SQ_FR_PMR_V3_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b) + #define SQ_FR_PMR_V3_WQE_TYPE_LAST SQ_FR_PMR_V3_WQE_TYPE_FR_PMR_V3 + uint8_t flags; /* - * The starting value of target rate. - * The max value supported for CC support level 1 is 1024. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). */ - uint16_t init_tr; - uint8_t tos_dscp_tos_ecn; - /* IP TOS ECN. Valid values are 1 or 2 when ECN is enabled. */ - #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK UINT32_C(0x3) - #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0 - /* IP TOS DSCP. */ - #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK UINT32_C(0xfc) - #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2 - uint8_t alt_vlan_pcp; - /* Alternate vlan pcp value for CNP packets. */ - #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK UINT32_C(0x7) - #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0 - /* rsvd3 is 5 b */ - #define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK UINT32_C(0xf8) - #define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3 - uint16_t alt_tos_dscp; - /* Alternate IP TOS DSCP. */ - #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK UINT32_C(0x3f) - #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0 - /* rsvd4 is 10 b */ - #define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK UINT32_C(0xffc0) - #define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6 - uint16_t rtt; + #define SQ_FR_PMR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_FR_PMR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_FR_PMR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_FR_PMR_V3_FLAGS_SE UINT32_C(0x8) /* - * Round trip time in units of usecs. - * The max value supported for CC support level 1 is 2047. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - #define CMDQ_MODIFY_ROCE_CC_RTT_MASK UINT32_C(0x3fff) - #define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0 - /* rsvd5 is 2 b */ - #define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK UINT32_C(0xc000) - #define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14 - uint16_t tcp_cp; - /* The value used as CP when cc_mode is 1(TCP) */ - #define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK UINT32_C(0x3ff) - #define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0 - /* rsvd6 is 6 b */ - #define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK UINT32_C(0xfc00) - #define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10 - uint8_t cc_mode; - /* DCTCP */ - #define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE UINT32_C(0x0) + #define SQ_FR_PMR_V3_FLAGS_INLINE UINT32_C(0x10) /* - * Probabilistic marking. On chips with CC Gen 0 support this - * will be TCP CC algorithm. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - #define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE UINT32_C(0x1) - #define CMDQ_MODIFY_ROCE_CC_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE + #define SQ_FR_PMR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) /* - * Specifies the RoCE Tx Queue to use for sending CNP packets. - * CC support level 0 support 0 to 3 Tx queues. - * CC support level 1 supports 0 to 7 Tx queues. + * When set to '1', this operation will cause a trace capture in + * each block it passes through. */ - uint8_t tx_queue; - /* Inactivity time after which QP CC parameters are initialized */ - uint16_t inactivity_th; - /* Amount of time per phase in units of ms. Max is 15 */ - uint8_t time_per_phase; - /* reserved8 is 8 b */ - uint8_t reserved8_1; - /* reserved16 is 16 b */ - uint16_t reserved16; - uint32_t reserved32; - uint64_t reserved64; -} cmdq_modify_roce_cc_t, *pcmdq_modify_roce_cc_t; - -/* - * TLV encapsulated modify CC command, with extended TLV record - * included for specifying the extended configuration for CC level 1. - */ -/* cmdq_modify_roce_cc_tlv (size:640b/80B) */ - -typedef struct cmdq_modify_roce_cc_tlv { + #define SQ_FR_PMR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size_zero_based; /* - * The command discriminator is used to differentiate between various - * types of HWRM messages. This includes legacy HWRM and RoCE slowpath - * command messages as well as newer TLV encapsulated HWRM commands. + * The size of the WQE in units of 16B chunks. * - * For TLV encapsulated messages this field must be 0x8000. + * For the FR-PMR WQE, this field will always have a value of 3. */ - uint16_t cmd_discr; - uint8_t reserved_8b; - uint8_t tlv_flags; + #define SQ_FR_PMR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_FR_PMR_V3_WQE_SIZE_SFT 0 /* - * Indicates the presence of additional TLV encapsulated data - * follows this TLV. + * If this is set, the PMR will be zero-based. If clear, the PMR + * will be non-zero-based. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE UINT32_C(0x1) - /* Last TLV in a sequence of TLVs. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) - /* More TLVs follow this TLV. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + #define SQ_FR_PMR_V3_ZERO_BASED UINT32_C(0x40) /* - * When an HWRM receiver detects a TLV type that it does not - * support with the TLV required flag set, the receiver must - * reject the HWRM message with an error code indicating an - * unsupported TLV type. + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) - /* No */ - #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) - /* Yes */ - #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) - #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES + uint8_t access_cntl; + /* Local Write Access */ + #define SQ_FR_PMR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* Remote Write Access */ + #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* Remote Atomic Access */ + #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* Window Binding Allowed */ + #define SQ_FR_PMR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) /* - * This field defines the TLV type value which is divided into - * two ranges to differentiate between global and local TLV types. - * Global TLV types must be unique across all defined TLV types. - * Local TLV types are valid only for extensions to a given - * HWRM message and may be repeated across different HWRM message - * types. There is a direct correlation of each HWRM message type - * to a single global TLV type value. - * - * Global TLV range: `0 - (63k-1)` - * - * Local TLV range: `63k - (64k-1)` + * This value will be returned in the completion if the completion is + * signaled. */ - uint16_t tlv_type; + uint32_t opaque; /* - * Length of the message data encapsulated by this TLV in bytes. - * This length does not include the size of the TLV header itself - * and it must be an integer multiple of 8B. + * Local Key; 24 msb of the key are used to index the MRW + * table, 8 lsb are assigned to the 8 bit key_lsb field in + * the MRWC. */ - uint16_t length; - /* Size of the tlv encapsulated command, including all tlvs and extension data in 16-byte units. */ - uint8_t total_size; - uint8_t reserved56[7]; - /* Command opcode. */ - uint8_t opcode; - /* Modify congestion control. Can only be issued from a PF. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c) - #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* Modify mask signifies the field that is requesting the change. */ - uint32_t modify_mask; - /* Enable change. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC UINT32_C(0x1) - /* Running average weight change. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G UINT32_C(0x2) - /* Number of phases in Fast Recovery. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE UINT32_C(0x4) - /* The starting value of rate change. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR UINT32_C(0x8) - /* The starting value of target rate change. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR UINT32_C(0x10) - /* IP TOS ECN change */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN UINT32_C(0x20) - /* IP TOS DSCP change */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP UINT32_C(0x40) - /* Alternate IP TOS ECN change */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP UINT32_C(0x80) - /* Alternate IP TOS DSCP change */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP UINT32_C(0x100) - /* Round trip time in units of usecs */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT UINT32_C(0x200) - /* Congestion Control mode */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE UINT32_C(0x400) - /* The value used as CP when cc_mode is 1(TCP) */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP UINT32_C(0x800) - /* Specifies the RoCE Tx Queue to use for sending CNP packets */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE UINT32_C(0x1000) - /* Inactivity time after which QP CC parameters are initialized */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP UINT32_C(0x2000) - /* Amount of time per phase in units of ms. Max is 15. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE UINT32_C(0x4000) - /* Number of packets per phase. Max is 255. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE UINT32_C(0x8000) - uint8_t enable_cc; - /* Enable. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC UINT32_C(0x1) - /* rsvd1 is 7 b */ - #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK UINT32_C(0xfe) - #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_SFT 1 - /* Congestion Probability averaging factor. */ - uint8_t g; - /* Number of phases in Fast Recovery. */ - uint8_t num_phases_per_state; - /* Number of packets per phase. Max is 255. */ - uint8_t pkts_per_phase; + uint32_t l_key; + uint16_t page_size_log; /* - * The starting value of rate. - * The max value supported for CC support level 1 is 1024. + * This value controls the page size for leaf memory pages in + * a PBL. While many page sizes are supported only the following + * should be tested - 4k, 8k, 64k, 256k, 1m, 2m, 4m, 1g */ - uint16_t init_cr; + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_LAST SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8T /* - * The starting value of target rate. - * The max value supported for CC support level 1 is 1024. + * This value controls the page size for page table elements + * within a PBL. While many page sizes are supported only the + * following should be tested - 4k, 8k, 64k, 256k, 1m, 2m, 4m, 1g */ - uint16_t init_tr; - uint8_t tos_dscp_tos_ecn; - /* IP TOS ECN. Valid values are 1 or 2 when ECN is enabled. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK UINT32_C(0x3) - #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0 - /* IP TOS DSCP. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK UINT32_C(0xfc) - #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_SFT 2 - uint8_t alt_vlan_pcp; - /* Alternate vlan pcp value for CNP packets. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK UINT32_C(0x7) - #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0 - /* rsvd3 is 5 b */ - #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK UINT32_C(0xf8) - #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_SFT 3 - uint16_t alt_tos_dscp; - /* Alternate IP TOS DSCP. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK UINT32_C(0x3f) - #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0 - /* rsvd4 is 10 b */ - #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK UINT32_C(0xffc0) - #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_SFT 6 - uint16_t rtt; + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x3e0) + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_SFT 5 + /* Page size is 4KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (UINT32_C(0x0) << 5) + /* Page size is 8KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (UINT32_C(0x1) << 5) + /* Page size is 16KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (UINT32_C(0x2) << 5) + /* Page size is 32KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (UINT32_C(0x3) << 5) + /* Page size is 64KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (UINT32_C(0x4) << 5) + /* Page size is 128KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (UINT32_C(0x5) << 5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (UINT32_C(0x6) << 5) + /* Page size is 512KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (UINT32_C(0x7) << 5) + /* Page size is 1MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (UINT32_C(0x8) << 5) + /* Page size is 2MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (UINT32_C(0x9) << 5) + /* Page size is 4MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (UINT32_C(0xa) << 5) + /* Page size is 8MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (UINT32_C(0xb) << 5) + /* Page size is 16MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (UINT32_C(0xc) << 5) + /* Page size is 32MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (UINT32_C(0xd) << 5) + /* Page size is 64MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (UINT32_C(0xe) << 5) + /* Page size is 128MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (UINT32_C(0xf) << 5) + /* Page size is 256MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (UINT32_C(0x10) << 5) + /* Page size is 512MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (UINT32_C(0x11) << 5) + /* Page size is 1GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (UINT32_C(0x12) << 5) + /* Page size is 2GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (UINT32_C(0x13) << 5) + /* Page size is 4GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (UINT32_C(0x14) << 5) + /* Page size is 8GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (UINT32_C(0x15) << 5) + /* Page size is 16GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (UINT32_C(0x16) << 5) + /* Page size is 32GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (UINT32_C(0x17) << 5) + /* Page size is 64GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (UINT32_C(0x18) << 5) + /* Page size is 128GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (UINT32_C(0x19) << 5) + /* Page size is 256GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (UINT32_C(0x1a) << 5) + /* Page size is 512GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (UINT32_C(0x1b) << 5) + /* Page size is 1TB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (UINT32_C(0x1c) << 5) + /* Page size is 2TB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (UINT32_C(0x1d) << 5) + /* Page size is 4TB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (UINT32_C(0x1e) << 5) + /* Page size is 8TB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (UINT32_C(0x1f) << 5) + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T + /* Number of levels of PBL for translation */ + #define SQ_FR_PMR_V3_NUMLEVELS_MASK UINT32_C(0xc00) + #define SQ_FR_PMR_V3_NUMLEVELS_SFT 10 /* - * Round trip time in units of usecs. - * The max value supported for CC support level 1 is 2047. + * A zero level PBL means that the VA is the physical address + * used for the operation. No translation is done by the PTU. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK UINT32_C(0x3fff) - #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0 - /* rsvd5 is 2 b */ - #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK UINT32_C(0xc000) - #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_SFT 14 - uint16_t tcp_cp; - /* The value used as CP when cc_mode is 1(TCP) */ - #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK UINT32_C(0x3ff) - #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0 - /* rsvd6 is 6 b */ - #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK UINT32_C(0xfc00) - #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_SFT 10 - uint8_t cc_mode; - /* DCTCP */ - #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE UINT32_C(0x0) + #define SQ_FR_PMR_V3_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 10) /* - * Probabilistic marking. On chips with CC Gen 0 support this - * will be TCP CC algorithm. + * A one layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical + * pages. */ - #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE UINT32_C(0x1) - #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE + #define SQ_FR_PMR_V3_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 10) /* - * Specifies the RoCE Tx Queue to use for sending CNP packets. - * CC support level 0 support 0 to 3 Tx queues. - * CC support level 1 supports 0 to 7 Tx queues. + * A two layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size + * physical pages that contain PBE values that point to actual + * physical pages. */ - uint8_t tx_queue; - /* Inactivity time after which QP CC parameters are initialized */ - uint16_t inactivity_th; - /* Amount of time per phase in units of ms. Max is 15 */ - uint8_t time_per_phase; - /* reserved8 is 8 b */ - uint8_t reserved8_1; - /* reserved16 is 16 b */ - uint16_t reserved16; - uint32_t reserved32; - uint64_t reserved64; - uint64_t reservedtlvpad; -} cmdq_modify_roce_cc_tlv_t, *pcmdq_modify_roce_cc_tlv_t; + #define SQ_FR_PMR_V3_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 10) + #define SQ_FR_PMR_V3_NUMLEVELS_LAST SQ_FR_PMR_V3_NUMLEVELS_LAYER2 + uint16_t reserved; + /* Local Virtual Address */ + uint64_t va; + /* Length in bytes of registered MR */ + uint64_t length; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t pbl_ptr; +} sq_fr_pmr_v3_t, *psq_fr_pmr_v3_t; -/* cmdq_modify_roce_cc_gen1_tlv (size:768b/96B) */ +/* SQ FR-PMR WQE V3 header for RC SQs. */ +/* sq_fr_pmr_hdr_v3 (size:320b/40B) */ -typedef struct cmdq_modify_roce_cc_gen1_tlv { +typedef struct sq_fr_pmr_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; /* - * The command discriminator is used to differentiate between various - * types of HWRM messages. This includes legacy HWRM and RoCE slowpath - * command messages as well as newer TLV encapsulated HWRM commands. + * FR-PMR (Fast Register Physical Memory Region) V3 * - * For TLV encapsulated messages this field must be 0x8000. + * Allowed only on reliable connection (RC) SQs. */ - uint16_t cmd_discr; - uint8_t reserved_8b; - uint8_t tlv_flags; + #define SQ_FR_PMR_HDR_V3_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b) + #define SQ_FR_PMR_HDR_V3_WQE_TYPE_LAST SQ_FR_PMR_HDR_V3_WQE_TYPE_FR_PMR_V3 + uint8_t flags; /* - * Indicates the presence of additional TLV encapsulated data - * follows this TLV. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE UINT32_C(0x1) - /* Last TLV in a sequence of TLVs. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) - /* More TLVs follow this TLV. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + #define SQ_FR_PMR_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) /* - * When an HWRM receiver detects a TLV type that it does not - * support with the TLV required flag set, the receiver must - * reject the HWRM message with an error code indicating an - * unsupported TLV type. + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) - /* No */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) - /* Yes */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES + #define SQ_FR_PMR_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) /* - * This field defines the TLV type value which is divided into - * two ranges to differentiate between global and local TLV types. - * Global TLV types must be unique across all defined TLV types. - * Local TLV types are valid only for extensions to a given - * HWRM message and may be repeated across different HWRM message - * types. There is a direct correlation of each HWRM message type - * to a single global TLV type value. - * - * Global TLV range: `0 - (63k-1)` - * - * Local TLV range: `63k - (64k-1)` + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. */ - uint16_t tlv_type; + #define SQ_FR_PMR_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) /* - * Length of the message data encapsulated by this TLV in bytes. - * This length does not include the size of the TLV header itself - * and it must be an integer multiple of 8B. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint16_t length; - uint64_t reserved64; - /* Modify mask signifies the field that is requesting the change. */ - uint64_t modify_mask; - /* Update the number of uS between generation of CNPs for probabilistic marking mode. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS UINT32_C(0x1) + #define SQ_FR_PMR_HDR_V3_FLAGS_SE UINT32_C(0x8) /* - * Update starting value of Congestion Probability (CP). - * Maximum value supported is 1023. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP UINT32_C(0x2) - /* Update Target Rate (TR) Update Mode. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE UINT32_C(0x4) - /* Update number of RTTs with CNPs in a row for TR update. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES UINT32_C(0x8) - /* Update number of RTTs in Fast Recovery stage. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS UINT32_C(0x10) - /* Update time increment to increase TR in active increase phase. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE UINT32_C(0x20) + #define SQ_FR_PMR_HDR_V3_FLAGS_INLINE UINT32_C(0x10) /* - * Update count of RTTs with CNPs, received after - * the first one, to wait, before reducing rate. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH UINT32_C(0x40) + #define SQ_FR_PMR_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) /* - * Update additional number of RTTS with CNPs, to wait, - * before further rate reduction, for low rates. + * When set to '1', this operation will cause a trace capture in + * each block it passes through. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH UINT32_C(0x80) - /* Update threshold for update to Actual Current Rate (CR) */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH UINT32_C(0x100) - /* Update log based averaging weight for QPC variable actual_cr */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT UINT32_C(0x200) - /* Update factor used in the computation of rate reduction. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR UINT32_C(0x400) - /* Update the level of CR above which CP is set to maximum level. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH UINT32_C(0x800) - /* Enable adding fraction of CR to CP. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN UINT32_C(0x1000) + #define SQ_FR_PMR_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size_zero_based; /* - * Update log based fraction of CR to add to CP - * when cp_bias_en is 1. + * The size of the WQE in units of 16B chunks. + * + * For the FR-PMR WQE, this field will always have a value of 3. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS UINT32_C(0x2000) - /* Update ECN bits in a CNP packet generated by hardware. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN UINT32_C(0x4000) - /* Update enable of jitter in RTT. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN UINT32_C(0x8000) - /* Update number of bytes per usec. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC UINT32_C(0x10000) - /* Update threshold used to reset QPC CC state to its initial state. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH UINT32_C(0x20000) - /* Update number of valid lsbits in CR and TR */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH UINT32_C(0x40000) - /* Update lower end of random selection of quota_period. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN UINT32_C(0x80000) - /* Update upper end of random selection of quota_period. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX UINT32_C(0x100000) + #define SQ_FR_PMR_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_FR_PMR_HDR_V3_WQE_SIZE_SFT 0 /* - * Update absolute maximum possible quota_period, - * when rate table for lower 24 levels is used. + * If this is set, the PMR will be zero-based. If clear, the PMR + * will be non-zero-based. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX UINT32_C(0x200000) - /* Update lower bound of TR. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND UINT32_C(0x400000) + #define SQ_FR_PMR_HDR_V3_ZERO_BASED UINT32_C(0x40) /* - * Update factor on probability threshold for adding - * 0.5 to CR randomly. + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR UINT32_C(0x800000) + uint8_t access_cntl; + /* Local Write Access */ + #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* Remote Write Access */ + #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* Remote Atomic Access */ + #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* Window Binding Allowed */ + #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) /* - * Update factor on probability threshold for adding - * 0.5 to TR randomly. + * This value will be returned in the completion if the completion is + * signaled. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR UINT32_C(0x1000000) + uint32_t opaque; /* - * Update threshold that ensures fairness between requester - * and responder + * Local Key; 24 msb of the key are used to index the MRW + * table, 8 lsb are assigned to the 8 bit key_lsb field in + * the MRWC. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH UINT32_C(0x2000000) - /* Update log based rate reduction divider. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV UINT32_C(0x4000000) + uint32_t l_key; + uint16_t page_size_log; /* - * Update threshold for rate reductions when CNPS received - * over last RTT. + * This value controls the page size for leaf memory pages in + * a PBL. While many page sizes are supported only the following + * should be tested - 4k, 8k, 64k, 256k, 1m, 2m, 4m, 1g */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH UINT32_C(0x8000000) + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8T + /* + * This value controls the page size for page table elements + * within a PBL. While many page sizes are supported only the + * following should be tested - 4k, 8k, 64k, 256k, 1m, 2m, 4m, 1g + */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x3e0) + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_SFT 5 + /* Page size is 4KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (UINT32_C(0x0) << 5) + /* Page size is 8KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (UINT32_C(0x1) << 5) + /* Page size is 16KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (UINT32_C(0x2) << 5) + /* Page size is 32KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (UINT32_C(0x3) << 5) + /* Page size is 64KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (UINT32_C(0x4) << 5) + /* Page size is 128KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (UINT32_C(0x5) << 5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (UINT32_C(0x6) << 5) + /* Page size is 512KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (UINT32_C(0x7) << 5) + /* Page size is 1MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (UINT32_C(0x8) << 5) + /* Page size is 2MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (UINT32_C(0x9) << 5) + /* Page size is 4MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (UINT32_C(0xa) << 5) + /* Page size is 8MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (UINT32_C(0xb) << 5) + /* Page size is 16MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (UINT32_C(0xc) << 5) + /* Page size is 32MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (UINT32_C(0xd) << 5) + /* Page size is 64MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (UINT32_C(0xe) << 5) + /* Page size is 128MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (UINT32_C(0xf) << 5) + /* Page size is 256MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (UINT32_C(0x10) << 5) + /* Page size is 512MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (UINT32_C(0x11) << 5) + /* Page size is 1GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (UINT32_C(0x12) << 5) + /* Page size is 2GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (UINT32_C(0x13) << 5) + /* Page size is 4GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (UINT32_C(0x14) << 5) + /* Page size is 8GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (UINT32_C(0x15) << 5) + /* Page size is 16GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (UINT32_C(0x16) << 5) + /* Page size is 32GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (UINT32_C(0x17) << 5) + /* Page size is 64GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (UINT32_C(0x18) << 5) + /* Page size is 128GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (UINT32_C(0x19) << 5) + /* Page size is 256GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (UINT32_C(0x1a) << 5) + /* Page size is 512GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (UINT32_C(0x1b) << 5) + /* Page size is 1TB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (UINT32_C(0x1c) << 5) + /* Page size is 2TB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (UINT32_C(0x1d) << 5) + /* Page size is 4TB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (UINT32_C(0x1e) << 5) + /* Page size is 8TB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (UINT32_C(0x1f) << 5) + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T + /* Number of levels of PBL for translation */ + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_MASK UINT32_C(0xc00) + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_SFT 10 /* - * Update extended number of RTTS to wait, - * when there is no congestion, to start doubling the rate. + * A zero level PBL means that the VA is the physical address + * used for the operation. No translation is done by the PTU. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS UINT32_C(0x10000000) - /* Update log based CR to CP ratio used in exponential increase. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO UINT32_C(0x20000000) + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 10) /* - * Update threshold, in congestion free RTTs, - * that triggers start of CP update to track CR. + * A one layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical + * pages. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH UINT32_C(0x40000000) + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 10) /* - * Update threshold on congestion free RTTs above - * which AI can increase to 16. + * A two layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size + * physical pages that contain PBE values that point to actual + * physical pages. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 UINT32_C(0x80000000) + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 10) + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAST SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER2 + uint16_t reserved; + /* Local Virtual Address */ + uint64_t va; + /* Length in bytes of registered MR */ + uint64_t length; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t pbl_ptr; +} sq_fr_pmr_hdr_v3_t, *psq_fr_pmr_hdr_v3_t; + +/* + * SQ Bind WQE V3. This WQE can perform either: + * * type1 "bind memory window", if mw_type==Type1 + * * type2 "post send bind memory window", if mw_type==Type2 + */ +/* sq_bind_v3 (size:256b/32B) */ + +typedef struct sq_bind_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; /* - * Update threshold on congestion free RTTs above - * which AI can increase to 32. + * Memory Bind V3 + * + * Allowed only on reliable connection (RC) SQs. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 UINT32_C(0x100000000)L - /* Update use of lowest 24 rate levels rate_table. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE UINT32_C(0x200000000)L + #define SQ_BIND_V3_WQE_TYPE_BIND_V3 UINT32_C(0x1c) + #define SQ_BIND_V3_WQE_TYPE_LAST SQ_BIND_V3_WQE_TYPE_BIND_V3 + uint8_t flags; /* - * Update the maximum number of 64B that can be transmitted - * during RTT time. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT UINT32_C(0x400000000)L + #define SQ_BIND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) /* - * Update number of congestion free RTTs above which - * reduction based on actual rate is enabled. + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH UINT32_C(0x800000000)L + #define SQ_BIND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) /* - * Update threshold used in severe congestion for - * limiting TR to 1.5 times CR. + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 UINT32_C(0x1000000000)L + #define SQ_BIND_V3_FLAGS_UC_FENCE UINT32_C(0x4) /* - * Update threshold used in severe congestion for - * limiting TR to 1.25 times CR. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 UINT32_C(0x2000000000)L + #define SQ_BIND_V3_FLAGS_SE UINT32_C(0x8) /* - * Update number of bytes to subtract from QPC.cc_bucket - * when an ack is scheduled. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES UINT32_C(0x4000000000)L - /* Update enable of reduction of CR, TR, and CP to init values. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN UINT32_C(0x8000000000)L - /* Update threshold used for reduction of CR, TR, and CP to init values. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH UINT32_C(0x10000000000)L - /* Update enable of random no reduction of CR. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN UINT32_C(0x20000000000)L - /* Update enable of coarse correction to actual CR. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN UINT32_C(0x40000000000)L - /* Update enable of adjustment to refill quota. */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN UINT32_C(0x80000000000)L - /* High order bits of inactivity threshold. */ - uint16_t inactivity_th_hi; - /* The number of uS between generation of CNPs when cc_mode is probabilistic marking. */ - uint16_t min_time_between_cnps; - /* The starting value of congestion probability. Input range is 0 - 1023. */ - uint16_t init_cp; + #define SQ_BIND_V3_FLAGS_INLINE UINT32_C(0x10) /* - * In tr_update_mode 0, Target Rate (TR) is updated to - * halfway between the Current Rate (CR) before and after reduction. - * In tr_update_mode 1, TR is updated to CR's value before reduction. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint8_t tr_update_mode; + #define SQ_BIND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) /* - * Determine for how many RTTs with CNPs in a row, TR is being updated. - * 0: TR is updated when QPC. rtts_with_cnps == 0 - * 1-6: TR is updated if QPC. rtts_with_cnps <= tr_update_cycles - * 7: TR is updated on all reductions. + * When set to '1', this operation will cause a trace capture in + * each block it passes through. */ - uint8_t tr_update_cycles; - /* Number of RTTs in Fast Recovery stage. */ - uint8_t fr_num_rtts; - /* Time increment to increase TR in active increase phase. */ - uint8_t ai_rate_increase; + #define SQ_BIND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint8_t wqe_size_zero_based_mw_type; /* - * Indicates for how many RTTs with CNPs after the first one - * to not reduce rate even if CNPs are received. + * The size of the WQE in units of 16B chunks. + * + * For the Bind WQE, this field will always have a value of 2. */ - uint16_t reduction_relax_rtts_th; + #define SQ_BIND_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_BIND_V3_WQE_SIZE_SFT 0 /* - * For low rates, additional number of RTTS with CNPs - * for which no rate reduction is made. - * num_bits: 14 + * If this bit is set, then the newly-bound memory window will be + * zero-based. If clear, then the newly-bound memory window will be + * non-zero-based. */ - uint16_t additional_relax_cr_th; + #define SQ_BIND_V3_ZERO_BASED UINT32_C(0x40) /* - * If CR is less than or equal to this value, - * then the actual CR average is set to this value - * (shifted by bw_avg_weight). + * If type1 is specified, then this WQE performs a "bind memory + * window" operation on a type1 window. If type2 is specified, then + * this WQE performs a "post send bind memory window" operation on a + * type2 window. + * + * Note that the bind WQE cannot change the type of the memory + * window. + * + * If a "bind memory window" operation is attempted on a memory + * window that was allocated as type2, then the bind will fail with + * an errored completion, as "bind memory window" is allowed only on + * type1 memory windows. + * + * Similarly, if a "post send bind memory window" operation is + * attempted on a memory window that was allocated as type1, then the + * bind will fail with an errored completions, as "post send bind + * memory window" is allowed only on type2 memory windows. */ - uint16_t cr_min_th; - /* Log based averaging weight for QPC variable actual_cr_avg. */ - uint8_t bw_avg_weight; + #define SQ_BIND_V3_MW_TYPE UINT32_C(0x80) + /* Type 1 Bind Memory Window */ + #define SQ_BIND_V3__TYPE1 (UINT32_C(0x0) << 7) + /* Type 2 Post Send Bind Memory Window */ + #define SQ_BIND_V3__TYPE2 (UINT32_C(0x1) << 7) + #define SQ_BIND_V3__LAST SQ_BIND_V3__TYPE2 /* - * Used to compare CR to this factor times QPC.actual_cr_average - * as a reduction reference. Values between 0 and 6 represent factor of - * 1.125, 1.25, 1.5, 1.75, 2, 2.25, 2.5 respectively. + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. */ - uint8_t actual_cr_factor; - /* The level of CR above which CP is set to maximum level. */ - uint16_t max_cp_cr_th; + uint8_t access_cntl; /* - * Enable adding fraction of CR to CP. - * 0 for disable, 1 for enable. + * Local Write Access. + * + * Local accesses are never allowed for memory windows, so this + * bit must always be zero in a bind WQE. If this bit is ever + * set, the bind will fail with an errored completion. */ - uint8_t cp_bias_en; - /* Log based fraction of cr to add to CP when cp_bias_en is 1. */ - uint8_t cp_bias; + #define SQ_BIND_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) /* - * The value of ECN bits in a CNP packet generated by hardware. - * ECN-Capable Transport (ECT) codepoints supported include: - * 0 for not_ect, 1 for ect_0, 2 for ect_1 + * Remote Write Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is not + * the case, then the bind will fail with an errored completion. */ - uint8_t cnp_ecn; - /* Not ECN capable Transport */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT UINT32_C(0x0) - /* ECN Capable Transport-1 */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 UINT32_C(0x1) - /* ECN Capable Transport-0 */ - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 UINT32_C(0x2) - #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 - /* Enables jitter in RTT. */ - uint8_t rtt_jitter_en; + #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) /* - * Number of bytes per usec, dependent on port speed. - * 200 Gbps: 25,000 - * 100 Gbps: 12,500 - * 50 Gbps: 6,250 - * 25 Gbps: 3125 - * 10 Gbps: 1250 + * Remote Atomic Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is not + * the case, then the bind will fail with an errored completion. */ - uint16_t link_bytes_per_usec; + #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) /* - * If CR is greater than or equal to this threshold, - * QPC's CC state is reset to its initial state. + * Window Binding Allowed. + * + * It is never allowed to bind windows to windows, so this bit + * must always be zero in a bind WQE. If this bit is ever set, + * the bind will fail with an errored completion. */ - uint16_t reset_cc_cr_th; + #define SQ_BIND_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) /* - * The number of valid lsbits in CR and TR. - * Supported values include 10 through 14 to support 2^cr_width rate. + * This value will be returned in the completion if the completion is + * signaled. */ - uint8_t cr_width; - /* Lower end of random selection of quota_period. */ - uint8_t quota_period_min; - /* Upper end of random selection of quota_period. */ - uint8_t quota_period_max; + uint32_t opaque; /* - * The absolute maximum possible quota_period, - * applicable when rate table for lower 24 levels is used. + * The L_Key of the parent MR; 24 msb of the key are used to + * index the MRW table, 8 lsb are compared with the 8 bit key + * in the MRWC. */ - uint8_t quota_period_abs_max; - /* TR never goes below this level. */ - uint16_t tr_lower_bound; - /* Factor on probability threshold for adding 0.5 to CR randomly. */ - uint8_t cr_prob_factor; - /* Factor on probability threshold for adding 0.5 to TR randomly. */ - uint8_t tr_prob_factor; + uint32_t parent_l_key; /* - * Threshold to ensure fairness between requester and responder. - * If CR is less than the fairness threshold and a quota period has passed - * priority will be given to the path that did not last transfer data. + * Local Key; 24 msb of the key are used to index the memory + * window being bound in the MRW table, 8 lsb are assign to the + * 8 bit key_lsb field in the MRWC. */ - uint16_t fairness_cr_th; - /* Log based rate reduction divider. */ - uint8_t red_div; - /* Threshold for rate reductions when CNPS received over last RTT. */ - uint8_t cnp_ratio_th; + uint32_t l_key; + /* Local Virtual Address */ + uint64_t va; /* - * Extended number of RTTS to wait, when there is no congestion, - * to start doubling the rate. + * Length in bytes of registered MW; 40 bits as this is the max + * size of an MR/W */ - uint16_t exp_ai_rtts; - /* Log based CR to CP ratio used in exponential increase. */ - uint8_t exp_ai_cr_cp_ratio; - /* Enable use of lowest 24 rate levels rate_table. */ - uint8_t use_rate_table; + uint64_t length; +} sq_bind_v3_t, *psq_bind_v3_t; + +/* + * SQ Bind WQE V3 header. This WQE can perform either: + * * type1 "bind memory window", if mw_type==Type1 + * * type2 "post send bind memory window", if mw_type==Type2 + */ +/* sq_bind_hdr_v3 (size:256b/32B) */ + +typedef struct sq_bind_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; /* - * Determines after how many congestion free RTTs to start - * updating CP to track CR. + * Memory Bind V3 + * + * Allowed only on reliable connection (RC) SQs. */ - uint16_t cp_exp_update_th; - /* The threshold on congestion free RTTs above which AI can increase to 16. */ - uint16_t high_exp_ai_rtts_th1; - /* The threshold on congestion free RTTs above which AI can increase to 32. */ - uint16_t high_exp_ai_rtts_th2; + #define SQ_BIND_HDR_V3_WQE_TYPE_BIND_V3 UINT32_C(0x1c) + #define SQ_BIND_HDR_V3_WQE_TYPE_LAST SQ_BIND_HDR_V3_WQE_TYPE_BIND_V3 + uint8_t flags; /* - * The number of congestion free RTTs above which - * reduction based on actual rate is enabled. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). */ - uint16_t actual_cr_cong_free_rtts_th; + #define SQ_BIND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) /* - * If rtts_with_cong is greater than 7 (severe congestion) and - * CR level post reduction is above this threshold, - * then TR is capped to 1.5 times CR.. + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE */ - uint16_t severe_cong_cr_th1; + #define SQ_BIND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) /* - * If rtts_with_cong is greater than 7 (severe congestion) and - * CR level post reduction is above this threshold, - * then TR is capped to 1.25 times CR.. + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. */ - uint16_t severe_cong_cr_th2; + #define SQ_BIND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) /* - * The maximum number of 64B that can be transmitted during RTT time, - * including all headers and Inter Packet Gap. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint32_t link64B_per_rtt; + #define SQ_BIND_HDR_V3_FLAGS_SE UINT32_C(0x8) /* - * The number of bytes to subtract from QPC.cc_bucket - * when an ack is scheduled. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint8_t cc_ack_bytes; + #define SQ_BIND_HDR_V3_FLAGS_INLINE UINT32_C(0x10) /* - * Enables reduction of CR, TR, and CP to init values when - * congestion free RTTs is greater than reduce2_init_cong_free_rtts_th. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint8_t reduce_init_en; + #define SQ_BIND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) /* - * Minimum threshold value for number of congestion free RTTs before reducing - * to init values for CR, TR, and CP when reduce_init_en is enabled. + * When set to '1', this operation will cause a trace capture in + * each block it passes through. */ - uint16_t reduce_init_cong_free_rtts_th; - /* Enables random no reduction of CR. */ - uint8_t random_no_red_en; - /* Enables coarse correction to actual CR when actual RTT is longer than nominal. */ - uint8_t actual_cr_shift_correction_en; - /* Enables adjustment to refill quota. */ - uint8_t quota_period_adjust_en; - uint8_t reserved[5]; -} cmdq_modify_roce_cc_gen1_tlv_t, *pcmdq_modify_roce_cc_gen1_tlv_t; - -/* creq_modify_roce_cc_resp (size:128b/16B) */ - -typedef struct creq_modify_roce_cc_resp { - uint8_t type; + #define SQ_BIND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint8_t wqe_size_zero_based_mw_type; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * The size of the WQE in units of 16B chunks. + * + * For the Bind WQE, this field will always have a value of 2. */ - #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_LAST CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - uint32_t reserved32; - uint8_t v; + #define SQ_BIND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_BIND_HDR_V3_WQE_SIZE_SFT 0 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * If this bit is set, then the newly-bound memory window will be + * zero-based. If clear, then the newly-bound memory window will be + * non-zero-based. */ - #define CREQ_MODIFY_ROCE_CC_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Modify congestion control response. */ - #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC UINT32_C(0x8c) - #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_LAST CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC - uint8_t reserved48[6]; -} creq_modify_roce_cc_resp_t, *pcreq_modify_roce_cc_resp_t; - -/****************************** - * cmdq_set_link_aggr_mode_cc * - ******************************/ - - -/* cmdq_set_link_aggr_mode_cc (size:320b/40B) */ - -typedef struct cmdq_set_link_aggr_mode_cc { - /* Command opcode. */ - uint8_t opcode; - /* Set LAG mode. */ - #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE UINT32_C(0x8f) - #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_LAST CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* Modify mask signifies the field that is requesting the change. */ - uint32_t modify_mask; - /* Enable Link aggregation. */ - #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN UINT32_C(0x1) - /* Bitmap of ports that are eligible to transmit RoCE traffic. */ - #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP UINT32_C(0x2) - /* Bitmap of ports that are members of the RoCE LAG. */ - #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP UINT32_C(0x4) - /* Link aggregation mode being used. */ - #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE UINT32_C(0x8) - /* Stat context ID for all the ports. */ - #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID UINT32_C(0x10) - uint8_t aggr_enable; - /* Enable Link aggregation. */ - #define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE UINT32_C(0x1) - /* rsvd1 is 7 b */ - #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK UINT32_C(0xfe) - #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_SFT 1 - uint8_t active_port_map; - /* Bitmap of ports that are eligible to transmit RoCE traffic. */ - #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK UINT32_C(0xf) - #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0 - /* rsvd2 is 4 b */ - #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK UINT32_C(0xf0) - #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_SFT 4 - /* Bitmap of ports that are members of the RoCE LAG. */ - uint8_t member_port_map; - /* Link aggregation mode being used. */ - uint8_t link_aggr_mode; - /* active active mode. */ - #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) - /* active backup mode. */ - #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) - /* Balance XOR mode. */ - #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) - /* 802.3AD mode. */ - #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD UINT32_C(0x4) - #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_LAST CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD - /* Stat context IDs for all 4 ports. */ - uint16_t stat_ctx_id[4]; - uint64_t rsvd1; -} cmdq_set_link_aggr_mode_cc_t, *pcmdq_set_link_aggr_mode_cc_t; - -/* creq_set_link_aggr_mode_resources_resp (size:128b/16B) */ - -typedef struct creq_set_link_aggr_mode_resources_resp { - uint8_t type; + #define SQ_BIND_HDR_V3_ZERO_BASED UINT32_C(0x40) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * If type1 is specified, then this WQE performs a "bind memory + * window" operation on a type1 window. If type2 is specified, then + * this WQE performs a "post send bind memory window" operation on a + * type2 window. + * + * Note that the bind WQE cannot change the type of the memory + * window. + * + * If a "bind memory window" operation is attempted on a memory + * window that was allocated as type2, then the bind will fail with + * an errored completion, as "bind memory window" is allowed only on + * type1 memory windows. + * + * Similarly, if a "post send bind memory window" operation is + * attempted on a memory window that was allocated as type1, then the + * bind will fail with an errored completions, as "post send bind + * memory window" is allowed only on type2 memory windows. */ - #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK UINT32_C(0x3f) - #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_LAST CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - uint32_t reserved32; - uint8_t v; + #define SQ_BIND_HDR_V3_MW_TYPE UINT32_C(0x80) + /* Type 1 Bind Memory Window */ + #define SQ_BIND_HDR_V3__TYPE1 (UINT32_C(0x0) << 7) + /* Type 2 Post Send Bind Memory Window */ + #define SQ_BIND_HDR_V3__TYPE2 (UINT32_C(0x1) << 7) + #define SQ_BIND_HDR_V3__LAST SQ_BIND_HDR_V3__TYPE2 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. */ - #define CREQ_SET_LINK_AGGR_MODE_RESP_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Set LAG mode. */ - #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE UINT32_C(0x8f) - #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_LAST CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE - uint8_t reserved48[6]; -} creq_set_link_aggr_mode_resources_resp_t, *pcreq_set_link_aggr_mode_resources_resp_t; - -/* Send a request from VF to pass a command to the PF. VF HSI is suspended. */ -/* cmdq_vf_backchannel_request (size:256b/32B) */ - -typedef struct cmdq_vf_backchannel_request { - /* Command opcode. */ - uint8_t opcode; - /* Send a request from VF to pass a command to the PF. VF HSI is suspended until the PF returns the response */ - #define CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86) - #define CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_LAST CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_VF_BACKCHANNEL_REQUEST - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* Address of command request structure in VF space */ - uint64_t command_addr; - /* Command request length (up to 4K). An optional address of the extended response buffer should be provided in the request */ - uint16_t command_length; - uint8_t unused_0[6]; -} cmdq_vf_backchannel_request_t, *pcmdq_vf_backchannel_request_t; - -/* Read VF memory (primarily to get the backchannel request blob). */ -/* cmdq_read_vf_memory (size:256b/32B) */ - -typedef struct cmdq_read_vf_memory { - /* Command opcode. */ - uint8_t opcode; - /* Read VF memory (primarily to get the backchannel request blob). Can only be issued from a PF. */ - #define CMDQ_READ_VF_MEMORY_OPCODE_READ_VF_MEMORY UINT32_C(0x87) - #define CMDQ_READ_VF_MEMORY_OPCODE_LAST CMDQ_READ_VF_MEMORY_OPCODE_READ_VF_MEMORY - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* Address of memory in VF space to read */ - uint64_t addr; - /* VF id, as provided in 0xC0 VF request notification */ - uint16_t vf_id; - /* Length to read, up to 4K */ - uint16_t length; - uint32_t unused_0; -} cmdq_read_vf_memory_t, *pcmdq_read_vf_memory_t; - -/* Write VF memory (primarily to put the backchannel response blob). */ -/* cmdq_complete_vf_request (size:320b/40B) */ - -typedef struct cmdq_complete_vf_request { - /* Command opcode. */ - uint8_t opcode; - /* Write VF memory (primarily to put the backchannel response blob), and reenable VF HSI (post a CAG completion to it). Can only be issued from a PF. */ - #define CMDQ_COMPLETE_VF_REQUEST_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88) - #define CMDQ_COMPLETE_VF_REQUEST_OPCODE_LAST CMDQ_COMPLETE_VF_REQUEST_OPCODE_COMPLETE_VF_REQUEST - /* Size of the command in 16-byte units. */ - uint8_t cmd_size; - /* Flags and attribs of the command. */ - uint16_t flags; - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - /* Size of the response buffer in 16-byte units. */ - uint8_t resp_size; - uint8_t reserved8; - /* Host address of the response. */ - uint64_t resp_addr; - /* Optional address of extended response in VF space to write. Length is in resp_size in 16 byte units. */ - uint64_t addr; - /* Completion misc field to VF CREQ */ - uint32_t vf_misc; - /* VF id, as provided in 0xC0 VF request notification */ - uint16_t vf_id; - /* Completion cookie for the VF command, goes to VF CREQ */ - uint16_t vf_cookie; - /* Completion status for the VF command, goes to VF CREQ */ - uint8_t vf_status; - uint8_t unused_0[3]; - uint32_t unused_1; -} cmdq_complete_vf_request_t, *pcmdq_complete_vf_request_t; - -/* RoCE function async event notifications. */ -/* creq_func_event (size:128b/16B) */ - -typedef struct creq_func_event { - uint8_t type; + uint8_t access_cntl; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Local Write Access. + * + * Local accesses are never allowed for memory windows, so this + * bit must always be zero in a bind WQE. If this bit is ever + * set, the bind will fail with an errored completion. */ - #define CREQ_FUNC_EVENT_TYPE_MASK UINT32_C(0x3f) - #define CREQ_FUNC_EVENT_TYPE_SFT 0 - /* Function Async Notification */ - #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT UINT32_C(0x3a) - #define CREQ_FUNC_EVENT_TYPE_LAST CREQ_FUNC_EVENT_TYPE_FUNC_EVENT - uint8_t reserved56[7]; - uint8_t v; + #define SQ_BIND_HDR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Remote Write Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is not + * the case, then the bind will fail with an errored completion. */ - #define CREQ_FUNC_EVENT_V UINT32_C(0x1) + #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) /* - * This value defines what type of async event has occurred - * on the function. + * Remote Atomic Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is not + * the case, then the bind will fail with an errored completion. */ - uint8_t event; + #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) /* - * Invalid PBL or PCIE UR response occurred - * in SQ WQE or IRRQ read access. + * Window Binding Allowed. + * + * It is never allowed to bind windows to windows, so this bit + * must always be zero in a bind WQE. If this bit is ever set, + * the bind will fail with an errored completion. */ - #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR UINT32_C(0x1) + #define SQ_BIND_HDR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) /* - * Invalid PBL or PCIE UR response occurred - * during data read access. + * This value will be returned in the completion if the completion is + * signaled. */ - #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR UINT32_C(0x2) + uint32_t opaque; /* - * Invalid PBL or PCIE UR response occurred - * in RQ/SRQ WQE or ORRQ read access. + * The L_Key of the parent MR; 24 msb of the key are used to + * index the MRW table, 8 lsb are compared with the 8 bit key + * in the MRWC. */ - #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR UINT32_C(0x3) - /* Invalid PBL occurred during data write access. */ - #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR UINT32_C(0x4) - /* Invalid PBL occurred during CQ write access. */ - #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR UINT32_C(0x5) + uint32_t parent_l_key; /* - * Invalid PBL or PCIE UR response occurred in TQM - * read access. + * Local Key; 24 msb of the key are used to index the memory + * window being bound in the MRW table, 8 lsb are assign to the + * 8 bit key_lsb field in the MRWC. */ - #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR UINT32_C(0x6) - /* PCIE UR response occurred in CFC read access. */ - #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR UINT32_C(0x7) - /* PCIE UR response occurred in CFC read access. */ - #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR UINT32_C(0x8) - /* PCIE UR response occurred in CFC read access. */ - #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR UINT32_C(0x9) - /* PCIE UR response occurred in CFC read access. */ - #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR UINT32_C(0xa) + uint32_t l_key; + /* Local Virtual Address */ + uint64_t va; /* - * Invalid PBL or - * PCIE UR response - * occurred on timer read access. + * Length in bytes of registered MW; 40 bits as this is the max + * size of an MR/W */ - #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR UINT32_C(0xb) - /* A VF sent a backchannel command request */ - #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST UINT32_C(0x80) - /* Communication resource (QPC, CQ, SRQ, MRW) exhausted, and resource array extension is enabled */ - #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED UINT32_C(0x81) - #define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED - uint8_t reserved48[6]; -} creq_func_event_t, *pcreq_func_event_t; + uint64_t length; +} sq_bind_hdr_v3_t, *psq_bind_hdr_v3_t; -/* RoCE slowpath command completion events. */ -/* creq_qp_event (size:128b/16B) */ +/* + * This is the Change UDP Source Port WQE V3 structure. It is supported + * for both RC and UD QP's. + * + * It is recommended to set the uc_fence flag for this WQE, so that the + * source port does not change while there are unacknowledged packets. + */ +/* sq_change_udpsrcport_v3 (size:128b/16B) */ -typedef struct creq_qp_event { - uint8_t type; +typedef struct sq_change_udpsrcport_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Change UDP Source Port V3 */ + #define SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e) + #define SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_LAST SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 + uint8_t flags; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). */ - #define CREQ_QP_EVENT_TYPE_MASK UINT32_C(0x3f) - #define CREQ_QP_EVENT_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_QP_EVENT_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_QP_EVENT_TYPE_LAST CREQ_QP_EVENT_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* Success. */ - #define CREQ_QP_EVENT_STATUS_SUCCESS UINT32_C(0x0) - /* Fail. */ - #define CREQ_QP_EVENT_STATUS_FAIL UINT32_C(0x1) - /* Resources. */ - #define CREQ_QP_EVENT_STATUS_RESOURCES UINT32_C(0x2) - /* Invalid command. */ - #define CREQ_QP_EVENT_STATUS_INVALID_CMD UINT32_C(0x3) - /* Not implemented. */ - #define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED UINT32_C(0x4) - /* Invalid parameter. */ - #define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER UINT32_C(0x5) - /* Hardware operation failed. */ - #define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR UINT32_C(0x6) - /* Firmware operation failed due to internal error. */ - #define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR UINT32_C(0x7) - #define CREQ_QP_EVENT_STATUS_LAST CREQ_QP_EVENT_STATUS_INTERNAL_ERROR - /* Driver supplied handle to associate the command and the response. */ - uint16_t cookie; - uint32_t reserved32; - uint8_t v; + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE */ - #define CREQ_QP_EVENT_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* Create QP command response. */ - #define CREQ_QP_EVENT_EVENT_CREATE_QP UINT32_C(0x1) - /* Destroy QP command response. */ - #define CREQ_QP_EVENT_EVENT_DESTROY_QP UINT32_C(0x2) - /* Modify QP command response. */ - #define CREQ_QP_EVENT_EVENT_MODIFY_QP UINT32_C(0x3) - /* Query QP command response. */ - #define CREQ_QP_EVENT_EVENT_QUERY_QP UINT32_C(0x4) - /* Create SRQ command response. */ - #define CREQ_QP_EVENT_EVENT_CREATE_SRQ UINT32_C(0x5) - /* Destroy SRQ command response. */ - #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ UINT32_C(0x6) - /* Query SRQ command response. */ - #define CREQ_QP_EVENT_EVENT_QUERY_SRQ UINT32_C(0x8) - /* Create CQ command response. */ - #define CREQ_QP_EVENT_EVENT_CREATE_CQ UINT32_C(0x9) - /* Destroy CQ command response. */ - #define CREQ_QP_EVENT_EVENT_DESTROY_CQ UINT32_C(0xa) - /* Resize CQ command response. */ - #define CREQ_QP_EVENT_EVENT_RESIZE_CQ UINT32_C(0xc) - /* Allocate MRW command response. */ - #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW UINT32_C(0xd) - /* De-allocate key command response. */ - #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY UINT32_C(0xe) - /* Register MR command response. */ - #define CREQ_QP_EVENT_EVENT_REGISTER_MR UINT32_C(0xf) - /* Deregister MR command response. */ - #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR UINT32_C(0x10) - /* Add GID command response. */ - #define CREQ_QP_EVENT_EVENT_ADD_GID UINT32_C(0x11) - /* Delete GID command response. */ - #define CREQ_QP_EVENT_EVENT_DELETE_GID UINT32_C(0x12) - /* Modify GID command response. */ - #define CREQ_QP_EVENT_EVENT_MODIFY_GID UINT32_C(0x17) - /* Query GID command response. */ - #define CREQ_QP_EVENT_EVENT_QUERY_GID UINT32_C(0x18) - /* Create QP1 command response. */ - #define CREQ_QP_EVENT_EVENT_CREATE_QP1 UINT32_C(0x13) - /* Destroy QP1 command response. */ - #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 UINT32_C(0x14) - /* Create AH command response. */ - #define CREQ_QP_EVENT_EVENT_CREATE_AH UINT32_C(0x15) - /* Destroy AH command response. */ - #define CREQ_QP_EVENT_EVENT_DESTROY_AH UINT32_C(0x16) - /* Initialize firmware command response. */ - #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW UINT32_C(0x80) - /* De-initialize firmware command response. */ - #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW UINT32_C(0x81) - /* Stop PF command response. */ - #define CREQ_QP_EVENT_EVENT_STOP_FUNC UINT32_C(0x82) - /* Query info PF command response. */ - #define CREQ_QP_EVENT_EVENT_QUERY_FUNC UINT32_C(0x83) - /* Set function resources command response. */ - #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84) - /* Read the current state of any internal resource context. Can only be issued from a PF. */ - #define CREQ_QP_EVENT_EVENT_READ_CONTEXT UINT32_C(0x85) - /* Map TC to COS response. */ - #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS UINT32_C(0x8a) - /* Query firmware and interface version response. */ - #define CREQ_QP_EVENT_EVENT_QUERY_VERSION UINT32_C(0x8b) - /* Modify congestion control response. */ - #define CREQ_QP_EVENT_EVENT_MODIFY_CC UINT32_C(0x8c) - /* Query congestion control response. */ - #define CREQ_QP_EVENT_EVENT_QUERY_CC UINT32_C(0x8d) - /* Query RoCE statistics. */ - #define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS UINT32_C(0x8e) - /* Set LAG mode. */ - #define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE UINT32_C(0x8f) + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) /* - * Query QP for a PF other than the requesting PF. Also can query for more - * than one QP. + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + * + * It is recommended to set this flag for Change UDP Source Port + * WQE's. */ - #define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND UINT32_C(0x91) - /* QP error notification event. */ - #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0) - /* CQ error notification event. */ - #define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION UINT32_C(0xc1) - #define CREQ_QP_EVENT_EVENT_LAST CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION - uint8_t reserved48[6]; -} creq_qp_event_t, *pcreq_qp_event_t; - -/* QP error notification event. */ -/* creq_qp_error_notification (size:128b/16B) */ - -typedef struct creq_qp_error_notification { - uint8_t type; + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_UC_FENCE UINT32_C(0x4) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK UINT32_C(0x3f) - #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0 - /* QP Async Notification */ - #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT UINT32_C(0x38) - #define CREQ_QP_ERROR_NOTIFICATION_TYPE_LAST CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT - /* Status of the response. */ - uint8_t status; - /* requestor slow path state */ - uint8_t req_slow_path_state; - /* requestor error reason */ - uint8_t req_err_state_reason; - /* QP context id */ - uint32_t xid; - uint8_t v; + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SE UINT32_C(0x8) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - #define CREQ_QP_ERROR_NOTIFICATION_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* QP error notification event. */ - #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0) - #define CREQ_QP_ERROR_NOTIFICATION_EVENT_LAST CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION - /* responder slow path state */ - uint8_t res_slow_path_state; - uint8_t res_err_state_reason; + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_INLINE UINT32_C(0x10) /* - * Final SQ Consumer Index value. Any additional SQ WQEs will - * have to be completed by the user provider. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - uint16_t sq_cons_idx; + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) /* - * Final RQ Consumer Index value. Any additional RQ WQEs will - * have to be completed by the user provider. + * When set to '1', this operation will cause a trace capture in + * each block it passes through. */ - uint16_t rq_cons_idx; -} creq_qp_error_notification_t, *pcreq_qp_error_notification_t; - -/* CQ error notification event. */ -/* creq_cq_error_notification (size:128b/16B) */ - -typedef struct creq_cq_error_notification { - uint8_t type; + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint8_t wqe_size; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * The size of the WQE in units of 16B chunks. + * + * For the Change UDP Source Port WQE, this field will always have + * a value of 1. */ - #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK UINT32_C(0x3f) - #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0 - /* CQ Async Notification */ - #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT UINT32_C(0x38) - #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_LAST CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT - /* Status of the response. */ - uint8_t status; - /* CQ error reason code. */ - uint8_t cq_err_reason; - /* Requester completion error for invalid CQ state. */ - #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR UINT32_C(0x1) - /* Requester completion error for CQ overflow. */ - #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR UINT32_C(0x2) - /* Attempt to load CQ context resulted in error. */ - #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR UINT32_C(0x3) - /* Responder completion error for invalid CQ state. */ - #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR UINT32_C(0x4) - /* Responder completion error for CQ overflow. */ - #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR UINT32_C(0x5) - /* Attempt to load CQ context resulted in error. */ - #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR UINT32_C(0x6) - #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_LAST CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR - uint8_t reserved8; - /* CQ context id */ - uint32_t xid; - uint8_t v; + #define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_SFT 0 + uint8_t reserved_1; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This value will be returned in the completion if the completion is + * signaled. */ - #define CREQ_CQ_ERROR_NOTIFICATION_V UINT32_C(0x1) - /* Event or command opcode. */ - uint8_t event; - /* CQ error notification event. */ - #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION UINT32_C(0xc1) - #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_LAST CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION - uint8_t reserved48[6]; -} creq_cq_error_notification_t, *pcreq_cq_error_notification_t; + uint32_t opaque; + /* The new value for the QP's UDP source port. */ + uint16_t udp_src_port; + uint16_t reserved_2; + uint32_t reserved_3; +} sq_change_udpsrcport_v3_t, *psq_change_udpsrcport_v3_t; -/* sq_base (size:64b/8B) */ +/* SQ Change UDP Source Port WQE V3 header */ +/* sq_change_udpsrcport_hdr_v3 (size:128b/16B) */ -typedef struct sq_base { +typedef struct sq_change_udpsrcport_hdr_v3 { /* This field defines the type of SQ WQE. */ uint8_t wqe_type; - /* Send */ - #define SQ_BASE_WQE_TYPE_SEND UINT32_C(0x0) + /* Change UDP Source Port V3 */ + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_LAST SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 + uint8_t flags; /* - * Send with Immediate - * - * Allowed only on reliable connection (RC) and - * unreliable datagram (UD) SQs. + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). */ - #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) /* - * Send with Invalidate. - * - * Allowed only on reliable connection (RC) SQs. + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE */ - #define SQ_BASE_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) /* - * RDMA Write. + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. * - * Allowed only on reliable connection (RC) SQs. + * It is recommended to set this flag for Change UDP Source Port + * WQE's. */ - #define SQ_BASE_WQE_TYPE_WRITE_WQE UINT32_C(0x4) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) /* - * RDMA Write with Immediate. - * - * Allowed only on reliable connection (RC) SQs. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SE UINT32_C(0x8) /* - * RDMA Read. - * - * Allowed only on reliable connection (RC) SQs. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - #define SQ_BASE_WQE_TYPE_READ_WQE UINT32_C(0x6) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_INLINE UINT32_C(0x10) /* - * Atomic Compare/Swap. - * - * Allowed only on reliable connection (RC) SQs. + * This flag is not applicable and should be 0 for a local memory + * operation WQE. */ - #define SQ_BASE_WQE_TYPE_ATOMIC_CS UINT32_C(0x8) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) /* - * Atomic Fetch/Add. - * - * Allowed only on reliable connection (RC) SQs. + * When set to '1', this operation will cause a trace capture in + * each block it passes through. */ - #define SQ_BASE_WQE_TYPE_ATOMIC_FA UINT32_C(0xb) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint8_t wqe_size; /* - * Local Invalidate. + * The size of the WQE in units of 16B chunks. * - * Allowed only on reliable connection (RC) SQs. + * For the Change UDP Source Port WQE, this field will always have + * a value of 1. */ - #define SQ_BASE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_SFT 0 + uint8_t reserved_1; /* - * FR-PMR (Fast Register Physical Memory Region) - * - * Allowed only on reliable connection (RC) SQs. + * This value will be returned in the completion if the completion is + * signaled. */ - #define SQ_BASE_WQE_TYPE_FR_PMR UINT32_C(0xd) + uint32_t opaque; + /* The new value for the QP's UDP source port. */ + uint16_t udp_src_port; + uint16_t reserved_2; + uint32_t reserved_3; +} sq_change_udpsrcport_hdr_v3_t, *psq_change_udpsrcport_hdr_v3_t; + +/* RQ/SRQ WQE */ +/* rq_wqe (size:1024b/128B) */ + +typedef struct rq_wqe { + /* wqe_type is 8 b */ + uint8_t wqe_type; /* - * Memory Bind - * - * Allowed only on reliable connection (RC) SQs. + * RQ/SRQ WQE. This WQE is used for posting buffers on + * an RQ or SRQ. */ - #define SQ_BASE_WQE_TYPE_BIND UINT32_C(0xe) + #define RQ_WQE_WQE_TYPE_RCV UINT32_C(0x80) + #define RQ_WQE_WQE_TYPE_LAST RQ_WQE_WQE_TYPE_RCV + /* No flags supported for this WQE type. */ + uint8_t flags; /* - * FR-PPMR (Fast Register Proxy Physical Memory Region) + * Specify the total number 16B chunks that make up the valid + * portion of the WQE. This includes the first chunk that is the + * WQE structure and up to 6 SGE structures. * - * Allowed only on reliable connection (RC) SQs. + * While the valid area is defined by the wqe_size field, the + * actual WQE size is fixed at 128B. */ - #define SQ_BASE_WQE_TYPE_FR_PPMR UINT32_C(0xf) - #define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_FR_PPMR - uint8_t unused_0[7]; -} sq_base_t, *psq_base_t; + uint8_t wqe_size; + uint8_t reserved8; + uint32_t reserved32; + uint64_t wr_id; + /* + * Opaque value used by upper layer SW to identify the id of the + * WR which generated the WQE. Used in CQE. Valid in the first + * SGE of an SRQ WQE. + */ + #define RQ_WQE_WR_ID_MASK UINT32_C(0xfffff) + #define RQ_WQE_WR_ID_SFT 0 + uint8_t reserved128[16]; + /* + * The data field for RQ WQE is filled with from 1 to 6 SGE + * structures as defined by the wqe_size field. + */ + uint32_t data[24]; +} rq_wqe_t, *prq_wqe_t; -/* sq_sge (size:128b/16B) */ +/* RQ/SRQ WQE header. */ +/* rq_wqe_hdr (size:256b/32B) */ -typedef struct sq_sge { +typedef struct rq_wqe_hdr { + /* wqe_type is 8 b */ + uint8_t wqe_type; /* - * The virtual address in local memory or a physical address - * when l_key value is a reserved value of a physical address. - * Driver configures this value in the chip and the chip compares - * l_key in SGEs with that reserved value, if equal it access - * the physical address specified. The chip however MUST verify - * that the QP allows the use reserved key. + * RQ/SRQ WQE. This WQE is used for posting buffers on + * an RQ or SRQ. */ - uint64_t va_or_pa; + #define RQ_WQE_HDR_WQE_TYPE_RCV UINT32_C(0x80) + #define RQ_WQE_HDR_WQE_TYPE_LAST RQ_WQE_HDR_WQE_TYPE_RCV + /* No flags supported for this WQE type. */ + uint8_t flags; /* - * Local Key associated with this registered MR; The 24 msb of - * the key used to index the MRW Table and the 8 lsb are compared - * with the 8 bits key part stored in the MRWC. The PBL in the - * MRW Context is used to translate the above VA to physical - * address. + * Specify the total number 16B chunks that make up the valid + * portion of the WQE. This includes the first chunk that is the + * WQE structure and up to 6 SGE structures. + * + * While the valid area is defined by the wqe_size field, the + * actual WQE size is fixed at 128B. */ - uint32_t l_key; + uint8_t wqe_size; + uint8_t reserved8; + uint32_t reserved32; + uint64_t wr_id; /* - * Size of SGE in bytes; Based on page size of the system the - * chip knows how many entries are in the PBL + * Opaque value used by upper layer SW to identify the id of the + * WR which generated the WQE. Used in CQE. Valid in the first + * SGE of an SRQ WQE. */ - uint32_t size; -} sq_sge_t, *psq_sge_t; - -/* sq_psn_search (size:64b/8B) */ - -typedef struct sq_psn_search { - /* Start PSN. */ - uint32_t opcode_start_psn; - /* Start PSN. */ - #define SQ_PSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff) - #define SQ_PSN_SEARCH_START_PSN_SFT 0 - /* The opcodes are software defined. */ - #define SQ_PSN_SEARCH_OPCODE_MASK UINT32_C(0xff000000) - #define SQ_PSN_SEARCH_OPCODE_SFT 24 - uint32_t flags_next_psn; - /* Next PSN. Equal to the start PSN of the next WQE. */ - #define SQ_PSN_SEARCH_NEXT_PSN_MASK UINT32_C(0xffffff) - #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0 - /* Opcode specific flags. */ - #define SQ_PSN_SEARCH_FLAGS_MASK UINT32_C(0xff000000) - #define SQ_PSN_SEARCH_FLAGS_SFT 24 -} sq_psn_search_t, *psq_psn_search_t; + #define RQ_WQE_HDR_WR_ID_MASK UINT32_C(0xfffff) + #define RQ_WQE_HDR_WR_ID_SFT 0 + uint8_t reserved128[16]; +} rq_wqe_hdr_t, *prq_wqe_hdr_t; -/* This PSN table structure is used only on devices where variable size WQEs are supported. */ -/* sq_psn_search_ext (size:128b/16B) */ +/* RQ/SRQ WQE V3 */ +/* rq_wqe_v3 (size:4096b/512B) */ -typedef struct sq_psn_search_ext { - /* Start PSN. */ - uint32_t opcode_start_psn; - /* Start PSN. */ - #define SQ_PSN_SEARCH_EXT_START_PSN_MASK UINT32_C(0xffffff) - #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0 - /* The opcodes are software defined. */ - #define SQ_PSN_SEARCH_EXT_OPCODE_MASK UINT32_C(0xff000000) - #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24 - uint32_t flags_next_psn; - /* Next PSN. Equal to the start PSN of the next WQE. */ - #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK UINT32_C(0xffffff) - #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0 - /* Opcode specific flags. */ - #define SQ_PSN_SEARCH_EXT_FLAGS_MASK UINT32_C(0xff000000) - #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24 +typedef struct rq_wqe_v3 { + /* wqe_type is 8 b */ + uint8_t wqe_type; /* - * This field is used only when variable sized WQEs are being used. - * This indicates the starting slot index of the corresponding WQE. + * RQ/SRQ WQE V3. This WQE is used for posting buffers on + * an RQ or SRQ. */ - uint16_t start_slot_idx; - /* reserved16 is 16 b */ - uint16_t reserved16; - /* reserved32 is 32 b */ - uint32_t reserved32; -} sq_psn_search_ext_t, *psq_psn_search_ext_t; - -/* This MSN table structure is used only on devices where Hardware based Requester retransmission is used. */ -/* sq_msn_search (size:64b/8B) */ - -typedef struct sq_msn_search { - /* MSN search entry. */ - uint64_t start_idx_next_psn_start_psn; - /* Start PSN. */ - #define SQ_MSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff) - #define SQ_MSN_SEARCH_START_PSN_SFT 0 - /* Next PSN. Equal to the start PSN of the next WQE. */ - #define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL - #define SQ_MSN_SEARCH_NEXT_PSN_SFT 24 + #define RQ_WQE_V3_WQE_TYPE_RCV_V3 UINT32_C(0x90) + #define RQ_WQE_V3_WQE_TYPE_LAST RQ_WQE_V3_WQE_TYPE_RCV_V3 + /* No flags supported for this WQE type. */ + uint8_t flags; + /* + * Specify the total number 16B chunks that make up the valid portion + * of the WQE. This includes the first chunk that is the WQE + * structure and up to 30 SGE structures. The maximum value for this + * field is 32, representing a maximum-sized WQE of 512B. + */ + uint8_t wqe_size; + uint8_t reserved1; + /* This value will be returned in the completion. */ + uint32_t opaque; + uint64_t reserved2; /* - * For variable-size WQEs, this field indicates the starting - * slot index that corresponds to the WQE. - * In backward-compatible mode, this is the starting WQE index. + * The data field for RQ WQE is filled with from 1 to 30 SGE + * structures as defined by the wqe_size field. */ - #define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL - #define SQ_MSN_SEARCH_START_IDX_SFT 48 -} sq_msn_search_t, *psq_msn_search_t; + uint32_t data[124]; +} rq_wqe_v3_t, *prq_wqe_v3_t; -/* Send SQ WQE */ -/* sq_send (size:1024b/128B) */ +/* RQ/SRQ WQE V3 header. */ +/* rq_wqe_hdr_v3 (size:128b/16B) */ -typedef struct sq_send { - /* This field defines the type of SQ WQE. */ +typedef struct rq_wqe_hdr_v3 { + /* wqe_type is 8 b */ uint8_t wqe_type; - /* Send */ - #define SQ_SEND_WQE_TYPE_SEND UINT32_C(0x0) /* - * Send with Immediate - * - * Allowed only on reliable connection (RC) and - * unreliable datagram (UD) SQs. - */ - #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1) - /* - * Send with Invalidate. - * - * Allowed only on reliable connection (RC) SQs. + * RQ/SRQ WQE V3. This WQE is used for posting buffers on + * an RQ or SRQ. */ - #define SQ_SEND_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2) - #define SQ_SEND_WQE_TYPE_LAST SQ_SEND_WQE_TYPE_SEND_W_INVALID + #define RQ_WQE_HDR_V3_WQE_TYPE_RCV_V3 UINT32_C(0x90) + #define RQ_WQE_HDR_V3_WQE_TYPE_LAST RQ_WQE_HDR_V3_WQE_TYPE_RCV_V3 + /* No flags supported for this WQE type. */ uint8_t flags; - #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled completion - * the controller should not generate a CQE unless there was - * an error. This refers to the CQE on the sender side. (The se - * flag refers to the receiver side). + * Specify the total number 16B chunks that make up the valid portion + * of the WQE. This includes the first chunk that is the WQE + * structure and up to 30 SGE structures. The maximum value for this + * field is 32, representing a maximum-sized WQE of 512B. */ - #define SQ_SEND_FLAGS_SIGNAL_COMP UINT32_C(0x1) + uint8_t wqe_size; + uint8_t reserved1; + /* This value will be returned in the completion. */ + uint32_t opaque; + uint64_t reserved2; +} rq_wqe_hdr_v3_t, *prq_wqe_hdr_v3_t; + +/* cq_base (size:256b/32B) */ + +typedef struct cq_base { + uint64_t reserved64_1; + uint64_t reserved64_2; + uint64_t reserved64_3; + uint8_t cqe_type_toggle; /* - * Indication to complete all previous RDMA Read or Atomic WQEs - * on the SQ before executing this WQE. - * - * This flag must be zero for a UD send. + * Indicate valid completion - written by the chip. The NIC + * toggle this bit each time it finished consuming all PBL + * entries. */ - #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_BASE_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_BASE_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_BASE_CQE_TYPE_SFT 1 /* - * For local invalidate request. Indication to complete all - * previous SQ's WQEs before executing this WQE. - * - * This flag must be zero for a UD send. + * Requester completion - This is used for both RC and UD SQ + * completions. */ - #define SQ_SEND_FLAGS_UC_FENCE UINT32_C(0x4) + #define CQ_BASE_CQE_TYPE_REQ (UINT32_C(0x0) << 1) /* - * Solicit event flag. Indication sent in BTH header to the - * receiver to generate a Completion Event Notification, i.e. - * CNQE. This bit should be set only in the last (or only) packet - * of the message. + * Responder RC Completion - This is used for both RQ and SRQ + * completions for RC service QPs. */ - #define SQ_SEND_FLAGS_SE UINT32_C(0x8) + #define CQ_BASE_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1) /* - * Indicate that inline data is posted to the SQ in the data - * area of this WQE. + * Responder UD Completion - This is used for both RQ and SRQ + * completion for UD service QPs. */ - #define SQ_SEND_FLAGS_INLINE UINT32_C(0x10) + #define CQ_BASE_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1) /* - * If set to 1, then the timestamp from the WQE is used. If - * cleared to 0, then TWE provides the timestamp. + * Responder RawEth and QP1 Completion - This is used for RQ + * completion for RawEth service and QP1 service QPs. */ - #define SQ_SEND_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * Responder UD completion with CFA. This is used for both RQ + * and SQ completion for UD service QPs. It includes cfa fields + * (some of which carry VLAN information), in place of QP handle. */ - #define SQ_SEND_FLAGS_DEBUG_TRACE UINT32_C(0x40) + #define CQ_BASE_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1) /* - * The number of 16 bytes chunks of data including this first - * word of the request that are a valid part of the request. The - * valid 16 bytes units other than the WQE structure can be - * SGEs (Scatter Gather Elements) OR inline data. - * - * While this field defines the valid WQE size. The actual - * total WQE size is always 128B. + * Requester completion V3 - This is used for both RC and UD SQ + * completions. */ - uint8_t wqe_size; - uint8_t reserved8_1; + #define CQ_BASE_CQE_TYPE_REQ_V3 (UINT32_C(0x8) << 1) /* - * Either invalidate key (R_Key of the remote host) that will - * be send with IETH (Invalidate ETH) if wqe_type is of Send - * with Invalidate, or immediate value that will be sent with - * ImmDt header if wqe_type is Send with Immediate. + * Responder RC Completion V3 - This is used for both RQ and SRQ + * completions for RC service QPs. */ - uint32_t inv_key_or_imm_data; - /* This field represents a 32-bit total data length, in bytes. */ - uint32_t length; + #define CQ_BASE_CQE_TYPE_RES_RC_V3 (UINT32_C(0x9) << 1) /* - * When in the SQ of a UD QP, indicates the q_key to be used in - * the transmitted packet. However, if the most significant bit - * of this field is set, then the q_key will be taken from QP - * context, rather than from this field. - * - * When in the SQ of a non-UD QP, this field is reserved and - * should be filled with zeros. + * Responder UD Completion V3 - This is used for both RQ and SRQ + * completion for UD service QPs. It is also used for QP1 QPs + * that are treated as UD. */ - uint32_t q_key; + #define CQ_BASE_CQE_TYPE_RES_UD_V3 (UINT32_C(0xa) << 1) /* - * When in the SQ of a UD QP, indicates the destination QP to be - * used in the transmitted packet. - * - * When in the SQ of a non-UD QP, this field is reserved and - * should be filled with zeros. + * Responder RawEth and QP1 Completion V3 - This is used for RQ and + * SRQ completion for RawEth service. It is also used for QP1 QPs + * that are treated as RawEth. */ - uint32_t dst_qp; - #define SQ_SEND_DST_QP_MASK UINT32_C(0xffffff) - #define SQ_SEND_DST_QP_SFT 0 - uint32_t avid; + #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (UINT32_C(0xb) << 1) /* - * If the serv_type is 'UD', then this field supplies the AVID - * (Address Vector ID). + * Responder UD Completion with CFA V3 - This is used for both RQ + * and SRQ completion for UD service QPs. It includes CFA fields + * (some of which carry VLAN information), in place of the QP + * handle. It is also used for QP1 QPs that are treated as UD. */ - #define SQ_SEND_AVID_MASK UINT32_C(0xfffff) - #define SQ_SEND_AVID_SFT 0 - uint32_t reserved32; - uint32_t timestamp; + #define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (UINT32_C(0xc) << 1) /* - * This field specifies a 24-bit timestamp that can be passed - * down the TX path and optionally logged in the TXP timestamp - * histogram. + * NO_OP completion - This is used to indicate that no + * operation completed. */ - #define SQ_SEND_TIMESTAMP_MASK UINT32_C(0xffffff) - #define SQ_SEND_TIMESTAMP_SFT 0 + #define CQ_BASE_CQE_TYPE_NO_OP (UINT32_C(0xd) << 1) /* - * When inline=0, then this area is filled with from 1 to 6 - * SGEs based on the wqe_size field. - * - * When inline=1, this area is filled with payload data for the - * send based on the length_or_AVID field. Bits [7:0] of word 0 - * hold the first byte to go out on the wire. + * Terminal completion - This is used to indicate that no + * further completions will be made for this QP on this CQ. */ - uint32_t data[24]; -} sq_send_t, *psq_send_t; - -/* Send SQ WQE header. */ -/* sq_send_hdr (size:256b/32B) */ - -typedef struct sq_send_hdr { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; - /* Send */ - #define SQ_SEND_HDR_WQE_TYPE_SEND UINT32_C(0x0) + #define CQ_BASE_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1) /* - * Send with Immediate - * - * Allowed only on reliable connection (RC) and - * unreliable datagram (UD) SQs. + * Cut off CQE; for CQ resize. This CQE is written to the "old" + * CQ as the last CQE written. SW may use this to know when the + * "old" CQ can be destroyed. */ - #define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1) + #define CQ_BASE_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1) + #define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF + /* This field indicates the status for the CQE. */ + uint8_t status; + /* The operation completed successfully. */ + #define CQ_BASE_STATUS_OK UINT32_C(0x0) /* - * Send with Invalidate. + * An unexpected BTH opcode or a First/Middle packet that is not + * the full MTU size was returned by the responder. * - * Allowed only on reliable connection (RC) SQs. - */ - #define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2) - #define SQ_SEND_HDR_WQE_TYPE_LAST SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID - uint8_t flags; - #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 - /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled completion - * the controller should not generate a CQE unless there was - * an error. This refers to the CQE on the sender side. (The se - * flag refers to the receiver side). + * This is a fatal error detected by the requester Rx. */ - #define SQ_SEND_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_BASE_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1) /* - * Indication to complete all previous RDMA Read or Atomic WQEs - * on the SQ before executing this WQE. + * Generated for a WQE posted to the local SQ when the sum of the + * lengths of the SGEs in the WQE exceeds the maximum message + * length of 2^31 bytes. * - * This flag must be zero for a UD send. + * Generated for a WQE posted to the local RQ/SRQ when the sum of + * the lengths of the SGEs in the WQE is too small to receive the + * (valid) incoming message or the length of the incoming message + * is greater than the maximum message size supported. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. */ - #define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_BASE_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2) /* - * For local invalidate request. Indication to complete all - * previous SQ's WQEs before executing this WQE. + * This indicates that the packet was too long for the WQE provided + * on the SRQ/RQ. * - * This flag must be zero for a UD send. + * This is not a fatal error. All the fields in the CQE are valid. */ - #define SQ_SEND_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + #define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3) /* - * Solicit event flag. Indication sent in BTH header to the - * receiver to generate a Completion Event Notification, i.e. - * CNQE. This bit should be set only in the last (or only) packet - * of the message. + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. */ - #define SQ_SEND_HDR_FLAGS_SE UINT32_C(0x8) + #define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) /* - * Indicate that inline data is posted to the SQ in the data - * area of this WQE. + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. */ - #define SQ_SEND_HDR_FLAGS_INLINE UINT32_C(0x10) + #define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) /* - * If set to 1, then the timestamp from the WQE is used. If - * cleared to 0, then TWE provides the timestamp. + * A protection error occurred on a local data buffer during the + * processing of a RDMA Write with Immediate Data operation sent + * from the remote node. + * + * This is a fatal error detected by the responder Rx. Only the + * opaque field in the CQE is valid. */ - #define SQ_SEND_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x6) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * The SSC detected an error on a local memory operation from the + * SQ (fast-register, local invalidate, or bind). + * + * This is a fatal error detected by the requester Tx. */ - #define SQ_SEND_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + #define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x7) /* - * The number of 16 bytes chunks of data including this first - * word of the request that are a valid part of the request. The - * valid 16 bytes units other than the WQE structure can be - * SGEs (Scatter Gather Elements) OR inline data. + * An invalid message was received by the responder. This could be + * an operation that is not supported by this QP, an IRRQ overflow + * error, or the length in an RDMA operation is greater than the + * maximum message size (2^31 bytes). * - * While this field defines the valid WQE size. The actual - * total WQE size is always 128B. + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Invalid Request. For responder + * CQEs, only the opaque field is valid. */ - uint8_t wqe_size; - uint8_t reserved8_1; + #define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8) /* - * Either invalidate key (R_Key of the remote host) that will - * be send with IETH (Invalidate ETH) if wqe_type is of Send - * with Invalidate, or immediate value that will be sent with - * ImmDt header if wqe_type is Send with Immediate. + * A protection error occurred on a remote data buffer to be read + * by an RDMA Read, written by an RDMA Write or accessed by an + * atomic operation. This error is reported only on RDMA operations + * or atomic operations. + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Remote Access Violation. */ - uint32_t inv_key_or_imm_data; - /* This field represents a 32-bit total data length, in bytes. */ - uint32_t length; + #define CQ_BASE_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x9) /* - * When in the SQ of a UD QP, indicates the q_key to be used in - * the transmitted packet. However, if the most significant bit - * of this field is set, then the q_key will be taken from QP - * context, rather than from this field. + * The operation could not be completed successfully by the + * responder. Possible causes include an RQ/SRQ WQE format error, + * an SSC error when validating an SGE from an RQ/SRQ WQE, or the + * message received was too long for the RQ/SRQ WQE. * - * When in the SQ of a non-UD QP, this field is reserved and - * should be filled with zeros. + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Remote Operation Error. */ - uint32_t q_key; + #define CQ_BASE_STATUS_REMOTE_OPERATION_ERR UINT32_C(0xa) /* - * When in the SQ of a UD QP, indicates the destination QP to be - * used in the transmitted packet. + * The RNR NAK retry count was exceeded while trying to send this + * message. * - * When in the SQ of a non-UD QP, this field is reserved and - * should be filled with zeros. + * This is a fatal error detected by the requester. */ - uint32_t dst_qp; - #define SQ_SEND_HDR_DST_QP_MASK UINT32_C(0xffffff) - #define SQ_SEND_HDR_DST_QP_SFT 0 - uint32_t avid; + #define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0xb) /* - * If the serv_type is 'UD', then this field supplies the AVID - * (Address Vector ID). + * The local transport timeout retry counter was exceeded while + * trying to send this message. + * + * This is a fatal error detected by the requester. */ - #define SQ_SEND_HDR_AVID_MASK UINT32_C(0xfffff) - #define SQ_SEND_HDR_AVID_SFT 0 - uint32_t reserved32; - uint32_t timestamp; + #define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xc) /* - * This field specifies a 24-bit timestamp that can be passed - * down the TX path and optionally logged in the TXP timestamp - * histogram. + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. */ - #define SQ_SEND_HDR_TIMESTAMP_MASK UINT32_C(0xffffff) - #define SQ_SEND_HDR_TIMESTAMP_SFT 0 -} sq_send_hdr_t, *psq_send_hdr_t; - -/* Send Raw Ethernet and QP1 SQ WQE */ -/* sq_send_raweth_qp1 (size:1024b/128B) */ - -typedef struct sq_send_raweth_qp1 { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; - /* Send */ - #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND UINT32_C(0x0) - #define SQ_SEND_RAWETH_QP1_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND - uint8_t flags; - #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + #define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled completion - * the controller should not generate a CQE unless there was - * an error. This refers to the CQE on the sender side. (The se - * flag refers to the receiver side). + * A WQE had already been taken off the RQ/SRQ when a fatal error + * was detected on responder Rx. Only the opaque field in the CQE + * is valid. */ - #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP UINT32_C(0x1) - /* This flag must be zero for a Raweth or QP1 send. */ - #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) - /* This flag must be zero for a Raweth or QP1 send. */ - #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE UINT32_C(0x4) - /* This flag must be zero for a Raweth or QP1 send. */ - #define SQ_SEND_RAWETH_QP1_FLAGS_SE UINT32_C(0x8) + #define CQ_BASE_STATUS_HW_FLUSH_ERR UINT32_C(0xe) /* - * Indicate that inline data is posted to the SQ in the data - * area of this WQE. + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. */ - #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE UINT32_C(0x10) + #define CQ_BASE_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_BASE_STATUS_LAST CQ_BASE_STATUS_OVERFLOW_ERR + uint16_t reserved16; /* - * If set to 1, then the timestamp from the WQE is used. If - * cleared to 0, then TWE provides the timestamp. + * This value is from the WQE that is being completed. This field is + * only applicable to V3 version of CQEs. */ - #define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN UINT32_C(0x20) + uint32_t opaque; +} cq_base_t, *pcq_base_t; + +/* Requester CQ CQE */ +/* cq_req (size:256b/32B) */ + +typedef struct cq_req { /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * This is an application level ID used to identify the + * QP and its SQ and RQ. */ - #define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint64_t qp_handle; /* - * The number of 16 bytes chunks of data including this first - * word of the request that are a valid part of the request. The - * valid 16 bytes units other than the WQE structure can be - * SGEs (Scatter Gather Elements) OR inline data. - * - * While this field defines the valid WQE size. The actual - * total WQE size is always 128B. + * SQ Consumer Index - points to the entry just past the last WQE + * that has been completed by the chip. Wraps around at + * QPC.sq_size (i.e. the valid range of the SQ Consumer Index is 0 + * to (QPC.sq_size - 1)). */ - uint8_t wqe_size; - uint8_t reserved8; + uint16_t sq_cons_idx; + uint16_t reserved16_1; + uint32_t reserved32_2; + uint64_t reserved64; + uint8_t cqe_type_toggle; /* - * All bits in this field must be valid on the first BD of a packet. - * Their value on other BDs of the packet will be ignored. + * Indicate valid completion - written by the chip. Cumulus + * toggle this bit each time it finished consuming all PBL + * entries */ - uint16_t lflags; + #define CQ_REQ_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_REQ_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_REQ_CQE_TYPE_SFT 1 /* - * If set to 1, the controller replaces the TCP/UPD checksum - * fields of normal TCP/UPD checksum, or the inner TCP/UDP - * checksum field of the encapsulated TCP/UDP packets with the - * hardware calculated TCP/UDP checksum for the packet associated - * with this descriptor. - * - * This bit must be valid on the first BD of a packet. + * Requester completion - This is used for both RC and UD SQ + * completions. */ - #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) + #define CQ_REQ_CQE_TYPE_REQ (UINT32_C(0x0) << 1) + #define CQ_REQ_CQE_TYPE_LAST CQ_REQ_CQE_TYPE_REQ /* - * If set to 1, the controller replaces the IP checksum of the - * normal packets, or the inner IP checksum of the encapsulated - * packets with the hardware calculated IP checksum for the - * packet associated with this descriptor. - * - * This bit must be valid on the first BD of a packet. + * When this bit is '1', it indicates that the packet completed + * was transmitted using the push accelerated data provided by + * the driver. When this bit is '0', it indicates that the packet + * had not push acceleration data written or was executed as a + * normal packet even though push data was provided. + * This field is intended to be used for driver-generated push + * statistics. It is not applicable for RC since not all RC packets + * return a CQE. */ - #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM UINT32_C(0x2) + #define CQ_REQ_PUSH UINT32_C(0x20) + /* This field indicates the status for the CQE. */ + uint8_t status; + /* OK is 0 */ + #define CQ_REQ_STATUS_OK UINT32_C(0x0) + /* BAD_RESPONSE_ERR is 1 */ + #define CQ_REQ_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1) + /* LOCAL_LENGTH_ERR is 2 */ + #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* LOCAL_QP_OPERATION_ERR is 3 */ + #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x3) + /* LOCAL_PROTECTION_ERR is 4 */ + #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x4) + /* MEMORY_MGT_OPERATION_ERR is 5 */ + #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) + /* REMOTE_INVALID_REQUEST_ERR is 6 */ + #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6) + /* REMOTE_ACCESS_ERR is 7 */ + #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x7) + /* REMOTE_OPERATION_ERR is 8 */ + #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR UINT32_C(0x8) + /* RNR_NAK_RETRY_CNT_ERR is 9 */ + #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0x9) + /* TRANSPORT_RETRY_CNT_ERR is 10 */ + #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xa) + /* WORK_REQUEST_FLUSHED_ERR is 11 */ + #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xb) + #define CQ_REQ_STATUS_LAST CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR + uint16_t reserved16_2; + uint32_t reserved32_1; +} cq_req_t, *pcq_req_t; + +/* Responder RC CQE */ +/* cq_res_rc (size:256b/32B) */ + +typedef struct cq_res_rc { /* - * If set to 1, the controller will not append an Ethernet CRC - * to the end of the frame. - * - * This bit must be valid on the first BD of a packet. - * - * Packet must be 64B or longer when this flag is set. It is not - * usefull to use this bit with any form of TX offload such as - * CSO or LSO. The intent is that the packet from the host already - * has a valid Ethernet CRC on the packet. + * The length of the message's payload in bytes, stored in + * the SGEs */ - #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC UINT32_C(0x4) + uint32_t length; /* - * If set to 1, the device will record the time at which the packet - * was actually transmitted at the TX MAC. - * - * This bit must be valid on the first BD of a packet. + * Immediate data in case the imm_flag set, R_Key to be + * invalidated in case inv_flag is set. */ - #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP UINT32_C(0x8) + uint32_t imm_data_or_inv_r_key; /* - * If set to 1, The controller replaces the tunnel IP checksum - * field with hardware calculated IP checksum for the IP header - * of the packet associated with this descriptor. In case of - * VXLAN, the controller also replaces the outer header UDP - * checksum with hardware calculated UDP checksum for the packet - * associated with this descriptor. + * This is an application level ID used to identify the + * QP and its SQ and RQ. */ - #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) + uint64_t qp_handle; /* - * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * Opaque value - valid when inv_flag is set. Used by driver + * to reference the buffer used to store PBL when the MR was + * fast registered. The driver can reclaim this buffer after + * an MR was remotely invalidated. The controller take that + * value from the MR referenced by R_Key */ - #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC UINT32_C(0x100) + uint64_t mr_handle; + uint8_t cqe_type_toggle; /* - * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * Indicate valid completion - written by the chip. Cumulus + * toggle this bit each time it finished consuming all PBL + * entries */ - #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC UINT32_C(0x200) + #define CQ_RES_RC_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_RC_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_RC_CQE_TYPE_SFT 1 /* - * This value selects a CFA action to perform on the packet. - * Set this value to zero if no CFA action is desired. - * - * This value must be valid on the first BD of a packet. + * Responder RC Completion - This is used for both RQ and SRQ + * completions for RC service QPs. */ - uint16_t cfa_action; + #define CQ_RES_RC_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1) + #define CQ_RES_RC_CQE_TYPE_LAST CQ_RES_RC_CQE_TYPE_RES_RC + /* This field indicates the status for the CQE. */ + uint8_t status; + /* OK is 0 */ + #define CQ_RES_RC_STATUS_OK UINT32_C(0x0) + /* LOCAL_ACCESS_ERROR is 1 */ + #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) + /* LOCAL_LENGTH_ERR is 2 */ + #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* LOCAL_PROTECTION_ERR is 3 */ + #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) + /* LOCAL_QP_OPERATION_ERR is 4 */ + #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* MEMORY_MGT_OPERATION_ERR is 5 */ + #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) + /* REMOTE_INVALID_REQUEST_ERR is 6 */ + #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6) + /* WORK_REQUEST_FLUSHED_ERR is 7 */ + #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) + /* HW_FLUSH_ERR is 8 */ + #define CQ_RES_RC_STATUS_HW_FLUSH_ERR UINT32_C(0x8) + #define CQ_RES_RC_STATUS_LAST CQ_RES_RC_STATUS_HW_FLUSH_ERR + uint16_t flags; /* - * This field represents a 32-bit total data length, in bytes. - * Note, however, that the length cannot exceed the MTU. + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. */ - uint32_t length; - uint32_t reserved32_1; + #define CQ_RES_RC_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_RC_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_RC_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ + /* Immediate data indicator */ + #define CQ_RES_RC_FLAGS_IMM UINT32_C(0x2) + /* R_Key invalidate indicator */ + #define CQ_RES_RC_FLAGS_INV UINT32_C(0x4) + #define CQ_RES_RC_FLAGS_RDMA UINT32_C(0x8) + /* CQE relates to an incoming Send request */ + #define CQ_RES_RC_FLAGS_RDMA_SEND (UINT32_C(0x0) << 3) + /* CQE relates to incoming RDMA Write request */ + #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (UINT32_C(0x1) << 3) + #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE + uint32_t srq_or_rq_wr_id; /* - * This value is action meta-data that defines CFA edit operations - * that are done in addition to any action editing. + * Opaque value from RQ or SRQ WQE. Used by driver/lib to + * reference the WQE in order to claim the received data + * and reuse the WQE space */ - uint32_t cfa_meta; - /* When key=1, This is the VLAN tag VID value. */ - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0 - /* When key=1, This is the VLAN tag DE value. */ - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE UINT32_C(0x1000) - /* When key=1, This is the VLAN tag PRI value. */ - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13 - /* When key=1, This is the VLAN tag TPID select value. */ - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16 - /* 0x88a8 */ - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) - /* 0x8100 */ - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) - /* 0x9100 */ - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) - /* 0x9200 */ - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) - /* 0x9300 */ - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) - /* Value programmed in CFA VLANTPID register. */ - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG - /* When key=1, This is the VLAN tag TPID select value. */ - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) - #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19 + #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) + #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0 +} cq_res_rc_t, *pcq_res_rc_t; + +/* Responder UD CQE */ +/* cq_res_ud (size:256b/32B) */ + +typedef struct cq_res_ud { + uint16_t length; /* - * This field identifies the type of edit to be performed - * on the packet. - * - * This value must be valid on the first BD of a packet. + * The length of the message's payload in bytes, stored in + * the SGEs */ - #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK UINT32_C(0xf0000000) - #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28 - /* No editing */ - #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + #define CQ_RES_UD_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_UD_LENGTH_SFT 0 /* - * - meta[17:16] - TPID select value (0 = 0x8100). - * - meta[15:12] - PRI/DE value. - * - meta[11:0] - VID value. + * This is data from the CFA or VNIC block as indicated by the + * ext_meta_format and meta_format fields. */ - #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) - #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG - uint32_t reserved32_2; - uint32_t reserved32_3; - uint32_t timestamp; + uint16_t cfa_metadata; + /* When meta_format=1, this value is the VLAN VID. */ + #define CQ_RES_UD_CFA_METADATA_VID_MASK UINT32_C(0xfff) + #define CQ_RES_UD_CFA_METADATA_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define CQ_RES_UD_CFA_METADATA_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define CQ_RES_UD_CFA_METADATA_PRI_MASK UINT32_C(0xe000) + #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13 + /* Immediate data in case the imm_flag set. */ + uint32_t imm_data; /* - * This field specifies a 24-bit timestamp that can be passed - * down the TX path and optionally logged in the TXP timestamp - * histogram. + * This is an application level ID used to identify the + * QP and its SQ and RQ. */ - #define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK UINT32_C(0xffffff) - #define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0 + uint64_t qp_handle; /* - * When inline=0, then this area is filled with from 1 to 6 - * SGEs based on the wqe_size field. - * - * When inline=1, this area is filled with payload data for the - * send based on the length_or_AVID field. Bits [7:0] of word 0 - * hold the first byte to go out on the wire. + * Source MAC address for the UD message placed in the WQE + * that is completed by this CQE. */ - uint32_t data[24]; -} sq_send_raweth_qp1_t, *psq_send_raweth_qp1_t; - -/* Send Raw Ethernet and QP1 SQ WQE header. */ -/* sq_send_raweth_qp1_hdr (size:256b/32B) */ - -typedef struct sq_send_raweth_qp1_hdr { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; - /* Send */ - #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND UINT32_C(0x0) - #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND - uint8_t flags; - #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + uint16_t src_mac[3]; + /* Lower 16b of the Source QP value from the DETH header. */ + uint16_t src_qp_low; + uint8_t cqe_type_toggle; /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled completion - * the controller should not generate a CQE unless there was - * an error. This refers to the CQE on the sender side. (The se - * flag refers to the receiver side). + * Indicate valid completion - written by the chip. Cumulus + * toggle this bit each time it finished consuming all PBL + * entries */ - #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) - /* This flag must be zero for a Raweth or QP1 send. */ - #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) - /* This flag must be zero for a Raweth or QP1 send. */ - #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE UINT32_C(0x4) - /* This flag must be zero for a Raweth or QP1 send. */ - #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE UINT32_C(0x8) + #define CQ_RES_UD_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_UD_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_UD_CQE_TYPE_SFT 1 /* - * Indicate that inline data is posted to the SQ in the data - * area of this WQE. + * Responder UD Completion - This is used for both RQ and SRQ + * completion for UD service QPs. */ - #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_UD_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1) + #define CQ_RES_UD_CQE_TYPE_LAST CQ_RES_UD_CQE_TYPE_RES_UD + /* This field indicates the status for the CQE. */ + uint8_t status; /* - * If set to 1, then the timestamp from the WQE is used. If - * cleared to 0, then TWE provides the timestamp. + * This indicates that the completion is without error. + * All fields are valid. */ - #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_UD_STATUS_OK UINT32_C(0x0) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * This indicates that write access was not allowed for + * at least one of the SGEs in the WQE. + * + * This is a fatal error. Only the srq_or_rq_wr_id is field + * is valid. */ - #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) /* - * The number of 16 bytes chunks of data including this first - * word of the request that are a valid part of the request. The - * valid 16 bytes units other than the WQE structure can be - * SGEs (Scatter Gather Elements) OR inline data. + * This indicates that the packet was too long for the WQE + * provided on the SRQ/RQ. * - * While this field defines the valid WQE size. The actual - * total WQE size is always 128B. + * This is not a fatal error. All the fields are valid. */ - uint8_t wqe_size; - uint8_t reserved8; + #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* LOCAL_PROTECTION_ERR is 3 */ + #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) + /* LOCAL_QP_OPERATION_ERR is 4 */ + #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* MEMORY_MGT_OPERATION_ERR is 5 */ + #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) + /* WORK_REQUEST_FLUSHED_ERR is 7 */ + #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) + /* HW_FLUSH_ERR is 8 */ + #define CQ_RES_UD_STATUS_HW_FLUSH_ERR UINT32_C(0x8) + #define CQ_RES_UD_STATUS_LAST CQ_RES_UD_STATUS_HW_FLUSH_ERR + uint16_t flags; /* - * All bits in this field must be valid on the first BD of a packet. - * Their value on other BDs of the packet will be ignored. + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. */ - uint16_t lflags; + #define CQ_RES_UD_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_UD_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_UD_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ + /* Immediate data indicator */ + #define CQ_RES_UD_FLAGS_IMM UINT32_C(0x2) + #define CQ_RES_UD_FLAGS_UNUSED_MASK UINT32_C(0xc) + #define CQ_RES_UD_FLAGS_UNUSED_SFT 2 + #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) + #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4 + /* RoCEv1 Message */ + #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) + /* RoCEv2 IPv4 Message */ + #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) + /* RoCEv2 IPv6 Message */ + #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) + #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 /* - * If set to 1, the controller replaces the TCP/UPD checksum - * fields of normal TCP/UPD checksum, or the inner TCP/UDP - * checksum field of the encapsulated TCP/UDP packets with the - * hardware calculated TCP/UDP checksum for the packet associated - * with this descriptor. - * - * This bit must be valid on the first BD of a packet. + * The combination of this value and ext_meta_format indicates + * what format the metadata field is. */ - #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) + #define CQ_RES_UD_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) + #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6 + /* No metadata information. Value is zero. */ + #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) /* - * If set to 1, the controller replaces the IP checksum of the - * normal packets, or the inner IP checksum of the encapsulated - * packets with the hardware calculated IP checksum for the - * packet associated with this descriptor. - * - * This bit must be valid on the first BD of a packet. + * The metadata field contains the VLAN tag and TPID value. + * - metadata[11:0] contains the vlan VID value. + * - metadata[12] contains the vlan DE value. + * - metadata[15:13] contains the vlan PRI value. */ - #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM UINT32_C(0x2) + #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (UINT32_C(0x1) << 6) /* - * If set to 1, the controller will not append an Ethernet CRC - * to the end of the frame. - * - * This bit must be valid on the first BD of a packet. - * - * Packet must be 64B or longer when this flag is set. It is not - * usefull to use this bit with any form of TX offload such as - * CSO or LSO. The intent is that the packet from the host already - * has a valid Ethernet CRC on the packet. + * If ext_meta_format is equal to 1, the metadata field + * contains the lower 16b of the tunnel ID value, justified + * to LSB + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier. + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0 + * - IPV4 = 0 (not populated) + * - IPV6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC UINT32_C(0x4) + #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6) /* - * If set to 1, the device will record the time at which the packet - * was actually transmitted at the TX MAC. - * - * This bit must be valid on the first BD of a packet. + * if ext_meta_format is equal to 1, metadata field contains + * 16b metadata from the prepended header (chdr_data). */ - #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP UINT32_C(0x8) + #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6) /* - * If set to 1, The controller replaces the tunnel IP checksum - * field with hardware calculated IP checksum for the IP header - * of the packet associated with this descriptor. In case of - * VXLAN, the controller also replaces the outer header UDP - * checksum with hardware calculated UDP checksum for the packet - * associated with this descriptor. + * If ext_meta_format is equal to 1, the metadata field contains + * the outer_l3_offset and lower 7 bits of the inner_l2_offset, + * - metadata[8:0] contains the outer_l3_offset. + * - metadata[15:9] contains the inner_l2_offset[6:0] */ - #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) + #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6) + #define CQ_RES_UD_FLAGS_META_FORMAT_LAST CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET /* - * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * The combination of this value and meta_format indicates what + * format the metadata field is */ - #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC UINT32_C(0x100) + #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK UINT32_C(0xc00) + #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10 + uint32_t src_qp_high_srq_or_rq_wr_id; /* - * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * Opaque value from RQ or SRQ WQE. Used by driver/lib to + * reference the WQE in order to claim the received data + * and reuse the WQE space */ - #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC UINT32_C(0x200) + #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) + #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0 + /* Upper 8b of the Source QP value from the DETH header. */ + #define CQ_RES_UD_SRC_QP_HIGH_MASK UINT32_C(0xff000000) + #define CQ_RES_UD_SRC_QP_HIGH_SFT 24 +} cq_res_ud_t, *pcq_res_ud_t; + +/* Responder UD CQE version 2 */ +/* cq_res_ud_v2 (size:256b/32B) */ + +typedef struct cq_res_ud_v2 { + uint16_t length; /* - * This value selects a CFA action to perform on the packet. - * Set this value to zero if no CFA action is desired. - * - * This value must be valid on the first BD of a packet. + * The length of the message's payload in bytes, stored in + * the SGEs */ - uint16_t cfa_action; + #define CQ_RES_UD_V2_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_UD_V2_LENGTH_SFT 0 + /* This is data from the CFA as indicated by the meta_format field. */ + uint16_t cfa_metadata0; + /* When meta_format=1, this value is the VLAN VID. */ + #define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff) + #define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define CQ_RES_UD_V2_CFA_METADATA0_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000) + #define CQ_RES_UD_V2_CFA_METADATA0_PRI_SFT 13 + /* Immediate data in case the imm_flag set. */ + uint32_t imm_data; /* - * This field represents a 32-bit total data length, in bytes. - * Note, however, that the length cannot exceed the MTU. + * This is an application level ID used to identify the + * QP and its SQ and RQ. */ - uint32_t length; - uint32_t reserved32_1; + uint64_t qp_handle; /* - * This value is action meta-data that defines CFA edit operations - * that are done in addition to any action editing. + * Source MAC address for the UD message placed in the WQE + * that is completed by this CQE. */ - uint32_t cfa_meta; - /* When key=1, This is the VLAN tag VID value. */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0 - /* When key=1, This is the VLAN tag DE value. */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE UINT32_C(0x1000) - /* When key=1, This is the VLAN tag PRI value. */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_SFT 13 - /* When key=1, This is the VLAN tag TPID select value. */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_SFT 16 - /* 0x88a8 */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) - /* 0x8100 */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) - /* 0x9100 */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) - /* 0x9200 */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) - /* 0x9300 */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) - /* Value programmed in CFA VLANTPID register. */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_LAST SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG - /* When key=1, This is the VLAN tag TPID select value. */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_SFT 19 + uint16_t src_mac[3]; + /* Lower 16b of the Source QP value from the DETH header. */ + uint16_t src_qp_low; + uint8_t cqe_type_toggle; /* - * This field identifies the type of edit to be performed - * on the packet. - * - * This value must be valid on the first BD of a packet. + * Indicate valid completion - written by the chip. Cumulus + * toggle this bit each time it finished consuming all PBL + * entries */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK UINT32_C(0xf0000000) - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_SFT 28 - /* No editing */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + #define CQ_RES_UD_V2_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_UD_V2_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_UD_V2_CQE_TYPE_SFT 1 /* - * - meta[17:16] - TPID select value (0 = 0x8100). - * - meta[15:12] - PRI/DE value. - * - meta[11:0] - VID value. + * Responder UD Completion - This is used for both RQ and SRQ + * completion for UD service QPs. */ - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) - #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG - uint32_t reserved32_2; - uint32_t reserved32_3; - uint32_t timestamp; + #define CQ_RES_UD_V2_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1) + #define CQ_RES_UD_V2_CQE_TYPE_LAST CQ_RES_UD_V2_CQE_TYPE_RES_UD + /* This field indicates the status for the CQE. */ + uint8_t status; /* - * This field specifies a 24-bit timestamp that can be passed - * down the TX path and optionally logged in the TXP timestamp - * histogram. + * This indicates that the completion is without error. + * All fields are valid. */ - #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK UINT32_C(0xffffff) - #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0 -} sq_send_raweth_qp1_hdr_t, *psq_send_raweth_qp1_hdr_t; - -/* RDMA SQ WQE */ -/* sq_rdma (size:1024b/128B) */ - -typedef struct sq_rdma { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; + #define CQ_RES_UD_V2_STATUS_OK UINT32_C(0x0) /* - * RDMA Write. + * This indicates that write access was not allowed for + * at least one of the SGEs in the WQE. * - * Allowed only on reliable connection (RC) SQs. + * This is a fatal error. Only the srq_or_rq_wr_id is field + * is valid. */ - #define SQ_RDMA_WQE_TYPE_WRITE_WQE UINT32_C(0x4) + #define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) /* - * RDMA Write with Immediate. + * This indicates that the packet was too long for the WQE + * provided on the SRQ/RQ. * - * Allowed only on reliable connection (RC) SQs. + * This is not a fatal error. All the fields are valid. */ - #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5) + #define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* LOCAL_PROTECTION_ERR is 3 */ + #define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) + /* LOCAL_QP_OPERATION_ERR is 4 */ + #define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* MEMORY_MGT_OPERATION_ERR is 5 */ + #define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) + /* WORK_REQUEST_FLUSHED_ERR is 7 */ + #define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) + /* HW_FLUSH_ERR is 8 */ + #define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8) + #define CQ_RES_UD_V2_STATUS_LAST CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR + uint16_t flags; /* - * RDMA Read. - * - * Allowed only on reliable connection (RC) SQs. + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. */ - #define SQ_RDMA_WQE_TYPE_READ_WQE UINT32_C(0x6) - #define SQ_RDMA_WQE_TYPE_LAST SQ_RDMA_WQE_TYPE_READ_WQE - uint8_t flags; - #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + #define CQ_RES_UD_V2_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_UD_V2_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_UD_V2_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_UD_V2_FLAGS_SRQ_LAST CQ_RES_UD_V2_FLAGS_SRQ_SRQ + /* Immediate data indicator */ + #define CQ_RES_UD_V2_FLAGS_IMM UINT32_C(0x2) + #define CQ_RES_UD_V2_FLAGS_UNUSED_MASK UINT32_C(0xc) + #define CQ_RES_UD_V2_FLAGS_UNUSED_SFT 2 + #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) + #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_SFT 4 + /* RoCEv1 Message */ + #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) + /* RoCEv2 IPv4 Message */ + #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) + /* RoCEv2 IPv6 Message */ + #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) + #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 + /* The field indicates what format the metadata field is. */ + #define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) + #define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6 + /* No metadata information. Value is zero. */ + #define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. */ - #define SQ_RDMA_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6) /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. i + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6) /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the + * prepended header (chdr_data). */ - #define SQ_RDMA_FLAGS_UC_FENCE UINT32_C(0x4) + #define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6) /* - * Solicit event. Indication sent in BTH header to the - * receiver to generate a Completion Event Notification, - * i.e. CNQE. This bit should be set only in the last (or - * only) packet of the message. + * If ext_meta_format is equal to 1, the metadata field contains + * the outer_l3_offset and lower 7 bits of the inner_l2_offset, + * - metadata[8:0] contains the outer_l3_offset. + * - metadata[15:9] contains the inner_l2_offset[6:0] + */ + #define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6) + #define CQ_RES_UD_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET + uint32_t src_qp_high_srq_or_rq_wr_id; + /* + * Opaque value from RQ or SRQ WQE. Used by driver/lib to + * reference the WQE in order to claim the received data + * and reuse the WQE space + */ + #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) + #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0 + #define CQ_RES_UD_V2_CFA_METADATA1_MASK UINT32_C(0xf00000) + #define CQ_RES_UD_V2_CFA_METADATA1_SFT 20 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000) + #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_SFT 20 + /* 0x88a8 */ + #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20) + /* 0x8100 */ + #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20) + /* 0x9100 */ + #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20) + /* 0x9200 */ + #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20) + /* 0x9300 */ + #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20) + /* Value programmed in CFA VLANTPID register. */ + #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20) + #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define CQ_RES_UD_V2_CFA_METADATA1_VALID UINT32_C(0x800000) + /* Upper 8b of the Source QP value from the DETH header. */ + #define CQ_RES_UD_V2_SRC_QP_HIGH_MASK UINT32_C(0xff000000) + #define CQ_RES_UD_V2_SRC_QP_HIGH_SFT 24 +} cq_res_ud_v2_t, *pcq_res_ud_v2_t; + +/* Responder UD with CFA CQE */ +/* cq_res_ud_cfa (size:256b/32B) */ + +typedef struct cq_res_ud_cfa { + uint16_t length; + /* + * The length of the message's payload in bytes, stored in + * the SGEs */ - #define SQ_RDMA_FLAGS_SE UINT32_C(0x8) + #define CQ_RES_UD_CFA_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_UD_CFA_LENGTH_SFT 0 /* - * Indicate that inline data is posted to the SQ following - * this WQE. This bit may be 1 only for write operations. + * This field identifies the CFA action rule that was used + * for this packet. */ - #define SQ_RDMA_FLAGS_INLINE UINT32_C(0x10) + uint16_t cfa_code; + /* Immediate data in case the imm_flag set. */ + uint32_t imm_data; + uint32_t qid; /* - * If set to 1, then the timestamp from the WQE is used. If - * cleared to 0, then TWE provides the timestamp. + * This value indicates the QPID associated with this operation. + * The driver will use the qid from this CQE to map a QP handle + * in the completion record returned to the application. */ - #define SQ_RDMA_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_UD_CFA_QID_MASK UINT32_C(0xfffff) + #define CQ_RES_UD_CFA_QID_SFT 0 /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * This is data from the CFA or VNIC block as indicated by the + * ext_meta_format and meta_format fields. */ - #define SQ_RDMA_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint32_t cfa_metadata; + /* When meta_format=1, this value is the VLAN VID. */ + #define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK UINT32_C(0xfff) + #define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define CQ_RES_UD_CFA_CFA_METADATA_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK UINT32_C(0xe000) + #define CQ_RES_UD_CFA_CFA_METADATA_PRI_SFT 13 + /* When meta_format=1, this value is the VLAN TPID. */ + #define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK UINT32_C(0xffff0000) + #define CQ_RES_UD_CFA_CFA_METADATA_TPID_SFT 16 /* - * The number of 16 bytes chunks of data including this first - * wqe of the request that are a valid part of the request. The - * valid 16 bytes units other than the WQE structure can be - * SGEs (Scatter Gather Elements) OR inline data. - * - * While this field defines the valid WQE size. The actual - * total WQE size is always 128B. + * Source MAC address for the UD message placed in the WQE + * that is completed by this CQE. */ - uint8_t wqe_size; - uint8_t reserved8; + uint16_t src_mac[3]; + /* Lower 16b of the Source QP value from the DETH header. */ + uint16_t src_qp_low; + uint8_t cqe_type_toggle; /* - * Immediate data - valid for RDMA Write with immediate and - * causes the controller to add immDt header with this value + * Indicate valid completion - written by the chip. Cumulus + * toggle this bit each time it finished consuming all PBL + * entries */ - uint32_t imm_data; - /* Total data length in bytes */ - uint32_t length; - uint32_t reserved32_1; - /* Remote VA sent to the destination QP */ - uint64_t remote_va; + #define CQ_RES_UD_CFA_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_UD_CFA_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_UD_CFA_CQE_TYPE_SFT 1 /* - * R_Key provided by remote node when the connection was - * established and placed in the RETH header. It identify the - * MRW on the remote host + * Responder UD Completion with CFA - This is used for both RQ + * and SRQ completion for UD service QPs. It includes cfa fields + * (some of which carry VLAN information), in place of the QP + * handle. It is also used for QP1 QPs that are treated as UD. */ - uint32_t remote_key; - uint32_t timestamp; + #define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1) + #define CQ_RES_UD_CFA_CQE_TYPE_LAST CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA + /* This field indicates the status for the CQE. */ + uint8_t status; /* - * This field specifies a 24-bit timestamp that can be passed - * down the TX path and optionally logged in the TXP timestamp - * histogram. + * This indicates that the completion is without error. + * All fields are valid. */ - #define SQ_RDMA_TIMESTAMP_MASK UINT32_C(0xffffff) - #define SQ_RDMA_TIMESTAMP_SFT 0 + #define CQ_RES_UD_CFA_STATUS_OK UINT32_C(0x0) /* - * When inline=0, then this area is filled with from 1 to 6 - * SGEs based on the wqe_size field. + * This indicates that write access was not allowed for + * at least one of the SGEs in the WQE. * - * When inline=1, this area is filled with payload data for the - * write based on the length field. Bits [7:0] of word 0 - * hold the first byte to go out on the wire. + * This is a fatal error. Only the srq_or_rq_wr_id is field + * is valid. */ - uint32_t data[24]; -} sq_rdma_t, *psq_rdma_t; - -/* RDMA SQ WQE header. */ -/* sq_rdma_hdr (size:256b/32B) */ - -typedef struct sq_rdma_hdr { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; + #define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) /* - * RDMA Write. + * This indicates that the packet was too long for the WQE + * provided on the SRQ/RQ. * - * Allowed only on reliable connection (RC) SQs. + * This is not a fatal error. All the fields are valid. */ - #define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE UINT32_C(0x4) + #define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* LOCAL_PROTECTION_ERR is 3 */ + #define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) + /* LOCAL_QP_OPERATION_ERR is 4 */ + #define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* MEMORY_MGT_OPERATION_ERR is 5 */ + #define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) + /* WORK_REQUEST_FLUSHED_ERR is 7 */ + #define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) + /* HW_FLUSH_ERR is 8 */ + #define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR UINT32_C(0x8) + #define CQ_RES_UD_CFA_STATUS_LAST CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR + uint16_t flags; /* - * RDMA Write with Immediate. - * - * Allowed only on reliable connection (RC) SQs. + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. */ - #define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5) + #define CQ_RES_UD_CFA_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_UD_CFA_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_UD_CFA_FLAGS_SRQ_LAST CQ_RES_UD_CFA_FLAGS_SRQ_SRQ + /* Immediate data indicator */ + #define CQ_RES_UD_CFA_FLAGS_IMM UINT32_C(0x2) + #define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK UINT32_C(0xc) + #define CQ_RES_UD_CFA_FLAGS_UNUSED_SFT 2 + #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) + #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_SFT 4 + /* RoCEv1 Message */ + #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) + /* RoCEv2 IPv4 Message */ + #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) + /* RoCEv2 IPv6 Message */ + #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) + #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 /* - * RDMA Read. - * - * Allowed only on reliable connection (RC) SQs. + * The combination of this value and ext_meta_format indicates + * what format the metadata field is. */ - #define SQ_RDMA_HDR_WQE_TYPE_READ_WQE UINT32_C(0x6) - #define SQ_RDMA_HDR_WQE_TYPE_LAST SQ_RDMA_HDR_WQE_TYPE_READ_WQE - uint8_t flags; - #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) + #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_SFT 6 /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * If ext_meta_format is equal to 0, there is no metadata + * information. Value is zero. */ - #define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * If ext_meta_format is equal to 0, the metadata field contains + * the VLAN tag and TPID value. + * - metadata[11:0] contains the vlan VID value. + * - metadata[12] contains the vlan DE value. + * - metadata[15:13] contains the vlan PRI value. + * - metadata[31:16] contains the vlan TPID value. */ - #define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (UINT32_C(0x1) << 6) /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * If ext_meta_format is equal to 1, the metadata field contains + * the Tunnel ID value, justified to LSB. + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0 + * - IPV4 = 0 (not populated) + * - IPV6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - #define SQ_RDMA_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6) /* - * Solicit event. Indication sent in BTH header to the - * receiver to generate a Completion Event Notification, - * i.e. CNQE. This bit should be set only in the last (or - * only) packet of the message. + * if ext_meta_format is equal to 1, metadata field contains + * 16b metadata from the prepended header (chdr_data). */ - #define SQ_RDMA_HDR_FLAGS_SE UINT32_C(0x8) + #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6) /* - * Indicate that inline data is posted to the SQ following - * this WQE. This bit may be 1 only for write operations. + * If ext_meta_format is equal to 1, the metadata field contains + * the outer_l3_offset, inner_l2_offset, inner_l3_offset, and + * inner_l4_size. + * - metadata[8:0] contains the outer_l3_offset. + * - metadata[17:9] contains the inner_l2_offset. + * - metadata[26:18] contains the inner_l3_offset. + * - metadata[31:27] contains the inner_l4_size. */ - #define SQ_RDMA_HDR_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6) + #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET /* - * If set to 1, then the timestamp from the WQE is used. If - * cleared to 0, then TWE provides the timestamp. + * The combination of this value and meta_format indicates what + * format the metadata field is */ - #define SQ_RDMA_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK UINT32_C(0xc00) + #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_SFT 10 + uint32_t src_qp_high_srq_or_rq_wr_id; /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * Opaque value from RQ or SRQ WQE. Used by driver/lib to + * reference the WQE in order to claim the received data + * and reuse the WQE space */ - #define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) + #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0 + /* Upper 8b of the Source QP value from the DETH header. */ + #define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK UINT32_C(0xff000000) + #define CQ_RES_UD_CFA_SRC_QP_HIGH_SFT 24 +} cq_res_ud_cfa_t, *pcq_res_ud_cfa_t; + +/* Responder UD with CFA CQE version 2 */ +/* cq_res_ud_cfa_v2 (size:256b/32B) */ + +typedef struct cq_res_ud_cfa_v2 { + uint16_t length; /* - * The number of 16 bytes chunks of data including this first - * wqe of the request that are a valid part of the request. The - * valid 16 bytes units other than the WQE structure can be - * SGEs (Scatter Gather Elements) OR inline data. - * - * While this field defines the valid WQE size. The actual - * total WQE size is always 128B. + * The length of the message's payload in bytes, stored in + * the SGEs */ - uint8_t wqe_size; - uint8_t reserved8; + #define CQ_RES_UD_CFA_V2_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_UD_CFA_V2_LENGTH_SFT 0 + /* This is data from the CFA as indicated by the meta_format field. */ + uint16_t cfa_metadata0; + /* When meta_format=1, this value is the VLAN VID. */ + #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff) + #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000) + #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_SFT 13 + /* Immediate data in case the imm_flag set. */ + uint32_t imm_data; + uint32_t qid; /* - * Immediate data - valid for RDMA Write with immediate and - * causes the controller to add immDt header with this value + * This value indicates the QPID associated with this operation. + * The driver will use the qid from this CQE to map a QP handle + * in the completion record returned to the application. */ - uint32_t imm_data; - /* Total data length in bytes */ - uint32_t length; - uint32_t reserved32_1; - /* Remote VA sent to the destination QP */ - uint64_t remote_va; + #define CQ_RES_UD_CFA_V2_QID_MASK UINT32_C(0xfffff) + #define CQ_RES_UD_CFA_V2_QID_SFT 0 /* - * R_Key provided by remote node when the connection was - * established and placed in the RETH header. It identify the - * MRW on the remote host + * This is data from the CFA block as indicated by the meta_format + * field. + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + * When vee_cmpl_mode is set in VNIC context, this is the upper 32b + * of the host address from the first BD used to place the packet. */ - uint32_t remote_key; - uint32_t timestamp; + uint32_t cfa_metadata2; /* - * This field specifies a 24-bit timestamp that can be passed - * down the TX path and optionally logged in the TXP timestamp - * histogram. + * Source MAC address for the UD message placed in the WQE + * that is completed by this CQE. */ - #define SQ_RDMA_HDR_TIMESTAMP_MASK UINT32_C(0xffffff) - #define SQ_RDMA_HDR_TIMESTAMP_SFT 0 -} sq_rdma_hdr_t, *psq_rdma_hdr_t; - -/* Atomic SQ WQE */ -/* sq_atomic (size:1024b/128B) */ - -typedef struct sq_atomic { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; + uint16_t src_mac[3]; + /* Lower 16b of the Source QP value from the DETH header. */ + uint16_t src_qp_low; + uint8_t cqe_type_toggle; /* - * Atomic Compare/Swap. - * - * Allowed only on reliable connection (RC) SQs. + * Indicate valid completion - written by the chip. Cumulus + * toggle this bit each time it finished consuming all PBL + * entries */ - #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS UINT32_C(0x8) + #define CQ_RES_UD_CFA_V2_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1 /* - * Atomic Fetch/Add. - * - * Allowed only on reliable connection (RC) SQs. + * Responder UD Completion with CFA - This is used for both RQ + * and SRQ completion for UD service QPs. It includes cfa fields + * (some of which carry VLAN information), in place of the QP + * handle. It is also used for QP1 QPs that are treated as UD. */ - #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA UINT32_C(0xb) - #define SQ_ATOMIC_WQE_TYPE_LAST SQ_ATOMIC_WQE_TYPE_ATOMIC_FA - uint8_t flags; - #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + #define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1) + #define CQ_RES_UD_CFA_V2_CQE_TYPE_LAST CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA + /* This field indicates the status for the CQE. */ + uint8_t status; /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * This indicates that the completion is without error. + * All fields are valid. */ - #define SQ_ATOMIC_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_UD_CFA_V2_STATUS_OK UINT32_C(0x0) /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * This indicates that write access was not allowed for + * at least one of the SGEs in the WQE. + * + * This is a fatal error. Only the srq_or_rq_wr_id is field + * is valid. */ - #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * This indicates that the packet was too long for the WQE + * provided on the SRQ/RQ. + * + * This is not a fatal error. All the fields are valid. */ - #define SQ_ATOMIC_FLAGS_UC_FENCE UINT32_C(0x4) + #define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* LOCAL_PROTECTION_ERR is 3 */ + #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) + /* LOCAL_QP_OPERATION_ERR is 4 */ + #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* MEMORY_MGT_OPERATION_ERR is 5 */ + #define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) + /* WORK_REQUEST_FLUSHED_ERR is 7 */ + #define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) + /* HW_FLUSH_ERR is 8 */ + #define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8) + #define CQ_RES_UD_CFA_V2_STATUS_LAST CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR + uint16_t flags; /* - * Solicit event. Indication sent in BTH header to the - * receiver to generate a Completion Event Notification, - * i.e. CNQE. This bit should be set only in the last (or - * only) packet of the message. + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. */ - #define SQ_ATOMIC_FLAGS_SE UINT32_C(0x8) - /* NA for this WQE */ - #define SQ_ATOMIC_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_UD_CFA_V2_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ + /* Immediate data indicator */ + #define CQ_RES_UD_CFA_V2_FLAGS_IMM UINT32_C(0x2) + #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK UINT32_C(0xc) + #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_SFT 2 + #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) + #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_SFT 4 + /* RoCEv1 Message */ + #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) + /* RoCEv2 IPv4 Message */ + #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) + /* RoCEv2 IPv6 Message */ + #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) + #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 + /* The field indicates what format the metadata field is. */ + #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) + #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6 + /* No metadata information. Value is zero. */ + #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) /* - * The atomic WQE does not have a timestamp field, so this field is - * ignored and should be zero. + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. */ - #define SQ_ATOMIC_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. i + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - #define SQ_ATOMIC_FLAGS_DEBUG_TRACE UINT32_C(0x40) - uint16_t reserved16; + #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6) /* - * R_Key provided by remote node when the connection was - * established and placed in the AETH header. It identify the - * MRW on the remote host + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the + * prepended header (chdr_data). */ - uint32_t remote_key; - /* Remote VA sent to the destination QP */ - uint64_t remote_va; - /* Data value to be placed in remote host specified address */ - uint64_t swap_data; + #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6) /* - * Data value to be compared with the value in the remote host - * specified address + * If ext_meta_format is equal to 1, the metadata field contains + * the outer_l3_offset and lower 7 bits of the inner_l2_offset, + * - metadata[8:0] contains the outer_l3_offset. + * - metadata[15:9] contains the inner_l2_offset[6:0] */ - uint64_t cmp_data; + #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6) + #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET + uint32_t src_qp_high_srq_or_rq_wr_id; /* - * The first 16B of the data field must be filled with a single - * SGE. This will be used to store the return value from the - * Atomic Ack response. The size of the single SGE must be 8B. + * Opaque value from RQ or SRQ WQE. Used by driver/lib to + * reference the WQE in order to claim the received data + * and reuse the WQE space */ - uint32_t data[24]; -} sq_atomic_t, *psq_atomic_t; + #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) + #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0 + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK UINT32_C(0xf00000) + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_SFT 20 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000) + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_SFT 20 + /* 0x88a8 */ + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20) + /* 0x8100 */ + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20) + /* 0x9100 */ + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20) + /* 0x9200 */ + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20) + /* 0x9300 */ + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20) + /* Value programmed in CFA VLANTPID register. */ + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20) + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID UINT32_C(0x800000) + /* Upper 8b of the Source QP value from the DETH header. */ + #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK UINT32_C(0xff000000) + #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_SFT 24 +} cq_res_ud_cfa_v2_t, *pcq_res_ud_cfa_v2_t; -/* Atomic SQ WQE header. */ -/* sq_atomic_hdr (size:256b/32B) */ +/* Responder RawEth and QP1 CQE */ +/* cq_res_raweth_qp1 (size:256b/32B) */ -typedef struct sq_atomic_hdr { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; - /* - * Atomic Compare/Swap. - * - * Allowed only on reliable connection (RC) SQs. - */ - #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS UINT32_C(0x8) +typedef struct cq_res_raweth_qp1 { + uint16_t length; /* - * Atomic Fetch/Add. - * - * Allowed only on reliable connection (RC) SQs. + * The length of the message's payload in bytes, stored in + * the SGEs */ - #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA UINT32_C(0xb) - #define SQ_ATOMIC_HDR_WQE_TYPE_LAST SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA - uint8_t flags; - #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + #define CQ_RES_RAWETH_QP1_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0 + uint16_t raweth_qp1_flags; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK UINT32_C(0x3ff) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0 /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * raweth_qp1_errors. */ - #define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1) /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * This value indicates what the inner packet determined for the + * packet was. */ - #define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK UINT32_C(0x3c0) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6 /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * Not Known: + * Indicates that the packet type was not known. */ - #define SQ_ATOMIC_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6) /* - * Solicit event. Indication sent in BTH header to the - * receiver to generate a Completion Event Notification, - * i.e. CNQE. This bit should be set only in the last (or - * only) packet of the message. + * IP Packet: + * Indicates that the packet was an IP packet, but further + * classification was not possible. */ - #define SQ_ATOMIC_HDR_FLAGS_SE UINT32_C(0x8) - /* NA for this WQE */ - #define SQ_ATOMIC_HDR_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (UINT32_C(0x1) << 6) /* - * The atomic WQE does not have a timestamp field, so this field is - * ignored and should be zero. + * TCP Packet: + * Indicates that the packet was IP and TCP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ - #define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 6) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * UDP Packet: + * Indicates that the packet was IP and UDP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ - #define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) - uint16_t reserved16; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 6) /* - * R_Key provided by remote node when the connection was - * established and placed in the AETH header. It identify the - * MRW on the remote host + * FCoE Packet: + * Indicates that the packet was recognized as a FCoE. + * This also indicates that the raweth_qp1_payload_offset field + * is valid. */ - uint32_t remote_key; - /* Remote VA sent to the destination QP */ - uint64_t remote_va; - /* Data value to be placed in remote host specified address */ - uint64_t swap_data; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 6) /* - * Data value to be compared with the value in the remote host - * specified address + * RoCE Packet: + * Indicates that the packet was recognized as a RoCE. + * This also indicates that the raweth_qp1_payload_offset field + * is valid. */ - uint64_t cmp_data; -} sq_atomic_hdr_t, *psq_atomic_hdr_t; - -/* Local Invalidate SQ WQE */ -/* sq_localinvalidate (size:1024b/128B) */ - -typedef struct sq_localinvalidate { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 6) /* - * Local Invalidate. - * - * Allowed only on reliable connection (RC) SQs. + * ICMP Packet: + * Indicates that the packet was recognized as ICMP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ - #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc) - #define SQ_LOCALINVALIDATE_WQE_TYPE_LAST SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID - uint8_t flags; - #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 6) /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * PtP packet wo/timestamp: + * Indicates that the packet was recognized as a PtP + * packet. */ - #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6) /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * PtP packet w/timestamp: + * Indicates that the packet was recognized as a PtP + * packet and that a timestamp was taken for the packet. */ - #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP + uint16_t raweth_qp1_errors; /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * This indicates that there was an error in the IP header + * checksum. */ - #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE UINT32_C(0x4) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10) /* - * Solicit event. Indication sent in BTH header to the - * receiver to generate a Completion Event Notification, - * i.e. CNQE. This bit should be set only in the last (or - * only) packet of the message. + * This indicates that there was an error in the TCP, UDP + * or ICMP checksum. */ - #define SQ_LOCALINVALIDATE_FLAGS_SE UINT32_C(0x8) - /* NA for this WQE */ - #define SQ_LOCALINVALIDATE_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20) /* - * This flag is not applicable and should be 0 for a local memory - * operation WQE. + * This indicates that there was an error in the tunnel + * IP header checksum. */ - #define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * This indicates that there was an error in the tunnel + * UDP checksum. */ - #define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE UINT32_C(0x40) - uint16_t reserved16; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80) /* - * The local key for the MR/W to invalidate; 24 msb of the key - * are used to index the MRW table, 8 lsb are compared with the - * 8 bit key in the MRWC + * This indicates that there was a CRC error on either an FCoE + * or RoCE packet. The itype indicates the packet type. */ - uint32_t inv_l_key; - uint64_t reserved64; - uint8_t reserved128[16]; - /* The data field for local invalidate is not used. */ - uint32_t data[24]; -} sq_localinvalidate_t, *psq_localinvalidate_t; - -/* Local Invalidate SQ WQE header. */ -/* sq_localinvalidate_hdr (size:256b/32B) */ - -typedef struct sq_localinvalidate_hdr { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100) /* - * Local Invalidate. - * - * Allowed only on reliable connection (RC) SQs. + * This indicates that there was an error in the tunnel + * portion of the packet when this + * field is non-zero. */ - #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc) - #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID - uint8_t flags; - #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * No additional error occurred on the tunnel portion + * of the packet of the packet does not have a tunnel. */ - #define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9) /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 + * in the tunnel header. */ - #define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9) /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * Indicates that header length is out of range in the + * tunnel header. Valid for + * IPv4. */ - #define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE UINT32_C(0x4) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9) /* - * Solicit event. Indication sent in BTH header to the - * receiver to generate a Completion Event Notification, - * i.e. CNQE. This bit should be set only in the last (or - * only) packet of the message. + * Indicates that the physical packet is shorter than that + * claimed by the PPPoE header length for a tunnel PPPoE + * packet. */ - #define SQ_LOCALINVALIDATE_HDR_FLAGS_SE UINT32_C(0x8) - /* NA for this WQE */ - #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9) /* - * This flag is not applicable and should be 0 for a local memory - * operation WQE. + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 + * tunnel packet packets. */ - #define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * Indicates that the physical packet is shorter than that + * claimed by the tunnel UDP header length for a tunnel + * UDP packet that is not fragmented. */ - #define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) - uint16_t reserved16; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9) /* - * The local key for the MR/W to invalidate; 24 msb of the key - * are used to index the MRW table, 8 lsb are compared with the - * 8 bit key in the MRWC + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0) in the tunnel header. Valid + * for IPv4, and IPv6. */ - uint32_t inv_l_key; - uint64_t reserved64; - uint8_t reserved128[16]; -} sq_localinvalidate_hdr_t, *psq_localinvalidate_hdr_t; - -/* FR-PMR SQ WQE */ -/* sq_fr_pmr (size:1024b/128B) */ - -typedef struct sq_fr_pmr { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL /* - * FR-PMR (Fast Register Physical Memory Region) - * - * Allowed only on reliable connection (RC) SQs. + * This indicates that there was an error in the inner + * portion of the packet when this + * field is non-zero. */ - #define SQ_FR_PMR_WQE_TYPE_FR_PMR UINT32_C(0xd) - #define SQ_FR_PMR_WQE_TYPE_LAST SQ_FR_PMR_WQE_TYPE_FR_PMR - uint8_t flags; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * No additional error occurred on the tunnel portion + * of the packet of the packet does not have a tunnel. */ - #define SQ_FR_PMR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12) /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 or that + * option other than VFT was parsed on + * FCoE packet. */ - #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12) /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * indicates that header length is out of range. Valid for + * IPv4 and RoCE */ - #define SQ_FR_PMR_FLAGS_UC_FENCE UINT32_C(0x4) - /* Not Applicable for FR_PMR. Nothing is sent */ - #define SQ_FR_PMR_FLAGS_SE UINT32_C(0x8) - /* NA */ - #define SQ_FR_PMR_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12) /* - * This flag is not applicable and should be 0 for a local memory - * operation WQE. + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 */ - #define SQ_FR_PMR_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * Indicates that physical packet is shorter than that + * claimed by the l3 header length. Valid for IPv4, + * IPv6 packet or RoCE packets. */ - #define SQ_FR_PMR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is - * not allowed. + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is + * not fragmented. */ - uint8_t access_cntl; - /* Local Write Access */ - #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) - /* Remote Read Access */ - #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) - /* Remote Write Access */ - #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) - /* Remote Atomic Access */ - #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) - /* Window Binding Allowed */ - #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) - uint8_t zero_based_page_size_log; - /* Page size. 0 for 4KB page size, ... to 8TB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) - #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0 - /* Page size is 4KB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) - /* Page size is 8KB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) - /* Page size is 16KB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) - /* Page size is 32KB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) - /* Page size is 64KB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) - /* Page size is 128KB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) - /* Page size is 256KB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) - /* Page size is 512KB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) - /* Page size is 1MB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) - /* Page size is 2MB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) - /* Page size is 4MB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) - /* Page size is 8MB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) - /* Page size is 16MB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) - /* Page size is 32MB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) - /* Page size is 64MB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) - /* Page size is 128MB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) - /* Page size is 256MB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) - /* Page size is 512MB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) - /* Page size is 1GB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) - /* Page size is 2GB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) - /* Page size is 4GB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) - /* Page size is 8GB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) - /* Page size is 16GB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) - /* Page size is 32GB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) - /* Page size is 64GB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) - /* Page size is 128GB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) - /* Page size is 256GB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) - /* Page size is 512GB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) - /* Page size is 1TB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) - /* Page size is 2TB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) - /* Page size is 4TB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) - /* Page size is 8TB. */ - #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) - #define SQ_FR_PMR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T - /* Indicate the MR is ZBVA (Zero Base VA) */ - #define SQ_FR_PMR_ZERO_BASED UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12) /* - * Local Key; 24 msb of the key are used to index the MRW - * table, 8 lsb are assigned to the 8 bit key_lsb field in - * the MRWC. + * Indicates that TCP header length > IP payload. Valid for + * TCP packets only. */ - uint32_t l_key; - /* Length in bytes of registered MR */ - uint8_t length[5]; - uint8_t reserved8_1; - uint8_t reserved8_2; - uint8_t numlevels_pbl_page_size_log; - /* PBL page size. 0 for 4KB page size, ... to 8TB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0 - /* Page size is 4KB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) - /* Page size is 8KB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) - /* Page size is 16KB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) - /* Page size is 32KB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) - /* Page size is 64KB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) - /* Page size is 128KB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) - /* Page size is 256KB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) - /* Page size is 512KB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) - /* Page size is 1MB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) - /* Page size is 2MB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) - /* Page size is 4MB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) - /* Page size is 8MB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) - /* Page size is 16MB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) - /* Page size is 32MB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) - /* Page size is 64MB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) - /* Page size is 128MB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) - /* Page size is 256MB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) - /* Page size is 512MB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) - /* Page size is 1GB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) - /* Page size is 2GB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) - /* Page size is 4GB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) - /* Page size is 8GB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) - /* Page size is 16GB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) - /* Page size is 32GB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) - /* Page size is 64GB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) - /* Page size is 128GB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) - /* Page size is 256GB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) - /* Page size is 512GB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) - /* Page size is 1TB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) - /* Page size is 2TB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) - /* Page size is 4TB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) - /* Page size is 8TB. */ - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) - #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T - /* Number of levels of PBL for translation */ - #define SQ_FR_PMR_NUMLEVELS_MASK UINT32_C(0xc0) - #define SQ_FR_PMR_NUMLEVELS_SFT 6 + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12) /* - * A zero level PBL means that the VA is the physical address used - * for the operation. No translation is done by the PTU. + * Indicates that TCP option headers result in a TCP header + * size that does not match data offset in TCP header. Valid + * for TCP. */ - #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN /* - * A one layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PBE values that point to actual pg_size physical pages. + * This field identifies the CFA action rule that was used for this + * packet. */ - #define SQ_FR_PMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) + uint16_t raweth_qp1_cfa_code; /* - * A two layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PDE values that in turn point to pbl_pg_size physical pages that contain - * PBE values that point to actual physical pages. + * This is an application level ID used to identify the + * QP and its SQ and RQ. */ - #define SQ_FR_PMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) - #define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2 - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t pblptr; - /* Local Virtual Address */ - uint64_t va; - /* The data field for FR-PMR is not used. */ - uint32_t data[24]; -} sq_fr_pmr_t, *psq_fr_pmr_t; - -/* FR-PMR SQ WQE header. */ -/* sq_fr_pmr_hdr (size:256b/32B) */ - -typedef struct sq_fr_pmr_hdr { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; + uint64_t qp_handle; + uint32_t raweth_qp1_flags2; /* - * FR-PMR (Fast Register Physical Memory Region) - * - * Allowed only on reliable connection (RC) SQs. + * This indicates that the ip checksum was calculated for the + * inner packet and that the ip_cs_error field indicates if there + * was an error. */ - #define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR UINT32_C(0xd) - #define SQ_FR_PMR_HDR_WQE_TYPE_LAST SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR - uint8_t flags; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC UINT32_C(0x1) /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * This indicates that the TCP, UDP or ICMP checksum was + * calculated for the inner packet and that the l4_cs_error field + * indicates if there was an error. */ - #define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC UINT32_C(0x2) /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * This indicates that the ip checksum was calculated for the + * tunnel header and that the t_ip_cs_error field indicates if + * there was an error. */ - #define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * This indicates that the UDP checksum was + * calculated for the tunnel packet and that the t_l4_cs_error + * field indicates if there was an error. */ - #define SQ_FR_PMR_HDR_FLAGS_UC_FENCE UINT32_C(0x4) - /* Not Applicable for FR_PMR. Nothing is sent */ - #define SQ_FR_PMR_HDR_FLAGS_SE UINT32_C(0x8) - /* NA */ - #define SQ_FR_PMR_HDR_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) /* - * This flag is not applicable and should be 0 for a local memory - * operation WQE. + * This value indicates what format the raweth_qp1_metadata field + * is. */ - #define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 + /* No metadata information. Value is zero. */ + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * The raweth_qp1_metadata field contains the VLAN tag and TPID + * value. + * - raweth_qp1_metadata[11:0] contains the vlan VID value. + * - raweth_qp1_metadata[12] contains the vlan DE value. + * - raweth_qp1_metadata[15:13] contains the vlan PRI value. + * - raweth_qp1_metadata[31:16] contains the vlan TPID value. */ - #define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is - * not allowed. + * If ext_meta_format is equal to 1, the metadata field + * contains the lower 16b of the tunnel ID value, justified + * to LSB + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier. + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0 + * - IPV4 = 0 (not populated) + * - IPV6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - uint8_t access_cntl; - /* Local Write Access */ - #define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) - /* Remote Read Access */ - #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) - /* Remote Write Access */ - #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) - /* Remote Atomic Access */ - #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) - /* Window Binding Allowed */ - #define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) - uint8_t zero_based_page_size_log; - /* Page size. 0 for 4KB page size, ... to 8TB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0 - /* Page size is 4KB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) - /* Page size is 8KB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) - /* Page size is 16KB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) - /* Page size is 32KB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) - /* Page size is 64KB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) - /* Page size is 128KB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) - /* Page size is 256KB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) - /* Page size is 512KB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) - /* Page size is 1MB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) - /* Page size is 2MB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) - /* Page size is 4MB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) - /* Page size is 8MB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) - /* Page size is 16MB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) - /* Page size is 32MB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) - /* Page size is 64MB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) - /* Page size is 128MB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) - /* Page size is 256MB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) - /* Page size is 512MB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) - /* Page size is 1GB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) - /* Page size is 2GB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) - /* Page size is 4GB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) - /* Page size is 8GB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) - /* Page size is 16GB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) - /* Page size is 32GB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) - /* Page size is 64GB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) - /* Page size is 128GB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) - /* Page size is 256GB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) - /* Page size is 512GB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) - /* Page size is 1TB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) - /* Page size is 2TB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) - /* Page size is 4TB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) - /* Page size is 8TB. */ - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) - #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T - /* Indicate the MR is ZBVA (Zero Base VA) */ - #define SQ_FR_PMR_HDR_ZERO_BASED UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4) /* - * Local Key; 24 msb of the key are used to index the MRW - * table, 8 lsb are assigned to the 8 bit key_lsb field in - * the MRWC. + * if ext_meta_format is equal to 1, metadata field contains + * 16b metadata from the prepended header (chdr_data). */ - uint32_t l_key; - /* Length in bytes of registered MR */ - uint8_t length[5]; - uint8_t reserved8_1; - uint8_t reserved8_2; - uint8_t numlevels_pbl_page_size_log; - /* PBL page size. 0 for 4KB page size, ... to 8TB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0 - /* Page size is 4KB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) - /* Page size is 8KB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) - /* Page size is 16KB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) - /* Page size is 32KB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) - /* Page size is 64KB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) - /* Page size is 128KB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) - /* Page size is 256KB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) - /* Page size is 512KB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) - /* Page size is 1MB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) - /* Page size is 2MB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) - /* Page size is 4MB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) - /* Page size is 8MB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) - /* Page size is 16MB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) - /* Page size is 32MB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) - /* Page size is 64MB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) - /* Page size is 128MB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) - /* Page size is 256MB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) - /* Page size is 512MB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) - /* Page size is 1GB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) - /* Page size is 2GB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) - /* Page size is 4GB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) - /* Page size is 8GB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) - /* Page size is 16GB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) - /* Page size is 32GB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) - /* Page size is 64GB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) - /* Page size is 128GB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) - /* Page size is 256GB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) - /* Page size is 512GB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) - /* Page size is 1TB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) - /* Page size is 2TB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) - /* Page size is 4TB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) - /* Page size is 8TB. */ - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) - #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T - /* Number of levels of PBL for translation */ - #define SQ_FR_PMR_HDR_NUMLEVELS_MASK UINT32_C(0xc0) - #define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6 + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4) /* - * A zero level PBL means that the VA is the physical address used - * for the operation. No translation is done by the PTU. + * If ext_meta_format is equal to 1, the metadata field contains + * the outer_l3_offset and lower 7 bits of the inner_l2_offset, + * - metadata[8:0] contains the outer_l3_offset. + * - metadata[15:9] contains the inner_l2_offset[6:0] */ - #define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET /* - * A one layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PBE values that point to actual pg_size physical pages. + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. */ - #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100) /* - * A two layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PDE values that in turn point to pbl_pg_size physical pages that contain - * PBE values that point to actual physical pages. + * This indicates that the complete 1's complement checksum was + * calculated for the packet. */ - #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) - #define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t pblptr; - /* Local Virtual Address */ - uint64_t va; -} sq_fr_pmr_hdr_t, *psq_fr_pmr_hdr_t; - -/* FR-PPMR SQ WQE */ -/* sq_fr_ppmr (size:1024b/128B) */ - -typedef struct sq_fr_ppmr { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200) /* - * FR-PPMR (Fast Register Proxy Physical Memory Region) - * - * Allowed only on reliable connection (RC) SQs. + * The combination of this value and meta_format indicated what + * format the metadata field is. */ - #define SQ_FR_PPMR_WQE_TYPE_FR_PPMR UINT32_C(0xf) - #define SQ_FR_PPMR_WQE_TYPE_LAST SQ_FR_PPMR_WQE_TYPE_FR_PPMR - uint8_t flags; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10 /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * This value is the complete 1's complement checksum calculated + * from the start of the outer L3 header to the end of the packet + * (not including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. */ - #define SQ_FR_PPMR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * This is data from the CFA block as indicated by the meta_format + * field. */ - #define SQ_FR_PPMR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + uint32_t raweth_qp1_metadata; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK UINT32_C(0xffff) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0 + /* When meta_format=1, this value is the VLAN VID. */ + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK UINT32_C(0xfff) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK UINT32_C(0xe000) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13 + /* When meta_format=1, this value is the VLAN TPID. */ + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK UINT32_C(0xffff0000) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16 + uint8_t cqe_type_toggle; /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * Indicate valid completion - written by the chip. Cumulus + * toggle this bit each time it finished consuming all PBL + * entries */ - #define SQ_FR_PPMR_FLAGS_UC_FENCE UINT32_C(0x4) - /* Not Applicable for FR_PPMR. Nothing is sent */ - #define SQ_FR_PPMR_FLAGS_SE UINT32_C(0x8) - /* NA */ - #define SQ_FR_PPMR_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_RAWETH_QP1_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1 /* - * This flag is not applicable and should be 0 for a local memory - * operation WQE. + * Responder RawEth and QP1 Completion - This is used for RQ + * completion for RawEth service and QP1 service QPs. */ - #define SQ_FR_PPMR_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1) + #define CQ_RES_RAWETH_QP1_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 + /* This field indicates the status for the CQE. */ + uint8_t status; /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * This indicates that the completion is without error. + * All fields are valid. */ - #define SQ_FR_PPMR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + #define CQ_RES_RAWETH_QP1_STATUS_OK UINT32_C(0x0) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is - * not allowed. + * This indicates that write access was not allowed for + * at least one of the SGEs in the WQE. + * + * This is a fatal error. Only the srq_or_rq_wr_id is field + * is valid. */ - uint8_t access_cntl; - /* Local Write Access */ - #define SQ_FR_PPMR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) - /* Remote Read Access */ - #define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) - /* Remote Write Access */ - #define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) - /* Remote Atomic Access */ - #define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) - /* Window Binding Allowed */ - #define SQ_FR_PPMR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) - uint8_t zero_based_page_size_log; - /* Page size. 0 for 4KB page size, ... to 8TB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) - #define SQ_FR_PPMR_PAGE_SIZE_LOG_SFT 0 - /* Page size is 4KB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) - /* Page size is 8KB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) - /* Page size is 16KB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) - /* Page size is 32KB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) - /* Page size is 64KB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) - /* Page size is 128KB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) - /* Page size is 256KB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) - /* Page size is 512KB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) - /* Page size is 1MB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) - /* Page size is 2MB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) - /* Page size is 4MB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) - /* Page size is 8MB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) - /* Page size is 16MB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) - /* Page size is 32MB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) - /* Page size is 64MB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) - /* Page size is 128MB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) - /* Page size is 256MB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) - /* Page size is 512MB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) - /* Page size is 1GB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) - /* Page size is 2GB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) - /* Page size is 4GB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) - /* Page size is 8GB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) - /* Page size is 16GB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) - /* Page size is 32GB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) - /* Page size is 64GB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) - /* Page size is 128GB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) - /* Page size is 256GB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) - /* Page size is 512GB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) - /* Page size is 1TB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) - /* Page size is 2TB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) - /* Page size is 4TB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) - /* Page size is 8TB. */ - #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) - #define SQ_FR_PPMR_PAGE_SIZE_LOG_LAST SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8T - /* Indicate the MR is ZBVA (Zero Base VA) */ - #define SQ_FR_PPMR_ZERO_BASED UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) /* - * Local Key; 24 msb of the key are used to index the MRW - * table, 8 lsb are assigned to the 8 bit key_lsb field in - * the MRWC. + * This indicates that the packet was too long for the WQE + * provided on the RQ. + * + * This is not a fatal error. All the fields are valid. */ - uint32_t l_key; - /* Length in bytes of registered MR */ - uint32_t length; - /* Sets the proxy_vfid field of the physical memory region. */ - uint16_t proxy_vfid; - /* Sets the proxy_pfid field of the physical memory region. */ - uint8_t proxy_pfid; - uint8_t numlevels_pbl_page_size_log; - /* PBL page size. 0 for 4KB page size, ... to 8TB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_SFT 0 - /* Page size is 4KB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) - /* Page size is 8KB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) - /* Page size is 16KB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) - /* Page size is 32KB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) - /* Page size is 64KB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) - /* Page size is 128KB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) - /* Page size is 256KB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) - /* Page size is 512KB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) - /* Page size is 1MB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) - /* Page size is 2MB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) - /* Page size is 4MB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) - /* Page size is 8MB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) - /* Page size is 16MB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) - /* Page size is 32MB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) - /* Page size is 64MB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) - /* Page size is 128MB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) - /* Page size is 256MB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) - /* Page size is 512MB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) - /* Page size is 1GB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) - /* Page size is 2GB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) - /* Page size is 4GB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) - /* Page size is 8GB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) - /* Page size is 16GB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) - /* Page size is 32GB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) - /* Page size is 64GB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) - /* Page size is 128GB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) - /* Page size is 256GB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) - /* Page size is 512GB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) - /* Page size is 1TB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) - /* Page size is 2TB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) - /* Page size is 4TB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) - /* Page size is 8TB. */ - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) - #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8T - /* Sets the proxy_vf_valid field of the physical memory region. */ - #define SQ_FR_PPMR_PROXY_VF_VALID UINT32_C(0x20) - /* Number of levels of PBL for translation */ - #define SQ_FR_PPMR_NUMLEVELS_MASK UINT32_C(0xc0) - #define SQ_FR_PPMR_NUMLEVELS_SFT 6 + #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* LOCAL_PROTECTION_ERR is 3 */ + #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) + /* LOCAL_QP_OPERATION_ERR is 4 */ + #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* MEMORY_MGT_OPERATION_ERR is 5 */ + #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) + /* WORK_REQUEST_FLUSHED_ERR is 7 */ + #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) + /* HW_FLUSH_ERR is 8 */ + #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR UINT32_C(0x8) + #define CQ_RES_RAWETH_QP1_STATUS_LAST CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR + uint16_t flags; /* - * A zero level PBL means that the VA is the physical address used - * for the operation. No translation is done by the PTU. + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. */ - #define SQ_FR_PPMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) + #define CQ_RES_RAWETH_QP1_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ + uint32_t raweth_qp1_payload_offset_srq_or_rq_wr_id; /* - * A one layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PBE values that point to actual pg_size physical pages. + * Opaque value from RQ or SRQ WQE. Used by driver/lib to + * reference the WQE in order to claim the received data + * and reuse the WQE space */ - #define SQ_FR_PPMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) + #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) + #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0 /* - * A two layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PDE values that in turn point to pbl_pg_size physical pages that contain - * PBE values that point to actual physical pages. + * This value indicates the offset in bytes from the beginning of the + * packet where the inner payload starts. This value is valid for + * TCP, UDP, FCoE, and RoCE packets. + * A value of zero indicates an offset of 256 bytes. */ - #define SQ_FR_PPMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) - #define SQ_FR_PPMR_NUMLEVELS_LAST SQ_FR_PPMR_NUMLEVELS_LAYER2 - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t pblptr; - /* Local Virtual Address */ - uint64_t va; - /* The data field for FR-PPMR is not used. */ - uint32_t data[24]; -} sq_fr_ppmr_t, *psq_fr_ppmr_t; + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000) + #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 +} cq_res_raweth_qp1_t, *pcq_res_raweth_qp1_t; -/* FR-PPMR SQ WQE header. */ -/* sq_fr_ppmr_hdr (size:256b/32B) */ +/* Responder RawEth and QP1 CQE version 2 */ +/* cq_res_raweth_qp1_v2 (size:256b/32B) */ -typedef struct sq_fr_ppmr_hdr { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; +typedef struct cq_res_raweth_qp1_v2 { + uint16_t length; /* - * FR-PPMR (Fast Register Proxy Physical Memory Region) - * - * Allowed only on reliable connection (RC) SQs. + * The length of the message's payload in bytes, stored in + * the SGEs */ - #define SQ_FR_PPMR_HDR_WQE_TYPE_FR_PPMR UINT32_C(0xf) - #define SQ_FR_PPMR_HDR_WQE_TYPE_LAST SQ_FR_PPMR_HDR_WQE_TYPE_FR_PPMR - uint8_t flags; + #define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0 + uint16_t raweth_qp1_flags; + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK UINT32_C(0x3ff) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0 /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * raweth_qp1_errors. */ - #define SQ_FR_PPMR_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1) /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * This value indicates what the inner packet determined for the + * packet was. */ - #define SQ_FR_PPMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK UINT32_C(0x3c0) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_SFT 6 /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * Not Known: + * Indicates that the packet type was not known. */ - #define SQ_FR_PPMR_HDR_FLAGS_UC_FENCE UINT32_C(0x4) - /* Not Applicable for FR_PPMR. Nothing is sent */ - #define SQ_FR_PPMR_HDR_FLAGS_SE UINT32_C(0x8) - /* NA */ - #define SQ_FR_PPMR_HDR_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6) /* - * This flag is not applicable and should be 0 for a local memory - * operation WQE. + * IP Packet: + * Indicates that the packet was an IP packet, but further + * classification was not possible. */ - #define SQ_FR_PPMR_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (UINT32_C(0x1) << 6) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * TCP Packet: + * Indicates that the packet was IP and TCP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ - #define SQ_FR_PPMR_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 6) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is - * not allowed. + * UDP Packet: + * Indicates that the packet was IP and UDP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ - uint8_t access_cntl; - /* Local Write Access */ - #define SQ_FR_PPMR_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) - /* Remote Read Access */ - #define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) - /* Remote Write Access */ - #define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) - /* Remote Atomic Access */ - #define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) - /* Window Binding Allowed */ - #define SQ_FR_PPMR_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) - uint8_t zero_based_page_size_log; - /* Page size. 0 for 4KB page size, ... to 8TB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_SFT 0 - /* Page size is 4KB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) - /* Page size is 8KB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) - /* Page size is 16KB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) - /* Page size is 32KB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) - /* Page size is 64KB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) - /* Page size is 128KB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) - /* Page size is 256KB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) - /* Page size is 512KB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) - /* Page size is 1MB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) - /* Page size is 2MB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) - /* Page size is 4MB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) - /* Page size is 8MB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) - /* Page size is 16MB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) - /* Page size is 32MB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) - /* Page size is 64MB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) - /* Page size is 128MB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) - /* Page size is 256MB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) - /* Page size is 512MB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) - /* Page size is 1GB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) - /* Page size is 2GB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) - /* Page size is 4GB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) - /* Page size is 8GB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) - /* Page size is 16GB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) - /* Page size is 32GB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) - /* Page size is 64GB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) - /* Page size is 128GB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) - /* Page size is 256GB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) - /* Page size is 512GB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) - /* Page size is 1TB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) - /* Page size is 2TB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) - /* Page size is 4TB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) - /* Page size is 8TB. */ - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) - #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8T - /* Indicate the MR is ZBVA (Zero Base VA) */ - #define SQ_FR_PPMR_HDR_ZERO_BASED UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 6) /* - * Local Key; 24 msb of the key are used to index the MRW - * table, 8 lsb are assigned to the 8 bit key_lsb field in - * the MRWC. + * FCoE Packet: + * Indicates that the packet was recognized as a FCoE. + * This also indicates that the raweth_qp1_payload_offset field + * is valid. */ - uint32_t l_key; - /* Length in bytes of registered MR */ - uint32_t length; - /* Sets the proxy_vfid field of the physical memory region. */ - uint16_t proxy_vfid; - /* Sets the proxy_pfid field of the physical memory region. */ - uint8_t proxy_pfid; - uint8_t numlevels_pbl_page_size_log; - /* PBL page size. 0 for 4KB page size, ... to 8TB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0 - /* Page size is 4KB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) - /* Page size is 8KB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) - /* Page size is 16KB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) - /* Page size is 32KB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) - /* Page size is 64KB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) - /* Page size is 128KB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) - /* Page size is 256KB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) - /* Page size is 512KB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) - /* Page size is 1MB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) - /* Page size is 2MB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) - /* Page size is 4MB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) - /* Page size is 8MB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) - /* Page size is 16MB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) - /* Page size is 32MB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) - /* Page size is 64MB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) - /* Page size is 128MB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) - /* Page size is 256MB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) - /* Page size is 512MB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) - /* Page size is 1GB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) - /* Page size is 2GB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) - /* Page size is 4GB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) - /* Page size is 8GB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) - /* Page size is 16GB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) - /* Page size is 32GB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) - /* Page size is 64GB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) - /* Page size is 128GB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) - /* Page size is 256GB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) - /* Page size is 512GB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) - /* Page size is 1TB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) - /* Page size is 2TB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) - /* Page size is 4TB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) - /* Page size is 8TB. */ - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) - #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T - /* Sets the proxy_vf_valid field of the physical memory region. */ - #define SQ_FR_PPMR_HDR_PROXY_VF_VALID UINT32_C(0x20) - /* Number of levels of PBL for translation */ - #define SQ_FR_PPMR_HDR_NUMLEVELS_MASK UINT32_C(0xc0) - #define SQ_FR_PPMR_HDR_NUMLEVELS_SFT 6 + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 6) /* - * A zero level PBL means that the VA is the physical address used - * for the operation. No translation is done by the PTU. + * RoCE Packet: + * Indicates that the packet was recognized as a RoCE. + * This also indicates that the raweth_qp1_payload_offset field + * is valid. */ - #define SQ_FR_PPMR_HDR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 6) /* - * A one layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PBE values that point to actual pg_size physical pages. + * ICMP Packet: + * Indicates that the packet was recognized as ICMP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ - #define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 6) /* - * A two layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PDE values that in turn point to pbl_pg_size physical pages that contain - * PBE values that point to actual physical pages. + * PtP packet wo/timestamp: + * Indicates that the packet was recognized as a PtP + * packet. */ - #define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) - #define SQ_FR_PPMR_HDR_NUMLEVELS_LAST SQ_FR_PPMR_HDR_NUMLEVELS_LAYER2 - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t pblptr; - /* Local Virtual Address */ - uint64_t va; -} sq_fr_ppmr_hdr_t, *psq_fr_ppmr_hdr_t; - -/* - * Bind SQ WQE. This WQE can perform either: - * * type1 "bind memory window", if mw_type==Type1 - * * type2 "post send bind memory window", if mw_type==Type2 - */ -/* sq_bind (size:1024b/128B) */ - -typedef struct sq_bind { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6) /* - * Memory Bind - * - * Allowed only on reliable connection (RC) SQs. + * PtP packet w/timestamp: + * Indicates that the packet was recognized as a PtP + * packet and that a timestamp was taken for the packet. */ - #define SQ_BIND_WQE_TYPE_BIND UINT32_C(0xe) - #define SQ_BIND_WQE_TYPE_LAST SQ_BIND_WQE_TYPE_BIND - uint8_t flags; - #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP + uint16_t raweth_qp1_errors; /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * This indicates that there was an error in the IP header + * checksum. */ - #define SQ_BIND_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10) /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * This indicates that there was an error in the TCP, UDP + * or ICMP checksum. */ - #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20) /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * This indicates that there was an error in the tunnel + * IP header checksum. */ - #define SQ_BIND_FLAGS_UC_FENCE UINT32_C(0x4) - /* NA, nothing is sent. */ - #define SQ_BIND_FLAGS_SE UINT32_C(0x8) - /* NA */ - #define SQ_BIND_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40) /* - * This flag is not applicable and should be 0 for a local memory - * operation WQE. + * This indicates that there was an error in the tunnel + * UDP checksum. */ - #define SQ_BIND_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * This indicates that there was a CRC error on either an FCoE + * or RoCE packet. The itype indicates the packet type. */ - #define SQ_BIND_FLAGS_DEBUG_TRACE UINT32_C(0x40) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is - * not allowed. + * This indicates that there was an error in the tunnel + * portion of the packet when this + * field is non-zero. */ - uint8_t access_cntl; - #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK UINT32_C(0xff) - #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0 + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 /* - * Local Write Access. - * - * Local accesses are never allowed for memory windows, so this - * bit must always be zero in a bind WQE. If this bit is ever - * set, the bind will fail with an errored completion. + * No additional error occurred on the tunnel portion + * of the packet of the packet does not have a tunnel. */ - #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) - /* Remote Read Access */ - #define SQ_BIND_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9) /* - * Remote Write Access. - * - * Note that, if this bit is set, then the parent region to which - * the window is being bound must allow local writes. If this is not - * the case, then the bind will fail with an errored completion. + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 + * in the tunnel header. */ - #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9) /* - * Remote Atomic Access. - * - * Note that, if this bit is set, then the parent region to which - * the window is being bound must allow local writes. If this is not - * the case, then the bind will fail with an errored completion. + * Indicates that header length is out of range in the + * tunnel header. Valid for + * IPv4. */ - #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9) /* - * Window Binding Allowed. - * - * It is never allowed to bind windows to windows, so this bit - * must always be zero in a bind WQE. If this bit is ever set, - * the bind will fail with an errored completion. + * Indicates that the physical packet is shorter than that + * claimed by the PPPoE header length for a tunnel PPPoE + * packet. */ - #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) - /* reserved8_1 is 8 b */ - uint8_t reserved8_1; - uint8_t mw_type_zero_based; + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9) /* - * If this bit is set, then the newly-bound memory window will be - * zero-based. If clear, then the newly-bound memory window will be - * non-zero-based. + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 + * tunnel packet packets. */ - #define SQ_BIND_ZERO_BASED UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9) /* - * If type1 is specified, then this WQE performs a "bind memory window" - * operation on a type1 window. If type2 is specified, then this WQE - * performs a "post send bind memory window" operation on a type2 - * window. - * - * Note that the bind WQE cannot change the type of the memory window. - * - * If a "bind memory window" operation is attempted on a memory window - * that was allocated as type2, then the bind will fail with an errored - * completion, as "bind memory window" is allowed only on type1 memory - * windows. - * - * Similarly, if a "post send bind memory window" operation is attempted - * on a memory window that was allocated as type1, then the bind will fail - * with an errored completions, as "post send bind memory window" is allowed - * only on type2 memory windows. + * Indicates that the physical packet is shorter than that + * claimed by the tunnel UDP header length for a tunnel + * UDP packet that is not fragmented. */ - #define SQ_BIND_MW_TYPE UINT32_C(0x2) - /* Type 1 Bind Memory Window */ - #define SQ_BIND_MW_TYPE_TYPE1 (UINT32_C(0x0) << 1) - /* Type 2 Post Send Bind Memory Window */ - #define SQ_BIND_MW_TYPE_TYPE2 (UINT32_C(0x1) << 1) - #define SQ_BIND_MW_TYPE_LAST SQ_BIND_MW_TYPE_TYPE2 - uint8_t reserved8_2; - uint16_t reserved16; + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9) /* - * The L_Key of the parent MR; 24 msb of the key are used to - * index the MRW table, 8 lsb are compared with the 8 bit key - * in the MRWC. + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0) in the tunnel header. Valid + * for IPv4, and IPv6. */ - uint32_t parent_l_key; + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL /* - * Local Key; 24 msb of the key are used to index the memory - * window being bound in the MRW table, 8 lsb are assign to the - * 8 bit key_lsb field in the MRWC. + * This indicates that there was an error in the inner + * portion of the packet when this + * field is non-zero. */ - uint32_t l_key; - /* Local Virtual Address */ - uint64_t va; + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 /* - * Length in bytes of registered MW; 40 bits as this is the max - * size of an MR/W + * No additional error occurred on the tunnel portion + * of the packet of the packet does not have a tunnel. */ - uint8_t length[5]; - uint8_t reserved24[3]; - /* The data field for Bind is not used. */ - uint32_t data[24]; -} sq_bind_t, *psq_bind_t; - -/* - * Bind SQ WQE header. This WQE can perform either: - * * type1 "bind memory window", if mw_type==Type1 - * * type2 "post send bind memory window", if mw_type==Type2 - */ -/* sq_bind_hdr (size:256b/32B) */ - -typedef struct sq_bind_hdr { - /* This field defines the type of SQ WQE. */ - uint8_t wqe_type; + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12) /* - * Memory Bind - * - * Allowed only on reliable connection (RC) SQs. + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 or that + * option other than VFT was parsed on + * FCoE packet. + */ + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12) + /* + * indicates that header length is out of range. Valid for + * IPv4 and RoCE + */ + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12) + /* + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 + */ + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12) + /* + * Indicates that physical packet is shorter than that + * claimed by the l3 header length. Valid for IPv4, + * IPv6 packet or RoCE packets. + */ + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12) + /* + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is + * not fragmented. + */ + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12) + /* + * Indicates that TCP header length > IP payload. Valid for + * TCP packets only. */ - #define SQ_BIND_HDR_WQE_TYPE_BIND UINT32_C(0xe) - #define SQ_BIND_HDR_WQE_TYPE_LAST SQ_BIND_HDR_WQE_TYPE_BIND - uint8_t flags; - #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff) - #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0 + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12) /* - * Set if completion signaling is requested. If this bit is - * 0, and the SQ is configured to support Unsignaled - * completion the controller should not generate a CQE - * unless there was an error. This refers to CQE on the - * sender side (se_flag refers to the receiver side) + * Indicates that TCP option headers result in a TCP header + * size that does not match data offset in TCP header. Valid + * for TCP. */ - #define SQ_BIND_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN + /* This is data from the CFA as indicated by the meta_format field. */ + uint16_t cfa_metadata0; + /* When meta_format=1, this value is the VLAN VID. */ + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff) + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000) + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_SFT 13 /* - * Indication to complete all previous RDMA Read or Atomic - * WQEs on the SQ before executing this WQE + * This is an application level ID used to identify the + * QP and its SQ and RQ. */ - #define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + uint64_t qp_handle; + uint32_t raweth_qp1_flags2; /* - * Unconditional fence. Indication to complete all previous - * SQ's WQEs before executing this WQE. + * When this bit is '0', the cs_ok field has the following + * definition:- ip_cs_ok[2:0] = The number of header groups with a + * valid IP checksum in the delivered packet, counted from the + * outer-most header group to the inner-most header group, stopping + * at the first error. - l4_cs_ok[5:3] = The number of header groups + * with a valid L4 checksum in the delivered packet, counted from + * the outer-most header group to the inner-most header group, + * stopping at the first error. When this bit is '1', the cs_ok + * field has the following definition: - hdr_cnt[2:0] = The number of + * header groups that were parsed by the chip and passed in the + * delivered packet. - ip_cs_all_ok[3] =This bit will be '1' if all + * the parsed header groups with an IP checksum are valid. + * - l4_cs_all_ok[4] = This bit will be '1' if all the parsed header + * groups with an L4 checksum are valid. */ - #define SQ_BIND_HDR_FLAGS_UC_FENCE UINT32_C(0x4) - /* NA, nothing is sent. */ - #define SQ_BIND_HDR_FLAGS_SE UINT32_C(0x8) - /* NA */ - #define SQ_BIND_HDR_FLAGS_INLINE UINT32_C(0x10) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4) /* - * This flag is not applicable and should be 0 for a local memory - * operation WQE. + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. */ - #define SQ_BIND_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4) /* - * When set to '1', this operation will cause a trace capture in - * each block it passes through. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. i + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - #define SQ_BIND_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is - * not allowed. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). */ - uint8_t access_cntl; - #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK UINT32_C(0xff) - #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0 + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4) /* - * Local Write Access. - * - * Local accesses are never allowed for memory windows, so this - * bit must always be zero in a bind WQE. If this bit is ever - * set, the bind will fail with an errored completion. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. */ - #define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) - /* Remote Read Access */ - #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET /* - * Remote Write Access. - * - * Note that, if this bit is set, then the parent region to which - * the window is being bound must allow local writes. If this is not - * the case, then the bind will fail with an errored completion. + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. */ - #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100) /* - * Remote Atomic Access. - * - * Note that, if this bit is set, then the parent region to which - * the window is being bound must allow local writes. If this is not - * the case, then the bind will fail with an errored completion. + * This indicates that the complete 1's complement checksum was + * calculated for the packet. */ - #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200) /* - * Window Binding Allowed. - * - * It is never allowed to bind windows to windows, so this bit - * must always be zero in a bind WQE. If this bit is ever set, - * the bind will fail with an errored completion. + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. */ - #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) - /* reserved8_1 is 8 b */ - uint8_t reserved8_1; - uint8_t mw_type_zero_based; + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK UINT32_C(0xfc00) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_SFT 10 /* - * If this bit is set, then the newly-bound memory window will be - * zero-based. If clear, then the newly-bound memory window will be - * non-zero-based. + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. */ - #define SQ_BIND_HDR_ZERO_BASED UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 /* - * If type1 is specified, then this WQE performs a "bind memory window" - * operation on a type1 window. If type2 is specified, then this WQE - * performs a "post send bind memory window" operation on a type2 - * window. - * - * Note that the bind WQE cannot change the type of the memory window. - * - * If a "bind memory window" operation is attempted on a memory window - * that was allocated as type2, then the bind will fail with an errored - * completion, as "bind memory window" is allowed only on type1 memory - * windows. - * - * Similarly, if a "post send bind memory window" operation is attempted - * on a memory window that was allocated as type1, then the bind will fail - * with an errored completions, as "post send bind memory window" is allowed - * only on type2 memory windows. + * This is data from the CFA block as indicated by the meta_format + * field. + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + * When vee_cmpl_mode is set in VNIC context, this is the upper 32b + * of the host address from the first BD used to place the packet. */ - #define SQ_BIND_HDR_MW_TYPE UINT32_C(0x2) - /* Type 1 Bind Memory Window */ - #define SQ_BIND_HDR_MW_TYPE_TYPE1 (UINT32_C(0x0) << 1) - /* Type 2 Post Send Bind Memory Window */ - #define SQ_BIND_HDR_MW_TYPE_TYPE2 (UINT32_C(0x1) << 1) - #define SQ_BIND_HDR_MW_TYPE_LAST SQ_BIND_HDR_MW_TYPE_TYPE2 - uint8_t reserved8_2; - uint16_t reserved16; + uint32_t cfa_metadata2; + uint8_t cqe_type_toggle; /* - * The L_Key of the parent MR; 24 msb of the key are used to - * index the MRW table, 8 lsb are compared with the 8 bit key - * in the MRWC. + * Indicate valid completion - written by the chip. Cumulus + * toggle this bit each time it finished consuming all PBL + * entries */ - uint32_t parent_l_key; + #define CQ_RES_RAWETH_QP1_V2_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1 /* - * Local Key; 24 msb of the key are used to index the memory - * window being bound in the MRW table, 8 lsb are assign to the - * 8 bit key_lsb field in the MRWC. + * Responder RawEth and QP1 Completion - This is used for RQ + * completion for RawEth service and QP1 service QPs. */ - uint32_t l_key; - /* Local Virtual Address */ - uint64_t va; + #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1) + #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 + /* This field indicates the status for the CQE. */ + uint8_t status; /* - * Length in bytes of registered MW; 40 bits as this is the max - * size of an MR/W + * This indicates that the completion is without error. + * All fields are valid. */ - uint8_t length[5]; - uint8_t reserved24[3]; -} sq_bind_hdr_t, *psq_bind_hdr_t; - -/* RQ/SRQ WQE */ -/* rq_wqe (size:1024b/128B) */ - -typedef struct rq_wqe { - /* wqe_type is 8 b */ - uint8_t wqe_type; + #define CQ_RES_RAWETH_QP1_V2_STATUS_OK UINT32_C(0x0) /* - * RQ/SRQ WQE. This WQE is used for posting buffers on - * an RQ or SRQ. + * This indicates that write access was not allowed for + * at least one of the SGEs in the WQE. + * + * This is a fatal error. Only the srq_or_rq_wr_id is field + * is valid. */ - #define RQ_WQE_WQE_TYPE_RCV UINT32_C(0x80) - #define RQ_WQE_WQE_TYPE_LAST RQ_WQE_WQE_TYPE_RCV - /* No flags supported for this WQE type. */ - uint8_t flags; + #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) /* - * Specify the total number 16B chunks that make up the valid - * portion of the WQE. This includes the first chunk that is the - * WQE structure and up to 6 SGE structures. + * This indicates that the packet was too long for the WQE + * provided on the RQ. * - * While the valid area is defined by the wqe_size field, the - * actual WQE size is fixed at 128B. + * This is not a fatal error. All the fields are valid. */ - uint8_t wqe_size; - uint8_t reserved8; - uint32_t reserved32; - uint64_t wr_id; + #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* LOCAL_PROTECTION_ERR is 3 */ + #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) + /* LOCAL_QP_OPERATION_ERR is 4 */ + #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* MEMORY_MGT_OPERATION_ERR is 5 */ + #define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) + /* WORK_REQUEST_FLUSHED_ERR is 7 */ + #define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) + /* HW_FLUSH_ERR is 8 */ + #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8) + #define CQ_RES_RAWETH_QP1_V2_STATUS_LAST CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR + uint16_t flags; /* - * Opaque value used by upper layer SW to identify the id of the - * WR which generated the WQE. Used in CQE. Valid in the first - * SGE of an SRQ WQE. + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. */ - #define RQ_WQE_WR_ID_MASK UINT32_C(0xfffff) - #define RQ_WQE_WR_ID_SFT 0 - uint8_t reserved128[16]; + #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ + uint32_t raweth_qp1_payload_offset_srq_or_rq_wr_id; /* - * The data field for RQ WQE is filled with from 1 to 6 SGE - * structures as defined by the wqe_size field. + * Opaque value from RQ or SRQ WQE. Used by driver/lib to + * reference the WQE in order to claim the received data + * and reuse the WQE space */ - uint32_t data[24]; -} rq_wqe_t, *prq_wqe_t; + #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) + #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0 + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK UINT32_C(0xf00000) + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_SFT 20 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000) + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_SFT 20 + /* 0x88a8 */ + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20) + /* 0x8100 */ + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20) + /* 0x9100 */ + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20) + /* 0x9200 */ + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20) + /* 0x9300 */ + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20) + /* Value programmed in CFA VLANTPID register. */ + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20) + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG + /* When meta_format != 0, this value is the VLAN valid. */ + #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID UINT32_C(0x800000) + /* + * This value indicates the offset in bytes from the beginning of + * the packet where the inner payload starts. This value is valid + * for TCP, UDP, FCoE, and RoCE packets. + * + * A value of zero indicates an offset of 256 bytes. + */ + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000) + #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 +} cq_res_raweth_qp1_v2_t, *pcq_res_raweth_qp1_v2_t; -/* RQ/SRQ WQE header. */ -/* rq_wqe_hdr (size:256b/32B) */ +/* + * This is the terminal CQE structure. This CQE is generated to + * indicate that no further completions will be generated for this QP. + */ +/* cq_terminal (size:256b/32B) */ -typedef struct rq_wqe_hdr { - /* wqe_type is 8 b */ - uint8_t wqe_type; +typedef struct cq_terminal { /* - * RQ/SRQ WQE. This WQE is used for posting buffers on - * an RQ or SRQ. + * This is an application level ID used to identify the + * QP and its SQ and RQ. */ - #define RQ_WQE_HDR_WQE_TYPE_RCV UINT32_C(0x80) - #define RQ_WQE_HDR_WQE_TYPE_LAST RQ_WQE_HDR_WQE_TYPE_RCV - /* No flags supported for this WQE type. */ - uint8_t flags; + uint64_t qp_handle; /* - * Specify the total number 16B chunks that make up the valid - * portion of the WQE. This includes the first chunk that is the - * WQE structure and up to 6 SGE structures. - * - * While the valid area is defined by the wqe_size field, the - * actual WQE size is fixed at 128B. + * Final SQ Consumer Index value. Any additional SQ WQEs will + * have to be completed by the user provider. */ - uint8_t wqe_size; - uint8_t reserved8; - uint32_t reserved32; - uint64_t wr_id; + uint16_t sq_cons_idx; /* - * Opaque value used by upper layer SW to identify the id of the - * WR which generated the WQE. Used in CQE. Valid in the first - * SGE of an SRQ WQE. + * Final RQ Consumer Index value. Any additional RQ WQEs will + * have to be completed by the user provider. */ - #define RQ_WQE_HDR_WR_ID_MASK UINT32_C(0xfffff) - #define RQ_WQE_HDR_WR_ID_SFT 0 - uint8_t reserved128[16]; -} rq_wqe_hdr_t, *prq_wqe_hdr_t; - -/* cq_base (size:256b/32B) */ - -typedef struct cq_base { - uint64_t reserved64_1; - uint64_t reserved64_2; + uint16_t rq_cons_idx; + uint32_t reserved32_1; uint64_t reserved64_3; uint8_t cqe_type_toggle; /* @@ -72728,59 +85117,112 @@ * toggle this bit each time it finished consuming all PBL * entries */ - #define CQ_BASE_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_BASE_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_BASE_CQE_TYPE_SFT 1 - /* - * Requester completion - This is used for both RC and UD SQ - * completions. - */ - #define CQ_BASE_CQE_TYPE_REQ (UINT32_C(0x0) << 1) - /* - * Responder RC Completion - This is used for both RQ and SRQ - * completions for RC service QPs. - */ - #define CQ_BASE_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1) + #define CQ_TERMINAL_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_TERMINAL_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_TERMINAL_CQE_TYPE_SFT 1 /* - * Responder UD Completion - This is used for both RQ and SRQ - * completion for UD service QPs. + * Terminal completion - This is used to indicate that no + * further completions will be made for this QP on this CQ. */ - #define CQ_BASE_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1) + #define CQ_TERMINAL_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1) + #define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL + /* This field indicates the status for the CQE. */ + uint8_t status; + /* The operation completed successfully. */ + #define CQ_TERMINAL_STATUS_OK UINT32_C(0x0) + #define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK + uint16_t reserved16; + uint32_t reserved32_2; +} cq_terminal_t, *pcq_terminal_t; + +/* Cutoff CQE */ +/* cq_cutoff (size:256b/32B) */ + +typedef struct cq_cutoff { + uint64_t reserved64_1; + uint64_t reserved64_2; + uint64_t reserved64_3; + uint8_t cqe_type_toggle; /* - * Responder RawEth and QP1 Completion - This is used for RQ - * completion for RawEth service and QP1 service QPs. + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries */ - #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1) + #define CQ_CUTOFF_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_CUTOFF_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_CUTOFF_CQE_TYPE_SFT 1 + /* Cut off CQE; for CQ resize see CQ and SRQ Resize */ + #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1) + #define CQ_CUTOFF_CQE_TYPE_LAST CQ_CUTOFF_CQE_TYPE_CUT_OFF /* - * Responder UD completion with CFA. This is used for both RQ - * and SQ completion for UD service QPs. It includes cfa fields - * (some of which carry VLAN information), in place of QP handle. + * This field carries the toggle value that must be used to + * acknowledge this CQ resize operation. When this CQE is + * processed, the driver should send a CQ_CUTOFF_ACK doorbell + * to the chip to let the chip know that the resize operation + * is complete. + * + * This value is used by HW to detect old and + * stale CQ_CUTOFF_ACK doorbells that are caused by having + * a backup doorbell location or by PCI or other reordering + * problems. Only doorbells with the latest value will be honored. + * This field is needed only for devices that use the hardware + * based doorbell drop recovery feature. */ - #define CQ_BASE_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1) + #define CQ_CUTOFF_RESIZE_TOGGLE_MASK UINT32_C(0x60) + #define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5 + /* This field indicates the status for the CQE. */ + uint8_t status; + /* The operation completed successfully. */ + #define CQ_CUTOFF_STATUS_OK UINT32_C(0x0) + #define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK + uint16_t reserved16; + uint32_t reserved32; +} cq_cutoff_t, *pcq_cutoff_t; + +/* No-Op CQE */ +/* cq_no_op (size:256b/32B) */ + +typedef struct cq_no_op { + uint64_t reserved64_1; + uint64_t reserved64_2; + uint64_t reserved64_3; + uint8_t cqe_type_toggle; /* - * NO_OP completion - This is used to indicate that no - * operation completion. + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries. */ - #define CQ_BASE_CQE_TYPE_NO_OP (UINT32_C(0xd) << 1) + #define CQ_NO_OP_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_NO_OP_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_NO_OP_CQE_TYPE_SFT 1 /* - * Terminal completion - This is used to indicate that no - * further completions will be made for this QP on this CQ. + * NO-OP completion - This is used to indicate that no operation + * completed. */ - #define CQ_BASE_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1) - /* Cut off CQE; for CQ resize see CQ and SRQ Resize */ - #define CQ_BASE_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1) - #define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF + #define CQ_NO_OP_CQE_TYPE_NO_OP (UINT32_C(0xd) << 1) + #define CQ_NO_OP_CQE_TYPE_LAST CQ_NO_OP_CQE_TYPE_NO_OP /* This field indicates the status for the CQE. */ uint8_t status; + /* The operation completed successfully. */ + #define CQ_NO_OP_STATUS_OK UINT32_C(0x0) + #define CQ_NO_OP_STATUS_LAST CQ_NO_OP_STATUS_OK uint16_t reserved16; uint32_t reserved32; -} cq_base_t, *pcq_base_t; +} cq_no_op_t, *pcq_no_op_t; -/* Requester CQ CQE */ -/* cq_req (size:256b/32B) */ +/* + * This is the Requester CQE V3 structure. This is used to complete each + * signaled SQ WQE. The sq_cons_idx and opaque is used to indicate + * which WQE has been completed. When a WQE is completed, it indicates + * that all WQEs before it in the SQ are also completed without error. + * Space freed by completed WQEs can be used for new WQEs. + */ +/* cq_req_v3 (size:256b/32B) */ -typedef struct cq_req { +typedef struct cq_req_v3 { /* * This is an application level ID used to identify the * QP and its SQ and RQ. @@ -72788,76 +85230,182 @@ uint64_t qp_handle; /* * SQ Consumer Index - points to the entry just past the last WQE - * that has been completed by the chip. Wraps around at - * QPC.sq_size (i.e. the valid range of the SQ Consumer Index is 0 - * to (QPC.sq_size - 1)). + * that has been completed by the chip. Wraps around at QPC.sq_size + * (i.e. the valid range of the SQ Consumer Index is 0 to + * (QPC.sq_size - 1)). The sq_cons_idx is in 16B units (as is + * QPC.sq_size). + * + * User can determine available space in the SQ by comparing + * sq_cons_idx to a sq_prod_idx maintained by the user. When the two + * values are equal, the SQ is empty. When + * (sq_prod_idx+1)%QPC.sq_size==sq_cons_idx, the queue is full. */ uint16_t sq_cons_idx; - uint16_t reserved16_1; - uint32_t reserved32_2; - uint64_t reserved64; + uint16_t reserved1; + uint32_t reserved2; + uint64_t reserved3; uint8_t cqe_type_toggle; /* - * Indicate valid completion - written by the chip. Cumulus - * toggle this bit each time it finished consuming all PBL - * entries + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries. */ - #define CQ_REQ_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_REQ_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_REQ_CQE_TYPE_SFT 1 + #define CQ_REQ_V3_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_REQ_V3_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_REQ_V3_CQE_TYPE_SFT 1 /* - * Requester completion - This is used for both RC and UD SQ + * Requester completion V3 - This is used for both RC and UD SQ * completions. */ - #define CQ_REQ_CQE_TYPE_REQ (UINT32_C(0x0) << 1) - #define CQ_REQ_CQE_TYPE_LAST CQ_REQ_CQE_TYPE_REQ + #define CQ_REQ_V3_CQE_TYPE_REQ_V3 (UINT32_C(0x8) << 1) + #define CQ_REQ_V3_CQE_TYPE_LAST CQ_REQ_V3_CQE_TYPE_REQ_V3 /* * When this bit is '1', it indicates that the packet completed * was transmitted using the push accelerated data provided by * the driver. When this bit is '0', it indicates that the packet * had not push acceleration data written or was executed as a * normal packet even though push data was provided. - * This field is intended to be used for driver-generated push - * statistics. It is not applicable for RC since not all RC packets - * return a CQE. + * + * Note: This field is intended to be used for driver-generated push + * statistics. As such, It is not applicable for RC since not all + * RC packets return a CQE. */ - #define CQ_REQ_PUSH UINT32_C(0x20) + #define CQ_REQ_V3_PUSH UINT32_C(0x20) /* This field indicates the status for the CQE. */ uint8_t status; - /* OK is 0 */ - #define CQ_REQ_STATUS_OK UINT32_C(0x0) - /* BAD_RESPONSE_ERR is 1 */ - #define CQ_REQ_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1) - /* LOCAL_LENGTH_ERR is 2 */ - #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2) - /* LOCAL_QP_OPERATION_ERR is 3 */ - #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x3) - /* LOCAL_PROTECTION_ERR is 4 */ - #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x4) - /* MEMORY_MGT_OPERATION_ERR is 5 */ - #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) - /* REMOTE_INVALID_REQUEST_ERR is 6 */ - #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6) - /* REMOTE_ACCESS_ERR is 7 */ - #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x7) - /* REMOTE_OPERATION_ERR is 8 */ - #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR UINT32_C(0x8) - /* RNR_NAK_RETRY_CNT_ERR is 9 */ - #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0x9) - /* TRANSPORT_RETRY_CNT_ERR is 10 */ - #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xa) - /* WORK_REQUEST_FLUSHED_ERR is 11 */ - #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xb) - #define CQ_REQ_STATUS_LAST CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR - uint16_t reserved16_2; - uint32_t reserved32_1; -} cq_req_t, *pcq_req_t; + /* The operation completed successfully. */ + #define CQ_REQ_V3_STATUS_OK UINT32_C(0x0) + /* + * An unexpected BTH opcode or a First/Middle packet that is not + * the full MTU size was returned by the responder. + * + * This is a fatal error detected by the requester Rx. + */ + #define CQ_REQ_V3_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1) + /* + * Generated for a WQE posted to the local SQ when the sum of the + * lengths of the SGEs in the WQE exceeds the maximum message + * length of 2^31 bytes. + * + * Generated for a WQE posted to the local RQ/SRQ when the sum of + * the lengths of the SGEs in the WQE is too small to receive the + * (valid) incoming message or the length of the incoming message + * is greater than the maximum message size supported. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_REQ_V3_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_REQ_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_REQ_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) + /* + * The SSC detected an error on a local memory operation from the + * SQ (fast-register, local invalidate, or bind). + * + * This is a fatal error detected by the requester Tx. + */ + #define CQ_REQ_V3_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x7) + /* + * An invalid message was received by the responder. This could be + * an operation that is not supported by this QP, an IRRQ overflow + * error, or the length in an RDMA operation is greater than the + * maximum message size (2^31 bytes). + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Invalid Request. For responder + * CQEs, only the opaque field is valid. + */ + #define CQ_REQ_V3_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8) + /* + * A protection error occurred on a remote data buffer to be read + * by an RDMA Read, written by an RDMA Write or accessed by an + * atomic operation. This error is reported only on RDMA operations + * or atomic operations. + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Remote Access Violation. + */ + #define CQ_REQ_V3_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x9) + /* + * The operation could not be completed successfully by the + * responder. Possible causes include an RQ/SRQ WQE format error, + * an SSC error when validating an SGE from an RQ/SRQ WQE, or the + * message received was too long for the RQ/SRQ WQE. + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Remote Operation Error. + */ + #define CQ_REQ_V3_STATUS_REMOTE_OPERATION_ERR UINT32_C(0xa) + /* + * The RNR NAK retry count was exceeded while trying to send this + * message. + * + * This is a fatal error detected by the requester. + */ + #define CQ_REQ_V3_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0xb) + /* + * The local transport timeout retry counter was exceeded while + * trying to send this message. + * + * This is a fatal error detected by the requester. + */ + #define CQ_REQ_V3_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xc) + /* + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. + */ + #define CQ_REQ_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) + /* + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. + */ + #define CQ_REQ_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_REQ_V3_STATUS_LAST CQ_REQ_V3_STATUS_OVERFLOW_ERR + uint16_t reserved4; + /* This value is from the WQE that is being completed. */ + uint32_t opaque; +} cq_req_v3_t, *pcq_req_v3_t; -/* Responder RC CQE */ -/* cq_res_rc (size:256b/32B) */ +/* + * This is the Responder RQ/SRQ CQE V3 structure for RC QPs. This is + * used to complete each RQ/SRQ WQE. When the WQE is completed, it + * indicates that there is room for one more WQE on the corresponding + * RQ/SRQ. + * + * User can determine available space in the RQ/SRQ by comparing + * a rq_cons_idx to a rq_prod_idx, both maintained by the user. The + * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The + * rq_prod_idx value increments by one for each WQE that is added to + * the RQ/SRQ by the user. Value must be wrapped at rq_size. The + * rq_cons_idx value increments by one for each WQE that is completed + * from that particular RQ/SRQ. The qp_handle can be used by the user + * to determine what RQ/SRQ to increment. Value must also be wrapped at + * rq_size. When the two values are equal, the RQ/SRQ is empty. When + * (rq_prod_idx+1)%QPC.rq_size==rq_cons_idx, the queue is full. + */ +/* cq_res_rc_v3 (size:256b/32B) */ -typedef struct cq_res_rc { +typedef struct cq_res_rc_v3 { /* * The length of the message's payload in bytes, stored in * the SGEs @@ -72883,96 +85431,151 @@ uint64_t mr_handle; uint8_t cqe_type_toggle; /* - * Indicate valid completion - written by the chip. Cumulus - * toggle this bit each time it finished consuming all PBL - * entries + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries. */ - #define CQ_RES_RC_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_RES_RC_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_RES_RC_CQE_TYPE_SFT 1 + #define CQ_RES_RC_V3_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_RC_V3_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_RC_V3_CQE_TYPE_SFT 1 /* * Responder RC Completion - This is used for both RQ and SRQ * completions for RC service QPs. */ - #define CQ_RES_RC_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1) - #define CQ_RES_RC_CQE_TYPE_LAST CQ_RES_RC_CQE_TYPE_RES_RC + #define CQ_RES_RC_V3_CQE_TYPE_RES_RC_V3 (UINT32_C(0x9) << 1) + #define CQ_RES_RC_V3_CQE_TYPE_LAST CQ_RES_RC_V3_CQE_TYPE_RES_RC_V3 /* This field indicates the status for the CQE. */ uint8_t status; - /* OK is 0 */ - #define CQ_RES_RC_STATUS_OK UINT32_C(0x0) - /* LOCAL_ACCESS_ERROR is 1 */ - #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) - /* LOCAL_LENGTH_ERR is 2 */ - #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2) - /* LOCAL_PROTECTION_ERR is 3 */ - #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) - /* LOCAL_QP_OPERATION_ERR is 4 */ - #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) - /* MEMORY_MGT_OPERATION_ERR is 5 */ - #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) - /* REMOTE_INVALID_REQUEST_ERR is 6 */ - #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6) - /* WORK_REQUEST_FLUSHED_ERR is 7 */ - #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) - /* HW_FLUSH_ERR is 8 */ - #define CQ_RES_RC_STATUS_HW_FLUSH_ERR UINT32_C(0x8) - #define CQ_RES_RC_STATUS_LAST CQ_RES_RC_STATUS_HW_FLUSH_ERR + /* The operation completed successfully. */ + #define CQ_RES_RC_V3_STATUS_OK UINT32_C(0x0) + /* + * Generated for a WQE posted to the local SQ when the sum of the + * lengths of the SGEs in the WQE exceeds the maximum message + * length of 2^31 bytes. + * + * Generated for a WQE posted to the local RQ/SRQ when the sum of + * the lengths of the SGEs in the WQE is too small to receive the + * (valid) incoming message or the length of the incoming message + * is greater than the maximum message size supported. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_RC_V3_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_RC_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_RC_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) + /* + * A protection error occurred on a local data buffer during the + * processing of a RDMA Write with Immediate Data operation sent + * from the remote node. + * + * This is a fatal error detected by the responder Rx. Only the + * opaque field in the CQE is valid. + */ + #define CQ_RES_RC_V3_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x6) + /* + * An invalid message was received by the responder. This could be + * an operation that is not supported by this QP, an IRRQ overflow + * error, or the length in an RDMA operation is greater than the + * maximum message size (2^31 bytes). + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Invalid Request. For responder + * CQEs, only the opaque field is valid. + */ + #define CQ_RES_RC_V3_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8) + /* + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. + */ + #define CQ_RES_RC_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) + /* + * A WQE had already been taken off the RQ/SRQ when a fatal error + * was detected on responder Rx. Only the opaque field in the CQE + * is valid. + */ + #define CQ_RES_RC_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe) + /* + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. + */ + #define CQ_RES_RC_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_RES_RC_V3_STATUS_LAST CQ_RES_RC_V3_STATUS_OVERFLOW_ERR uint16_t flags; /* * This flag indicates that the completion is for a SRQ entry * rather than for an RQ entry. */ - #define CQ_RES_RC_FLAGS_SRQ UINT32_C(0x1) + #define CQ_RES_RC_V3_FLAGS_SRQ UINT32_C(0x1) /* CQE relates to RQ WQE. */ - #define CQ_RES_RC_FLAGS_SRQ_RQ UINT32_C(0x0) + #define CQ_RES_RC_V3_FLAGS_SRQ_RQ UINT32_C(0x0) /* CQE relates to SRQ WQE. */ - #define CQ_RES_RC_FLAGS_SRQ_SRQ UINT32_C(0x1) - #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ + #define CQ_RES_RC_V3_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_RC_V3_FLAGS_SRQ_LAST CQ_RES_RC_V3_FLAGS_SRQ_SRQ /* Immediate data indicator */ - #define CQ_RES_RC_FLAGS_IMM UINT32_C(0x2) + #define CQ_RES_RC_V3_FLAGS_IMM UINT32_C(0x2) /* R_Key invalidate indicator */ - #define CQ_RES_RC_FLAGS_INV UINT32_C(0x4) - #define CQ_RES_RC_FLAGS_RDMA UINT32_C(0x8) + #define CQ_RES_RC_V3_FLAGS_INV UINT32_C(0x4) + #define CQ_RES_RC_V3_FLAGS_RDMA UINT32_C(0x8) /* CQE relates to an incoming Send request */ - #define CQ_RES_RC_FLAGS_RDMA_SEND (UINT32_C(0x0) << 3) + #define CQ_RES_RC_V3_FLAGS_RDMA_SEND (UINT32_C(0x0) << 3) /* CQE relates to incoming RDMA Write request */ - #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (UINT32_C(0x1) << 3) - #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE - uint32_t srq_or_rq_wr_id; - /* - * Opaque value from RQ or SRQ WQE. Used by driver/lib to - * reference the WQE in order to claim the received data - * and reuse the WQE space - */ - #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) - #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0 -} cq_res_rc_t, *pcq_res_rc_t; + #define CQ_RES_RC_V3_FLAGS_RDMA_RDMA_WRITE (UINT32_C(0x1) << 3) + #define CQ_RES_RC_V3_FLAGS_RDMA_LAST CQ_RES_RC_V3_FLAGS_RDMA_RDMA_WRITE + /* This value is from the WQE that is being completed. */ + uint32_t opaque; +} cq_res_rc_v3_t, *pcq_res_rc_v3_t; -/* Responder UD CQE */ -/* cq_res_ud (size:256b/32B) */ +/* + * This is the Responder RQ/SRQ CQE V3 structure for UD QPs and QP1 QPs + * that are treated as UD. This is used to complete RQ/SRQ WQE's. When + * the WQE is completed, it indicates that there is room for one more + * WQE on the corresponding RQ/SRQ. + * + * User can determine available space in the RQ/SRQ by comparing + * a rq_cons_idx to a rq_prod_idx, both maintained by the user. The + * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The + * rq_prod_idx value increments by one for each WQE that is added to + * the RQ/SRQ by the user. Value must be wrapped at rq_size. The + * rq_cons_idx value increments by one for each WQE that is completed + * from that particular RQ/SRQ. The qp_handle can be used by the user + * to determine what RQ/SRQ to increment. Value must also be wrapped at + * rq_size. When the two values are equal, the RQ/SRQ is empty. When + * (rq_prod_idx+1)%QPC.rq_size==rq_cons_idx, the queue is full. + */ +/* cq_res_ud_v3 (size:256b/32B) */ -typedef struct cq_res_ud { +typedef struct cq_res_ud_v3 { uint16_t length; /* * The length of the message's payload in bytes, stored in * the SGEs */ - #define CQ_RES_UD_LENGTH_MASK UINT32_C(0x3fff) - #define CQ_RES_UD_LENGTH_SFT 0 - /* - * This is data from the CFA or VNIC block as indicated by the - * ext_meta_format and meta_format fields. - */ - uint16_t cfa_metadata; - /* When meta_format=1, this value is the VLAN VID. */ - #define CQ_RES_UD_CFA_METADATA_VID_MASK UINT32_C(0xfff) - #define CQ_RES_UD_CFA_METADATA_VID_SFT 0 - /* When meta_format=1, this value is the VLAN DE. */ - #define CQ_RES_UD_CFA_METADATA_DE UINT32_C(0x1000) - /* When meta_format=1, this value is the VLAN PRI. */ - #define CQ_RES_UD_CFA_METADATA_PRI_MASK UINT32_C(0xe000) - #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13 + #define CQ_RES_UD_V3_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_UD_V3_LENGTH_SFT 0 + uint8_t reserved1; + /* Upper 8b of the Source QP value from the DETH header. */ + uint8_t src_qp_high; /* Immediate data in case the imm_flag set. */ uint32_t imm_data; /* @@ -72989,562 +85592,638 @@ uint16_t src_qp_low; uint8_t cqe_type_toggle; /* - * Indicate valid completion - written by the chip. Cumulus - * toggle this bit each time it finished consuming all PBL - * entries + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries. */ - #define CQ_RES_UD_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_RES_UD_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_RES_UD_CQE_TYPE_SFT 1 + #define CQ_RES_UD_V3_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_UD_V3_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_UD_V3_CQE_TYPE_SFT 1 /* * Responder UD Completion - This is used for both RQ and SRQ - * completion for UD service QPs. + * completion for UD service QPs. It is also used for QP1 QPs + * that are treated as UD. */ - #define CQ_RES_UD_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1) - #define CQ_RES_UD_CQE_TYPE_LAST CQ_RES_UD_CQE_TYPE_RES_UD + #define CQ_RES_UD_V3_CQE_TYPE_RES_UD_V3 (UINT32_C(0xa) << 1) + #define CQ_RES_UD_V3_CQE_TYPE_LAST CQ_RES_UD_V3_CQE_TYPE_RES_UD_V3 /* This field indicates the status for the CQE. */ uint8_t status; + /* The operation completed successfully. */ + #define CQ_RES_UD_V3_STATUS_OK UINT32_C(0x0) /* - * This indicates that the completion is without error. - * All fields are valid. + * This indicates that the packet was too long for the WQE provided + * on the SRQ/RQ. + * + * This is not a fatal error. All the fields in the CQE are valid. */ - #define CQ_RES_UD_STATUS_OK UINT32_C(0x0) + #define CQ_RES_UD_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3) /* - * This indicates that write access was not allowed for - * at least one of the SGEs in the WQE. + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. * - * This is a fatal error. Only the srq_or_rq_wr_id is field - * is valid. + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. */ - #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) + #define CQ_RES_UD_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) /* - * This indicates that the packet was too long for the WQE - * provided on the SRQ/RQ. + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. * - * This is not a fatal error. All the fields are valid. + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. */ - #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) - /* LOCAL_PROTECTION_ERR is 3 */ - #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) - /* LOCAL_QP_OPERATION_ERR is 4 */ - #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) - /* MEMORY_MGT_OPERATION_ERR is 5 */ - #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) - /* WORK_REQUEST_FLUSHED_ERR is 7 */ - #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) - /* HW_FLUSH_ERR is 8 */ - #define CQ_RES_UD_STATUS_HW_FLUSH_ERR UINT32_C(0x8) - #define CQ_RES_UD_STATUS_LAST CQ_RES_UD_STATUS_HW_FLUSH_ERR + #define CQ_RES_UD_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) + /* + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. + */ + #define CQ_RES_UD_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) + /* + * A WQE had already been taken off the RQ/SRQ when a fatal error + * was detected on responder Rx. Only the opaque field in the CQE + * is valid. + */ + #define CQ_RES_UD_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe) + /* + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. + */ + #define CQ_RES_UD_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_RES_UD_V3_STATUS_LAST CQ_RES_UD_V3_STATUS_OVERFLOW_ERR uint16_t flags; /* * This flag indicates that the completion is for a SRQ entry * rather than for an RQ entry. */ - #define CQ_RES_UD_FLAGS_SRQ UINT32_C(0x1) + #define CQ_RES_UD_V3_FLAGS_SRQ UINT32_C(0x1) /* CQE relates to RQ WQE. */ - #define CQ_RES_UD_FLAGS_SRQ_RQ UINT32_C(0x0) + #define CQ_RES_UD_V3_FLAGS_SRQ_RQ UINT32_C(0x0) /* CQE relates to SRQ WQE. */ - #define CQ_RES_UD_FLAGS_SRQ_SRQ UINT32_C(0x1) - #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ + #define CQ_RES_UD_V3_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_UD_V3_FLAGS_SRQ_LAST CQ_RES_UD_V3_FLAGS_SRQ_SRQ /* Immediate data indicator */ - #define CQ_RES_UD_FLAGS_IMM UINT32_C(0x2) - #define CQ_RES_UD_FLAGS_UNUSED_MASK UINT32_C(0xc) - #define CQ_RES_UD_FLAGS_UNUSED_SFT 2 - #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) - #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4 + #define CQ_RES_UD_V3_FLAGS_IMM UINT32_C(0x2) + #define CQ_RES_UD_V3_FLAGS_UNUSED_MASK UINT32_C(0xc) + #define CQ_RES_UD_V3_FLAGS_UNUSED_SFT 2 + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_SFT 4 /* RoCEv1 Message */ - #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) /* RoCEv2 IPv4 Message */ - #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) /* RoCEv2 IPv6 Message */ - #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) - #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV6 + /* This value is from the WQE that is being completed. */ + uint32_t opaque; +} cq_res_ud_v3_t, *pcq_res_ud_v3_t; + +/* + * This is the Responder RQ/SRQ CQE V3 structure for RawEth. This is + * used to complete RQ/SRQ WQE's. When the WQE is completed, it + * indicates that there is room for one more WQE on the corresponding + * RQ/SRQ. + * + * User can determine available space in the RQ/SRQ by comparing + * a rq_cons_idx to a rq_prod_idx, both maintained by the user. The + * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The + * rq_prod_idx value increments by one for each WQE that is added to + * the RQ/SRQ by the user. Value must be wrapped at rq_size. The + * rq_cons_idx value increments by one for each WQE that is completed + * from that particular RQ/SRQ. The qp_handle can be used by the user + * to determine what RQ/SRQ to increment. Value must also be wrapped at + * rq_size. When the two values are equal, the RQ/SRQ is empty. When + * (rq_prod_idx+1)%QPC.rq_size==rq_cons_idx, the queue is full. + */ +/* cq_res_raweth_qp1_v3 (size:256b/32B) */ + +typedef struct cq_res_raweth_qp1_v3 { + uint16_t length; /* - * The combination of this value and ext_meta_format indicates - * what format the metadata field is. + * The length of the message's payload in bytes, stored in + * the SGEs */ - #define CQ_RES_UD_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) - #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6 - /* No metadata information. Value is zero. */ - #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) + #define CQ_RES_RAWETH_QP1_V3_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_RAWETH_QP1_V3_LENGTH_SFT 0 + uint16_t raweth_qp1_flags_cfa_metadata1; /* - * The metadata field contains the VLAN tag and TPID value. - * - metadata[11:0] contains the vlan VID value. - * - metadata[12] contains the vlan DE value. - * - metadata[15:13] contains the vlan PRI value. + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * raweth_qp1_errors. */ - #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (UINT32_C(0x1) << 6) + #define CQ_RES_RAWETH_QP1_V3_ERROR UINT32_C(0x1) /* - * If ext_meta_format is equal to 1, the metadata field - * contains the lower 16b of the tunnel ID value, justified - * to LSB - * - VXLAN = VNI[23:0] -> VXLAN Network ID - * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier. - * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0 - * - IPV4 = 0 (not populated) - * - IPV6 = Flow Label[19:0] - * - PPPoE = sessionID[15:0] - * - MPLs = Outer label[19:0] - * - UPAR = Selected[31:0] with bit mask + * This value indicates what the inner packet determined for the + * packet was. */ - #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6) + #define CQ_RES_RAWETH_QP1_V3_ITYPE_MASK UINT32_C(0x3c0) + #define CQ_RES_RAWETH_QP1_V3_ITYPE_SFT 6 /* - * if ext_meta_format is equal to 1, metadata field contains - * 16b metadata from the prepended header (chdr_data). + * Not Known: + * Indicates that the packet type was not known. */ - #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6) + #define CQ_RES_RAWETH_QP1_V3_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6) /* - * If ext_meta_format is equal to 1, the metadata field contains - * the outer_l3_offset and lower 7 bits of the inner_l2_offset, - * - metadata[8:0] contains the outer_l3_offset. - * - metadata[15:9] contains the inner_l2_offset[6:0] + * IP Packet: + * Indicates that the packet was an IP packet, but further + * classification was not possible. */ - #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6) - #define CQ_RES_UD_FLAGS_META_FORMAT_LAST CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET + #define CQ_RES_RAWETH_QP1_V3_ITYPE_IP (UINT32_C(0x1) << 6) /* - * The combination of this value and meta_format indicates what - * format the metadata field is + * TCP Packet: + * Indicates that the packet was IP and TCP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ - #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK UINT32_C(0xc00) - #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10 - uint32_t src_qp_high_srq_or_rq_wr_id; + #define CQ_RES_RAWETH_QP1_V3_ITYPE_TCP (UINT32_C(0x2) << 6) /* - * Opaque value from RQ or SRQ WQE. Used by driver/lib to - * reference the WQE in order to claim the received data - * and reuse the WQE space + * UDP Packet: + * Indicates that the packet was IP and UDP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ - #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) - #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0 - /* Upper 8b of the Source QP value from the DETH header. */ - #define CQ_RES_UD_SRC_QP_HIGH_MASK UINT32_C(0xff000000) - #define CQ_RES_UD_SRC_QP_HIGH_SFT 24 -} cq_res_ud_t, *pcq_res_ud_t; - -/* Responder UD CQE version 2 */ -/* cq_res_ud_v2 (size:256b/32B) */ - -typedef struct cq_res_ud_v2 { - uint16_t length; + #define CQ_RES_RAWETH_QP1_V3_ITYPE_UDP (UINT32_C(0x3) << 6) /* - * The length of the message's payload in bytes, stored in - * the SGEs + * FCoE Packet: + * Indicates that the packet was recognized as a FCoE. + * This also indicates that the raweth_qp1_payload_offset field is + * valid. */ - #define CQ_RES_UD_V2_LENGTH_MASK UINT32_C(0x3fff) - #define CQ_RES_UD_V2_LENGTH_SFT 0 - /* This is data from the CFA as indicated by the meta_format field. */ - uint16_t cfa_metadata0; - /* When meta_format=1, this value is the VLAN VID. */ - #define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff) - #define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0 - /* When meta_format=1, this value is the VLAN DE. */ - #define CQ_RES_UD_V2_CFA_METADATA0_DE UINT32_C(0x1000) - /* When meta_format=1, this value is the VLAN PRI. */ - #define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000) - #define CQ_RES_UD_V2_CFA_METADATA0_PRI_SFT 13 - /* Immediate data in case the imm_flag set. */ - uint32_t imm_data; + #define CQ_RES_RAWETH_QP1_V3_ITYPE_FCOE (UINT32_C(0x4) << 6) /* - * This is an application level ID used to identify the - * QP and its SQ and RQ. + * RoCE Packet: + * Indicates that the packet was recognized as a RoCE. + * This also indicates that the raweth_qp1_payload_offset field is + * valid. */ - uint64_t qp_handle; + #define CQ_RES_RAWETH_QP1_V3_ITYPE_ROCE (UINT32_C(0x5) << 6) /* - * Source MAC address for the UD message placed in the WQE - * that is completed by this CQE. + * ICMP Packet: + * Indicates that the packet was recognized as ICMP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ - uint16_t src_mac[3]; - /* Lower 16b of the Source QP value from the DETH header. */ - uint16_t src_qp_low; - uint8_t cqe_type_toggle; + #define CQ_RES_RAWETH_QP1_V3_ITYPE_ICMP (UINT32_C(0x7) << 6) /* - * Indicate valid completion - written by the chip. Cumulus - * toggle this bit each time it finished consuming all PBL - * entries + * PtP packet wo/timestamp: + * Indicates that the packet was recognized as a PtP + * packet. */ - #define CQ_RES_UD_V2_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_RES_UD_V2_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_RES_UD_V2_CQE_TYPE_SFT 1 + #define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6) /* - * Responder UD Completion - This is used for both RQ and SRQ - * completion for UD service QPs. + * PtP packet w/timestamp: + * Indicates that the packet was recognized as a PtP + * packet and that a timestamp was taken for the packet. */ - #define CQ_RES_UD_V2_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1) - #define CQ_RES_UD_V2_CQE_TYPE_LAST CQ_RES_UD_V2_CQE_TYPE_RES_UD - /* This field indicates the status for the CQE. */ - uint8_t status; + #define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6) + #define CQ_RES_RAWETH_QP1_V3_ITYPE_LAST CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_W_TIMESTAMP + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_MASK UINT32_C(0xf000) + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x7000) + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_TPID_SEL_SFT 12 + /* When meta_format != 0, this value is the VLAN valid. */ + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_VALID UINT32_C(0x8000) + uint16_t raweth_qp1_errors; /* - * This indicates that the completion is without error. - * All fields are valid. + * This indicates that there was an error in the IP header + * checksum. */ - #define CQ_RES_UD_V2_STATUS_OK UINT32_C(0x0) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10) /* - * This indicates that write access was not allowed for - * at least one of the SGEs in the WQE. - * - * This is a fatal error. Only the srq_or_rq_wr_id is field - * is valid. + * This indicates that there was an error in the TCP, UDP + * or ICMP checksum. */ - #define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20) /* - * This indicates that the packet was too long for the WQE - * provided on the SRQ/RQ. - * - * This is not a fatal error. All the fields are valid. + * This indicates that there was an error in the tunnel + * IP header checksum. */ - #define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) - /* LOCAL_PROTECTION_ERR is 3 */ - #define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) - /* LOCAL_QP_OPERATION_ERR is 4 */ - #define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) - /* MEMORY_MGT_OPERATION_ERR is 5 */ - #define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) - /* WORK_REQUEST_FLUSHED_ERR is 7 */ - #define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) - /* HW_FLUSH_ERR is 8 */ - #define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8) - #define CQ_RES_UD_V2_STATUS_LAST CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR - uint16_t flags; + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40) /* - * This flag indicates that the completion is for a SRQ entry - * rather than for an RQ entry. + * This indicates that there was an error in the tunnel + * UDP checksum. */ - #define CQ_RES_UD_V2_FLAGS_SRQ UINT32_C(0x1) - /* CQE relates to RQ WQE. */ - #define CQ_RES_UD_V2_FLAGS_SRQ_RQ UINT32_C(0x0) - /* CQE relates to SRQ WQE. */ - #define CQ_RES_UD_V2_FLAGS_SRQ_SRQ UINT32_C(0x1) - #define CQ_RES_UD_V2_FLAGS_SRQ_LAST CQ_RES_UD_V2_FLAGS_SRQ_SRQ - /* Immediate data indicator */ - #define CQ_RES_UD_V2_FLAGS_IMM UINT32_C(0x2) - #define CQ_RES_UD_V2_FLAGS_UNUSED_MASK UINT32_C(0xc) - #define CQ_RES_UD_V2_FLAGS_UNUSED_SFT 2 - #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) - #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_SFT 4 - /* RoCEv1 Message */ - #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) - /* RoCEv2 IPv4 Message */ - #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) - /* RoCEv2 IPv6 Message */ - #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) - #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 - /* The field indicates what format the metadata field is. */ - #define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) - #define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6 - /* No metadata information. Value is zero. */ - #define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80) /* - * The {metadata1, metadata0} fields contain the vtag - * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], - * de, vid[11:0]} The metadata2 field contains the table scope - * and action record pointer. - metadata2[25:0] contains the - * action record pointer. - metadata2[31:26] contains the table - * scope. + * This indicates that there was a CRC error on either an FCoE + * or RoCE packet. The itype indicates the packet type. */ - #define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100) /* - * The {metadata1, metadata0} fields contain the vtag - * information: - * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} - * The metadata2 field contains the Tunnel ID - * value, justified to LSB. i - * - VXLAN = VNI[23:0] -> VXLAN Network ID - * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier - * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 - * - IPv4 = 0 (not populated) - * - IPv6 = Flow Label[19:0] - * - PPPoE = sessionID[15:0] - * - MPLs = Outer label[19:0] - * - UPAR = Selected[31:0] with bit mask + * This indicates that there was an error in the tunnel + * portion of the packet when this + * field is non-zero. */ - #define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 /* - * The {metadata1, metadata0} fields contain the vtag - * information: - * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} - * The metadata2 field contains the 32b metadata from the - * prepended header (chdr_data). + * No additional error occurred on the tunnel portion + * of the packet of the packet does not have a tunnel. */ - #define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9) /* - * If ext_meta_format is equal to 1, the metadata field contains - * the outer_l3_offset and lower 7 bits of the inner_l2_offset, - * - metadata[8:0] contains the outer_l3_offset. - * - metadata[15:9] contains the inner_l2_offset[6:0] + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 + * in the tunnel header. */ - #define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6) - #define CQ_RES_UD_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET - uint32_t src_qp_high_srq_or_rq_wr_id; + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9) /* - * Opaque value from RQ or SRQ WQE. Used by driver/lib to - * reference the WQE in order to claim the received data - * and reuse the WQE space + * Indicates that header length is out of range in the + * tunnel header. Valid for + * IPv4. */ - #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) - #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0 - #define CQ_RES_UD_V2_CFA_METADATA1_MASK UINT32_C(0xf00000) - #define CQ_RES_UD_V2_CFA_METADATA1_SFT 20 - /* When meta_format != 0, this value is the VLAN TPID_SEL. */ - #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000) - #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_SFT 20 - /* 0x88a8 */ - #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20) - /* 0x8100 */ - #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20) - /* 0x9100 */ - #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20) - /* 0x9200 */ - #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20) - /* 0x9300 */ - #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20) - /* Value programmed in CFA VLANTPID register. */ - #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20) - #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG - /* When meta_format != 0, this value is the VLAN valid. */ - #define CQ_RES_UD_V2_CFA_METADATA1_VALID UINT32_C(0x800000) - /* Upper 8b of the Source QP value from the DETH header. */ - #define CQ_RES_UD_V2_SRC_QP_HIGH_MASK UINT32_C(0xff000000) - #define CQ_RES_UD_V2_SRC_QP_HIGH_SFT 24 -} cq_res_ud_v2_t, *pcq_res_ud_v2_t; - -/* Responder UD with CFA CQE */ -/* cq_res_ud_cfa (size:256b/32B) */ - -typedef struct cq_res_ud_cfa { - uint16_t length; + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9) /* - * The length of the message's payload in bytes, stored in - * the SGEs + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 + * tunnel packet packets. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x3) << 9) + /* + * Indicates that the physical packet is shorter than that + * claimed by the tunnel UDP header length for a tunnel + * UDP packet that is not fragmented. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x4) << 9) + /* + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0) in the tunnel header. Valid + * for IPv4, and IPv6. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5) << 9) + /* + * Indicates that the physical packet is shorter than that + * claimed by the tunnel header length. Valid for GTPv1-U + * packets. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (UINT32_C(0x6) << 9) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR + /* + * This indicates that there was an error in the inner + * portion of the packet when this + * field is non-zero. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 + /* + * No additional error occurred on the tunnel portion + * of the packet of the packet does not have a tunnel. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12) + /* + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 or that + * option other than VFT was parsed on + * FCoE packet. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12) + /* + * indicates that header length is out of range. Valid for + * IPv4 and RoCE + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12) + /* + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12) + /* + * Indicates that physical packet is shorter than that + * claimed by the l3 header length. Valid for IPv4, + * IPv6 packet or RoCE packets. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12) + /* + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is + * not fragmented. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12) + /* + * Indicates that TCP header length > IP payload. Valid for + * TCP packets only. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12) + /* + * Indicates that TCP option headers result in a TCP header + * size that does not match data offset in TCP header. Valid + * for TCP. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN + /* This is data from the CFA as indicated by the meta_format field. */ + uint16_t cfa_metadata0; + /* When meta_format=1, this value is the VLAN VID. */ + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_MASK UINT32_C(0xfff) + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_PRI_MASK UINT32_C(0xe000) + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_PRI_SFT 13 + /* + * This is an application level ID used to identify the + * QP and its SQ and RQ. */ - #define CQ_RES_UD_CFA_LENGTH_MASK UINT32_C(0x3fff) - #define CQ_RES_UD_CFA_LENGTH_SFT 0 + uint64_t qp_handle; + uint32_t raweth_qp1_flags2; /* - * This field identifies the CFA action rule that was used - * for this packet. + * This indicates that the ip checksum was calculated for the + * inner packet and that the ip_cs_error field indicates if there + * was an error. */ - uint16_t cfa_code; - /* Immediate data in case the imm_flag set. */ - uint32_t imm_data; - uint32_t qid; + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_CS_CALC UINT32_C(0x1) /* - * This value indicates the QPID associated with this operation. - * The driver will use the qid from thie CQE to map a QP handle - * in the completion record returned to the application. + * This indicates that the TCP, UDP or ICMP checksum was + * calculated for the inner packet and that the l4_cs_error field + * indicates if there was an error. */ - #define CQ_RES_UD_CFA_QID_MASK UINT32_C(0xfffff) - #define CQ_RES_UD_CFA_QID_SFT 0 + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_L4_CS_CALC UINT32_C(0x2) /* - * This is data from the CFA or VNIC block as indicated by the - * ext_meta_format and meta_format fields. + * This indicates that the ip checksum was calculated for the + * tunnel header and that the t_ip_cs_error field indicates if + * there was an error. */ - uint32_t cfa_metadata; - /* When meta_format=1, this value is the VLAN VID. */ - #define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK UINT32_C(0xfff) - #define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0 - /* When meta_format=1, this value is the VLAN DE. */ - #define CQ_RES_UD_CFA_CFA_METADATA_DE UINT32_C(0x1000) - /* When meta_format=1, this value is the VLAN PRI. */ - #define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK UINT32_C(0xe000) - #define CQ_RES_UD_CFA_CFA_METADATA_PRI_SFT 13 - /* When meta_format=1, this value is the VLAN TPID. */ - #define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK UINT32_C(0xffff0000) - #define CQ_RES_UD_CFA_CFA_METADATA_TPID_SFT 16 + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) /* - * Source MAC address for the UD message placed in the WQE - * that is completed by this CQE. + * This indicates that the UDP checksum was + * calculated for the tunnel packet and that the t_l4_cs_error + * field indicates if there was an error. */ - uint16_t src_mac[3]; - /* Lower 16b of the Source QP value from the DETH header. */ - uint16_t src_qp_low; - uint8_t cqe_type_toggle; + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) + /* The field indicates what format the metadata field is. */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 + /* No metadata information. Values are zero. */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4) /* - * Indicate valid completion - written by the chip. Cumulus - * toggle this bit each time it finished consuming all PBL - * entries + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * + * The metadata2 field contains the table scope + * and action record pointer. + * + * - metadata2[25:0] contains the action record pointer. + * - metadata2[31:26] contains the table scope. */ - #define CQ_RES_UD_CFA_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_RES_UD_CFA_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_RES_UD_CFA_CQE_TYPE_SFT 1 + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4) /* - * Responder UD Completion with CFA - This is used for both RQ - * and SRQ completion for UD service QPs. It includes cfa fields - * (some of which carry VLAN information), in place of the QP - * handle. It is also used for QP1 QPs that are treated as UD. + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * + * The metadata2 field contains the Tunnel ID value, justified + * to LSB. + * + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - #define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1) - #define CQ_RES_UD_CFA_CQE_TYPE_LAST CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA - /* This field indicates the status for the CQE. */ - uint8_t status; + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4) /* - * This indicates that the completion is without error. - * All fields are valid. + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * + * The metadata2 field contains the 32b metadata from the + * prepended header (chdr_data). */ - #define CQ_RES_UD_CFA_STATUS_OK UINT32_C(0x0) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4) /* - * This indicates that write access was not allowed for - * at least one of the SGEs in the WQE. + * The {metadata1, metadata0} fields contain the vtag + * information: * - * This is a fatal error. Only the srq_or_rq_wr_id is field - * is valid. + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. */ - #define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET /* - * This indicates that the packet was too long for the WQE - * provided on the SRQ/RQ. + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100) + /* + * This indicates that the complete 1's complement checksum was + * calculated for the packet. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE UINT32_C(0x400) + /* Indicates that the Tunnel IP type was IPv4. */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV4 (UINT32_C(0x0) << 10) + /* Indicates that the Tunnel IP type was IPv6. */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV6 (UINT32_C(0x1) << 10) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV6 + /* + * This value is the complete 1's complement checksum calculated + * from the start of the outer L3 header to the end of the packet + * (not including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + /* + * This is data from the CFA block as indicated by the meta_format + * field. * - * This is not a fatal error. All the fields are valid. + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] */ - #define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) - /* LOCAL_PROTECTION_ERR is 3 */ - #define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) - /* LOCAL_QP_OPERATION_ERR is 4 */ - #define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) - /* MEMORY_MGT_OPERATION_ERR is 5 */ - #define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) - /* WORK_REQUEST_FLUSHED_ERR is 7 */ - #define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) - /* HW_FLUSH_ERR is 8 */ - #define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR UINT32_C(0x8) - #define CQ_RES_UD_CFA_STATUS_LAST CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR - uint16_t flags; + uint32_t cfa_metadata2; + uint8_t cqe_type_toggle; /* - * This flag indicates that the completion is for a SRQ entry - * rather than for an RQ entry. + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries. */ - #define CQ_RES_UD_CFA_FLAGS_SRQ UINT32_C(0x1) - /* CQE relates to RQ WQE. */ - #define CQ_RES_UD_CFA_FLAGS_SRQ_RQ UINT32_C(0x0) - /* CQE relates to SRQ WQE. */ - #define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ UINT32_C(0x1) - #define CQ_RES_UD_CFA_FLAGS_SRQ_LAST CQ_RES_UD_CFA_FLAGS_SRQ_SRQ - /* Immediate data indicator */ - #define CQ_RES_UD_CFA_FLAGS_IMM UINT32_C(0x2) - #define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK UINT32_C(0xc) - #define CQ_RES_UD_CFA_FLAGS_UNUSED_SFT 2 - #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) - #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_SFT 4 - /* RoCEv1 Message */ - #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) - /* RoCEv2 IPv4 Message */ - #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) - /* RoCEv2 IPv6 Message */ - #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) - #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 + #define CQ_RES_RAWETH_QP1_V3_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_SFT 1 /* - * The combination of this value and ext_meta_format indicates - * what format the metadata field is. + * Responder RawEth and QP1 Completion - This is used for RQ and + * SRQ completion for RawEth service. It is also used for QP1 QPs + * that are treated as RawEth. */ - #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) - #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_SFT 6 + #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_RES_RAWETH_QP1_V3 (UINT32_C(0xb) << 1) + #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V3_CQE_TYPE_RES_RAWETH_QP1_V3 + /* This field indicates the status for the CQE. */ + uint8_t status; + /* The operation completed successfully. */ + #define CQ_RES_RAWETH_QP1_V3_STATUS_OK UINT32_C(0x0) /* - * If ext_meta_format is equal to 0, there is no metadata - * information. Value is zero. + * This indicates that the packet was too long for the WQE provided + * on the SRQ/RQ. + * + * This is not a fatal error. All the fields in the CQE are valid. */ - #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) + #define CQ_RES_RAWETH_QP1_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3) /* - * If ext_meta_format is equal to 0, the metadata field contains - * the VLAN tag and TPID value. - * - metadata[11:0] contains the vlan VID value. - * - metadata[12] contains the vlan DE value. - * - metadata[15:13] contains the vlan PRI value. - * - metadata[31:16] contains the vlan TPID value. + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. */ - #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (UINT32_C(0x1) << 6) + #define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) /* - * If ext_meta_format is equal to 1, the metadata field contains - * the Tunnel ID value, justified to LSB. - * - VXLAN = VNI[23:0] -> VXLAN Network ID - * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier - * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0 - * - IPV4 = 0 (not populated) - * - IPV6 = Flow Label[19:0] - * - PPPoE = sessionID[15:0] - * - MPLs = Outer label[19:0] - * - UPAR = Selected[31:0] with bit mask + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. */ - #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6) + #define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) /* - * if ext_meta_format is equal to 1, metadata field contains - * 16b metadata from the prepended header (chdr_data). + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. */ - #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6) + #define CQ_RES_RAWETH_QP1_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) /* - * If ext_meta_format is equal to 1, the metadata field contains - * the outer_l3_offset, inner_l2_offset, inner_l3_offset, and - * inner_l4_size. - * - metadata[8:0] contains the outer_l3_offset. - * - metadata[17:9] contains the inner_l2_offset. - * - metadata[26:18] contains the inner_l3_offset. - * - metadata[31:27] contains the inner_l4_size. + * A WQE had already been taken off the RQ/SRQ when a fatal error + * was detected on responder Rx. Only the opaque field in the CQE + * is valid. */ - #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6) - #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET + #define CQ_RES_RAWETH_QP1_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe) /* - * The combination of this value and meta_format indicates what - * format the metadata field is + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. */ - #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK UINT32_C(0xc00) - #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_SFT 10 - uint32_t src_qp_high_srq_or_rq_wr_id; + #define CQ_RES_RAWETH_QP1_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_RES_RAWETH_QP1_V3_STATUS_LAST CQ_RES_RAWETH_QP1_V3_STATUS_OVERFLOW_ERR + uint8_t flags; /* - * Opaque value from RQ or SRQ WQE. Used by driver/lib to - * reference the WQE in order to claim the received data - * and reuse the WQE space + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. */ - #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) - #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0 - /* Upper 8b of the Source QP value from the DETH header. */ - #define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK UINT32_C(0xff000000) - #define CQ_RES_UD_CFA_SRC_QP_HIGH_SFT 24 -} cq_res_ud_cfa_t, *pcq_res_ud_cfa_t; + #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_SRQ + /* + * This value indicates the offset in bytes from the beginning of the + * packet where the inner payload starts. This value is valid for + * TCP, UDP, FCoE, and RoCE packets. + * + * A value of zero indicates an offset of 256 bytes. + */ + uint8_t raweth_qp1_payload_offset; + /* This value is from the WQE that is being completed. */ + uint32_t opaque; +} cq_res_raweth_qp1_v3_t, *pcq_res_raweth_qp1_v3_t; -/* Responder UD with CFA CQE version 2 */ -/* cq_res_ud_cfa_v2 (size:256b/32B) */ +/* + * This is the Responder RQ/SRQ CQE V3 structure for UD QPs and QP1 QPs + * treated as UD. This is used to complete RQ/SRQ WQE's. It differs + * from the Res_UD CQE in that it carries additional CFA fields, in + * place of the QP handle. (Instead of the QP handle, this CQE carries + * the QID. It is up to the user to map the QID back to a QP handle.) + * When the WQE is completed, it indicates that there is room for one + * more WQE on the corresponding RQ/SRQ. + * + * User can determine available space in the RQ/SRQ by comparing + * a rq_cons_idx to a rq_prod_idx, both maintained by the user. The + * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The + * rq_prod_idx value increments by one for each WQE that is added to + * the RQ/SRQ by the user. Value must be wrapped at rq_size. The + * rq_cons_idx value increments by one for each WQE that is completed + * from that particular RQ/SRQ. The qp_handle can be used by the user + * to determine what RQ/SRQ to increment. Value must also be wrapped at + * rq_size. When the two values are equal, the RQ/SRQ is empty. When + * (rq_prod_idx+1)%QPC.rq_size==rq_cons_idx, the queue is full. + */ +/* cq_res_ud_cfa_v3 (size:256b/32B) */ -typedef struct cq_res_ud_cfa_v2 { +typedef struct cq_res_ud_cfa_v3 { uint16_t length; /* * The length of the message's payload in bytes, stored in * the SGEs */ - #define CQ_RES_UD_CFA_V2_LENGTH_MASK UINT32_C(0x3fff) - #define CQ_RES_UD_CFA_V2_LENGTH_SFT 0 + #define CQ_RES_UD_CFA_V3_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_UD_CFA_V3_LENGTH_SFT 0 /* This is data from the CFA as indicated by the meta_format field. */ uint16_t cfa_metadata0; /* When meta_format=1, this value is the VLAN VID. */ - #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff) - #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0 + #define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_MASK UINT32_C(0xfff) + #define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_SFT 0 /* When meta_format=1, this value is the VLAN DE. */ - #define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE UINT32_C(0x1000) + #define CQ_RES_UD_CFA_V3_CFA_METADATA0_DE UINT32_C(0x1000) /* When meta_format=1, this value is the VLAN PRI. */ - #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000) - #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_SFT 13 + #define CQ_RES_UD_CFA_V3_CFA_METADATA0_PRI_MASK UINT32_C(0xe000) + #define CQ_RES_UD_CFA_V3_CFA_METADATA0_PRI_SFT 13 /* Immediate data in case the imm_flag set. */ uint32_t imm_data; - uint32_t qid; + uint32_t qid_cfa_metadata1_src_qp_high; /* * This value indicates the QPID associated with this operation. - * The driver will use the qid from thie CQE to map a QP handle + * + * The driver will use the qid from this CQE to map a QP handle * in the completion record returned to the application. */ - #define CQ_RES_UD_CFA_V2_QID_MASK UINT32_C(0xfffff) - #define CQ_RES_UD_CFA_V2_QID_SFT 0 + #define CQ_RES_UD_CFA_V3_QID_MASK UINT32_C(0x7ff) + #define CQ_RES_UD_CFA_V3_QID_SFT 0 + #define CQ_RES_UD_CFA_V3_UNUSED_MASK UINT32_C(0xff800) + #define CQ_RES_UD_CFA_V3_UNUSED_SFT 11 + #define CQ_RES_UD_CFA_V3_CFA_METADATA1_MASK UINT32_C(0xf00000) + #define CQ_RES_UD_CFA_V3_CFA_METADATA1_SFT 20 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define CQ_RES_UD_CFA_V3_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000) + #define CQ_RES_UD_CFA_V3_CFA_METADATA1_TPID_SEL_SFT 20 + /* When meta_format != 0, this value is the VLAN valid. */ + #define CQ_RES_UD_CFA_V3_CFA_METADATA1_VALID UINT32_C(0x800000) + /* Upper 8b of the Source QP value from the DETH header. */ + #define CQ_RES_UD_CFA_V3_SRC_QP_HIGH_MASK UINT32_C(0xff000000) + #define CQ_RES_UD_CFA_V3_SRC_QP_HIGH_SFT 24 /* * This is data from the CFA block as indicated by the meta_format * field. + * * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], * act_rec_ptr[25:0]} * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] - * When vee_cmpl_mode is set in VNIC context, this is the upper 32b - * of the host address from the first BD used to place the packet. */ uint32_t cfa_metadata2; /* @@ -73556,99 +86235,122 @@ uint16_t src_qp_low; uint8_t cqe_type_toggle; /* - * Indicate valid completion - written by the chip. Cumulus - * toggle this bit each time it finished consuming all PBL + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL * entries */ - #define CQ_RES_UD_CFA_V2_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1 + #define CQ_RES_UD_CFA_V3_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_UD_CFA_V3_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_UD_CFA_V3_CQE_TYPE_SFT 1 /* * Responder UD Completion with CFA - This is used for both RQ * and SRQ completion for UD service QPs. It includes cfa fields * (some of which carry VLAN information), in place of the QP * handle. It is also used for QP1 QPs that are treated as UD. */ - #define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1) - #define CQ_RES_UD_CFA_V2_CQE_TYPE_LAST CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA + #define CQ_RES_UD_CFA_V3_CQE_TYPE_RES_UD_CFA_V3 (UINT32_C(0xc) << 1) + #define CQ_RES_UD_CFA_V3_CQE_TYPE_LAST CQ_RES_UD_CFA_V3_CQE_TYPE_RES_UD_CFA_V3 /* This field indicates the status for the CQE. */ uint8_t status; + /* The operation completed successfully. */ + #define CQ_RES_UD_CFA_V3_STATUS_OK UINT32_C(0x0) /* - * This indicates that the completion is without error. - * All fields are valid. + * This indicates that the packet was too long for the WQE provided + * on the SRQ/RQ. + * + * This is not a fatal error. All the fields in the CQE are valid. */ - #define CQ_RES_UD_CFA_V2_STATUS_OK UINT32_C(0x0) + #define CQ_RES_UD_CFA_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3) /* - * This indicates that write access was not allowed for - * at least one of the SGEs in the WQE. + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. * - * This is a fatal error. Only the srq_or_rq_wr_id is field - * is valid. + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. */ - #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) + #define CQ_RES_UD_CFA_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) /* - * This indicates that the packet was too long for the WQE - * provided on the SRQ/RQ. + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. * - * This is not a fatal error. All the fields are valid. + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. */ - #define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) - /* LOCAL_PROTECTION_ERR is 3 */ - #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) - /* LOCAL_QP_OPERATION_ERR is 4 */ - #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) - /* MEMORY_MGT_OPERATION_ERR is 5 */ - #define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) - /* WORK_REQUEST_FLUSHED_ERR is 7 */ - #define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) - /* HW_FLUSH_ERR is 8 */ - #define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8) - #define CQ_RES_UD_CFA_V2_STATUS_LAST CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR + #define CQ_RES_UD_CFA_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) + /* + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. + */ + #define CQ_RES_UD_CFA_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) + /* + * A WQE had already been taken off the RQ/SRQ when a fatal error + * was detected on responder Rx. Only the opaque field in the CQE + * is valid. + */ + #define CQ_RES_UD_CFA_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe) + /* + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. + */ + #define CQ_RES_UD_CFA_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_RES_UD_CFA_V3_STATUS_LAST CQ_RES_UD_CFA_V3_STATUS_OVERFLOW_ERR uint16_t flags; /* * This flag indicates that the completion is for a SRQ entry * rather than for an RQ entry. */ - #define CQ_RES_UD_CFA_V2_FLAGS_SRQ UINT32_C(0x1) + #define CQ_RES_UD_CFA_V3_FLAGS_SRQ UINT32_C(0x1) /* CQE relates to RQ WQE. */ - #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ UINT32_C(0x0) + #define CQ_RES_UD_CFA_V3_FLAGS_SRQ_RQ UINT32_C(0x0) /* CQE relates to SRQ WQE. */ - #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ UINT32_C(0x1) - #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ + #define CQ_RES_UD_CFA_V3_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_UD_CFA_V3_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V3_FLAGS_SRQ_SRQ /* Immediate data indicator */ - #define CQ_RES_UD_CFA_V2_FLAGS_IMM UINT32_C(0x2) - #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK UINT32_C(0xc) - #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_SFT 2 - #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) - #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_SFT 4 + #define CQ_RES_UD_CFA_V3_FLAGS_IMM UINT32_C(0x2) + #define CQ_RES_UD_CFA_V3_FLAGS_UNUSED_MASK UINT32_C(0xc) + #define CQ_RES_UD_CFA_V3_FLAGS_UNUSED_SFT 2 + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_SFT 4 /* RoCEv1 Message */ - #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) /* RoCEv2 IPv4 Message */ - #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) /* RoCEv2 IPv6 Message */ - #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) - #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV6 /* The field indicates what format the metadata field is. */ - #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) - #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6 - /* No metadata information. Value is zero. */ - #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_SFT 6 + /* No metadata information. Value is zero. */ + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) /* * The {metadata1, metadata0} fields contain the vtag - * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], - * de, vid[11:0]} The metadata2 field contains the table scope - * and action record pointer. - metadata2[25:0] contains the - * action record pointer. - metadata2[31:26] contains the table - * scope. + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * + * The metadata2 field contains the table scope + * and action record pointer. + * + * - metadata2[25:0] contains the action record pointer. + * - metadata2[31:26] contains the table scope. */ - #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6) + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6) /* * The {metadata1, metadata0} fields contain the vtag * information: + * * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * * The metadata2 field contains the Tunnel ID - * value, justified to LSB. i + * value, justified to LSB. + * * - VXLAN = VNI[23:0] -> VXLAN Network ID * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier * - NVGRE = TNI[23:0] -> Tenant Network ID @@ -73659,2333 +86361,2666 @@ * - MPLs = Outer label[19:0] * - UPAR = Selected[31:0] with bit mask */ - #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6) + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6) /* * The {metadata1, metadata0} fields contain the vtag * information: + * * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * * The metadata2 field contains the 32b metadata from the * prepended header (chdr_data). */ - #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6) + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6) /* - * If ext_meta_format is equal to 1, the metadata field contains - * the outer_l3_offset and lower 7 bits of the inner_l2_offset, - * - metadata[8:0] contains the outer_l3_offset. - * - metadata[15:9] contains the inner_l2_offset[6:0] + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. */ - #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6) - #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET - uint32_t src_qp_high_srq_or_rq_wr_id; + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6) + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_HDR_OFFSET /* - * Opaque value from RQ or SRQ WQE. Used by driver/lib to - * reference the WQE in order to claim the received data - * and reuse the WQE space + * This value will be returned in the completion if the completion is + * signaled. */ - #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) - #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0 - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK UINT32_C(0xf00000) - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_SFT 20 - /* When meta_format != 0, this value is the VLAN TPID_SEL. */ - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000) - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_SFT 20 - /* 0x88a8 */ - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20) - /* 0x8100 */ - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20) - /* 0x9100 */ - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20) - /* 0x9200 */ - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20) - /* 0x9300 */ - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20) - /* Value programmed in CFA VLANTPID register. */ - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20) - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG - /* When meta_format != 0, this value is the VLAN valid. */ - #define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID UINT32_C(0x800000) - /* Upper 8b of the Source QP value from the DETH header. */ - #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK UINT32_C(0xff000000) - #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_SFT 24 -} cq_res_ud_cfa_v2_t, *pcq_res_ud_cfa_v2_t; + uint32_t opaque; +} cq_res_ud_cfa_v3_t, *pcq_res_ud_cfa_v3_t; -/* Responder RawEth and QP1 CQE */ -/* cq_res_raweth_qp1 (size:256b/32B) */ +/* nq_base (size:128b/16B) */ -typedef struct cq_res_raweth_qp1 { - uint16_t length; - /* - * The length of the message's payload in bytes, stored in - * the SGEs - */ - #define CQ_RES_RAWETH_QP1_LENGTH_MASK UINT32_C(0x3fff) - #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0 - uint16_t raweth_qp1_flags; - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK UINT32_C(0x3ff) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0 - /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * raweth_qp1_errors. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1) - /* - * This value indicates what the inner packet determined for the - * packet was. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK UINT32_C(0x3c0) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6 - /* - * Not Known: - * Indicates that the packet type was not known. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6) - /* - * IP Packet: - * Indicates that the packet was an IP packet, but further - * classification was not possible. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (UINT32_C(0x1) << 6) - /* - * TCP Packet: - * Indicates that the packet was IP and TCP. - * This indicates that the raweth_qp1_payload_offset field is valid. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 6) - /* - * UDP Packet: - * Indicates that the packet was IP and UDP. - * This indicates that the raweth_qp1_payload_offset field is valid. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 6) - /* - * FCoE Packet: - * Indicates that the packet was recognized as a FCoE. - * This also indicates that the raweth_qp1_payload_offset field is valid. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 6) - /* - * RoCE Packet: - * Indicates that the packet was recognized as a RoCE. - * This also indicates that the raweth_qp1_payload_offset field is valid. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 6) - /* - * ICMP Packet: - * Indicates that the packet was recognized as ICMP. - * This indicates that the raweth_qp1_payload_offset field is valid. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 6) - /* - * PtP packet wo/timestamp: - * Indicates that the packet was recognized as a PtP - * packet. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6) - /* - * PtP packet w/timestamp: - * Indicates that the packet was recognized as a PtP - * packet and that a timestamp was taken for the packet. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP - uint16_t raweth_qp1_errors; - /* - * This indicates that there was an error in the IP header - * checksum. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10) - /* - * This indicates that there was an error in the TCP, UDP - * or ICMP checksum. - */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20) +typedef struct nq_base { + uint16_t info10_type; /* - * This indicates that there was an error in the tunnel - * IP header checksum. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40) + #define NQ_BASE_TYPE_MASK UINT32_C(0x3f) + #define NQ_BASE_TYPE_SFT 0 + /* CQ Notification */ + #define NQ_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30) + /* SRQ Threshold Event */ + #define NQ_BASE_TYPE_SRQ_EVENT UINT32_C(0x32) + /* DBQ Threshold Event */ + #define NQ_BASE_TYPE_DBQ_EVENT UINT32_C(0x34) + /* QP Async Notification */ + #define NQ_BASE_TYPE_QP_EVENT UINT32_C(0x38) + /* Function Async Notification */ + #define NQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a) + /* NQ Reassign Notification */ + #define NQ_BASE_TYPE_NQ_REASSIGN UINT32_C(0x3c) + #define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_NQ_REASSIGN + /* info10 is 10 b */ + #define NQ_BASE_INFO10_MASK UINT32_C(0xffc0) + #define NQ_BASE_INFO10_SFT 6 + /* info16 is 16 b */ + uint16_t info16; + /* info32 is 32 b */ + uint32_t info32; + /* info32 is 32 b */ + uint64_t info63_v; /* - * This indicates that there was an error in the tunnel - * UDP checksum. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80) + #define NQ_BASE_V UINT32_C(0x1) + /* info63 is 63 b */ + #define NQ_BASE_INFO63_MASK UINT32_C(0xfffffffe) + #define NQ_BASE_INFO63_SFT 1 +} nq_base_t, *pnq_base_t; + +/* Completion Queue Notification */ +/* nq_cn (size:128b/16B) */ + +typedef struct nq_cn { + uint16_t type; /* - * This indicates that there was a CRC error on either an FCoE - * or RoCE packet. The itype indicates the packet type. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100) + #define NQ_CN_TYPE_MASK UINT32_C(0x3f) + #define NQ_CN_TYPE_SFT 0 + /* CQ Notification */ + #define NQ_CN_TYPE_CQ_NOTIFICATION UINT32_C(0x30) + #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION /* - * This indicates that there was an error in the tunnel - * portion of the packet when this - * field is non-zero. + * This field carries the toggle value that must be used to + * re-arm this CQ. The toggle value should be copied into the + * doorbell used to CQ_ARMENA, CQ_ARMALL or CQ_ARMSE doorbells. + * + * This value is used by HW to detect old and stale CQ_ARMENA, + * CQ_ARMALL, or CQ_ARMSE doorbells that are caused by having + * a backup doorbell location or by PCI or other reordering + * problems. Only the doorbells that match the latest value of + * toggle will be honored. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 + #define NQ_CN_TOGGLE_MASK UINT32_C(0xc0) + #define NQ_CN_TOGGLE_SFT 6 + uint16_t reserved16; /* - * No additional error occurred on the tunnel portion - * of the packet of the packet does not have a tunnel. + * This is an application level ID used to identify the + * CQ. This field carries the lower 32b of the value. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9) + uint32_t cq_handle_low; + uint32_t v; /* - * Indicates that IP header version does not match - * expectation from L2 Ethertype for IPv4 and IPv6 - * in the tunnel header. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9) + #define NQ_CN_V UINT32_C(0x1) /* - * Indicates that header length is out of range in the - * tunnel header. Valid for - * IPv4. + * This is an application level ID used to identify the + * CQ. This field carries the upper 32b of the value. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9) + uint32_t cq_handle_high; +} nq_cn_t, *pnq_cn_t; + +/* SRQ Event Notification */ +/* nq_srq_event (size:128b/16B) */ + +typedef struct nq_srq_event { + uint8_t type; /* - * Indicates that the physical packet is shorter than that - * claimed by the PPPoE header length for a tunnel PPPoE - * packet. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B records. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9) + #define NQ_SRQ_EVENT_TYPE_MASK UINT32_C(0x3f) + #define NQ_SRQ_EVENT_TYPE_SFT 0 + /* SRQ Threshold Event */ + #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT UINT32_C(0x32) + #define NQ_SRQ_EVENT_TYPE_LAST NQ_SRQ_EVENT_TYPE_SRQ_EVENT /* - * Indicates that physical packet is shorter than that claimed - * by the tunnel l3 header length. Valid for IPv4, or IPv6 - * tunnel packet packets. + * This field carries the toggle value that must be used + * to re-arm this SRQ. The toggle value should be copied + * into the doorbell used to SRQ_ARMENA or SRQ_ARM doorbells. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9) + #define NQ_SRQ_EVENT_TOGGLE_MASK UINT32_C(0xc0) + #define NQ_SRQ_EVENT_TOGGLE_SFT 6 /* - * Indicates that the physical packet is shorter than that - * claimed by the tunnel UDP header length for a tunnel - * UDP packet that is not fragmented. + * This value define what type of async event has occurred + * on the SRQ. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9) + uint8_t event; + /* The threshold event has occurred on the specified SRQ. */ + #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT UINT32_C(0x1) + #define NQ_SRQ_EVENT_EVENT_LAST NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT + uint16_t reserved16; /* - * indicates that the IPv4 TTL or IPv6 hop limit check - * have failed (e.g. TTL = 0) in the tunnel header. Valid - * for IPv4, and IPv6. + * This is the SRQ handle value for the queue that has + * reached it's event threshold. This field carries the + * lower 32b of the value. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL + uint32_t srq_handle_low; + uint32_t v; /* - * This indicates that there was an error in the inner - * portion of the packet when this - * field is non-zero. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 + #define NQ_SRQ_EVENT_V UINT32_C(0x1) /* - * No additional error occurred on the tunnel portion - * of the packet of the packet does not have a tunnel. + * This is the SRQ handle value for the queue that has + * reached it's event threshold. This field carries the + * upper 32b of the value. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12) + uint32_t srq_handle_high; +} nq_srq_event_t, *pnq_srq_event_t; + +/* DBQ Async Event Notification */ +/* nq_dbq_event (size:128b/16B) */ + +typedef struct nq_dbq_event { + uint8_t type; /* - * Indicates that IP header version does not match - * expectation from L2 Ethertype for IPv4 and IPv6 or that - * option other than VFT was parsed on - * FCoE packet. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12) + #define NQ_DBQ_EVENT_TYPE_MASK UINT32_C(0x3f) + #define NQ_DBQ_EVENT_TYPE_SFT 0 + /* DBQ Threshold Event */ + #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT UINT32_C(0x34) + #define NQ_DBQ_EVENT_TYPE_LAST NQ_DBQ_EVENT_TYPE_DBQ_EVENT + /* This value define what type of action the driver should take. */ + uint8_t event; /* - * indicates that header length is out of range. Valid for - * IPv4 and RoCE + * The driver should start writing dummy values to the + * the doorbell in an attempt to consume all the PCIE + * posted write resources and prevent doorbell overflow. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12) + #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT UINT32_C(0x1) + #define NQ_DBQ_EVENT_EVENT_LAST NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT + uint16_t db_pfid; /* - * indicates that the IPv4 TTL or IPv6 hop limit check - * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 + * This is the PFID of function that wrote the doorbell that + * crossed the async event threshold. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12) + #define NQ_DBQ_EVENT_DB_PFID_MASK UINT32_C(0xf) + #define NQ_DBQ_EVENT_DB_PFID_SFT 0 + uint32_t db_dpi; /* - * Indicates that physical packet is shorter than that - * claimed by the l3 header length. Valid for IPv4, - * IPv6 packet or RoCE packets. + * This is the DPI of the doorbell write that crossed + * the async event threshold. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12) + #define NQ_DBQ_EVENT_DB_DPI_MASK UINT32_C(0xfffff) + #define NQ_DBQ_EVENT_DB_DPI_SFT 0 + uint32_t v; /* - * Indicates that the physical packet is shorter than that - * claimed by the UDP header length for a UDP packet that is - * not fragmented. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12) + #define NQ_DBQ_EVENT_V UINT32_C(0x1) + uint32_t db_type_db_xid; /* - * Indicates that TCP header length > IP payload. Valid for - * TCP packets only. + * DB 'XID' field from doorbell that crossed the async event + * threshold. This is a QPID, SID, or CID, depending on + * the db_type field. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12) - /* Indicates that TCP header length < 5. Valid for TCP. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12) + #define NQ_DBQ_EVENT_DB_XID_MASK UINT32_C(0xfffff) + #define NQ_DBQ_EVENT_DB_XID_SFT 0 /* - * Indicates that TCP option headers result in a TCP header - * size that does not match data offset in TCP header. Valid - * for TCP. + * DB 'type' field from doorbell that crossed the async event + * threshold. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN + #define NQ_DBQ_EVENT_DB_TYPE_MASK UINT32_C(0xf0000000) + #define NQ_DBQ_EVENT_DB_TYPE_SFT 28 +} nq_dbq_event_t, *pnq_dbq_event_t; + +/* + * This completion indicates that the NQ Reassign doorbell has been + * executed by the CQ processing block and no further NQE will arrive + * for this CQ on this NQ. + */ +/* nq_reassign (size:128b/16B) */ + +typedef struct nq_reassign { + uint16_t type; /* - * This field identifies the CFA action rule that was used for this - * packet. + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B records. */ - uint16_t raweth_qp1_cfa_code; + #define NQ_REASSIGN_TYPE_MASK UINT32_C(0x3f) + #define NQ_REASSIGN_TYPE_SFT 0 + /* NQ Reassign Notification */ + #define NQ_REASSIGN_TYPE_NQ_REASSIGN UINT32_C(0x3c) + #define NQ_REASSIGN_TYPE_LAST NQ_REASSIGN_TYPE_NQ_REASSIGN + uint16_t reserved16; /* * This is an application level ID used to identify the - * QP and its SQ and RQ. + * CQ. This field carries the lower 32b of the value. */ - uint64_t qp_handle; - uint32_t raweth_qp1_flags2; + uint32_t cq_handle_low; + uint32_t v; /* - * This indicates that the ip checksum was calculated for the - * inner packet and that the ip_cs_error field indicates if there - * was an error. + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC UINT32_C(0x1) + #define NQ_REASSIGN_V UINT32_C(0x1) /* - * This indicates that the TCP, UDP or ICMP checksum was - * calculated for the inner packet and that the l4_cs_error field - * indicates if there was an error. + * This is an application level ID used to identify the + * CQ. This field carries the upper 32b of the value. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC UINT32_C(0x2) + uint32_t cq_handle_high; +} nq_reassign_t, *pnq_reassign_t; + +/* Input Read Request Queue (IRRQ) Message */ +/* xrrq_irrq (size:256b/32B) */ + +typedef struct xrrq_irrq { + uint16_t credits_type; + /* Type indication */ + #define XRRQ_IRRQ_TYPE UINT32_C(0x1) + /* RDMA Read */ + #define XRRQ_IRRQ_TYPE_READ_REQ UINT32_C(0x0) + /* Atomic */ + #define XRRQ_IRRQ_TYPE_ATOMIC_REQ UINT32_C(0x1) + #define XRRQ_IRRQ_TYPE_LAST XRRQ_IRRQ_TYPE_ATOMIC_REQ /* - * This indicates that the ip checksum was calculated for the - * tunnel header and that the t_ip_cs_error field indicates if there - * was an error. + * The credit code calculated by Rx path when receiving the + * request. It will be placed in the syndrome credit code with + * the acks on first and last response. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) + #define XRRQ_IRRQ_CREDITS_MASK UINT32_C(0xf800) + #define XRRQ_IRRQ_CREDITS_SFT 11 + uint16_t reserved16; + uint32_t reserved32; + uint32_t psn; + /* The PSN of the outstanding incoming request */ + #define XRRQ_IRRQ_PSN_MASK UINT32_C(0xffffff) + #define XRRQ_IRRQ_PSN_SFT 0 + uint32_t msn; /* - * This indicates that the UDP checksum was - * calculated for the tunnel packet and that the t_l4_cs_error field - * indicates if there was an error. + * The value of QPC.pending_ack_msn after it is incremented as a + * result of receiving the read/atomic request. IRRQ.msn-1 will + * be placed in the MSN field of the first response and IRRQ.msn + * will placed in the MSN field of the last or only response. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) - /* This value indicates what format the raweth_qp1_metadata field is. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 - /* No metadata information. Value is zero. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4) + #define XRRQ_IRRQ_MSN_MASK UINT32_C(0xffffff) + #define XRRQ_IRRQ_MSN_SFT 0 /* - * The raweth_qp1_metadata field contains the VLAN tag and TPID value. - * - raweth_qp1_metadata[11:0] contains the vlan VID value. - * - raweth_qp1_metadata[12] contains the vlan DE value. - * - raweth_qp1_metadata[15:13] contains the vlan PRI value. - * - raweth_qp1_metadata[31:16] contains the vlan TPID value. + * Virtual address on local host for RDMA READ + * + * In case of duplicate Atomic, the VA is not required to + * be validated, only the PSN is, thus this field is used + * to store the value returned in the Ack to the atomic + * request, and if duplicate arrives, this value is used + * again for resending the ack. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4) + uint64_t va_or_atomic_result; + /* The key to the MR/W in the request */ + uint32_t rdma_r_key; /* - * If ext_meta_format is equal to 1, the metadata field - * contains the lower 16b of the tunnel ID value, justified - * to LSB - * - VXLAN = VNI[23:0] -> VXLAN Network ID - * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier. - * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0 - * - IPV4 = 0 (not populated) - * - IPV6 = Flow Label[19:0] - * - PPPoE = sessionID[15:0] - * - MPLs = Outer label[19:0] - * - UPAR = Selected[31:0] with bit mask + * Length in bytes of the data requested. Length must be 8 if type is + * atomic. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4) + uint32_t length; +} xrrq_irrq_t, *pxrrq_irrq_t; + +/* Output Read Request Queue (ORRQ) Message */ +/* xrrq_orrq (size:256b/32B) */ + +typedef struct xrrq_orrq { + uint16_t num_sges_type; + /* Type indication */ + #define XRRQ_ORRQ_TYPE UINT32_C(0x1) + /* RDMA Read */ + #define XRRQ_ORRQ_TYPE_READ_REQ UINT32_C(0x0) + /* Atomic */ + #define XRRQ_ORRQ_TYPE_ATOMIC_REQ UINT32_C(0x1) + #define XRRQ_ORRQ_TYPE_LAST XRRQ_ORRQ_TYPE_ATOMIC_REQ /* - * if ext_meta_format is equal to 1, metadata field contains - * 16b metadata from the prepended header (chdr_data). + * Up to 6 SGEs. This value is 1 if type is atomic as one + * SGE is required to store Atomic response result field. 2 + * more bits allocated for future growth. + * + * Note that, if num_sges is 1 for an RDMA Read request, then + * the first_sge_phy_or_sing_sge_va, single_sge_l_key, and + * single_sge_size fields will be populated from the single + * SGE. + * + * If num_sges is 2 or more for an RDMA Read request, then + * the first_sge_phy_or_sing_sge_va field carries the + * physical address in host memory where the first sge is + * stored. The single_sge_l_key and single_sge_size fields + * are unused in this case. + * + * A special case is a zero-length, zero-sge RDMA read request + * WQE. In this situation, num_sges will be 1. However, + * first_sge_phy_or_sing_sge_va, single_sge_l_key, and + * single_sge_size will all be populated with zeros. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4) + #define XRRQ_ORRQ_NUM_SGES_MASK UINT32_C(0xf800) + #define XRRQ_ORRQ_NUM_SGES_SFT 11 + uint16_t reserved16; /* - * If ext_meta_format is equal to 1, the metadata field contains - * the outer_l3_offset and lower 7 bits of the inner_l2_offset, - * - metadata[8:0] contains the outer_l3_offset. - * - metadata[15:9] contains the inner_l2_offset[6:0] + * Length in bytes of the data requested. Length must be 8 if type is + * atomic. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET + uint32_t length; + uint32_t psn; + /* The PSN of the outstanding outgoing request */ + #define XRRQ_ORRQ_PSN_MASK UINT32_C(0xffffff) + #define XRRQ_ORRQ_PSN_SFT 0 + uint32_t end_psn; /* - * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. - * This value is only valid if itype indicates a packet - * with an IP header. + * The expected last PSN on a response to this request where + * an ack with response, rather than just response, should + * arrive. If ack arrive with smaller PSN than end_psn then it + * is considered a NAK. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100) + #define XRRQ_ORRQ_END_PSN_MASK UINT32_C(0xffffff) + #define XRRQ_ORRQ_END_PSN_SFT 0 /* - * This indicates that the complete 1's complement checksum was - * calculated for the packet. + * If num_sges == 1 this is the va of that SGE. Otherwise, + * physical address to the first SGE specified by the WQE. + * Points to the first SGE in the Request's WQE in the SQ. + * It is assumed that WQE does not cross page boundaries! + * Driver is responsible to enforce that. SGEs are 16B + * aligned 0b0000 lsb added to get 64 bit address. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200) + uint64_t first_sge_phy_or_sing_sge_va; + /* The L_Key of a single SGE if used */ + uint32_t single_sge_l_key; + /* The size in bytes of the single SGE if used */ + uint32_t single_sge_size; +} xrrq_orrq_t, *pxrrq_orrq_t; + +/* Page Table Entry (PTE) */ +/* ptu_pte (size:64b/8B) */ + +typedef struct ptu_pte { + uint64_t page_next_to_last_last_valid; /* - * The combination of this value and meta_format indicated what - * format the metadata field is. + * This field indicates if the PTE is valid. A value of '0' + * indicates that the page is not valid. A value of '1' + * indicates that the page is valid. A reference to an + * invalid page will return a PTU error. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10 + #define PTU_PTE_VALID UINT32_C(0x1) /* - * This value is the complete 1's complement checksum calculated from - * the start of the outer L3 header to the end of the packet (not - * including the ethernet crc). It is valid when the - * 'complete_checksum_calc' flag is set. + * This field is used only for "ring" PBLs that are used for + * SQ, RQ, SRQ, or CQ structures. For all other PBL structures, + * this bit should be zero. When this bit is '1', it indicates + * that the page pointed to by this PTE is the last page in the + * ring. A prefetch for the ring should use the first PTE in + * the PBL. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + #define PTU_PTE_LAST UINT32_C(0x2) /* - * This is data from the CFA block as indicated by the meta_format - * field. + * This field is used only for "ring" PBLs that are used for + * SQ, RQ, SRQ, or CQ structures. For all other PBL structures, + * this bit should be zero. When this bit is '1', it indicates + * that this is the next-to-last page of the PBL. */ - uint32_t raweth_qp1_metadata; - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK UINT32_C(0xffff) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0 - /* When meta_format=1, this value is the VLAN VID. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK UINT32_C(0xfff) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0 - /* When meta_format=1, this value is the VLAN DE. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE UINT32_C(0x1000) - /* When meta_format=1, this value is the VLAN PRI. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK UINT32_C(0xe000) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13 - /* When meta_format=1, this value is the VLAN TPID. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK UINT32_C(0xffff0000) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16 - uint8_t cqe_type_toggle; + #define PTU_PTE_NEXT_TO_LAST UINT32_C(0x4) + /* These bits should be programmed to zero. */ + #define PTU_PTE_UNUSED_MASK UINT32_C(0xff8) + #define PTU_PTE_UNUSED_SFT 3 /* - * Indicate valid completion - written by the chip. Cumulus - * toggle this bit each time it finished consuming all PBL - * entries + * This is the upper bits of the physical page controlled by + * this PTE. If the page is larger than 4KB, then the unused + * lower bits of the page address should be zero. */ - #define CQ_RES_RAWETH_QP1_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1 + #define PTU_PTE_PAGE_MASK UINT32_C(0xfffffffffffff000)L + #define PTU_PTE_PAGE_SFT 12 +} ptu_pte_t, *pptu_pte_t; + +/* Page Directory Entry (PDE) */ +/* ptu_pde (size:64b/8B) */ + +typedef struct ptu_pde { + uint64_t page_valid; /* - * Responder RawEth and QP1 Completion - This is used for RQ - * completion for RawEth service and QP1 service QPs. + * This field indicates if the PTE is valid. A value of '0' + * indicates that the page is not valid. A value of '1' + * indicates that the page is valid. A reference to an + * invalid page will return a PTU error. */ - #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1) - #define CQ_RES_RAWETH_QP1_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 - /* This field indicates the status for the CQE. */ - uint8_t status; + #define PTU_PDE_VALID UINT32_C(0x1) + /* These bits should be programmed to zero. */ + #define PTU_PDE_UNUSED_MASK UINT32_C(0xffe) + #define PTU_PDE_UNUSED_SFT 1 /* - * This indicates that the completion is without error. - * All fields are valid. + * This is the upper bits of the physical page controlled by + * this PTE. If the page is larger than 4KB, then the unused + * lower bits of the page address should be zero. */ - #define CQ_RES_RAWETH_QP1_STATUS_OK UINT32_C(0x0) + #define PTU_PDE_PAGE_MASK UINT32_C(0xfffffffffffff000)L + #define PTU_PDE_PAGE_SFT 12 +} ptu_pde_t, *pptu_pde_t; + +/* + * This is the 64b doorbell format. The host writes this message + * format directly to byte offset 0 of the appropriate doorbell page. + */ +/* dbc_dbc (size:64b/8B) */ + +typedef struct dbc_dbc { + uint32_t index; /* - * This indicates that write access was not allowed for - * at least one of the SGEs in the WQE. + * This value is the index being written. * - * This is a fatal error. Only the srq_or_rq_wr_id is field - * is valid. - */ - #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) - /* - * This indicates that the packet was too long for the WQE - * provided on the RQ. + * For SQ, RQ, and SRQ, this is the producer index and the unit is + * 16B of queue space for L2 path and for the Engine path. For RoCE + * path there is a legacy mode with 128B unit size and a variable + * size WQE mode with 16B unit size of queue space. This mode is + * configured in the QP. + * + * For CQ this is the consumer index and the unit is 32B of queue + * space for the RoCE/Engine path and the CQ index unit is 16B of + * queue space for the L2 path. * - * This is not a fatal error. All the fields are valid. + * For NQ this is the consumer index and the unit is always 16B of + * queue space. + * + * The index size is 24b for L2 and engine paths and 16b for the + * RoCE path. Unused bits should be written as zero. */ - #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) - /* LOCAL_PROTECTION_ERR is 3 */ - #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) - /* LOCAL_QP_OPERATION_ERR is 4 */ - #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) - /* MEMORY_MGT_OPERATION_ERR is 5 */ - #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) - /* WORK_REQUEST_FLUSHED_ERR is 7 */ - #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) - /* HW_FLUSH_ERR is 8 */ - #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR UINT32_C(0x8) - #define CQ_RES_RAWETH_QP1_STATUS_LAST CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR - uint16_t flags; + #define DBC_DBC_INDEX_MASK UINT32_C(0xffffff) + #define DBC_DBC_INDEX_SFT 0 /* - * This flag indicates that the completion is for a SRQ entry - * rather than for an RQ entry. + * The epoch bit provides a frame of reference for the queue index. + * S/W will toggle this bit in the doorbell each time index range is + * wrapped. This allows the receiving HW block to more efficiently + * detect out-of-order doorbells and to ignore the older doorbells. + * Out-of-order doorbells occur normally during dropped doorbell + * recovery. */ - #define CQ_RES_RAWETH_QP1_FLAGS_SRQ UINT32_C(0x1) - /* CQE relates to RQ WQE. */ - #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ UINT32_C(0x0) - /* CQE relates to SRQ WQE. */ - #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ UINT32_C(0x1) - #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ - uint32_t raweth_qp1_payload_offset_srq_or_rq_wr_id; - /* - * Opaque value from RQ or SRQ WQE. Used by driver/lib to - * reference the WQE in order to claim the received data - * and reuse the WQE space + #define DBC_DBC_EPOCH UINT32_C(0x1000000) + /* + * The toggle value is used in CQ_ARMENA, CQ_ARMSE, CQ_ARMALL, + * SRQ_ARMENA, SRQ_ARM, and CQ_CUTOFF_ACK doorbells to qualify the + * doorbell as valid. This value should be taken from the latest + * NQE or cutoff completion. + * + * Doorbells of the above types with the wrong toggle value will + * be ignored. This is how old values in of backup doorbells + * are ignored. */ - #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) - #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0 + #define DBC_DBC_TOGGLE_MASK UINT32_C(0x6000000) + #define DBC_DBC_TOGGLE_SFT 25 + uint32_t type_path_xid; /* - * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, - * FCoE, and RoCE packets. + * This value identifies the resource that the doorbell is intended + * to notify. * - * A value of zero indicates an offset of 256 bytes. + * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For + * CQ, this is the CID. For NQ, this is the NID. + * + * Bits [19:16] of this values must be zero for a SID value. */ - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000) - #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 -} cq_res_raweth_qp1_t, *pcq_res_raweth_qp1_t; - -/* Responder RawEth and QP1 CQE version 2 */ -/* cq_res_raweth_qp1_v2 (size:256b/32B) */ - -typedef struct cq_res_raweth_qp1_v2 { - uint16_t length; + #define DBC_DBC_XID_MASK UINT32_C(0xfffff) + #define DBC_DBC_XID_SFT 0 /* - * The length of the message's payload in bytes, stored in - * the SGEs + * This value defines the intended doorbell path between RoCE and + * L2. */ - #define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK UINT32_C(0x3fff) - #define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0 - uint16_t raweth_qp1_flags; - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK UINT32_C(0x3ff) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0 + #define DBC_DBC_PATH_MASK UINT32_C(0x3000000) + #define DBC_DBC_PATH_SFT 24 + /* This is a RoCE doorbell message. */ + #define DBC_DBC_PATH_ROCE (UINT32_C(0x0) << 24) + /* This is a L2 doorbell message. */ + #define DBC_DBC_PATH_L2 (UINT32_C(0x1) << 24) + /* Engine path doorbell. */ + #define DBC_DBC_PATH_ENGINE (UINT32_C(0x2) << 24) + #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * raweth_qp1_errors. + * This indicates it is valid doorbell update. It should be set for + * each doorbell written to the chip and set when doorbell message is + * written to the backup doorbell location. The bit should be cleared + * in the backup doorbell location at time zero to indicate that the + * backup doorbell has not yet been written. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1) + #define DBC_DBC_VALID UINT32_C(0x4000000) /* - * This value indicates what the inner packet determined for the - * packet was. + * When this bit is set to one, the chip will capture debug + * information for the doorbell ring. This is intended to only be + * used on SQ doorbell rings. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK UINT32_C(0x3c0) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_SFT 6 + #define DBC_DBC_DEBUG_TRACE UINT32_C(0x8000000) + /* This value identifies the type of doorbell being written. */ + #define DBC_DBC_TYPE_MASK UINT32_C(0xf0000000) + #define DBC_DBC_TYPE_SFT 28 /* - * Not Known: - * Indicates that the packet type was not known. + * This is a SQ producer index update. It indicates one or more + * new entries have been written to the SQ for the QPID indicated + * on the xID field. This type is valid for L2, RoCE and Engine + * path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6) + #define DBC_DBC_TYPE_SQ (UINT32_C(0x0) << 28) /* - * IP Packet: - * Indicates that the packet was an IP packet, but further - * classification was not possible. + * This is a RQ producer index update. It indicates one or more + * new entries have been written to the RQ for the QPID indicated + * on the xID field. This type is valid for RoCE path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (UINT32_C(0x1) << 6) + #define DBC_DBC_TYPE_RQ (UINT32_C(0x1) << 28) /* - * TCP Packet: - * Indicates that the packet was IP and TCP. - * This indicates that the raweth_qp1_payload_offset field is - * valid. + * This is a SRQ producer index update. It indicates one or more + * new entries have been written to the SRQ for the SID indicated + * on the xID field. This type is valid for L2 and RoCE path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 6) + #define DBC_DBC_TYPE_SRQ (UINT32_C(0x2) << 28) /* - * UDP Packet: - * Indicates that the packet was IP and UDP. - * This indicates that the raweth_qp1_payload_offset field is - * valid. + * This doorbell command arms the SRQ async event. + * The xID field must identify the SID that is begin armed. + * The index field is will set the arm threshold such that + * a notification will be generated if less than that number + * or SRQ entries are posted. This type is valid for RoCE path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 6) + #define DBC_DBC_TYPE_SRQ_ARM (UINT32_C(0x3) << 28) /* - * FCoE Packet: - * Indicates that the packet was recognized as a FCoE. - * This also indicates that the raweth_qp1_payload_offset field - * is valid. + * This is a CQ consumer index update. It indicates one or more + * entries have been processed off the CQ indicated on the xID + * field.This type is valid for L2, RoCE and Engine path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 6) + #define DBC_DBC_TYPE_CQ (UINT32_C(0x4) << 28) /* - * RoCE Packet: - * Indicates that the packet was recognized as a RoCE. - * This also indicates that the raweth_qp1_payload_offset field - * is valid. + * this is a CQ consumer index update that also arms the CQ for + * solicited events. This type is valid for RoCE path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 6) + #define DBC_DBC_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28) /* - * ICMP Packet: - * Indicates that the packet was recognized as ICMP. - * This indicates that the raweth_qp1_payload_offset field is - * valid. + * This is a CQ consumer index update that also arms the CQ + * for any new CQE. This type is valid for L2, RoCE and Engine + * path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 6) + #define DBC_DBC_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28) /* - * PtP packet wo/timestamp: - * Indicates that the packet was recognized as a PtP - * packet. + * This is a CQ arm enable message. This message must be sent + * from the privileged driver before a new CQ_ARMSE or CQ_ARMALL + * message will be accepted. + * + * This doorbell can only be sent from the privileged (first) + * doorbell page of a function. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6) + #define DBC_DBC_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28) /* - * PtP packet w/timestamp: - * Indicates that the packet was recognized as a PtP - * packet and that a timestamp was taken for the packet. + * This doorbell command enables the SRQ async event + * to be armed. This message must be sent from the privileged + * driver before a new SRQ_ARM message will be accepted. + * The xID field must identify the SID that is begin enabled + * for arm. + * + * This doorbell can only be sent from the privileged (first) + * doorbell page of a function. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP - uint16_t raweth_qp1_errors; + #define DBC_DBC_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28) /* - * This indicates that there was an error in the IP header - * checksum. + * This doorbell command indicates that the cutoff CQE has + * been processed and the driver is now processing completions + * from the new CQ. + * + * The index field for this doorbell type must be zero. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10) + #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9) << 28) /* - * This indicates that there was an error in the TCP, UDP - * or ICMP checksum. + * This is a NQ consumer index update. It indicates one or more + * entries have been processed off the NQ indicated on the xID + * field. This type is valid for L2, RoCE and Engine path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20) + #define DBC_DBC_TYPE_NQ (UINT32_C(0xa) << 28) /* - * This indicates that there was an error in the tunnel - * IP header checksum. + * This is a NQ consumer index update that also arms the NQ for + * any new NQE. This type is valid for L2, RoCE and Engine path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40) + #define DBC_DBC_TYPE_NQ_ARM (UINT32_C(0xb) << 28) /* - * This indicates that there was an error in the tunnel - * UDP checksum. + * This is a NQ consumer index update that also arms the NQ for + * any new NQE. It is used for the legacy INT mask. This type + * is valid for L2, RoCE and Engine path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80) + #define DBC_DBC_TYPE_NQ_MASK (UINT32_C(0xe) << 28) /* - * This indicates that there was a CRC error on either an FCoE - * or RoCE packet. The itype indicates the packet type. + * This doorbell command is used during doorbell moderation + * to consume system BW and help prevent doorbell FIFO + * overflow. + * + * All other fields should be zero for NULL doorbell. + * For doorbell recovery, NULL doorbell type in the Application + * table indicates that it is the last QP entry for the function. + * This type is valid for L2, RoCE and Engine path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100) + #define DBC_DBC_TYPE_NULL (UINT32_C(0xf) << 28) + #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL +} dbc_dbc_t, *pdbc_dbc_t; + +/* + * This is the 32b doorbell format. The host writes this message + * format directly to byte offset 8 of the appropriate doorbell page. + */ +/* dbc_dbc32 (size:32b/4B) */ + +typedef struct dbc_dbc32 { + uint32_t type_abs_incr_xid; /* - * This indicates that there was an error in the tunnel - * portion of the packet when this - * field is non-zero. + * This value identifies the resource that the doorbell is intended + * to notify. + * + * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For + * CQ, this is the CID. + * + * Bits [19:16] of this values must be zero for a SID value. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 + #define DBC_DBC32_XID_MASK UINT32_C(0xfffff) + #define DBC_DBC32_XID_SFT 0 /* - * No additional error occurred on the tunnel portion - * of the packet of the packet does not have a tunnel. + * This value defines the intended doorbell path between RoCE and + * L2. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9) + #define DBC_DBC32_PATH_MASK UINT32_C(0xc00000) + #define DBC_DBC32_PATH_SFT 22 + /* This is a RoCE doorbell message. */ + #define DBC_DBC32_PATH_ROCE (UINT32_C(0x0) << 22) + /* This is a L2 doorbell message. */ + #define DBC_DBC32_PATH_L2 (UINT32_C(0x1) << 22) + #define DBC_DBC32_PATH_LAST DBC_DBC32_PATH_L2 /* - * Indicates that IP header version does not match - * expectation from L2 Ethertype for IPv4 and IPv6 - * in the tunnel header. + * When abs=0, this value is the value to add to the appropriate + * index value. + * + * When abs=1, this value is the new value for the index. Absolute + * value is used when the queue is being wrapped. When abs=1, + * the incr value follows the same rules as the index value + * in the 64b doorbell. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9) + #define DBC_DBC32_INCR_MASK UINT32_C(0xf000000) + #define DBC_DBC32_INCR_SFT 24 + /* This value defines how the incr value will be interpreted. */ + #define DBC_DBC32_ABS UINT32_C(0x10000000) + /* This value identifies the type of doorbell being written. */ + #define DBC_DBC32_TYPE_MASK UINT32_C(0xe0000000) + #define DBC_DBC32_TYPE_SFT 29 /* - * Indicates that header length is out of range in the - * tunnel header. Valid for - * IPv4. + * This is a SQ producer index update. It indicates one or more + * new entries have been written to the SQ for the QPID + * indicated on the xID field. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9) + #define DBC_DBC32_TYPE_SQ (UINT32_C(0x0) << 29) + #define DBC_DBC32_TYPE_LAST DBC_DBC32_TYPE_SQ +} dbc_dbc32_t, *pdbc_dbc32_t; + +/* + * This is the 64b Push Start doorbell format. The host writes this + * message format directly to offset of each push associated WCB (write + * combine buffer) within doorbell page. WCB#0 = offset 16, WCB#1 = + * offset 24, WCB#2 = offset 32, ... The start doorbell is followed by + * write combining data to the WCB and then that is followed by a end + * doorbell. + */ +/* db_push_start (size:64b/8B) */ + +typedef struct db_push_start { + uint64_t db; /* - * Indicates that the physical packet is shorter than that - * claimed by the PPPoE header length for a tunnel PPPoE - * packet. + * This is the push index and should be the SQ slot index, + * aligned to the start of the corresponding push WQE/packet in + * the Send Queue. + * + * The index size is 16b for RoCE path and 24b for L2 and Engine + * paths. Any unused bits should be written as zero. + * + * The index unit is 16B for L2 path. For RoCE there is a legacy + * mode with 128B unit size and a variable size mode with 16B + * unit size. For Engine mode, the unit size is 16B, where RQEs + * are always 128B - so it always increments by eight 16B slots + * per RQE. + * + * > This field is not used by the older versions of the chip, + * > but is used in this and future revisions of the chip. In + * > older versions of the chip, the driver is required to + * > complete the push doorbell operation by following it with a + * > regular doorbell which will be used to properly increment + * > the producer index. This extra doorbell write is not needed + * > on this and future versions of the chip. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9) + #define DB_PUSH_START_DB_INDEX_MASK UINT32_C(0xffffff) + #define DB_PUSH_START_DB_INDEX_SFT 0 /* - * Indicates that physical packet is shorter than that claimed - * by the tunnel l3 header length. Valid for IPv4, or IPv6 - * tunnel packet packets. + * This value is the PI index (lower 8bits) within 4K DPI + * associated with push write. It is the doorbell page that + * contains the WCB that will be used. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9) + #define DB_PUSH_START_DB_PI_LO_MASK UINT32_C(0xff000000) + #define DB_PUSH_START_DB_PI_LO_SFT 24 /* - * Indicates that the physical packet is shorter than that - * claimed by the tunnel UDP header length for a tunnel - * UDP packet that is not fragmented. + * This value identifies the resource that the doorbell is + * intended to notify. + * + * This is the QPID. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9) + #define DB_PUSH_START_DB_XID_MASK UINT32_C(0xfffff00000000)L + #define DB_PUSH_START_DB_XID_SFT 32 /* - * indicates that the IPv4 TTL or IPv6 hop limit check - * have failed (e.g. TTL = 0) in the tunnel header. Valid - * for IPv4, and IPv6. + * This value is the PI index (upper 4bits) within 4K DPI + * associated with push write. It is the doorbell page that + * contains the WCB that will be used. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL + #define DB_PUSH_START_DB_PI_HI_MASK UINT32_C(0xf0000000000000)L + #define DB_PUSH_START_DB_PI_HI_SFT 52 + /* This value identifies the type of doorbell being written. */ + #define DB_PUSH_START_DB_TYPE_MASK UINT32_C(0xf000000000000000)L + #define DB_PUSH_START_DB_TYPE_SFT 60 /* - * This indicates that there was an error in the inner - * portion of the packet when this - * field is non-zero. + * This is a SQ producer index update for Push. It indicates + * one or more new entries have been written to the SQ for + * the QPID indicated on the `xid` field. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 + #define DB_PUSH_START_DB_TYPE_PUSH_START (UINT32_C(0xc)L << 60) /* - * No additional error occurred on the tunnel portion - * of the packet of the packet does not have a tunnel. + * This is a SQ producer index update for Push. It indicates + * one or more new entries have been written to the SQ for + * the QPID indicated on the `xid` field. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12) + #define DB_PUSH_START_DB_TYPE_PUSH_END (UINT32_C(0xd)L << 60) + #define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END +} db_push_start_t, *pdb_push_start_t; + +/* + * This is the 64b Push End doorbell format. The host writes this message + * format directly to offset of each push associated WCB (write combine + * buffer) within doorbell page. WCB#0 = offset 16, WCB#1 = offset 24, + * WCB#2 = offset 32, ... The start doorbell is followed by write + * combining data to the WCB and then that is followed by a end doorbell. + */ +/* db_push_end (size:64b/8B) */ + +typedef struct db_push_end { + uint64_t db; /* - * Indicates that IP header version does not match - * expectation from L2 Ethertype for IPv4 and IPv6 or that - * option other than VFT was parsed on - * FCoE packet. + * This is the producer index and should be the queue index of + * the last WQE written plus the length field contained in that + * WQE. For example, if the length is 8 index units and the WQE + * was written to the first location in the queue (zero), this + * index should be written to 8. The index should point to the + * start of the first location that has not been filled in with + * WQE data. + * + * For L2 and Engine SQ, the index unit is 16B. For RoCE there + * are two modes. For Legacy fixed size RQE mode, the unit is + * 128B. For variable size RQE mode, the unit is 16B. + * + * The index size is 24b for L2 and engine paths and 16b for the + * RoCE path. Unused bits should be written as zero. + * + * > In past revisions of this chip, this field was the push + * > index rather than the producer index. For this version of + * > the chip and future versions of the chip, this field must be + * > the producer index, as described above. + * > + * > Also, in past revisions of this chip, an additional + * > doorbell write was needed to communicate the producer index. + * > In this and future versions of the chip, this extra doorbell + * > write is no longer needed. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12) + #define DB_PUSH_END_DB_INDEX_MASK UINT32_C(0xffffff) + #define DB_PUSH_END_DB_INDEX_SFT 0 /* - * indicates that header length is out of range. Valid for - * IPv4 and RoCE + * This value is the PI index (lower 8bits) within 4K DPI + * associated with push write. It is the doorbell page that + * contains the WCB that will be used. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12) + #define DB_PUSH_END_DB_PI_LO_MASK UINT32_C(0xff000000) + #define DB_PUSH_END_DB_PI_LO_SFT 24 /* - * indicates that the IPv4 TTL or IPv6 hop limit check - * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 + * This value identifies the resource that the doorbell is + * intended to notify. + * + * This is the QPID. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12) + #define DB_PUSH_END_DB_XID_MASK UINT32_C(0xfffff00000000)L + #define DB_PUSH_END_DB_XID_SFT 32 /* - * Indicates that physical packet is shorter than that - * claimed by the l3 header length. Valid for IPv4, - * IPv6 packet or RoCE packets. + * This value is the PI index (upper 4bits) within 4K DPI + * associated with push write. It is the doorbell page that + * contains the WCB that will be used. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12) + #define DB_PUSH_END_DB_PI_HI_MASK UINT32_C(0xf0000000000000)L + #define DB_PUSH_END_DB_PI_HI_SFT 52 /* - * Indicates that the physical packet is shorter than that - * claimed by the UDP header length for a UDP packet that is - * not fragmented. + * This value defines the intended doorbell path between RoCE and + * L2. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12) + #define DB_PUSH_END_DB_PATH_MASK UINT32_C(0x300000000000000)L + #define DB_PUSH_END_DB_PATH_SFT 56 + /* This is a RoCE doorbell message. */ + #define DB_PUSH_END_DB_PATH_ROCE (UINT32_C(0x0)L << 56) + /* This is a L2 doorbell message. */ + #define DB_PUSH_END_DB_PATH_L2 (UINT32_C(0x1)L << 56) + /* Engine path doorbell. */ + #define DB_PUSH_END_DB_PATH_ENGINE (UINT32_C(0x2)L << 56) + #define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE /* - * Indicates that TCP header length > IP payload. Valid for - * TCP packets only. + * When this bit is set to one, the chip will capture debug + * information for the doorbell ring. This is intended to only be + * used on SQ doorbell rings. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12) - /* Indicates that TCP header length < 5. Valid for TCP. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12) + #define DB_PUSH_END_DB_DEBUG_TRACE UINT32_C(0x800000000000000)L + /* This value identifies the type of doorbell being written. */ + #define DB_PUSH_END_DB_TYPE_MASK UINT32_C(0xf000000000000000)L + #define DB_PUSH_END_DB_TYPE_SFT 60 /* - * Indicates that TCP option headers result in a TCP header - * size that does not match data offset in TCP header. Valid - * for TCP. + * This is a SQ producer index update for Push. It indicates + * one or more new entries have been written to the SQ for + * the QPID indicated on the `xid` field. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN - /* This is data from the CFA as indicated by the meta_format field. */ - uint16_t cfa_metadata0; - /* When meta_format=1, this value is the VLAN VID. */ - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff) - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0 - /* When meta_format=1, this value is the VLAN DE. */ - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE UINT32_C(0x1000) - /* When meta_format=1, this value is the VLAN PRI. */ - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000) - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_SFT 13 + #define DB_PUSH_END_DB_TYPE_PUSH_START (UINT32_C(0xc)L << 60) /* - * This is an application level ID used to identify the - * QP and its SQ and RQ. + * This is a SQ producer index update for Push. It indicates + * one or more new entries have been written to the SQ for + * the QPID indicated on the `xid` field. */ - uint64_t qp_handle; - uint32_t raweth_qp1_flags2; + #define DB_PUSH_END_DB_TYPE_PUSH_END (UINT32_C(0xd)L << 60) + #define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END +} db_push_end_t, *pdb_push_end_t; + +/* + * This is the Push information that is the second 8B of the Push + * Doorbell. + */ +/* db_push_info (size:64b/8B) */ + +typedef struct db_push_info { + uint32_t push_size_push_index; /* - * When this bit is '0', the cs_ok field has the following - * definition:- ip_cs_ok[2:0] = The number of header groups with a - * valid IP checksum in the delivered packet, counted from the - * outer-most header group to the inner-most header group, stopping - * at the first error. - l4_cs_ok[5:3] = The number of header groups - * with a valid L4 checksum in the delivered packet, counted from - * the outer-most header group to the inner-most header group, - * stopping at the first error. When this bit is '1', the cs_ok - * field has the following definition: - hdr_cnt[2:0] = The number of - * header groups that were parsed by the chip and passed in the - * delivered packet. - ip_cs_all_ok[3] =This bit will be '1' if all - * the parsed header groups with an IP checksum are valid. - * - l4_cs_all_ok[4] = This bit will be '1' if all the parsed header - * groups with an L4 checksum are valid. + * This value is the index for the push being started. For + * example, if the push_size is 8 index units and the WQE was + * written to the first location in the queue (zero), this + * push_index should be written to 0. The push_index should point + * to the start of the first location that the push is started. + * + * The push_index unit is 16B, except in RoCE legacy WQE mode, in + * which case the unit is 128B. + * + * The push_index size is 24b for L2 and 16b for the RoCE path. + * Unused bits should be written as zero. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE UINT32_C(0x8) - /* This value indicates what format the metadata field is. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 - /* There is no metadata information. Values are zero. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4) + #define DB_PUSH_INFO_PUSH_INDEX_MASK UINT32_C(0xffffff) + #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 + /* + * This value defines the size of push. The unit is 8B. The value + * 0 means 256B size of push. The push write is done in 8B units + * by the SW. + * + * Note: For packet rate performance reasons, it is recommended + * that SW aligns push requests with a granularity of 16B. + */ + #define DB_PUSH_INFO_PUSH_SIZE_MASK UINT32_C(0x1f000000) + #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 + uint32_t reserved32; +} db_push_info_t, *pdb_push_info_t; + +/* + * This is the "Absolute" 32b Doorbell format. The host writes this + * message format directly to byte offset 0xC of the appropriate + * doorbell page. + * + * Absolute doorbells are supported for only a limited number of + * functions and for a limited number of xID values within each + * function. + * + * Doorbell recovery can be supported for absolute 32b doorbells. + */ +/* dbc_absolute_db_32 (size:32b/4B) */ + +typedef struct dbc_absolute_db_32 { + uint32_t index; + /* + * This value is the index being written. For SQ, RQ, SRQ, this is + * the producer index and should be the queue index of the last WQE + * or BD written plus the length field contained in that WQE/BD. + * For example, if the length is 8 index units and the WQE was + * written to the first location in the queue (zero), this index + * should be written to 8. The index should point to the start of + * the first location that has not been filled in with WQE/BD data. + * + * For CQ, this is the consumer index and should be the starting + * queue index of the last CQE processed plus the size of the last + * processed CQE in index units. The index should point to the start + * of the first CQE in the queue that has not been processed. + * + * For NQ, this is the consumer index and should be the starting + * queue index of the last NQE processed plus the size of the last + * processed NQE in index units. The index should point to the start + * of the first NQE in the queue that has not been processed. + * + * For L2 and Engine SQ, the index unit is 16B. For RoCE there are + * two modes. For Legacy fixed size RQE mode, the unit is 128B. For + * variable size RQE mode, the unit is 16B. For RoCE and engine CQs, + * the index unit is 32B. For L2 CQs, the index unit is 16B. + * + * For NQ this is the consumer index and the unit is always 16B of + * queue space. + * + * The index size is 16b for all queue types. This limits the size + * of some queues when absolute doorbells are in use. Unused bits + * should be written as zero. + */ + #define DBC_ABSOLUTE_DB_32_INDEX_MASK UINT32_C(0xffff) + #define DBC_ABSOLUTE_DB_32_INDEX_SFT 0 /* - * The {metadata1, metadata0} fields contain the vtag - * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], - * de, vid[11:0]} The metadata2 field contains the table scope - * and action record pointer. - metadata2[25:0] contains the - * action record pointer. - metadata2[31:26] contains the table - * scope. + * The epoch bit provides a frame of reference for the queue index. + * S/W will toggle this bit in the doorbell each time index range is + * wrapped. This allows the receiving HW block to more efficiently + * detect out-of-order doorbells and to ignore the older doorbells. + * Out-of-order doorbells occur normally during dropped doorbell + * recovery. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4) + #define DBC_ABSOLUTE_DB_32_EPOCH UINT32_C(0x10000) /* - * The {metadata1, metadata0} fields contain the vtag - * information: - * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} - * The metadata2 field contains the Tunnel ID - * value, justified to LSB. i - * - VXLAN = VNI[23:0] -> VXLAN Network ID - * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier - * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 - * - IPv4 = 0 (not populated) - * - IPv6 = Flow Label[19:0] - * - PPPoE = sessionID[15:0] - * - MPLs = Outer label[19:0] - * - UPAR = Selected[31:0] with bit mask + * The toggle value is used in CQ_ARMENA, CQ_ARMSE, CQ_ARMALL, + * SRQ_ARMENA, SRQ_ARM, and CQ_CUTOFF_ACK doorbells to qualify the + * doorbell as valid. This value should be taken from the latest NQE + * or cutoff completion. + * + * Doorbells of the above types with the wrong toggle value will be + * ignored. This is how old values in of backup doorbells are + * ignored. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4) + #define DBC_ABSOLUTE_DB_32_TOGGLE_MASK UINT32_C(0x60000) + #define DBC_ABSOLUTE_DB_32_TOGGLE_SFT 17 /* - * The {metadata1, metadata0} fields contain the vtag - * information: - * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} - * The metadata2 field contains the 32b metadata from the prepended - * header (chdr_data). + * This value identifies the resource that the doorbell is intended + * to notify. + * + * This is a "modified" xID value. The DBR block will convert this + * value into the full xID value by looking up the base xID for this + * particular function and adding the mxID value to that base value. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4) + #define DBC_ABSOLUTE_DB_32_MXID_MASK UINT32_C(0x1f80000) + #define DBC_ABSOLUTE_DB_32_MXID_SFT 19 /* - * The {metadata1, metadata0} fields contain the vtag - * information: - * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} - * The metadata2 field contains the outer_l3_offset, - * inner_l2_offset, inner_l3_offset, and inner_l4_size. - * - metadata2[8:0] contains the outer_l3_offset. - * - metadata2[17:9] contains the inner_l2_offset. - * - metadata2[26:18] contains the inner_l3_offset. - * - metadata2[31:27] contains the inner_l4_size. + * This value defines the intended doorbell path between RoCE and + * L2. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET + #define DBC_ABSOLUTE_DB_32_PATH_MASK UINT32_C(0x6000000) + #define DBC_ABSOLUTE_DB_32_PATH_SFT 25 + /* This is a RoCE doorbell message. */ + #define DBC_ABSOLUTE_DB_32_PATH_ROCE (UINT32_C(0x0) << 25) + /* This is a L2 doorbell message. */ + #define DBC_ABSOLUTE_DB_32_PATH_L2 (UINT32_C(0x1) << 25) + #define DBC_ABSOLUTE_DB_32_PATH_LAST DBC_ABSOLUTE_DB_32_PATH_L2 /* - * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. - * This value is only valid if itype indicates a packet - * with an IP header. + * This indicates it is valid doorbell update. It should be set for + * each doorbell written to the chip and set when doorbell message is + * written to the backup doorbell location. The bit should be cleared + * in the backup doorbell location at time zero to indicate that the + * backup doorbell has not yet been written. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100) + #define DBC_ABSOLUTE_DB_32_VALID UINT32_C(0x8000000) + /* This value identifies the type of doorbell being written. */ + #define DBC_ABSOLUTE_DB_32_TYPE_MASK UINT32_C(0xf0000000) + #define DBC_ABSOLUTE_DB_32_TYPE_SFT 28 /* - * This indicates that the complete 1's complement checksum was - * calculated for the packet. + * This is a SQ producer index update. It indicates one or more + * new entries have been written to the SQ for the QPID indicated + * on the xID field. This type is valid for L2, RoCE and Engine + * path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200) + #define DBC_ABSOLUTE_DB_32_TYPE_SQ (UINT32_C(0x0) << 28) /* - * This field indicates the status of IP and L4 CS calculations done - * by the chip. The format of this field is indicated by the - * cs_all_ok_mode bit. + * This is a RQ producer index update. It indicates one or more + * new entries have been written to the RQ for the QPID indicated + * on the xID field. This type is valid for RoCE path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK UINT32_C(0xfc00) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_SFT 10 + #define DBC_ABSOLUTE_DB_32_TYPE_RQ (UINT32_C(0x1) << 28) /* - * This value is the complete 1's complement checksum calculated from - * the start of the outer L3 header to the end of the packet (not - * including the ethernet crc). It is valid when the - * 'complete_checksum_calc' flag is set. + * This is a SRQ producer index update. It indicates one or more + * new entries have been written to the SRQ for the SID indicated + * on the xID field. This type is valid for L2 and RoCE path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + #define DBC_ABSOLUTE_DB_32_TYPE_SRQ (UINT32_C(0x2) << 28) /* - * This is data from the CFA block as indicated by the meta_format - * field. - * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped - * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], - * act_rec_ptr[25:0]} - * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] - * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] - * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] - * When vee_cmpl_mode is set in VNIC context, this is the upper 32b - * of the host address from the first BD used to place the packet. + * This doorbell command arms the SRQ async event. + * The xID field must identify the SID that is begin armed. + * The index field is will set the arm threshold such that + * a notification will be generated if less than that number + * or SRQ entries are posted. This type is valid for RoCE path. */ - uint32_t cfa_metadata2; - uint8_t cqe_type_toggle; + #define DBC_ABSOLUTE_DB_32_TYPE_SRQ_ARM (UINT32_C(0x3) << 28) /* - * Indicate valid completion - written by the chip. Cumulus - * toggle this bit each time it finished consuming all PBL - * entries + * This is a CQ consumer index update. It indicates one or more + * entries have been processed off the CQ indicated on the xID + * field.This type is valid for L2, RoCE and Engine path. */ - #define CQ_RES_RAWETH_QP1_V2_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1 + #define DBC_ABSOLUTE_DB_32_TYPE_CQ (UINT32_C(0x4) << 28) /* - * Responder RawEth and QP1 Completion - This is used for RQ - * completion for RawEth service and QP1 service QPs. + * this is a CQ consumer index update that also arms the CQ for + * solicited events. This type is valid for RoCE path. */ - #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1) - #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 - /* This field indicates the status for the CQE. */ - uint8_t status; + #define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28) /* - * This indicates that the completion is without error. - * All fields are valid. + * This is a CQ consumer index update that also arms the CQ + * for any new CQE. This type is valid for L2, RoCE and Engine + * path. */ - #define CQ_RES_RAWETH_QP1_V2_STATUS_OK UINT32_C(0x0) + #define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28) /* - * This indicates that write access was not allowed for - * at least one of the SGEs in the WQE. + * This is a CQ arm enable message. This message must be sent from + * the privileged driver before a new CQ_ARMSE or CQ_ARMALL message + * will be accepted from user space (non-privileged doorbell page). + * The index and epoch for this doorbell type are unused. * - * This is a fatal error. Only the srq_or_rq_wr_id is field - * is valid. + * This doorbell can only be sent from the privileged (first) + * doorbell page of a function. */ - #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) + #define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28) /* - * This indicates that the packet was too long for the WQE - * provided on the RQ. + * This doorbell command enables the SRQ async event to be armed. + * This message must be sent from the privileged driver before a + * new SRQ_ARM message will be accepted from user space. + * The xID field must identify the SID that is being enabled for + * arm. The index and epoch for this doorbell type are unused. * - * This is not a fatal error. All the fields are valid. + * This doorbell can only be sent from the privileged (first) + * doorbell page of a function. */ - #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) - /* LOCAL_PROTECTION_ERR is 3 */ - #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3) - /* LOCAL_QP_OPERATION_ERR is 4 */ - #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) - /* MEMORY_MGT_OPERATION_ERR is 5 */ - #define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5) - /* WORK_REQUEST_FLUSHED_ERR is 7 */ - #define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7) - /* HW_FLUSH_ERR is 8 */ - #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8) - #define CQ_RES_RAWETH_QP1_V2_STATUS_LAST CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR - uint16_t flags; + #define DBC_ABSOLUTE_DB_32_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28) /* - * This flag indicates that the completion is for a SRQ entry - * rather than for an RQ entry. + * This is a NQ consumer index update. It indicates one or more + * entries have been processed off the NQ indicated on the xID + * field. This type is valid for L2, RoCE and Engine path. */ - #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ UINT32_C(0x1) - /* CQE relates to RQ WQE. */ - #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ UINT32_C(0x0) - /* CQE relates to SRQ WQE. */ - #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ UINT32_C(0x1) - #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ - uint32_t raweth_qp1_payload_offset_srq_or_rq_wr_id; + #define DBC_ABSOLUTE_DB_32_TYPE_NQ (UINT32_C(0xa) << 28) /* - * Opaque value from RQ or SRQ WQE. Used by driver/lib to - * reference the WQE in order to claim the received data - * and reuse the WQE space + * This is a NQ consumer index update that also arms the NQ for + * any new NQE. This type is valid for L2, RoCE and Engine path. */ - #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) - #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0 - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK UINT32_C(0xf00000) - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_SFT 20 - /* When meta_format != 0, this value is the VLAN TPID_SEL. */ - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000) - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_SFT 20 - /* 0x88a8 */ - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20) - /* 0x8100 */ - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20) - /* 0x9100 */ - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20) - /* 0x9200 */ - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20) - /* 0x9300 */ - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20) - /* Value programmed in CFA VLANTPID register. */ - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20) - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG - /* When meta_format != 0, this value is the VLAN valid. */ - #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID UINT32_C(0x800000) + #define DBC_ABSOLUTE_DB_32_TYPE_NQ_ARM (UINT32_C(0xb) << 28) /* - * This value indicates the offset in bytes from the beginning of - * the packet where the inner payload starts. This value is valid - * for TCP, UDP, FCoE, and RoCE packets. + * This is a NQ consumer index update that also arms the NQ for + * any new NQE. It is used for the legacy INT mask. This type + * is valid for L2, RoCE and Engine path. + */ + #define DBC_ABSOLUTE_DB_32_TYPE_NQ_MASK (UINT32_C(0xe) << 28) + /* + * This doorbell command is used during doorbell moderation + * to consume system BW and help prevent doorbell FIFO + * overflow. * - * A value of zero indicates an offset of 256 bytes. + * All other fields should be zero for NULL doorbell. + * For doorbell recovery, NULL doorbell type in the Application + * table indicates that it is the last QP entry for the function. + * This type is valid for L2, RoCE and Engine path. */ - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000) - #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 -} cq_res_raweth_qp1_v2_t, *pcq_res_raweth_qp1_v2_t; + #define DBC_ABSOLUTE_DB_32_TYPE_NULL (UINT32_C(0xf) << 28) + #define DBC_ABSOLUTE_DB_32_TYPE_LAST DBC_ABSOLUTE_DB_32_TYPE_NULL +} dbc_absolute_db_32_t, *pdbc_absolute_db_32_t; -/* Terminal CQE */ -/* cq_terminal (size:256b/32B) */ +/* + * This is the "Relative" 32b Doorbell format. The host writes this + * message format directly to byte offset 8 of the appropriate doorbell + * page. + * + * Doorbell recovery can not be supported for relative doorbells. So + * relative doorbells are only safe to use when SOC is supporting the + * context backing store in local DDR. If that is the case, it is safe + * to turn off doorbell drops and use this type of doorbell. + */ +/* dbc_relative_db_32 (size:32b/4B) */ -typedef struct cq_terminal { +typedef struct dbc_relative_db_32 { + uint32_t xid; /* - * This is an application level ID used to identify the - * QP and its SQ and RQ. + * This value identifies the resource that the doorbell is intended + * to notify. + * + * For SQ, this is the QPID value. */ - uint64_t qp_handle; + #define DBC_RELATIVE_DB_32_XID_MASK UINT32_C(0xfffff) + #define DBC_RELATIVE_DB_32_XID_SFT 0 /* - * Final SQ Consumer Index value. Any additional SQ WQEs will - * have to be completed by the user provider. + * This value defines the intended doorbell path between RoCE and + * L2. */ - uint16_t sq_cons_idx; + #define DBC_RELATIVE_DB_32_PATH_MASK UINT32_C(0xc00000) + #define DBC_RELATIVE_DB_32_PATH_SFT 22 + /* This is a RoCE doorbell message. */ + #define DBC_RELATIVE_DB_32_PATH_ROCE (UINT32_C(0x0) << 22) + /* This is a L2 doorbell message. */ + #define DBC_RELATIVE_DB_32_PATH_L2 (UINT32_C(0x1) << 22) + #define DBC_RELATIVE_DB_32_PATH_LAST DBC_RELATIVE_DB_32_PATH_L2 /* - * Final RQ Consumer Index value. Any additional RQ WQEs will - * have to be completed by the user provider. + * This value is the value to add to the appropriate index value. + * + * The increment unit is 16B for L2 path. For RoCE there is a + * legacy mode with 128B unit size and a variable size mode with + * 32B unit size. For Engine mode, the unit size is always 128B. */ - uint16_t rq_cons_idx; - uint32_t reserved32_1; - uint64_t reserved64_3; - uint8_t cqe_type_toggle; + #define DBC_RELATIVE_DB_32_INCR_MASK UINT32_C(0x1f000000) + #define DBC_RELATIVE_DB_32_INCR_SFT 24 + /* This value identifies the type of doorbell being written. */ + #define DBC_RELATIVE_DB_32_TYPE_MASK UINT32_C(0xe0000000) + #define DBC_RELATIVE_DB_32_TYPE_SFT 29 /* - * Indicate valid completion - written by the chip. Cumulus - * toggle this bit each time it finished consuming all PBL - * entries + * This is a SQ producer index update. It indicates one or more + * new entries have been written to the SQ for the QPID indicated + * on the xID field. This type is valid for L2, RoCE and Engine + * path. */ - #define CQ_TERMINAL_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_TERMINAL_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_TERMINAL_CQE_TYPE_SFT 1 + #define DBC_RELATIVE_DB_32_TYPE_SQ (UINT32_C(0x0) << 29) /* - * Terminal completion - This is used to indicate that no - * further completions will be made for this QP on this CQ. + * This is a SRQ producer index update. It indicates one or more + * new entries have been written to the SRQ for the SID indicated + * on the xID field. This type is valid for L2 and RoCE path. */ - #define CQ_TERMINAL_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1) - #define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL - /* This field indicates the status for the CQE. */ - uint8_t status; - /* OK is 0 */ - #define CQ_TERMINAL_STATUS_OK UINT32_C(0x0) - #define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK - uint16_t reserved16; - uint32_t reserved32_2; -} cq_terminal_t, *pcq_terminal_t; - -/* Cutoff CQE */ -/* cq_cutoff (size:256b/32B) */ - -typedef struct cq_cutoff { - uint64_t reserved64_1; - uint64_t reserved64_2; - uint64_t reserved64_3; - uint8_t cqe_type_toggle; + #define DBC_RELATIVE_DB_32_TYPE_SRQ (UINT32_C(0x1) << 29) /* - * Indicate valid completion - written by the chip. Cumulus - * toggle this bit each time it finished consuming all PBL - * entries + * This is a CQ consumer index update. It indicates one or more + * entries have been processed off the CQ indicated on the xID + * field.This type is valid for L2, RoCE and Engine path. */ - #define CQ_CUTOFF_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_CUTOFF_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_CUTOFF_CQE_TYPE_SFT 1 - /* Cut off CQE; for CQ resize see CQ and SRQ Resize */ - #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1) - #define CQ_CUTOFF_CQE_TYPE_LAST CQ_CUTOFF_CQE_TYPE_CUT_OFF + #define DBC_RELATIVE_DB_32_TYPE_CQ (UINT32_C(0x2) << 29) /* - * This field carries the toggle value that must be used to - * acknowledge this CQ resize operation. When this CQE is - * processed, the driver should send a CQ_CUTOFF_ACK doorbell - * to the chip to let the chip know that the resize operation - * is complete. This value is used by HW to detect old and - * stale CQ_CUTOFF_ACK doorbells that are caused by having - * a backup doorbell location or by PCI or other reordering - * problems. Only doorbells with the latest value will be honored. - * This field is needed only for devices that use the hardware - * based doorbell drop recovery feature. + * This is a CQ consumer index update that also arms the CQ + * for any new CQE. This type is valid for L2, RoCE and Engine + * path. */ - #define CQ_CUTOFF_RESIZE_TOGGLE_MASK UINT32_C(0x60) - #define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5 - /* This field indicates the status for the CQE. */ - uint8_t status; - /* OK is 0 */ - #define CQ_CUTOFF_STATUS_OK UINT32_C(0x0) - #define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK - uint16_t reserved16; - uint32_t reserved32; -} cq_cutoff_t, *pcq_cutoff_t; - -/* nq_base (size:128b/16B) */ - -typedef struct nq_base { - uint16_t info10_type; + #define DBC_RELATIVE_DB_32_TYPE_CQ_ARMALL (UINT32_C(0x3) << 29) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This is a NQ consumer index update. It indicates one or more + * entries have been processed off the NQ indicated on the xID + * field. This type is valid for L2, RoCE and Engine path. */ - #define NQ_BASE_TYPE_MASK UINT32_C(0x3f) - #define NQ_BASE_TYPE_SFT 0 - /* CQ Notification */ - #define NQ_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30) - /* SRQ Threshold Event */ - #define NQ_BASE_TYPE_SRQ_EVENT UINT32_C(0x32) - /* DBQ Threshold Event */ - #define NQ_BASE_TYPE_DBQ_EVENT UINT32_C(0x34) - /* QP Async Notification */ - #define NQ_BASE_TYPE_QP_EVENT UINT32_C(0x38) - /* Function Async Notification */ - #define NQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a) - #define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_FUNC_EVENT - /* info10 is 10 b */ - #define NQ_BASE_INFO10_MASK UINT32_C(0xffc0) - #define NQ_BASE_INFO10_SFT 6 - /* info16 is 16 b */ - uint16_t info16; - /* info32 is 32 b */ - uint32_t info32; - /* info32 is 32 b */ - uint64_t info63_v; + #define DBC_RELATIVE_DB_32_TYPE_NQ (UINT32_C(0x4) << 29) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This is a NQ consumer index update that also arms the NQ for + * any new NQE. This type is valid for L2, RoCE and Engine path. */ - #define NQ_BASE_V UINT32_C(0x1) - /* info63 is 63 b */ - #define NQ_BASE_INFO63_MASK UINT32_C(0xfffffffe) - #define NQ_BASE_INFO63_SFT 1 -} nq_base_t, *pnq_base_t; + #define DBC_RELATIVE_DB_32_TYPE_NQ_ARM (UINT32_C(0x5) << 29) + /* + * This is a NQ consumer index update that also arms the NQ for + * any new NQE. It is used for the legacy INT mask. This type + * is valid for L2, RoCE and Engine path. + */ + #define DBC_RELATIVE_DB_32_TYPE_NQ_MASK (UINT32_C(0x6) << 29) + #define DBC_RELATIVE_DB_32_TYPE_LAST DBC_RELATIVE_DB_32_TYPE_NQ_MASK +} dbc_relative_db_32_t, *pdbc_relative_db_32_t; -/* Completion Queue Notification */ -/* nq_cn (size:128b/16B) */ +/* + * The kernel memory structure is per-type (SQ, RQ, SRQ/SRQ_ARM and + * CQ/CQ_ARMSE/CQ_ARMALL). Each kernel driver will support a table for + * the doorbell recovery. + */ +/* dbc_drk (size:128b/16B) */ -typedef struct nq_cn { - uint16_t type; +typedef struct dbc_drk { + uint32_t db_format_linked_last_valid_stride_size; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This indicates it is valid entry. It should be set for each + * doorbell written to the chip. The bit should be cleared at time + * zero to indicate that it has not yet been written. The bit i + * should be cleared when the function for the table is disabled. */ - #define NQ_CN_TYPE_MASK UINT32_C(0x3f) - #define NQ_CN_TYPE_SFT 0 - /* CQ Notification */ - #define NQ_CN_TYPE_CQ_NOTIFICATION UINT32_C(0x30) - #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION + #define DBC_DRK_VALID UINT32_C(0x1) + /* This indicates it is last entry for the table. */ + #define DBC_DRK_LAST UINT32_C(0x2) + /* This indicates it is entry for the next 4KB kernel memory pointer. */ + #define DBC_DRK_LINKED UINT32_C(0x4) /* - * This field carries the toggle value that must be used to - * re-arm this CQ. The toggle value should be copied into the - * doorbell used to CQ_ARMENA, CQ_ARMALL or CQ_ARMSE doorbells. + * This field indicates if the doorbells in the table are 32b + * absolute or 64b format. */ - #define NQ_CN_TOGGLE_MASK UINT32_C(0xc0) - #define NQ_CN_TOGGLE_SFT 6 - uint16_t reserved16; + #define DBC_DRK_DB_FORMAT UINT32_C(0x8) + /* The doorbells are 64b format. */ + #define DBC_DRK_DB_FORMAT_B64 (UINT32_C(0x0) << 3) /* - * This is an application level ID used to identify the - * CQ. This field carries the lower 32b of the value. + * The doorbells are in the absolute 32b format. The doorbell + * is in the right-most half of the 64b space provided in the + * application table entry. */ - uint32_t cq_handle_low; - uint32_t v; + #define DBC_DRK_DB_FORMAT_B32A (UINT32_C(0x1) << 3) + #define DBC_DRK_DB_FORMAT_LAST DBC_DRK_DB_FORMAT_B32A /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This field controls the stride feature. The stride feature is + * more bandwidth efficient on the PCIE bus when only a small number + * of doorbells are used in each cache line. */ - #define NQ_CN_V UINT32_C(0x1) + #define DBC_DRK_STRIDE_MASK UINT32_C(0x300) + #define DBC_DRK_STRIDE_SFT 8 /* - * This is an application level ID used to identify the - * CQ. This field carries the upper 32b of the value. + * When stride is off, the DBR will read all the bytes in + * an application page until a NULL doorbell is found or + * the end of the 4K page is reached. */ - uint32_t cq_handle_high; -} nq_cn_t, *pnq_cn_t; + #define DBC_DRK_STRIDE_OFF (UINT32_C(0x0) << 8) + /* + * When stride is 1, the DBR will read the 'size' doorbells, + * starting at the next 64B cache line boundary or until + * a NULL doorbell is found in the application page or + * the end of the 4K page is reached. + */ + #define DBC_DRK_STRIDE_SZ64 (UINT32_C(0x1) << 8) + /* + * When stride is 2, the DBR will read the 'size' doorbells, + * starting at the next 128B cache line boundary or until + * a NULL doorbell is found in the application page or + * the end of the 4K page is reached. + */ + #define DBC_DRK_STRIDE_SZ128 (UINT32_C(0x2) << 8) + #define DBC_DRK_STRIDE_LAST DBC_DRK_STRIDE_SZ128 + /* + * This value controls how many doorbells are read at each stride + * when stride mode is in use. + */ + #define DBC_DRK_SIZE_MASK UINT32_C(0xc00) + #define DBC_DRK_SIZE_SFT 10 + /* 4*8B is read at the start of each stride. */ + #define DBC_DRK_SIZE_FOUR (UINT32_C(0x0) << 10) + /* 1*8B is read at the start of each stride. */ + #define DBC_DRK_SIZE_ONE (UINT32_C(0x1) << 10) + /* 2*8B is read at the start of each stride. */ + #define DBC_DRK_SIZE_TWO (UINT32_C(0x2) << 10) + /* 3*8B is read at the start of each stride. */ + #define DBC_DRK_SIZE_THREE (UINT32_C(0x3) << 10) + #define DBC_DRK_SIZE_LAST DBC_DRK_SIZE_THREE + uint32_t pi; + /* + * Page Index portion of DPI{VF_VALID,VFID,PI}. The pi needs to match + * the value from the context DPI for the operation to be valid or + * the pi must be zero, indicating a write from the privileged + * driver. + * + * pi in the kernel memory table is there for DBR to generate the DPI + * message to the client. + */ + #define DBC_DRK_PI_MASK UINT32_C(0xffff) + #define DBC_DRK_PI_SFT 0 + /* + * It is the application memory page(4KB) pointer when linked = 0. + * It is the next kernel memory page(4KB) pointer when linked = 1. + * The pointer doesn't have to be aligned to the page(4KB) but it + * should be aligned to 128B boundary. This means that the bottom + * 7b of the pointer must be zero. + */ + uint64_t memptr; +} dbc_drk_t, *pdbc_drk_t; -/* SRQ Event Notification */ -/* nq_srq_event (size:128b/16B) */ +/* + * This is the 64b doorbell format. The host writes this message + * format directly to byte offset 0 of the appropriate doorbell page. + */ +/* dbc_dbc_v3 (size:64b/8B) */ -typedef struct nq_srq_event { - uint8_t type; +typedef struct dbc_dbc_v3 { + uint32_t index; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This value is the index being written. + * + * For SQ/RQ/SRQ, this is the producer index. It should be set to + * the queue index of the last WQE/BD written plus the number of + * index units in the WQE/BD. For example, if the number of index + * units in an SQ WQE is 8 and the WQE was written to the first + * location in the queue (zero), this index should be written to 8. + * The index should point to the start of the first location that + * has not been filled in with WQE/BD data. For SQ (both RoCE and + * L2), the index unit is 16B. For RQ/SRQ, the index unit is 1 WQE + * (RoCE) or 1 BD (L2). + * + * For CQ, this is the consumer index and should be the starting + * queue index of the last CQE processed plus the size of the last + * processed CQE in index units. The index should point to the + * start of the first CQE in the queue that has not been processed. + * The index unit is 16B. + * + * For NQ, this is the consumer index and should be the starting + * queue index of the last NQE processed plus the size of the last + * processed NQE in index units. The index should point to the + * start of the first NQE in the queue that has not been processed. + * The index unit is 16B. + */ + #define DBC_DBC_V3_INDEX_MASK UINT32_C(0xffffff) + #define DBC_DBC_V3_INDEX_SFT 0 + /* + * The epoch bit provides a frame of reference for the queue index. + * S/W will toggle this bit in the doorbell each time index range is + * wrapped. This allows the receiving HW block to more efficiently + * detect out-of-order doorbells and to ignore the older doorbells. + * Out-of-order doorbells occur normally during dropped doorbell + * recovery. + */ + #define DBC_DBC_V3_EPOCH UINT32_C(0x1000000) + /* + * The toggle value is used in CQ_ARMENA, CQ_ARMSE, CQ_ARMALL, + * SRQ_ARMENA, SRQ_ARM, and CQ_CUTOFF_ACK doorbells to qualify the + * doorbell as valid. This value should be taken from the latest + * NQE or cutoff completion. + * + * Doorbells of the above types with the wrong toggle value will + * be ignored. This is how old values in of backup doorbells + * are ignored. + */ + #define DBC_DBC_V3_TOGGLE_MASK UINT32_C(0x6000000) + #define DBC_DBC_V3_TOGGLE_SFT 25 + uint32_t type_path_xid; + /* + * This value identifies the resource that the doorbell is intended + * to notify. + * + * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For + * CQ, this is the CID. For NQ, this is the NID. + * + * Unused bits (for example bits [11:7] of the SID value) must be + * zero. */ - #define NQ_SRQ_EVENT_TYPE_MASK UINT32_C(0x3f) - #define NQ_SRQ_EVENT_TYPE_SFT 0 - /* SRQ Threshold Event */ - #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT UINT32_C(0x32) - #define NQ_SRQ_EVENT_TYPE_LAST NQ_SRQ_EVENT_TYPE_SRQ_EVENT + #define DBC_DBC_V3_XID_MASK UINT32_C(0xfff) + #define DBC_DBC_V3_XID_SFT 0 /* - * This field carries the toggle value that must be used - * to re-arm this SRQ. The toggle value should be copied - * into the doorbell used to SRQ_ARMENA or SRQ_ARM doorbells. + * This value defines the intended doorbell path between RoCE and + * L2. */ - #define NQ_SRQ_EVENT_TOGGLE_MASK UINT32_C(0xc0) - #define NQ_SRQ_EVENT_TOGGLE_SFT 6 + #define DBC_DBC_V3_PATH_MASK UINT32_C(0x3000000) + #define DBC_DBC_V3_PATH_SFT 24 + /* This is a RoCE doorbell message. */ + #define DBC_DBC_V3_PATH_ROCE (UINT32_C(0x0) << 24) + /* This is a L2 doorbell message. */ + #define DBC_DBC_V3_PATH_L2 (UINT32_C(0x1) << 24) + #define DBC_DBC_V3_PATH_LAST DBC_DBC_V3_PATH_L2 /* - * This value define what type of async event has occurred - * on the SRQ. + * This indicates it is valid doorbell update. It should be set for + * each doorbell written to the chip and set when doorbell message is + * written to the backup doorbell location. The bit should be cleared + * in the backup doorbell location at time zero to indicate that the + * backup doorbell has not yet been written. */ - uint8_t event; - /* The threshold event has occurred on the specified SRQ. */ - #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT UINT32_C(0x1) - #define NQ_SRQ_EVENT_EVENT_LAST NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT - uint16_t reserved16; + #define DBC_DBC_V3_VALID UINT32_C(0x4000000) /* - * This is the SRQ handle value for the queue that has - * reached it's event threshold. This field carries the - * lower 32b of the value. + * When this bit is set to one, the chip will capture debug + * information for the doorbell ring. This is intended to only be + * used on SQ doorbell rings. */ - uint32_t srq_handle_low; - uint32_t v; + #define DBC_DBC_V3_DEBUG_TRACE UINT32_C(0x8000000) + /* This value identifies the type of doorbell being written. */ + #define DBC_DBC_V3_TYPE_MASK UINT32_C(0xf0000000) + #define DBC_DBC_V3_TYPE_SFT 28 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This is a SQ producer index update. It indicates one or more + * new entries have been written to the SQ for the QPID indicated + * on the xID field. This type is valid for L2 and RoCE path. */ - #define NQ_SRQ_EVENT_V UINT32_C(0x1) + #define DBC_DBC_V3_TYPE_SQ (UINT32_C(0x0) << 28) /* - * This is the SRQ handle value for the queue that has - * reached it's event threshold. This field carries the - * upper 32b of the value. + * This is a RQ producer index update. It indicates one or more + * new entries have been written to the RQ for the QPID indicated + * on the xID field. This type is valid for RoCE path. */ - uint32_t srq_handle_high; -} nq_srq_event_t, *pnq_srq_event_t; - -/* DBQ Async Event Notification */ -/* nq_dbq_event (size:128b/16B) */ - -typedef struct nq_dbq_event { - uint8_t type; + #define DBC_DBC_V3_TYPE_RQ (UINT32_C(0x1) << 28) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This is a SRQ producer index update. It indicates one or more + * new entries have been written to the SRQ for the SID indicated + * on the xID field. This type is valid for L2 and RoCE path. */ - #define NQ_DBQ_EVENT_TYPE_MASK UINT32_C(0x3f) - #define NQ_DBQ_EVENT_TYPE_SFT 0 - /* DBQ Threshold Event */ - #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT UINT32_C(0x34) - #define NQ_DBQ_EVENT_TYPE_LAST NQ_DBQ_EVENT_TYPE_DBQ_EVENT - /* This value define what type of action the driver should take. */ - uint8_t event; + #define DBC_DBC_V3_TYPE_SRQ (UINT32_C(0x2) << 28) /* - * The driver should start writing dummy values to the - * the doorbell in an attempt to consume all the PCIE - * posted write resources and prevent doorbell overflow. + * This doorbell command arms the SRQ async event. The xID field + * must identify the SID that is begin armed. The index field is + * will set the arm threshold such that a notification will be + * generated if less than that number or SRQ entries are posted. + * + * This type is valid for RoCE path. */ - #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT UINT32_C(0x1) - #define NQ_DBQ_EVENT_EVENT_LAST NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT - uint16_t db_pfid; + #define DBC_DBC_V3_TYPE_SRQ_ARM (UINT32_C(0x3) << 28) /* - * This is the PFID of function that wrote the doorbell that - * crossed the async event threshold. + * CQ doorbell is used to update the consumer index for the CQ + * for overflow detection. It should only be sent if overflow + * detection is enabled for the CQ. Keep in mind that if + * doorbells are being dropped due to PCIE ordering rules, you + * may get a false overflow detection if you are checking for CQ + * overflow. + * + * This type is valid for L2 and RoCE path. */ - #define NQ_DBQ_EVENT_DB_PFID_MASK UINT32_C(0xf) - #define NQ_DBQ_EVENT_DB_PFID_SFT 0 - uint32_t db_dpi; + #define DBC_DBC_V3_TYPE_CQ (UINT32_C(0x4) << 28) /* - * This is the DPI of the doorbell write that crossed - * the async event threshold. + * This is a CQ consumer index update that also arms the CQ for + * solicited events. This is for roce only not for l2. + * + * The index is used as the location of the last CQE that was + * processed by the driver. The new interrupt will be generated + * based on this location. + * + * This type is valid for RoCE path. */ - #define NQ_DBQ_EVENT_DB_DPI_MASK UINT32_C(0xfffff) - #define NQ_DBQ_EVENT_DB_DPI_SFT 0 - uint32_t v; + #define DBC_DBC_V3_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This is a CQ consumer index update that also arms the CQ for + * any new CQE. + * + * The index is used as the location of the last CQE that was + * processed by the driver. The new interrupt will be generated + * based on this location. + * + * This type is valid for L2 and RoCE path. */ - #define NQ_DBQ_EVENT_V UINT32_C(0x1) - uint32_t db_type_db_xid; + #define DBC_DBC_V3_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28) /* - * DB 'XID' field from doorbell that crossed the async event - * threshold. This is a QPID, SID, or CID, depending on - * the db_type field. + * This is a CQ arm enable message. This message must be sent + * from the privileged driver before a new CQ_ARMSE or CQ_ARMALL + * message will be accepted from user space (non-privileged + * doorbell page). The index and epoch for this doorbell type are + * unused. + * + * This doorbell can only be sent from the privileged (first) + * doorbell page of a function. */ - #define NQ_DBQ_EVENT_DB_XID_MASK UINT32_C(0xfffff) - #define NQ_DBQ_EVENT_DB_XID_SFT 0 + #define DBC_DBC_V3_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28) /* - * DB 'type' field from doorbell that crossed the async event - * threshold. + * This doorbell command enables the SRQ async event to be armed. + * This message must be sent from the privileged driver before + * a new SRQ_ARM message will be accepted from user space. The + * xID field must identify the SID that is being enabled for arm. + * The index and epoch for this doorbell type are unused. + * + * This doorbell can only be sent from the privileged (first) + * doorbell page of a function. */ - #define NQ_DBQ_EVENT_DB_TYPE_MASK UINT32_C(0xf0000000) - #define NQ_DBQ_EVENT_DB_TYPE_SFT 28 -} nq_dbq_event_t, *pnq_dbq_event_t; - -/* Input Read Request Queue (IRRQ) Message */ -/* xrrq_irrq (size:256b/32B) */ - -typedef struct xrrq_irrq { - uint16_t credits_type; - /* Type indication */ - #define XRRQ_IRRQ_TYPE UINT32_C(0x1) - /* RDMA Read */ - #define XRRQ_IRRQ_TYPE_READ_REQ UINT32_C(0x0) - /* Atomic */ - #define XRRQ_IRRQ_TYPE_ATOMIC_REQ UINT32_C(0x1) - #define XRRQ_IRRQ_TYPE_LAST XRRQ_IRRQ_TYPE_ATOMIC_REQ + #define DBC_DBC_V3_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28) /* - * The credit code calculated by Rx path when receiving the - * request. It will be placed in the syndrome credit code with - * the acks on first and last response. + * This doorbell type is used to acknowledge a cutoff completion + * in the CQ. The index and epoch for this doorbell type are + * unused. This doorbell is sent when the cutoff completion has + * been processed and the old CQ in a CQ resize operation is no + * longer needed. + * + * The index and epoch must be valid for this doorbell if + * overflow checking is enabled for the CQ. */ - #define XRRQ_IRRQ_CREDITS_MASK UINT32_C(0xf800) - #define XRRQ_IRRQ_CREDITS_SFT 11 - uint16_t reserved16; - uint32_t reserved32; - uint32_t psn; - /* The PSN of the outstanding incoming request */ - #define XRRQ_IRRQ_PSN_MASK UINT32_C(0xffffff) - #define XRRQ_IRRQ_PSN_SFT 0 - uint32_t msn; + #define DBC_DBC_V3_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9) << 28) /* - * The value of QPC.pending_ack_msn after it is incremented as a - * result of receiving the read/atomic request. IRRQ.msn-1 will be - * placed in the MSN field of the first response and IRRQ.msn will - * placed in the MSN field of the last or only response. + * This is a NQ consumer index update. It indicates one or more + * entries have been processed off the NQ indicated on the xID + * field. It will also mask the NQ for any new NQE. This type is + * valid for L2 and RoCE path. + * + * Thor is broken in that it doesn't mask a legacy INTA interrupt + * when used at the start of an ISR, as it is supposed to be. + * + * type=NQ masks the current interrupt. When the iSR starts, it + * writes a type=NQ with the current consumer index. For legacy + * PCI interrupts, this needs to mask the interrupt so the legacy + * interrupt is deasserted. Then the driver does some work and + * writes some more type=NQ. Finally the driver stops the ISR and + * does a type=NQ_ARM to get another interrupt (when needed). The + * only reason to use type=NQ_MASK is to back out of the armed + * state. In that request, the index update is not required. */ - #define XRRQ_IRRQ_MSN_MASK UINT32_C(0xffffff) - #define XRRQ_IRRQ_MSN_SFT 0 + #define DBC_DBC_V3_TYPE_NQ (UINT32_C(0xa) << 28) /* - * Virtual address on local host for RDMA READ + * This is a NQ consumer index update that also arms the NQ for + * any new NQE. * - * In case of duplicate Atomic, the VA is not required to - * be validated, only the PSN is, thus this field is used - * to store the value returned in the Ack to the atomic - * request, and if duplicate arrives, this value is used - * again for resending the ack. + * This type is valid for L2 and RoCE path. */ - uint64_t va_or_atomic_result; - /* The key to the MR/W in the request */ - uint32_t rdma_r_key; - /* Length in bytes of the data requested. Length must be 8 if type is atomic. */ - uint32_t length; -} xrrq_irrq_t, *pxrrq_irrq_t; - -/* Output Read Request Queue (ORRQ) Message */ -/* xrrq_orrq (size:256b/32B) */ - -typedef struct xrrq_orrq { - uint16_t num_sges_type; - /* Type indication */ - #define XRRQ_ORRQ_TYPE UINT32_C(0x1) - /* RDMA Read */ - #define XRRQ_ORRQ_TYPE_READ_REQ UINT32_C(0x0) - /* Atomic */ - #define XRRQ_ORRQ_TYPE_ATOMIC_REQ UINT32_C(0x1) - #define XRRQ_ORRQ_TYPE_LAST XRRQ_ORRQ_TYPE_ATOMIC_REQ + #define DBC_DBC_V3_TYPE_NQ_ARM (UINT32_C(0xb) << 28) /* - * Up to 6 SGEs. This value is 1 if type is atomic as one - * SGE is required to store Atomic response result field. 2 - * more bits allocated for future growth. + * This doorbell will assign a new NQ to a CQ. This is handy if + * the user wants to change which interrupt handler is going to + * process a particular CQ. This doorbell must be sent from the + * privileged driver. * - * Note that, if num_sges is 1 for an RDMA Read request, then - * the first_sge_phy_or_sing_sge_va, single_sge_l_key, and - * single_sge_size fields will be populated from the single - * SGE. + * The xID must be the CID for the CQ that needs to be changed. + * The index value is the NQID of the new NQ that will be used + * for future notifications. epoch and toggle are ignored for + * this doorbell type. * - * If num_sges is 2 or more for an RDMA Read request, then - * the first_sge_phy_or_sing_sge_va field carries the - * physical address in host memory where the first sge is - * stored. The single_sge_l_key and single_sge_size fields - * are unused in this case. + * The CQ will disarm notifications and generate a NQE to the old + * NQ with the nq_reassign type value. The chip will guarantee + * that no notification will be sent to the old NQ after the + * nq_reassign NQE has been sent. * - * A special case is a zero-length, zero-sge RDMA read request - * WQE. In this situation, num_sges will be 1. However, - * first_sge_phy_or_sing_sge_va, single_sge_l_key, and - * single_sge_size will all be populated with zeros. + * This type is valid for L2 and RoCE CQs. */ - #define XRRQ_ORRQ_NUM_SGES_MASK UINT32_C(0xf800) - #define XRRQ_ORRQ_NUM_SGES_SFT 11 - uint16_t reserved16; - /* Length in bytes of the data requested. Length must be 8 if type is atomic. */ - uint32_t length; - uint32_t psn; - /* The PSN of the outstanding outgoing request */ - #define XRRQ_ORRQ_PSN_MASK UINT32_C(0xffffff) - #define XRRQ_ORRQ_PSN_SFT 0 - uint32_t end_psn; + #define DBC_DBC_V3_TYPE_CQ_REASSIGN (UINT32_C(0xc) << 28) /* - * The expected last PSN on a response to this request where - * an ack with response, rather than just response, should - * arrive. If ack arrive with smaller PSN than end_psn then it - * is considered a NAK. + * This masks the NQ for any new NQE. This will NOT update the NQ + * consumer index. + * + * This type is valid for L2 and RoCE path. */ - #define XRRQ_ORRQ_END_PSN_MASK UINT32_C(0xffffff) - #define XRRQ_ORRQ_END_PSN_SFT 0 + #define DBC_DBC_V3_TYPE_NQ_MASK (UINT32_C(0xe) << 28) /* - * If num_sges == 1 this is the va of that SGE. Otherwise, - * physical address to the first SGE specified by the WQE. - * Points to the first SGE in the Request's WQE in the SQ. - * It is assumed that WQE does not cross page boundaries! - * Driver is responsible to enforce that. SGEs are 16B - * aligned 0b0000 lsb added to get 64 bit address. + * All other fields should be zero for NULL doorbell. + * + * For doorbell recovery, NULL doorbell type in the Application + * table indicates that it is the last QP entry for the function. + * This type is valid for L2 and RoCE path. */ - uint64_t first_sge_phy_or_sing_sge_va; - /* The L_Key of a single SGE if used */ - uint32_t single_sge_l_key; - /* The size in bytes of the single SGE if used */ - uint32_t single_sge_size; -} xrrq_orrq_t, *pxrrq_orrq_t; + #define DBC_DBC_V3_TYPE_NULL (UINT32_C(0xf) << 28) + #define DBC_DBC_V3_TYPE_LAST DBC_DBC_V3_TYPE_NULL +} dbc_dbc_v3_t, *pdbc_dbc_v3_t; -/* Page Table Entry (PTE) */ -/* ptu_pte (size:64b/8B) */ +/* + * This is the RoCE Express Doorbell format. The host writes this + * message format directly to offset 0x40 of the appropriate doorbell + * page. Express doorbells are used when the chip will be owning the + * SQ, RQ, and SRQ as well as the producer indexes for each queue. This + * provides a simple fastpath programming model. + * + * Express doorbell must be received by the chip as a single TLP + * message. + */ +/* dbc_xp (size:512b/64B) */ -typedef struct ptu_pte { - uint64_t page_next_to_last_last_valid; +typedef struct dbc_xp { + uint32_t reserved; + uint32_t type_xid; /* - * This field indicates if the PTE is valid. A value of '0' - * indicates that the page is not valid. A value of '1' - * indicates that the page is valid. A reference to an - * invalid page will return a PTU error. + * This value identifies the resource that the doorbell is intended + * to notify. + * + * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For + * CQ, this is the CID. For NQ, this is the NID. + * + * Unused bits (for example bits [11:7] of the SID value) must be + * zero. */ - #define PTU_PTE_VALID UINT32_C(0x1) + #define DBC_XP_XID_MASK UINT32_C(0xfff) + #define DBC_XP_XID_SFT 0 /* - * This field is used only for "ring" PBLs that are used for - * SQ, RQ, SRQ, or CQ structures. For all other PBL structures, - * this bit should be zero. When this bit is '1', it indicates - * that the page pointed to by this PTE is the last page in the - * ring. A prefetch for the ring should use the first PTE in - * the PBL. + * When this bit is set to one, the chip will capture debug + * information for the doorbell ring. This is intended to only be + * used on SQ doorbell rings. */ - #define PTU_PTE_LAST UINT32_C(0x2) + #define DBC_XP_DEBUG_TRACE UINT32_C(0x1000000) + /* This value identifies the type of doorbell being written. */ + #define DBC_XP_TYPE_MASK UINT32_C(0xf0000000) + #define DBC_XP_TYPE_SFT 28 /* - * This field is used only for "ring" PBLs that are used for - * SQ, RQ, SRQ, or CQ structures. For all other PBL structures, - * this bit should be zero. When this bit is '1', it indicates - * that this is the next-to-last page of the PBL. + * This is a SQ producer index update. It indicates one or more + * new entries have been written to the SQ for the QPID indicated + * on the xID field. This type is valid for L2, RoCE and Engine + * path. */ - #define PTU_PTE_NEXT_TO_LAST UINT32_C(0x4) - /* These bits should be programmed to zero. */ - #define PTU_PTE_UNUSED_MASK UINT32_C(0xff8) - #define PTU_PTE_UNUSED_SFT 3 + #define DBC_XP_TYPE_SQ (UINT32_C(0x0) << 28) /* - * This is the upper bits of the physical page controlled by - * this PTE. If the page is larger than 4KB, then the unused - * lower bits of the page address should be zero. + * This is a RQ producer index update. It indicates one or more + * new entries have been written to the RQ for the QPID indicated + * on the xID field. This type is valid for RoCE path. */ - #define PTU_PTE_PAGE_MASK UINT32_C(0xfffff000) - #define PTU_PTE_PAGE_SFT 12 -} ptu_pte_t, *pptu_pte_t; - -/* Page Directory Entry (PDE) */ -/* ptu_pde (size:64b/8B) */ - -typedef struct ptu_pde { - uint64_t page_valid; + #define DBC_XP_TYPE_RQ (UINT32_C(0x1) << 28) /* - * This field indicates if the PTE is valid. A value of '0' - * indicates that the page is not valid. A value of '1' - * indicates that the page is valid. A reference to an - * invalid page will return a PTU error. + * This is a SRQ producer index update. It indicates one or more + * new entries have been written to the SRQ for the SID indicated + * on the xID field. This type is valid for L2 and RoCE path. */ - #define PTU_PDE_VALID UINT32_C(0x1) - /* These bits should be programmed to zero. */ - #define PTU_PDE_UNUSED_MASK UINT32_C(0xffe) - #define PTU_PDE_UNUSED_SFT 1 + #define DBC_XP_TYPE_SRQ (UINT32_C(0x2) << 28) + #define DBC_XP_TYPE_LAST DBC_XP_TYPE_SRQ /* - * This is the upper bits of the physical page controlled by - * this PTE. If the page is larger than 4KB, then the unused - * lower bits of the page address should be zero. + * This field hold one express WQE. The WQE must be appropriate for + * the queue selected by the type field. */ - #define PTU_PDE_PAGE_MASK UINT32_C(0xfffff000) - #define PTU_PDE_PAGE_SFT 12 -} ptu_pde_t, *pptu_pde_t; + uint32_t wqe[14]; +} dbc_xp_t, *pdbc_xp_t; /* - * This is the 64b doorbell format. The host writes this message - * format directly to byte offset 0 of the appropriate doorbell page. + * This is a firmware status register that indicates the software status + * exposed by the firmware to the host. + * + * > This register is not present in previous versions of this chip. */ -/* dbc_dbc (size:64b/8B) */ +/* fw_status_reg (size:32b/4B) */ -typedef struct dbc_dbc { - uint32_t index; +typedef struct fw_status_reg { + uint32_t fw_status; /* - * This value is the index being written. + * These bits indicate the status as being reported by the firmware. * - * For SQ, RQ, and SRQ, this is the producer index and the unit is - * 16B of queue space for L2 path and for the Engine path. For RoCE - * path there is a legacy mode with 128B unit size and a variable - * size WQE mode with 16B unit size of queue space. This mode is - * configured in the QP. + * The value should be interpreted as follows: + * A value below 0x8000 is an indication that the firmware is still + * in the process of starting up and is not ready. The host driver + * should continue waiting with a timeout for firmware status to be + * ready. + * > 0x0000 to 0x00FF : SBL state information + * > 0x0200 to 0x02FF : SBI state information + * > 0x0400 to 0x04FF : SRT state information + * > 0x0600 to 0x06FF : CRT/CHIMP state information + * > 0x0800 to 0x08FF : External Firmware state information + * > 0x0A00 to 0x0FFF : Reserved for future fw functionality * - * For CQ this is the consumer index and the unit is 32B of queue - * space for the RoCE/Engine path and the CQ index unit is 16B of - * queue space for the L2 path. + * A value of 0x8000 indicates firmware is ready and healthy. The + * host driver can start initiating HWRM commands to the firmware. * - * For NQ this is the consumer index and the unit is always 16B of - * queue space. + * A value over 0x8000 is an indication that the firmware has + * detected a fatal error, this error could be in one of the hardware + * block or in a software module. The lower 8 bits indicate a + * block/module specific error and the upper 8 bits identify the + * hardware block or firmware module that was the source of the + * error. + * > 0x81XX - 0xBFXX : 63 ASIC blocks + * > 0xC0XX to 0xFDXX : 62 Firmware modules + * > 0xFE00 to 0xFEFF : External firmware module + * > 0xFFXX : Reserved for future + */ + #define FW_STATUS_REG_CODE_MASK UINT32_C(0xffff) + #define FW_STATUS_REG_CODE_SFT 0 + /* Indicates firmware is ready. */ + #define FW_STATUS_REG_CODE_READY UINT32_C(0x8000) + #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY + /* + * Image Degraded bit. If set indicates that one of the firmware + * image is degraded. * - * The index size is 24b for L2 and engine paths and 16b for the - * RoCE path. Unused bits should be written as zero. + * The firmware binary located on NVM has redundant copies to protect + * against corruption. When one of the primary or secondary copy is + * detected as corrupted, this bit will be set by the firmware either + * as part of power on from the context of hwrm_fw_health_check. */ - #define DBC_DBC_INDEX_MASK UINT32_C(0xffffff) - #define DBC_DBC_INDEX_SFT 0 + #define FW_STATUS_REG_IMAGE_DEGRADED UINT32_C(0x10000) /* - * The epoch bit provides a frame of reference for the queue index. - * S/W will toggle this bit in the doorbell each time index range is - * wrapped. This allows the receiving HW block to more efficiently - * detect out-of-order doorbells and to ignore the older doorbells. - * Out-of-order doorbells occur normally during dropped doorbell - * recovery. + * Recoverable bit. If set indicates that the fatal error is + * recoverable with a full reset. + * + * This bit should be used by host software and deployment models + * that support error recovery by resetting the controller. A + * recovery should be attempted from a fatal error condition only if + * this bit is set. This bit is meaningful only when the code field + * is greater than 0x8000 (32768 decimal). */ - #define DBC_DBC_EPOCH UINT32_C(0x1000000) + #define FW_STATUS_REG_RECOVERABLE UINT32_C(0x20000) /* - * The toggle value is used in CQ_ARMENA, CQ_ARMSE, CQ_ARMALL, - * SRQ_ARMENA, SRQ_ARM, and CQ_CUTOFF_ACK doorbells to qualify the - * doorbell as valid. This value should be taken from the latest - * NQE or cutoff completion. + * Crash dump is in process. If set indicates that the firmware is + * currently recording a crash dump. * - * Doorbells of the above types with the wrong toggle value will - * be ignored. This is how old values in of backup doorbells - * are ignored. + * This bit provides a hint to the host driver if the firmware is + * currently recording a crash dump. Host driers should avoid + * resetting the controller when a crash dump is in progress if + * possible. This bit is meaningful only when the code field is + * greater than 0x8000 (32768 decimal). */ - #define DBC_DBC_TOGGLE_MASK UINT32_C(0x6000000) - #define DBC_DBC_TOGGLE_SFT 25 - uint32_t type_path_xid; + #define FW_STATUS_REG_CRASHDUMP_ONGOING UINT32_C(0x40000) /* - * This value identifies the resource that the doorbell is intended - * to notify. + * Crash dump is available. If set indicates that a firmware crash + * dump was recorded before and is now available. * - * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For - * CQ, this is the CID. For NQ, this is the NID. + * This bit provides indication to the host driver that the firmware + * has completed a crash dump. This bit is meaningful only when the + * code field is greater than 0x8000 (32768 decimal). + */ + #define FW_STATUS_REG_CRASHDUMP_COMPLETE UINT32_C(0x80000) + /* + * This bit is used to indicate device state when it enters the + * shutdown mode and stopped the communication with the host. The + * host should initiate the reload of firmware image or initiate the + * reset to bring the device to the normal operational state and + * re-establish the communication. * - * Bits [19:16] of this values must be zero for a SID value. + * This bit is meaningful only when the code field is greater than + * 0x8000 (32768 decimal). */ - #define DBC_DBC_XID_MASK UINT32_C(0xfffff) - #define DBC_DBC_XID_SFT 0 + #define FW_STATUS_REG_SHUTDOWN UINT32_C(0x100000) /* - * This value defines the intended doorbell path between RoCE and - * L2. + * This bit will be set to 1 by the FW when FW crashed without master + * function. + * + * This bit is controller specific, not all products will support + * this bit. This bit is valid only when the code field is greater + * than 0x8000 (32768 decimal). */ - #define DBC_DBC_PATH_MASK UINT32_C(0x3000000) - #define DBC_DBC_PATH_SFT 24 - /* This is a RoCE doorbell message. */ - #define DBC_DBC_PATH_ROCE (UINT32_C(0x0) << 24) - /* This is a L2 doorbell message. */ - #define DBC_DBC_PATH_L2 (UINT32_C(0x1) << 24) - /* Engine path doorbell. */ - #define DBC_DBC_PATH_ENGINE (UINT32_C(0x2) << 24) - #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE + #define FW_STATUS_REG_CRASHED_NO_MASTER UINT32_C(0x200000) + /* + * The firmware sets this bit to 1 when the firmware has taken an + * exception and expects to initiate error recovery. + * + * This bit is valid only when the code field is greater than 0x8000 + * (32768 decimal). + */ + #define FW_STATUS_REG_RECOVERING UINT32_C(0x400000) + /* + * The SBL sets this bit to indicate whether manu_debug pin is + * detected high or low. + */ + #define FW_STATUS_REG_MANU_DEBUG_STATUS UINT32_C(0x800000) +} fw_status_reg_t, *pfw_status_reg_t; + +/* + * This structure is fixed at the beginning of the ChiMP SRAM (GRC + * offset: 0x31001F0). Host software is expected to read from this + * location for a defined signature. If it exists, the software can + * assume the presence of this structure and the validity of the + * FW_STATUS location in the next field. + */ +/* hcomm_status (size:64b/8B) */ + +typedef struct hcomm_status { + uint32_t sig_ver; + /* + * This field defines the version of the structure. The latest + * version value is 1. + */ + #define HCOMM_STATUS_VER_MASK UINT32_C(0xff) + #define HCOMM_STATUS_VER_SFT 0 + #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1) + #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST + /* + * This field is to store the signature value to indicate the + * presence of the structure. + */ + #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00) + #define HCOMM_STATUS_SIGNATURE_SFT 8 + #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8) + #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL + uint32_t fw_status_loc; + #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3) + #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 + /* PCIE configuration space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0) + /* GRC space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1) + /* BAR0 space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2) + /* BAR1 space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3) + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 + /* + * This offset where the fw_status register is located. The value + * is generally 4-byte aligned. + */ + #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc) + #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 +} hcomm_status_t, *phcomm_status_t; + +/* This is the GRC offset where the hcomm_status struct resides. */ +#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL + +/*********************** + * hwrm_selftest_qlist * + ***********************/ + + +/* hwrm_selftest_qlist_input (size:128b/16B) */ + +typedef struct hwrm_selftest_qlist_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} hwrm_selftest_qlist_input_t, *phwrm_selftest_qlist_input_t; + +/* hwrm_selftest_qlist_output (size:2240b/280B) */ + +typedef struct hwrm_selftest_qlist_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This field represents the number of tests available to be + * requested by a driver. + */ + uint8_t num_tests; + /* This field indicates which self-test is available to be run. */ + uint8_t available_tests; + /* Can run the NVM test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_NVM_TEST UINT32_C(0x1) + /* Can run the link test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_LINK_TEST UINT32_C(0x2) + /* Can run the register test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_REGISTER_TEST UINT32_C(0x4) + /* Can run the memory test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_MEMORY_TEST UINT32_C(0x8) + /* Can run the PCIe serdes test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10) + /* Can run the Ethernet serdes test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20) + uint8_t offline_tests; + /* The NVM test is an offline test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_NVM_TEST UINT32_C(0x1) + /* The link test is an offline test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_LINK_TEST UINT32_C(0x2) + /* The register test is an offline test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_REGISTER_TEST UINT32_C(0x4) + /* The memory test is an offline test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_MEMORY_TEST UINT32_C(0x8) + /* The PCIe serdes test is an offline test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10) + /* The Ethernet serdes test is an offline test. */ + #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20) + uint8_t unused_0; /* - * This indicates it is valid doorbell update. It should be set for - * each doorbell written to the chip and set when doorbell message is - * written to the backup doorbell location. The bit should be cleared - * in the backup doorbell location at time zero to indicate that the - * backup doorbell has not yet been written. + * This field represents the maximum timeout for all the + * tests to complete in milliseconds. */ - #define DBC_DBC_VALID UINT32_C(0x4000000) + uint16_t test_timeout; + uint8_t unused_1[2]; /* - * When this bit is set to one, the chip will capture debug - * information for the doorbell ring. This is intended to only be - * used on SQ doorbell rings. + * This field represents array of 8 test name strings (ASCII chars + * with NULL at the end). */ - #define DBC_DBC_DEBUG_TRACE UINT32_C(0x8000000) - /* This value identifies the type of doorbell being written. */ - #define DBC_DBC_TYPE_MASK UINT32_C(0xf0000000) - #define DBC_DBC_TYPE_SFT 28 + char test_name[8][32]; /* - * This is a SQ producer index update. It indicates one or more - * new entries have been written to the SQ for the QPID indicated - * on the xID field. This type is valid for L2, RoCE and Engine - * path. + * The lowest available target BER that is supported by FW eyescope. + * A Value of 3 indicates that FW supports 1e-8, 1e-9, 1e-10, and + * 1e-11. */ - #define DBC_DBC_TYPE_SQ (UINT32_C(0x0) << 28) + uint8_t eyescope_target_BER_support; + /* Eyescope supports a target BER of 1e-8 */ + #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED UINT32_C(0x0) + /* Eyescope supports a target BER of 1e-9 */ + #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED UINT32_C(0x1) + /* Eyescope supports a target BER of 1e-10 */ + #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED UINT32_C(0x2) + /* Eyescope supports a target BER of 1e-11 */ + #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED UINT32_C(0x3) + /* Eyescope supports a target BER of 1e-12 */ + #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED UINT32_C(0x4) + #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_LAST HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED + uint8_t unused_2[6]; /* - * This is a RQ producer index update. It indicates one or more - * new entries have been written to the RQ for the QPID indicated - * on the xID field. This type is valid for RoCE path. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define DBC_DBC_TYPE_RQ (UINT32_C(0x1) << 28) + uint8_t valid; +} hwrm_selftest_qlist_output_t, *phwrm_selftest_qlist_output_t; + +/********************** + * hwrm_selftest_exec * + **********************/ + + +/* hwrm_selftest_exec_input (size:192b/24B) */ + +typedef struct hwrm_selftest_exec_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This is a SRQ producer index update. It indicates one or more - * new entries have been written to the SRQ for the SID indicated - * on the xID field. This type is valid for L2 and RoCE path. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define DBC_DBC_TYPE_SRQ (UINT32_C(0x2) << 28) + uint16_t cmpl_ring; /* - * This doorbell command arms the SRQ async event. - * The xID field must identify the SID that is begin armed. - * The index field is will set the arm threshold such that - * a notification will be generated if less than that number - * or SRQ entries are posted. This type is valid for RoCE path. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define DBC_DBC_TYPE_SRQ_ARM (UINT32_C(0x3) << 28) + uint16_t seq_id; /* - * This is a CQ consumer index update. It indicates one or more - * entries have been processed off the CQ indicated on the xID - * field.This type is valid for L2, RoCE and Engine path. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define DBC_DBC_TYPE_CQ (UINT32_C(0x4) << 28) + uint16_t target_id; /* - * this is a CQ consumer index update that also arms the CQ for - * solicited events. This type is valid for RoCE path. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define DBC_DBC_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28) + uint64_t resp_addr; + /* This field indicates which self-test is being requested to run. */ + uint8_t flags; + /* Run the NVM test. */ + #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_NVM_TEST UINT32_C(0x1) + /* Run the link test. */ + #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_LINK_TEST UINT32_C(0x2) + /* Run the register test. */ + #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_REGISTER_TEST UINT32_C(0x4) + /* Run the memory test. */ + #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_MEMORY_TEST UINT32_C(0x8) + /* Run the PCIe serdes test. */ + #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10) + /* Run the Ethernet serdes test. */ + #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20) + uint8_t unused_0[7]; +} hwrm_selftest_exec_input_t, *phwrm_selftest_exec_input_t; + +/* hwrm_selftest_exec_output (size:128b/16B) */ + +typedef struct hwrm_selftest_exec_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The following tests were requested to be run. */ + uint8_t requested_tests; + /* A request was made to run the NVM test. */ + #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_NVM_TEST UINT32_C(0x1) + /* A request was made to run the link test. */ + #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_LINK_TEST UINT32_C(0x2) + /* A request was made to run the register test. */ + #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_REGISTER_TEST UINT32_C(0x4) + /* A request was made to run the memory test. */ + #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_MEMORY_TEST UINT32_C(0x8) + /* A request was made to run the PCIe serdes test. */ + #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PCIE_SERDES_TEST UINT32_C(0x10) + /* A request was made to run the Ethernet serdes test. */ + #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20) /* - * This is a CQ consumer index update that also arms the CQ - * for any new CQE. This type is valid for L2, RoCE and Engine - * path. + * If a test was requested to be run as seen in the requested_tests + * field, this bit indicates whether the test was successful(1) or + * failed(0). */ - #define DBC_DBC_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28) + uint8_t test_success; /* - * This is a CQ arm enable message. This message must be sent - * from the privileged driver before a new CQ_ARMSE or CQ_ARMALL - * message will be accepted. - * - * This doorbell can only be sent from the privileged (first) - * doorbell page of a function. + * If requested, a value of 1 indicates the NVM test completed + * successfully. */ - #define DBC_DBC_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28) + #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_NVM_TEST UINT32_C(0x1) /* - * This doorbell command enables the SRQ async event - * to be armed. This message must be sent from the privileged - * driver before a new SRQ_ARM message will be accepted. - * The xID field must identify the SID that is begin enabled - * for arm. - * - * This doorbell can only be sent from the privileged (first) - * doorbell page of a function. + * If requested, a value of 1 indicates the link test completed + * successfully. */ - #define DBC_DBC_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28) + #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_LINK_TEST UINT32_C(0x2) /* - * This doorbell command indicates that the cutoff CQE has - * been processed and the driver is now processing completions - * from the new CQ. - * - * The index field for this doorbell type must be zero. + * If requested, a value of 1 indicates the register test completed + * successfully. */ - #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9) << 28) + #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_REGISTER_TEST UINT32_C(0x4) /* - * This is a NQ consumer index update. It indicates one or more - * entries have been processed off the NQ indicated on the xID - * field. This type is valid for L2, RoCE and Engine path. + * If requested, a value of 1 indicates the memory test completed + * successfully. */ - #define DBC_DBC_TYPE_NQ (UINT32_C(0xa) << 28) + #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_MEMORY_TEST UINT32_C(0x8) /* - * This is a NQ consumer index update that also arms the NQ for - * any new NQE. This type is valid for L2, RoCE and Engine path. + * If requested, a value of 1 indicates the PCIe serdes test + * completed successfully. */ - #define DBC_DBC_TYPE_NQ_ARM (UINT32_C(0xb) << 28) + #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PCIE_SERDES_TEST UINT32_C(0x10) /* - * This is a NQ consumer index update that also arms the NQ for - * any new NQE. It is used for the legacy INT mask. This type - * is valid for L2, RoCE and Engine path. + * If requested, a value of 1 indicates the Ethernet serdes test + * completed successfully. */ - #define DBC_DBC_TYPE_NQ_MASK (UINT32_C(0xe) << 28) + #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_ETHERNET_SERDES_TEST UINT32_C(0x20) + uint8_t unused_0[5]; /* - * This doorbell command is used during doorbell moderation - * to consume system BW and help prevent doorbell FIFO - * overflow. - * - * All other fields should be zero for NULL doorbell. - * For doorbell recovery, NULL doorbell type in the Application - * table indicates that it is the last QP entry for the function. - * This type is valid for L2, RoCE and Engine path. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define DBC_DBC_TYPE_NULL (UINT32_C(0xf) << 28) - #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL -} dbc_dbc_t, *pdbc_dbc_t; + uint8_t valid; +} hwrm_selftest_exec_output_t, *phwrm_selftest_exec_output_t; -/* - * This is the 32b doorbell format. The host writes this message - * format directly to byte offset 8 of the appropriate doorbell page. - */ -/* dbc_dbc32 (size:32b/4B) */ +/********************* + * hwrm_selftest_irq * + *********************/ -typedef struct dbc_dbc32 { - uint32_t type_abs_incr_xid; - /* - * This value identifies the resource that the doorbell is intended - * to notify. - * - * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For - * CQ, this is the CID. - * - * Bits [19:16] of this values must be zero for a SID value. - */ - #define DBC_DBC32_XID_MASK UINT32_C(0xfffff) - #define DBC_DBC32_XID_SFT 0 - /* - * This value defines the intended doorbell path between RoCE and - * L2. - */ - #define DBC_DBC32_PATH_MASK UINT32_C(0xc00000) - #define DBC_DBC32_PATH_SFT 22 - /* This is a RoCE doorbell message. */ - #define DBC_DBC32_PATH_ROCE (UINT32_C(0x0) << 22) - /* This is a L2 doorbell message. */ - #define DBC_DBC32_PATH_L2 (UINT32_C(0x1) << 22) - #define DBC_DBC32_PATH_LAST DBC_DBC32_PATH_L2 - /* - * When abs=0, this value is the value to add to the appropriate - * index value. - * - * When abs=1, this value is the new value for the index. Absolute - * value is used when the queue is being wrapped. When abs=1, - * the incr value follows the same rules as the index value - * in the 64b doorbell. - */ - #define DBC_DBC32_INCR_MASK UINT32_C(0xf000000) - #define DBC_DBC32_INCR_SFT 24 - /* This value defines how the incr value will be interpreted. */ - #define DBC_DBC32_ABS UINT32_C(0x10000000) - /* This value identifies the type of doorbell being written. */ - #define DBC_DBC32_TYPE_MASK UINT32_C(0xe0000000) - #define DBC_DBC32_TYPE_SFT 29 - /* - * This is a SQ producer index update. It indicates one or more - * new entries have been written to the SQ for the QPID indicated - * on the xID field. - */ - #define DBC_DBC32_TYPE_SQ (UINT32_C(0x0) << 29) - #define DBC_DBC32_TYPE_LAST DBC_DBC32_TYPE_SQ -} dbc_dbc32_t, *pdbc_dbc32_t; -/* - * This is the 64b Push Start doorbell format. The host writes this message - * format directly to offset of each push associated WCB (write combine - * buffer) within doorbell page. WCB#0 = offset 16, WCB#1 = offset 24, - * WCB#2 = offset 32, ... The start doorbell is followed by write combining - * data to the WCB and then that is followed by a end doorbell. - */ -/* db_push_start (size:64b/8B) */ +/* hwrm_selftest_irq_input (size:128b/16B) */ -typedef struct db_push_start { - uint64_t db; - /* - * This is the push index and should be the SQ slot index, aligned - * to the start of the corresponding push WQE/packet in the Send - * Queue. - * - * The index size is 16b for RoCE path and 24b for L2 and Engine - * paths. Any unused bits should be written as zero. - * - * The index unit is 16B for L2 path. For RoCE there is a legacy - * mode with 128B unit size and a variable size mode with 16B unit - * size. For Engine mode, the unit size is 16B, where RQEs are - * always 128B - so it always increments by eight 16B slots per - * RQE. - * - * > This field is not used by the older versions of the chip, but - * > is used in this and future revisions of the chip. In older - * > versions of the chip, the driver is required to complete the - * > push doorbell operation by following it with a regular doorbell - * > which will be used to properly increment the producer index. - * > This extra doorbell write is not needed on this and future - * > versions of the chip. - */ - #define DB_PUSH_START_DB_INDEX_MASK UINT32_C(0xffffff) - #define DB_PUSH_START_DB_INDEX_SFT 0 +typedef struct hwrm_selftest_irq_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This value is the PI index (lower 8bits) within 4K DPI - * associated with push write. It is the doorbell page that - * contains the WCB that will be used. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define DB_PUSH_START_DB_PI_LO_MASK UINT32_C(0xff000000) - #define DB_PUSH_START_DB_PI_LO_SFT 24 + uint16_t cmpl_ring; /* - * This value identifies the resource that the doorbell is intended - * to notify. - * - * This is the QPID. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define DB_PUSH_START_DB_XID_MASK UINT32_C(0xfffff00000000)L - #define DB_PUSH_START_DB_XID_SFT 32 + uint16_t seq_id; /* - * This value is the PI index (upper 4bits) within 4K DPI - * associated with push write. It is the doorbell page that - * contains the WCB that will be used. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define DB_PUSH_START_DB_PI_HI_MASK UINT32_C(0xf0000000000000)L - #define DB_PUSH_START_DB_PI_HI_SFT 52 - /* This value identifies the type of doorbell being written. */ - #define DB_PUSH_START_DB_TYPE_MASK UINT32_C(0xf000000000000000)L - #define DB_PUSH_START_DB_TYPE_SFT 60 + uint16_t target_id; /* - * This is a SQ producer index update for Push. It indicates - * one or more new entries have been written to the SQ for the - * QPID indicated on the `xid` field. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define DB_PUSH_START_DB_TYPE_PUSH_START (UINT32_C(0xc)L << 60) + uint64_t resp_addr; +} hwrm_selftest_irq_input_t, *phwrm_selftest_irq_input_t; + +/* hwrm_selftest_irq_output (size:128b/16B) */ + +typedef struct hwrm_selftest_irq_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This is a SQ producer index update for Push. It indicates - * one or more new entries have been written to the SQ for the - * QPID indicated on the `xid` field. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define DB_PUSH_START_DB_TYPE_PUSH_END (UINT32_C(0xd)L << 60) - #define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END -} db_push_start_t, *pdb_push_start_t; + uint8_t valid; +} hwrm_selftest_irq_output_t, *phwrm_selftest_irq_output_t; -/* - * This is the 64b Push End doorbell format. The host writes this message - * format directly to offset of each push associated WCB (write combine - * buffer) within doorbell page. WCB#0 = offset 16, WCB#1 = offset 24, - * WCB#2 = offset 32, ... The start doorbell is followed by write combining - * data to the WCB and then that is followed by a end doorbell. - */ -/* db_push_end (size:64b/8B) */ +/************************************** + * hwrm_selftest_retrieve_serdes_data * + **************************************/ -typedef struct db_push_end { - uint64_t db; + +/* hwrm_selftest_retrieve_serdes_data_input (size:320b/40B) */ + +typedef struct hwrm_selftest_retrieve_serdes_data_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This is the producer index and should be the queue index of the - * last WQE written plus the length field contained in that WQE. - * For example, if the length is 8 index units and the WQE was - * written to the first location in the queue (zero), this index - * should be written to 8. The index should point to the start of - * the first location that has not been filled in with WQE data. - * - * For L2 and Engine SQ, the index unit is 16B. For RoCE there are - * two modes. For Legacy fixed size RQE mode, the unit is 128B. For - * variable size RQE mode, the unit is 16B. - * - * The index size is 24b for L2 and engine paths and 16b for the - * RoCE path. Unused bits should be written as zero. - * - * > In past revisions of this chip, this field was the push index - * > rather than the producer index. For this version of the chip - * > and future versions of the chip, this field must be the - * > producer index, as described above. - * > - * > Also, in past revisions of this chip, an additional - * > doorbell write was needed to communicate the producer index. - * > In this and future versions of the chip, this extra doorbell - * > write is no longer needed. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define DB_PUSH_END_DB_INDEX_MASK UINT32_C(0xffffff) - #define DB_PUSH_END_DB_INDEX_SFT 0 + uint16_t cmpl_ring; /* - * This value is the PI index (lower 8bits) within 4K DPI - * associated with push write. It is the doorbell page that - * contains the WCB that will be used. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define DB_PUSH_END_DB_PI_LO_MASK UINT32_C(0xff000000) - #define DB_PUSH_END_DB_PI_LO_SFT 24 + uint16_t seq_id; /* - * This value identifies the resource that the doorbell is intended - * to notify. - * - * This is the QPID. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define DB_PUSH_END_DB_XID_MASK UINT32_C(0xfffff00000000)L - #define DB_PUSH_END_DB_XID_SFT 32 + uint16_t target_id; /* - * This value is the PI index (upper 4bits) within 4K DPI - * associated with push write. It is the doorbell page that - * contains the WCB that will be used. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define DB_PUSH_END_DB_PI_HI_MASK UINT32_C(0xf0000000000000)L - #define DB_PUSH_END_DB_PI_HI_SFT 52 + uint64_t resp_addr; + /* Host address data is to DMA'd to. */ + uint64_t resp_data_addr; /* - * This value defines the intended doorbell path between RoCE and - * L2. + * This field contains the offset into the captured data to begin + * copying the data to the host from. This should be set to 0 on the + * initial call to this command. */ - #define DB_PUSH_END_DB_PATH_MASK UINT32_C(0x300000000000000)L - #define DB_PUSH_END_DB_PATH_SFT 56 - /* This is a RoCE doorbell message. */ - #define DB_PUSH_END_DB_PATH_ROCE (UINT32_C(0x0)L << 56) - /* This is a L2 doorbell message. */ - #define DB_PUSH_END_DB_PATH_L2 (UINT32_C(0x1)L << 56) - /* Engine path doorbell. */ - #define DB_PUSH_END_DB_PATH_ENGINE (UINT32_C(0x2)L << 56) - #define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE + uint32_t resp_data_offset; /* - * When this bit is set to one, the chip will capture debug - * information for the doorbell ring. This is intended to only be - * used on SQ doorbell rings. + * Size of the buffer pointed to by resp_data_addr. The firmware may + * use this entire buffer or less than the entire buffer, but never + * more. */ - #define DB_PUSH_END_DB_DEBUG_TRACE UINT32_C(0x800000000000000)L - /* This value identifies the type of doorbell being written. */ - #define DB_PUSH_END_DB_TYPE_MASK UINT32_C(0xf000000000000000)L - #define DB_PUSH_END_DB_TYPE_SFT 60 + uint16_t data_len; /* - * This is a SQ producer index update for Push. It indicates - * one or more new entries have been written to the SQ for the - * QPID indicated on the `xid` field. + * This field allows this command to request the individual serdes + * tests to be run using this command. */ - #define DB_PUSH_END_DB_TYPE_PUSH_START (UINT32_C(0xc)L << 60) + uint8_t flags; + /* Unused. */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_MASK UINT32_C(0x7) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_SFT 0 + /* Display eye_projection */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_EYE_PROJECTION UINT32_C(0x8) + /* Run the PCIe serdes test. */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10) + /* Run the Ethernet serdes test. */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20) + uint8_t options; /* - * This is a SQ producer index update for Push. It indicates - * one or more new entries have been written to the SQ for the - * QPID indicated on the `xid` field. + * This field represents the PCIE lane number on which tools wants to + * retrieve eye plot. This field is valid only when 'pcie_serdes_test' + * flag is set. + * Valid values from 0 to 16. */ - #define DB_PUSH_END_DB_TYPE_PUSH_END (UINT32_C(0xd)L << 60) - #define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END -} db_push_end_t, *pdb_push_end_t; - -/* - * This is the Push information that is the second 8B of the Push - * Doorbell. - */ -/* db_push_info (size:64b/8B) */ - -typedef struct db_push_info { - uint32_t push_size_push_index; + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PCIE_LANE_NO_MASK UINT32_C(0xf) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PCIE_LANE_NO_SFT 0 + /* This value indicates the Horizontal or vertical plot direction. */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION UINT32_C(0x10) + /* Value 0 indicates Horizontal plot request. */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_HORIZONTAL (UINT32_C(0x0) << 4) + /* Value 1 indicates vertical plot request. */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_VERTICAL (UINT32_C(0x1) << 4) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_VERTICAL + /* This value indicates eye projection type */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE UINT32_C(0x20) /* - * This value is the index for the push being started. For - * example, if the push_size is 8 index units and the WQE was - * written to the first location in the queue (zero), this - * push_index should be written to 0. The push_index should point - * to the start of the first location that the push is started. - * - * The push_index unit is 16B, except in RoCE legacy WQE mode, in - * which case the unit is 128B. - * - * The push_index size is 24b for L2 and 16b for the RoCE path. - * Unused bits should be written as zero. + * Value 0 indicates left/top projection in horizontal/vertical + * This value is valid only when eye_projection flag was set. */ - #define DB_PUSH_INFO_PUSH_INDEX_MASK UINT32_C(0xffffff) - #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_LEFT_TOP (UINT32_C(0x0) << 5) /* - * This value defines the size of push. The unit is 8B. The value - * 0 means 256B size of push. The push write is done in 8B units - * by the SW. - * - * Note: For packet rate performance reasons, it is recommended - * that SW aligns push requests with a granularity of 16B. + * Value 1 indicates right/bottom projection in + * horizontal/vertical. This value is valid only when + * eye_projection flag was set. */ - #define DB_PUSH_INFO_PUSH_SIZE_MASK UINT32_C(0x1f000000) - #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 - uint32_t reserved32; -} db_push_info_t, *pdb_push_info_t; - -/* - * This is the "Absolute" 32b Doorbell format. The host writes this - * message format directly to byte offset 0xC of the appropriate - * doorbell page. - * - * Absolute doorbells are supported for only a limited number of - * functions and for a limited number of xID values within each - * function. - * - * Doorbell recovery can be supported for absolute 32b doorbells. - */ -/* dbc_absolute_db_32 (size:32b/4B) */ - -typedef struct dbc_absolute_db_32 { - uint32_t index; + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM (UINT32_C(0x1) << 5) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM + /* Reserved for future. */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_RSVD_MASK UINT32_C(0xc0) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_RSVD_SFT 6 /* - * This value is the index being written. For SQ, RQ, SRQ, this is - * the producer index and should be the queue index of the last WQE - * or BD written plus the length field contained in that WQE/BD. - * For example, if the length is 8 index units and the WQE was - * written to the first location in the queue (zero), this index - * should be written to 8. The index should point to the start of - * the first location that has not been filled in with WQE/BD data. - * - * For CQ, this is the consumer index and should be the starting - * queue index of the last CQE processed plus the size of the last - * processed CQE in index units. The index should point to the start - * of the first CQE in the queue that has not been processed. - * - * For NQ, this is the consumer index and should be the starting - * queue index of the last NQE processed plus the size of the last - * processed NQE in index units. The index should point to the start - * of the first NQE in the queue that has not been processed. - * - * For L2 and Engine SQ, the index unit is 16B. For RoCE there are - * two modes. For Legacy fixed size RQE mode, the unit is 128B. For - * variable size RQE mode, the unit is 16B. For RoCE and engine CQs, - * the index unit is 32B. For L2 CQs, the index unit is 16B. - * - * For NQ this is the consumer index and the unit is always 16B of - * queue space. - * - * The index size is 16b for all queue types. This limits the size - * of some queues when absolute doorbells are in use. Unused bits - * should be written as zero. + * This field allows this command to request a specific targetBER + * to be run using this command. */ - #define DBC_ABSOLUTE_DB_32_INDEX_MASK UINT32_C(0xffff) - #define DBC_ABSOLUTE_DB_32_INDEX_SFT 0 + uint8_t targetBER; + /* When collecting an eyescope, measure with a target BER of 1e-8 */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E8 UINT32_C(0x0) + /* When collecting an eyescope, measure with a target BER of 1e-9 */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E9 UINT32_C(0x1) + /* When collecting an eyescope, measure with a target BER of 1e-10 */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E10 UINT32_C(0x2) + /* When collecting an eyescope, measure with a target BER of 1e-11 */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E11 UINT32_C(0x3) + /* When collecting an eyescope, measure with a target BER of 1e-12 */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E12 UINT32_C(0x4) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E12 /* - * The epoch bit provides a frame of reference for the queue index. - * S/W will toggle this bit in the doorbell each time index range is - * wrapped. This allows the receiving HW block to more efficiently - * detect out-of-order doorbells and to ignore the older doorbells. - * Out-of-order doorbells occur normally during dropped doorbell - * recovery. + * This field allows this command to specify the action to take when + * collecting an eyescope. */ - #define DBC_ABSOLUTE_DB_32_EPOCH UINT32_C(0x10000) + uint8_t action; /* - * The resize_toggle bit tells that the CQ cutoff is done. - * Every time CQ is resized by CQ cutoff, this bit toggles when it - * is done. If this bit toggles, HW can restart to use the resized - * CQ. + * Value 0 indicates that collection of the eyescope should be + * returned synchronously in the output. This only applies to + * a targetBER of 1e-8. */ - #define DBC_ABSOLUTE_DB_32_RESIZE_TOGGLE UINT32_C(0x20000) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_SYNCHRONOUS UINT32_C(0x0) /* - * This value identifies the resource that the doorbell is intended - * to notify. - * - * This is a "modified" xID value. The DBR block will convert this - * value into the full xID value by looking up the base xID for this - * particular function and adding the mxID value to that base value. + * Value 1 indicates to the firmware to start the collection of the + * eyescope. */ - #define DBC_ABSOLUTE_DB_32_MXID_MASK UINT32_C(0xfc0000) - #define DBC_ABSOLUTE_DB_32_MXID_SFT 18 + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_START UINT32_C(0x1) /* - * This value defines the intended doorbell path between RoCE and - * L2. + * Value 2 indicates to the firmware to respond with a progress + * percentage of the current eyescope collection from 0.0 to 100.0. */ - #define DBC_ABSOLUTE_DB_32_PATH_MASK UINT32_C(0x3000000) - #define DBC_ABSOLUTE_DB_32_PATH_SFT 24 - /* This is a RoCE doorbell message. */ - #define DBC_ABSOLUTE_DB_32_PATH_ROCE (UINT32_C(0x0) << 24) - /* This is a L2 doorbell message. */ - #define DBC_ABSOLUTE_DB_32_PATH_L2 (UINT32_C(0x1) << 24) - #define DBC_ABSOLUTE_DB_32_PATH_LAST DBC_ABSOLUTE_DB_32_PATH_L2 + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_PROGRESS UINT32_C(0x2) /* - * This indicates it is valid doorbell update. It should be set for - * each doorbell written to the chip and set when doorbell message is - * written to the backup doorbell location. The bit should be cleared - * in the backup doorbell location at time zero to indicate that the - * backup doorbell has not yet been written. + * Value 3 indicates to stop the eyescope. if the progress + * percentage is 100.0, the data will be DMAed back to + * resp_data_addr. */ - #define DBC_ABSOLUTE_DB_32_VALID UINT32_C(0x4000000) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_STOP UINT32_C(0x3) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_STOP + uint8_t unused[6]; +} hwrm_selftest_retrieve_serdes_data_input_t, *phwrm_selftest_retrieve_serdes_data_input_t; + +/* hwrm_selftest_retrieve_serdes_data_output (size:192b/24B) */ + +typedef struct hwrm_selftest_retrieve_serdes_data_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Total length of stored data. */ + uint16_t total_data_len; /* - * When this bit is set to one, the chip will capture debug - * information for the doorbell ring. This is intended to only be - * used on SQ doorbell rings. + * Amount of data DMA'd to host by this call. The driver can use this + * field along with the total_data_len field above to determine the + * value to write to the resp_data_offset field in the next call + * if more than one call to these commands is required to retrieve all + * the stored data. */ - #define DBC_ABSOLUTE_DB_32_DEBUG_TRACE UINT32_C(0x8000000) - /* This value identifies the type of doorbell being written. */ - #define DBC_ABSOLUTE_DB_32_TYPE_MASK UINT32_C(0xf0000000) - #define DBC_ABSOLUTE_DB_32_TYPE_SFT 28 + uint16_t copied_data_len; /* - * This is a SQ producer index update. It indicates one or more - * new entries have been written to the SQ for the QPID indicated - * on the xID field. This type is valid for L2, RoCE and Engine - * path. + * Percentage of completion of collection of BER values from the + * current eyescope operation in tenths of a percentage. 0 (0.0) to + * 1000 (100.0). */ - #define DBC_ABSOLUTE_DB_32_TYPE_SQ (UINT32_C(0x0) << 28) + uint16_t progress_percent; + /* Timeout in seconds for timeout of an individual BER point. */ + uint16_t timeout; + uint8_t flags; /* - * This is a RQ producer index update. It indicates one or more - * new entries have been written to the RQ for the QPID indicated - * on the xID field. This type is valid for RoCE path. + * This value indicates the structure of data returned by the + * firmware when DMA'ed to resp_data_addr. */ - #define DBC_ABSOLUTE_DB_32_TYPE_RQ (UINT32_C(0x1) << 28) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE UINT32_C(0x1) /* - * This is a SRQ producer index update. It indicates one or more - * new entries have been written to the SRQ for the SID indicated - * on the xID field. This type is valid for L2 and RoCE path. + * Value 0 indicates that bit_count value is a raw total + * such that BER = error_count / bit_count. */ - #define DBC_ABSOLUTE_DB_32_TYPE_SRQ (UINT32_C(0x2) << 28) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_TOTAL UINT32_C(0x0) /* - * This doorbell command arms the SRQ async event. - * The xID field must identify the SID that is begin armed. - * The index field is will set the arm threshold such that - * a notification will be generated if less than that number - * or SRQ entries are posted. This type is valid for RoCE path. + * Value 1 indicates that bit count is a power of + * 2 that bit_count is normalized to. A Value of 42 indicates + * that BER = error_count / 2^42 */ - #define DBC_ABSOLUTE_DB_32_TYPE_SRQ_ARM (UINT32_C(0x3) << 28) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_POW2 UINT32_C(0x1) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_POW2 + /* Reserved for future. */ + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_RSVD_MASK UINT32_C(0xfe) + #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_RSVD_SFT 1 + uint8_t unused_0; /* - * This is a CQ consumer index update. It indicates one or more - * entries have been processed off the CQ indicated on the xID - * field.This type is valid for L2, RoCE and Engine path. + * Size of header prepended to the bit_count and error_count array. + * Use this value to skip forward to the bit_count and error_count + * array. */ - #define DBC_ABSOLUTE_DB_32_TYPE_CQ (UINT32_C(0x4) << 28) + uint16_t hdr_size; + uint8_t unused_1[3]; /* - * this is a CQ consumer index update that also arms the CQ for - * solicited events. This type is valid for RoCE path. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28) + uint8_t valid; +} hwrm_selftest_retrieve_serdes_data_output_t, *phwrm_selftest_retrieve_serdes_data_output_t; + +/****************************** + * hwrm_mfg_fru_write_control * + ******************************/ + + +/* hwrm_mfg_fru_write_control_input (size:192b/24B) */ + +typedef struct hwrm_mfg_fru_write_control_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This is a CQ consumer index update that also arms the CQ - * for any new CQE. This type is valid for L2, RoCE and Engine - * path. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28) + uint16_t cmpl_ring; /* - * This is a NQ consumer index update. It indicates one or more - * entries have been processed off the NQ indicated on the xID - * field. This type is valid for L2, RoCE and Engine path. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define DBC_ABSOLUTE_DB_32_TYPE_NQ (UINT32_C(0xa) << 28) + uint16_t seq_id; /* - * This is a NQ consumer index update that also arms the NQ for - * any new NQE. This type is valid for L2, RoCE and Engine path. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define DBC_ABSOLUTE_DB_32_TYPE_NQ_ARM (UINT32_C(0xb) << 28) + uint16_t target_id; /* - * This is a NQ consumer index update that also arms the NQ for - * any new NQE. It is used for the legacy INT mask. This type - * is valid for L2, RoCE and Engine path. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define DBC_ABSOLUTE_DB_32_TYPE_NQ_MASK (UINT32_C(0xe) << 28) + uint64_t resp_addr; /* - * This doorbell command is used during doorbell moderation - * to consume system BW and help prevent doorbell FIFO - * overflow. - * - * All other fields should be zero for NULL doorbell. - * For doorbell recovery, NULL doorbell type in the Application - * table indicates that it is the last QP entry for the function. - * This type is valid for L2, RoCE and Engine path. + * This field indicates the lock/unlock operation. 0 means Unlock and + * 1 means Lock. */ - #define DBC_ABSOLUTE_DB_32_TYPE_NULL (UINT32_C(0xf) << 28) - #define DBC_ABSOLUTE_DB_32_TYPE_LAST DBC_ABSOLUTE_DB_32_TYPE_NULL -} dbc_absolute_db_32_t, *pdbc_absolute_db_32_t; + uint32_t fru_lock; + uint32_t unused_0; +} hwrm_mfg_fru_write_control_input_t, *phwrm_mfg_fru_write_control_input_t; -/* - * This is the "Relative" 32b Doorbell format. The host writes this - * message format directly to byte offset 8 of the appropriate doorbell - * page. - * - * Doorbell recovery can not be supported for relative doorbells. So - * relative doorbells are only safe to use when SOC is supporting the - * context backing store in local DDR. If that is the case, it is safe - * to turn off doorbell drops and use this type of doorbell. - */ -/* dbc_relative_db_32 (size:32b/4B) */ +/* hwrm_mfg_fru_write_control_output (size:128b/16B) */ -typedef struct dbc_relative_db_32 { - uint32_t xid; - /* - * This value identifies the resource that the doorbell is intended - * to notify. - * - * For SQ, this is the QPID value. - */ - #define DBC_RELATIVE_DB_32_XID_MASK UINT32_C(0xfffff) - #define DBC_RELATIVE_DB_32_XID_SFT 0 +typedef struct hwrm_mfg_fru_write_control_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * This value defines the intended doorbell path between RoCE and - * L2. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define DBC_RELATIVE_DB_32_PATH_MASK UINT32_C(0xc00000) - #define DBC_RELATIVE_DB_32_PATH_SFT 22 - /* This is a RoCE doorbell message. */ - #define DBC_RELATIVE_DB_32_PATH_ROCE (UINT32_C(0x0) << 22) - /* This is a L2 doorbell message. */ - #define DBC_RELATIVE_DB_32_PATH_L2 (UINT32_C(0x1) << 22) - #define DBC_RELATIVE_DB_32_PATH_LAST DBC_RELATIVE_DB_32_PATH_L2 + uint8_t valid; +} hwrm_mfg_fru_write_control_output_t, *phwrm_mfg_fru_write_control_output_t; + +/************************* + * hwrm_mfg_timers_query * + *************************/ + + +/* hwrm_mfg_timers_query_input (size:192b/24B) */ + +typedef struct hwrm_mfg_timers_query_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This value is the value to add to the appropriate index value. - * - * The increment unit is 16B for L2 path. For RoCE there is a - * legacy mode with 128B unit size and a variable size mode with - * 32B unit size. For Engine mode, the unit size is always 128B. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define DBC_RELATIVE_DB_32_INCR_MASK UINT32_C(0x1f000000) - #define DBC_RELATIVE_DB_32_INCR_SFT 24 - /* This value identifies the type of doorbell being written. */ - #define DBC_RELATIVE_DB_32_TYPE_MASK UINT32_C(0xe0000000) - #define DBC_RELATIVE_DB_32_TYPE_SFT 29 + uint16_t cmpl_ring; /* - * This is a SQ producer index update. It indicates one or more - * new entries have been written to the SQ for the QPID indicated - * on the xID field. This type is valid for L2, RoCE and Engine - * path. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define DBC_RELATIVE_DB_32_TYPE_SQ (UINT32_C(0x0) << 29) + uint16_t seq_id; /* - * This is a SRQ producer index update. It indicates one or more - * new entries have been written to the SRQ for the SID indicated - * on the xID field. This type is valid for L2 and RoCE path. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define DBC_RELATIVE_DB_32_TYPE_SRQ (UINT32_C(0x1) << 29) + uint16_t target_id; /* - * This is a CQ consumer index update. It indicates one or more - * entries have been processed off the CQ indicated on the xID - * field.This type is valid for L2, RoCE and Engine path. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define DBC_RELATIVE_DB_32_TYPE_CQ (UINT32_C(0x2) << 29) + uint64_t resp_addr; + uint64_t unused_0; +} hwrm_mfg_timers_query_input_t, *phwrm_mfg_timers_query_input_t; + +/* hwrm_mfg_timers_query_output (size:192b/24B) */ + +typedef struct hwrm_mfg_timers_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * This is a CQ consumer index update that also arms the CQ - * for any new CQE. This type is valid for L2, RoCE and Engine - * path. + * This is free running counter value running at 1 usec per tick. + * The value can wrap around. On error, a value of 0 on all ticks + * will be returned. */ - #define DBC_RELATIVE_DB_32_TYPE_CQ_ARMALL (UINT32_C(0x3) << 29) + uint32_t us_tick; /* - * This is a NQ consumer index update. It indicates one or more - * entries have been processed off the NQ indicated on the xID - * field. This type is valid for L2, RoCE and Engine path. + * This is free running counter value running at 1 msec per tick. + * The value can wrap around. On error, a value of 0 on all ticks + * will be returned. */ - #define DBC_RELATIVE_DB_32_TYPE_NQ (UINT32_C(0x4) << 29) + uint32_t ms_tick; /* - * This is a NQ consumer index update that also arms the NQ for - * any new NQE. This type is valid for L2, RoCE and Engine path. + * This is free running counter value running at 100 msec per tick. + * The value can wrap around. On error, a value of 0 on all ticks + * will be returned. */ - #define DBC_RELATIVE_DB_32_TYPE_NQ_ARM (UINT32_C(0x5) << 29) + uint32_t ms100_tick; + uint8_t unused_0[3]; /* - * This is a NQ consumer index update that also arms the NQ for - * any new NQE. It is used for the legacy INT mask. This type - * is valid for L2, RoCE and Engine path. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define DBC_RELATIVE_DB_32_TYPE_NQ_MASK (UINT32_C(0x6) << 29) - #define DBC_RELATIVE_DB_32_TYPE_LAST DBC_RELATIVE_DB_32_TYPE_NQ_MASK -} dbc_relative_db_32_t, *pdbc_relative_db_32_t; + uint8_t valid; +} hwrm_mfg_timers_query_output_t, *phwrm_mfg_timers_query_output_t; -/* - * The kernel memory structure is per-type (SQ, RQ, SRQ/SRQ_ARM and - * CQ/CQ_ARMSE/CQ_ARMALL). Each kernel driver will support a table for - * the doorbell recovery. - */ -/* dbc_drk (size:128b/16B) */ +/******************** + * hwrm_mfg_otp_cfg * + ********************/ -typedef struct dbc_drk { - uint32_t db_format_linked_last_valid; + +/* hwrm_mfg_otp_cfg_input (size:256b/32B) */ + +typedef struct hwrm_mfg_otp_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This indicates it is valid entry. It should be set for each - * doorbell written to the chip. The bit should be cleared at time - * zero to indicate that it has not yet been written. The bit i - * should be cleared when the function for the table is disabled. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define DBC_DRK_VALID UINT32_C(0x1) - /* This indicates it is last entry for the table. */ - #define DBC_DRK_LAST UINT32_C(0x2) - /* This indicates it is entry for the next 4KB kernel memory pointer. */ - #define DBC_DRK_LINKED UINT32_C(0x4) + uint16_t cmpl_ring; /* - * This field indicates if the doorbells in the table are 32b - * absolute or 64b format. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define DBC_DRK_DB_FORMAT UINT32_C(0x8) - /* The doorbells are 64b format. */ - #define DBC_DRK_DB_FORMAT_B64 (UINT32_C(0x0) << 3) + uint16_t seq_id; /* - * The doorbells are in the absolute 32b format. The doorbell - * is in the right-most half of the 64b space provided in the - * application table entry. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define DBC_DRK_DB_FORMAT_B32A (UINT32_C(0x1) << 3) - #define DBC_DRK_DB_FORMAT_LAST DBC_DRK_DB_FORMAT_B32A - uint32_t pi; + uint16_t target_id; /* - * Page Index portion of DPI{VF_VALID,VFID,PI}. The pi needs to match - * the value from the context DPI for the operation to be valid or the - * pi must be zero, indicating a write from the privileged driver. - * - * pi in the kernel memory table is there for DBR to generate the DPI - * message to the client. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define DBC_DRK_PI_MASK UINT32_C(0xffff) - #define DBC_DRK_PI_SFT 0 + uint64_t resp_addr; + uint16_t enables; /* - * It is the application memory page(4KB) pointer when linked = 0. - * It is the next kernel memory page(4KB) pointer when linked = 1. - * The pointer doesn't have to be aligned to the page(4KB) but it - * should be aligned to 128B boundary. This means that the bottom - * 7b of the pointer must be zero. + * This bit must be '1' for the crid field to be + * configured. */ - uint64_t memptr; -} dbc_drk_t, *pdbc_drk_t; + #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_CRID UINT32_C(0x1) + /* + * This bit must be '1' for the srt_rev_id field to be + * configured. + */ + #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_SRT_REV_ID UINT32_C(0x2) + /* + * This bit must be '1' for the crt_rev_id field to be + * configured. + */ + #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_CRT_REV_ID UINT32_C(0x4) + /* + * This bit must be '1' for the sbi_rev_id field to be + * configured. + */ + #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_SBI_REV_ID UINT32_C(0x8) + /* This field indicates the crid value to be set. */ + uint16_t crid_cfg_value; + /* This field indicates the srt rev id value to be set. */ + uint16_t srt_rev_id_cfg_value; + /* This field indicates the crt rev id value to be set. */ + uint16_t crt_rev_id_cfg_value; + /* This field indicates the sbi rev id value to be set. */ + uint16_t sbi_rev_id_cfg_value; + uint8_t unused_0[6]; +} hwrm_mfg_otp_cfg_input_t, *phwrm_mfg_otp_cfg_input_t; -/* - * This is a firmware status register that indicates the software status - * exposed by the firmware to the host. - * - * > This register is not present in previous versions of this chip. - */ -/* fw_status_reg (size:32b/4B) */ +/* hwrm_mfg_otp_cfg_output (size:128b/16B) */ -typedef struct fw_status_reg { - uint32_t fw_status; +typedef struct hwrm_mfg_otp_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* - * These bits indicate the status as being reported by the firmware. - * - * The value should be interpreted as follows: - * A value below 0x8000 is an indication that the firmware is still in the - * process of starting up and is not ready. The host driver should - * continue waiting with a timeout for firmware status to be ready. - * > 0x0000 to 0x00FF : SBL state information - * > 0x0200 to 0x02FF : SBI state information - * > 0x0400 to 0x04FF : SRT state information - * > 0x0600 to 0x06FF : CRT/CHIMP state information - * > 0x0800 to 0x08FF : External Firmware state information - * > 0x0A00 to 0x0FFF : Reserved for future fw functionality - * - * A value of 0x8000 indicates firmware is ready and healthy. The host - * driver can start initiating HWRM commands to the firmware. - * - * A value over 0x8000 is an indication that the firmware has detected - * a fatal error, this error could be in one of the hardware block or - * in a software module. The lower 8 bits indicate a block/module - * specific error and the upper 8 bits identify the hardware block - * or firmware module that was the source of the error. - * > 0x81XX - 0xBFXX : 63 ASIC blocks - * > 0xC0XX to 0xFDXX : 62 Firmware modules - * > 0xFE00 to 0xFEFF : External firmware module - * > 0xFFXX : Reserved for future + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define FW_STATUS_REG_CODE_MASK UINT32_C(0xffff) - #define FW_STATUS_REG_CODE_SFT 0 - /* Indicates firmware is ready. */ - #define FW_STATUS_REG_CODE_READY UINT32_C(0x8000) - #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY + uint8_t valid; +} hwrm_mfg_otp_cfg_output_t, *phwrm_mfg_otp_cfg_output_t; + +/********************* + * hwrm_mfg_otp_qcfg * + *********************/ + + +/* hwrm_mfg_otp_qcfg_input (size:192b/24B) */ + +typedef struct hwrm_mfg_otp_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * Image Degraded bit. If set indicates that one of the firmware - * image is degraded. - * - * The firmware binary located on NVM has redundant copies to protect - * against corruption. When one of the primary or secondary copy is - * detected as corrupted, this bit will be set by the firmware either - * as part of power on from the context of hwrm_fw_health_check. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define FW_STATUS_REG_IMAGE_DEGRADED UINT32_C(0x10000) + uint16_t cmpl_ring; /* - * Recoverable bit. If set indicates that the fatal error is - * recoverable with a full reset. - * - * This bit should be used by host software and deployment models - * that support error recovery by resetting the controller. A recovery - * should be attempted from a fatal error condition only if this bit - * is set. This bit is meaningful only when the code field is greater - * than 0x8000 (32768 decimal). + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define FW_STATUS_REG_RECOVERABLE UINT32_C(0x20000) + uint16_t seq_id; /* - * Crash dump is in process. If set indicates that the firmware is - * currently recording a crash dump. - * - * This bit provides a hint to the host driver if the firmware is - * currently recording a crash dump. Host driers should avoid resetting - * the controller when a crash dump is in progress if possible. This - * bit is meaningful only when the code field is greater than - * 0x8000 (32768 decimal). + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define FW_STATUS_REG_CRASHDUMP_ONGOING UINT32_C(0x40000) + uint16_t target_id; /* - * Crash dump is available. If set indicates that a firmware crash dump - * was recorded before and is now available. - * - * This bit provides indication to the host driver that the firmware has - * completed a crash dump. This bit is meaningful only when the code - * field is greater than 0x8000 (32768 decimal). + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define FW_STATUS_REG_CRASHDUMP_COMPLETE UINT32_C(0x80000) + uint64_t resp_addr; + uint16_t enables; /* - * This bit is used to indicate device state when it enters the shutdown mode - * and stopped the communication with the host. The host should initiate the - * reload of firmware image or initiate the reset to bring the device to the - * normal operational state and re-establish the communication. - * - * This bit is meaningful only when the code field is greater than 0x8000 - * (32768 decimal). + * This bit must be '1' for the crid field to be + * queried. */ - #define FW_STATUS_REG_SHUTDOWN UINT32_C(0x100000) + #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_CRID UINT32_C(0x1) /* - * This bit will be set to 1 by the FW when FW crashed without master - * function. - * - * This bit is controller specific, not all products will support this bit. - * This bit is valid only when the code field is greater than 0x8000 - * (32768 decimal). + * This bit must be '1' for the srt_rev_id field to be + * queried. */ - #define FW_STATUS_REG_CRASHED_NO_MASTER UINT32_C(0x200000) + #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_SRT_REV_ID UINT32_C(0x2) /* - * The firmware sets this bit to 1 when the firmware has taken an exception - * and expects to initiate error recovery. - * - * This bit is valid only when the code field is greater than 0x8000 - * (32768 decimal). + * This bit must be '1' for the crt_rev_id field to be + * queried. */ - #define FW_STATUS_REG_RECOVERING UINT32_C(0x400000) + #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_CRT_REV_ID UINT32_C(0x4) /* - * The SBL sets this bit to indicate whether manu_debug pin is detected high - * or low. + * This bit must be '1' for the sbi_rev_id field to be + * queried. */ - #define FW_STATUS_REG_MANU_DEBUG_STATUS UINT32_C(0x800000) -} fw_status_reg_t, *pfw_status_reg_t; + #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_SBI_REV_ID UINT32_C(0x8) + uint8_t unused_0[6]; +} hwrm_mfg_otp_qcfg_input_t, *phwrm_mfg_otp_qcfg_input_t; -/* - * This structure is fixed at the beginning of the ChiMP SRAM (GRC - * offset: 0x31001F0). Host software is expected to read from this - * location for a defined signature. If it exists, the software can - * assume the presence of this structure and the validity of the - * FW_STATUS location in the next field. - */ -/* hcomm_status (size:64b/8B) */ +/* hwrm_mfg_otp_qcfg_output (size:192b/24B) */ -typedef struct hcomm_status { - uint32_t sig_ver; - /* - * This field defines the version of the structure. The latest - * version value is 1. - */ - #define HCOMM_STATUS_VER_MASK UINT32_C(0xff) - #define HCOMM_STATUS_VER_SFT 0 - #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1) - #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST +typedef struct hwrm_mfg_otp_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * This field is to store the signature value to indicate the - * presence of the structure. + * This field contains the value of current device type. The + * value indicates the current chip mode (Unassigned/AB_PROD). */ - #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00) - #define HCOMM_STATUS_SIGNATURE_SFT 8 - #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8) - #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL - uint32_t fw_status_loc; - #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3) - #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 - /* PCIE configuration space */ - #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0) - /* GRC space */ - #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1) - /* BAR0 space */ - #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2) - /* BAR1 space */ - #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3) - #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 + uint32_t enc_device_type; + /* This field indicates the current crid value. */ + uint16_t crid; + /* This field indicates the current srt rev id value. */ + uint16_t srt_rev_id; + /* This field indicates the current crt rev id value. */ + uint16_t crt_rev_id; + /* This field indicates the current sbi rev id value. */ + uint16_t sbi_rev_id; + uint8_t unused_0[3]; /* - * This offset where the fw_status register is located. The value - * is generally 4-byte aligned. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc) - #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 -} hcomm_status_t, *phcomm_status_t; - -/* This is the GRC offset where the hcomm_status struct resides. */ -#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL + uint8_t valid; +} hwrm_mfg_otp_qcfg_output_t, *phwrm_mfg_otp_qcfg_output_t; -/*********************** - * hwrm_selftest_qlist * - ***********************/ +/********************** + * hwrm_mfg_hdma_test * + **********************/ -/* hwrm_selftest_qlist_input (size:128b/16B) */ +/* hwrm_mfg_hdma_test_input (size:384b/48B) */ -typedef struct hwrm_selftest_qlist_input { +typedef struct hwrm_mfg_hdma_test_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -76014,11 +89049,35 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_selftest_qlist_input_t, *phwrm_selftest_qlist_input_t; + /* The host (DMA) buffer physical addr for the firmware to read from. */ + uint64_t host_src_data_addr; + /* The host (DMA) buffer physical addr for the firmware to write to. */ + uint64_t host_dst_data_addr; + /* + * The user provided data pattern which will be used in the DMA + * transfer. + */ + uint64_t user_data_pattern; + /* Timeout value to stop the test. */ + uint16_t timeout; + /* The number of DMA transfers to be done in the test. */ + uint16_t repeat_count; + /* Types can be any of "incremental", "fixed", or "random". */ + uint16_t subtype; + /* Test is run with the incremental data pattern. */ + #define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_INCREMENTAL UINT32_C(0x1) + /* Test is run with the fixed data pattern. */ + #define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_FIXED UINT32_C(0x2) + /* Test is run with a random data pattern. */ + #define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_RANDOM UINT32_C(0x3) + #define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_LAST HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_RANDOM + /* The length of the data used in the DMA transfers. */ + uint16_t data_len; +} hwrm_mfg_hdma_test_input_t, *phwrm_mfg_hdma_test_input_t; -/* hwrm_selftest_qlist_output (size:2240b/280B) */ +/* hwrm_mfg_hdma_test_output (size:128b/16B) */ -typedef struct hwrm_selftest_qlist_output { +typedef struct hwrm_mfg_hdma_test_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -76027,120 +89086,181 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + uint8_t unused_0[7]; /* - * This field represents the number of tests available to be - * requested by a driver. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint8_t num_tests; - /* This field indicates which self-test is available to be run. */ - uint8_t available_tests; - /* Can run the NVM test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_NVM_TEST UINT32_C(0x1) - /* Can run the link test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_LINK_TEST UINT32_C(0x2) - /* Can run the register test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_REGISTER_TEST UINT32_C(0x4) - /* Can run the memory test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_MEMORY_TEST UINT32_C(0x8) - /* Can run the PCIe serdes test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10) - /* Can run the Ethernet serdes test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20) - uint8_t offline_tests; - /* The NVM test is an offline test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_NVM_TEST UINT32_C(0x1) - /* The link test is an offline test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_LINK_TEST UINT32_C(0x2) - /* The register test is an offline test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_REGISTER_TEST UINT32_C(0x4) - /* The memory test is an offline test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_MEMORY_TEST UINT32_C(0x8) - /* The PCIe serdes test is an offline test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10) - /* The Ethernet serdes test is an offline test. */ - #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20) - uint8_t unused_0; + uint8_t valid; +} hwrm_mfg_hdma_test_output_t, *phwrm_mfg_hdma_test_output_t; + +/***************************** + * hwrm_mfg_fru_eeprom_write * + *****************************/ + + +/* hwrm_mfg_fru_eeprom_write_input (size:256b/32B) */ + +typedef struct hwrm_mfg_fru_eeprom_write_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This field represents the maximum timeout for all the - * tests to complete in milliseconds. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t test_timeout; - uint8_t unused_1[2]; + uint16_t cmpl_ring; /* - * This field represents the name of the NVM test (ASCII chars - * with NULL at the end). + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - char test0_name[32]; + uint16_t seq_id; /* - * This field represents the name of the link test (ASCII chars - * with NULL at the end). + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - char test1_name[32]; + uint16_t target_id; /* - * This field represents the name of the register test (ASCII chars - * with NULL at the end). + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - char test2_name[32]; + uint64_t resp_addr; /* - * This field represents the name of the memory test (ASCII chars - * with NULL at the end). + * The host (DMA) buffer physical addr for the firmware to read from. + * This buffer is populated with the fru binary bits which is going + * to be programmed into the fru memory. */ - char test3_name[32]; + uint64_t data_addr; + /* i2c slave address. If set to 0xffff, fw will decide what to use. */ + uint16_t i2c_slave_addr; + /* Size of the buffer pointed to by data_addr. */ + uint16_t data_len; + /* The offset within the SEEPROM to start programming. */ + uint16_t offset; + uint8_t unused[2]; +} hwrm_mfg_fru_eeprom_write_input_t, *phwrm_mfg_fru_eeprom_write_input_t; + +/* hwrm_mfg_fru_eeprom_write_output (size:128b/16B) */ + +typedef struct hwrm_mfg_fru_eeprom_write_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Total length of data written to the fru memory. */ + uint16_t total_data_len; + uint16_t unused_0; + uint8_t unused_1[3]; /* - * This field represents the name of the PCIe serdes test (ASCII chars - * with NULL at the end). + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - char test4_name[32]; + uint8_t valid; +} hwrm_mfg_fru_eeprom_write_output_t, *phwrm_mfg_fru_eeprom_write_output_t; + +/**************************** + * hwrm_mfg_fru_eeprom_read * + ****************************/ + + +/* hwrm_mfg_fru_eeprom_read_input (size:256b/32B) */ + +typedef struct hwrm_mfg_fru_eeprom_read_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This field represents the name of the Ethernet serdes test (ASCII chars - * with NULL at the end). + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - char test5_name[32]; + uint16_t cmpl_ring; /* - * This field represents the name of some future test (ASCII chars - * with NULL at the end). + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - char test6_name[32]; + uint16_t seq_id; /* - * This field represents the name of some future test (ASCII chars - * with NULL at the end). + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - char test7_name[32]; + uint16_t target_id; /* - * The lowest available target BER that is supported by FW eyescope. - * A Value of 3 indicates that FW supports 1e-8, 1e-9, 1e-10, and 1e-11. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint8_t eyescope_target_BER_support; - /* Eyescope supports a target BER of 1e-8 */ - #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED UINT32_C(0x0) - /* Eyescope supports a target BER of 1e-9 */ - #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED UINT32_C(0x1) - /* Eyescope supports a target BER of 1e-10 */ - #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED UINT32_C(0x2) - /* Eyescope supports a target BER of 1e-11 */ - #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED UINT32_C(0x3) - /* Eyescope supports a target BER of 1e-12 */ - #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED UINT32_C(0x4) - #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_LAST HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED - uint8_t unused_2[6]; + uint64_t resp_addr; + /* + * The host (DMA) buffer physical addr for the firmware to write to. + * This buffer is populated with the fru binary bits which is going + * to be read from the fru memory. + */ + uint64_t data_addr; + /* i2c slave address. If set to 0xffff, fw will decide what to use. */ + uint16_t i2c_slave_addr; + /* + * Size of the buffer pointed to by data_addr. The firmware may + * use this entire buffer or less than the entire buffer, but never + * more. + */ + uint16_t data_len; + /* The offset within the SEEPROM to start reading. */ + uint16_t offset; + uint8_t unused[2]; +} hwrm_mfg_fru_eeprom_read_input_t, *phwrm_mfg_fru_eeprom_read_input_t; + +/* hwrm_mfg_fru_eeprom_read_output (size:128b/16B) */ + +typedef struct hwrm_mfg_fru_eeprom_read_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Total length of data written to the host memory. */ + uint16_t total_data_len; + uint16_t unused_0; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_selftest_qlist_output_t, *phwrm_selftest_qlist_output_t; +} hwrm_mfg_fru_eeprom_read_output_t, *phwrm_mfg_fru_eeprom_read_output_t; /********************** - * hwrm_selftest_exec * + * hwrm_mfg_soc_image * **********************/ -/* hwrm_selftest_exec_input (size:192b/24B) */ +/* hwrm_mfg_soc_image_input (size:512b/64B) */ -typedef struct hwrm_selftest_exec_input { +typedef struct hwrm_mfg_soc_image_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -76169,26 +89289,76 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This field indicates which self-test is being requested to run. */ - uint8_t flags; - /* Run the NVM test. */ - #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_NVM_TEST UINT32_C(0x1) - /* Run the link test. */ - #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_LINK_TEST UINT32_C(0x2) - /* Run the register test. */ - #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_REGISTER_TEST UINT32_C(0x4) - /* Run the memory test. */ - #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_MEMORY_TEST UINT32_C(0x8) - /* Run the PCIe serdes test. */ - #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10) - /* Run the Ethernet serdes test. */ - #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20) - uint8_t unused_0[7]; -} hwrm_selftest_exec_input_t, *phwrm_selftest_exec_input_t; + /* + * TBD. Work in progress. + * This field is the signature value used by SoC UEFI. + */ + uint32_t image_signature; + /* + * TBD. Work in progress. + * This field is unused for now. + */ + uint32_t image_type; + /* + * The offset within the image content that is being provided by the + * current invocation of this HWRM command. The primate firmware does + * not offer any score boarding services to ensure entire image + * content is transferred, it is the responsibility of the caller to + * ensure image consistency. + */ + uint32_t image_offset; + /* + * Size in bytes for the image content. The maximum value this field + * can specify is 4096. + */ + uint32_t image_length; + /* + * Address in host memory where the image content is located. This + * location should be 4KB aligned. + */ + uint64_t host_src_addr; + /* + * Address in SoC address space where the provided image content is + * to be copied. Primate firmware will copy the image content from + * host memory to this location. If the image size is more than the + * maximum size that can be transferred with each invocation of this + * command, then this address should be updated by the caller for + * each invocation to copy the full image. + */ + uint64_t soc_dest_addr; + /* + * Indicates the entrypoint in the image that should be used. This + * field is optional. When set to 0, the SoC will determine the + * entrypoint on its own. + */ + uint32_t entrypoint_offset; + uint32_t flags; + /* + * This bit should be set to '1' only when an image transfer is + * being initiated for each unique image_signature. + */ + #define HWRM_MFG_SOC_IMAGE_INPUT_FLAGS_START UINT32_C(0x1) + /* + * This bit should be set to '1' only when an image transfer for a + * given image_signature is complete. + */ + #define HWRM_MFG_SOC_IMAGE_INPUT_FLAGS_END UINT32_C(0x2) + /* + * An incrementing number starting with 1 for each invocation of this + * HWRM command for any given image_id. No two invocation of this + * command for a given image_id shall carry the same seq_number. Each + * consecutive invocation of this command for any given image_id + * shall increment this number by 1. The value 0 is used when + * seq_number is invalid when no image content is being moved. + */ + uint32_t seq_number; + /* */ + uint32_t reserved1; +} hwrm_mfg_soc_image_input_t, *phwrm_mfg_soc_image_input_t; -/* hwrm_selftest_exec_output (size:128b/16B) */ +/* hwrm_mfg_soc_image_output (size:128b/16B) */ -typedef struct hwrm_selftest_exec_output { +typedef struct hwrm_mfg_soc_image_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -76197,56 +89367,26 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The following tests were requested to be run. */ - uint8_t requested_tests; - /* A request was made to run the NVM test. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_NVM_TEST UINT32_C(0x1) - /* A request was made to run the link test. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_LINK_TEST UINT32_C(0x2) - /* A request was made to run the register test. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_REGISTER_TEST UINT32_C(0x4) - /* A request was made to run the memory test. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_MEMORY_TEST UINT32_C(0x8) - /* A request was made to run the PCIe serdes test. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PCIE_SERDES_TEST UINT32_C(0x10) - /* A request was made to run the Ethernet serdes test. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20) - /* - * If a test was requested to be run as seen in the requested_tests field, - * this bit indicates whether the test was successful(1) or failed(0). - */ - uint8_t test_success; - /* If requested, a value of 1 indicates the NVM test completed successfully. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_NVM_TEST UINT32_C(0x1) - /* If requested, a value of 1 indicates the link test completed successfully. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_LINK_TEST UINT32_C(0x2) - /* If requested, a value of 1 indicates the register test completed successfully. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_REGISTER_TEST UINT32_C(0x4) - /* If requested, a value of 1 indicates the memory test completed successfully. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_MEMORY_TEST UINT32_C(0x8) - /* If requested, a value of 1 indicates the PCIe serdes test completed successfully. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PCIE_SERDES_TEST UINT32_C(0x10) - /* If requested, a value of 1 indicates the Ethernet serdes test completed successfully. */ - #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_ETHERNET_SERDES_TEST UINT32_C(0x20) - uint8_t unused_0[5]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_selftest_exec_output_t, *phwrm_selftest_exec_output_t; +} hwrm_mfg_soc_image_output_t, *phwrm_mfg_soc_image_output_t; -/********************* - * hwrm_selftest_irq * - *********************/ +/************************ + * hwrm_mfg_soc_qstatus * + ************************/ -/* hwrm_selftest_irq_input (size:128b/16B) */ +/* hwrm_mfg_soc_qstatus_input (size:192b/24B) */ -typedef struct hwrm_selftest_irq_input { +typedef struct hwrm_mfg_soc_qstatus_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -76275,11 +89415,15 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_selftest_irq_input_t, *phwrm_selftest_irq_input_t; + /* */ + uint32_t reserved1; + /* */ + uint32_t reserved2; +} hwrm_mfg_soc_qstatus_input_t, *phwrm_mfg_soc_qstatus_input_t; -/* hwrm_selftest_irq_output (size:128b/16B) */ +/* hwrm_mfg_soc_qstatus_output (size:576b/72B) */ -typedef struct hwrm_selftest_irq_output { +typedef struct hwrm_mfg_soc_qstatus_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -76288,25 +89432,57 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * This field describes capabilities of primate firmware for SoC + * image. + */ + uint32_t primate_flags; + /* */ + uint32_t reserved1; + /* This field contains the current content of the AP_STATUS register. */ + uint32_t ap_status; + /* + * This field contains the current content of the CRMU_STATUS + * register. + */ + uint32_t crmu_status; + /* + * If an image provision operation is in process, this field will + * provide information on requested image signature else the contents + * are undefined. + */ + uint32_t image_signature; + /* + * If an image provision operation is in process, this field will + * provide information on requested image command else the contents + * are undefined. + */ + uint32_t image_command; + /* + * If an image provision operation is in process, this field will + * provide the requested image name else the contents are undefined. + */ + uint8_t image_name[32]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_selftest_irq_output_t, *phwrm_selftest_irq_output_t; +} hwrm_mfg_soc_qstatus_output_t, *phwrm_mfg_soc_qstatus_output_t; -/************************************** - * hwrm_selftest_retrieve_serdes_data * - **************************************/ +/***************************************** + * hwrm_mfg_param_critical_data_finalize * + *****************************************/ -/* hwrm_selftest_retrieve_serdes_data_input (size:320b/40B) */ +/* hwrm_mfg_param_critical_data_finalize_input (size:192b/24B) */ -typedef struct hwrm_selftest_retrieve_serdes_data_input { +typedef struct hwrm_mfg_param_critical_data_finalize_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -76335,110 +89511,19 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Host address data is to DMA'd to. */ - uint64_t resp_data_addr; - /* - * This field contains the offset into the captured data to begin - * copying the data to the host from. This should be set to 0 on the - * initial call to this command. - */ - uint32_t resp_data_offset; - /* - * Size of the buffer pointed to by resp_data_addr. The firmware may - * use this entire buffer or less than the entire buffer, but never more. - */ - uint16_t data_len; - /* - * This field allows this command to request the individual serdes tests - * to be run using this command. - */ - uint8_t flags; - /* Unused. */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_MASK UINT32_C(0x7) - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_SFT 0 - /* Display eye_projection */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_EYE_PROJECTION UINT32_C(0x8) - /* Run the PCIe serdes test. */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10) - /* Run the Ethernet serdes test. */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20) - uint8_t options; - /* - * This field represents the PCIE lane number on which tools wants to - * retrieve eye plot. This field is valid only when ‘pcie_serdes_test’ flag is set. - * Valid values from 0 to 16. - */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PCIE_LANE_NO_MASK UINT32_C(0xf) - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PCIE_LANE_NO_SFT 0 - /* This value indicates the Horizontal or vertical plot direction. */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION UINT32_C(0x10) - /* Value 0 indicates Horizontal plot request. */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_HORIZONTAL (UINT32_C(0x0) << 4) - /* Value 1 indicates vertical plot request. */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_VERTICAL (UINT32_C(0x1) << 4) - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_VERTICAL - /* This value indicates eye projection type */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE UINT32_C(0x20) - /* - * Value 0 indicates left/top projection in horizontal/vertical - * This value is valid only when eye_projection flag was set. - */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_LEFT_TOP (UINT32_C(0x0) << 5) - /* - * Value 1 indicates right/bottom projection in horizontal/vertical - * This value is valid only when eye_projection flag was set. - */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM (UINT32_C(0x1) << 5) - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM - /* Reserved for future. */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_RSVD_MASK UINT32_C(0xc0) - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_RSVD_SFT 6 - /* - * This field allows this command to request a specific targetBER - * to be run using this command. - */ - uint8_t targetBER; - /* When collecting an eyescope, measure with a target BER of 1e-8 */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E8 UINT32_C(0x0) - /* When collecting an eyescope, measure with a target BER of 1e-9 */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E9 UINT32_C(0x1) - /* When collecting an eyescope, measure with a target BER of 1e-10 */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E10 UINT32_C(0x2) - /* When collecting an eyescope, measure with a target BER of 1e-11 */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E11 UINT32_C(0x3) - /* When collecting an eyescope, measure with a target BER of 1e-12 */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E12 UINT32_C(0x4) - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E12 - /* - * This field allows this command to specify the action to take when - * collecting an eyescope. - */ - uint8_t action; - /* - * Value 0 indicates that collection of the eyescope should be - * returned synchronously in the output. This only applies to - * a targetBER of 1e-8. - */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_SYNCHRONOUS UINT32_C(0x0) - /* Value 1 indicates to the firmware to start the collection of the eyescope. */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_START UINT32_C(0x1) - /* - * Value 2 indicates to the firmware to respond with a progress percentage - * of the current eyescope collection from 0.0 to 100.0. - */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_PROGRESS UINT32_C(0x2) + uint16_t flags; /* - * Value 3 indicates to stop the eyescope. if the progress percentage - * is 100.0, the data will be DMAed back to resp_data_addr. + * Set to 1 if you wish to unlock and erase the region + * before finalizing the data. */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_STOP UINT32_C(0x3) - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_STOP - uint8_t unused[6]; -} hwrm_selftest_retrieve_serdes_data_input_t, *phwrm_selftest_retrieve_serdes_data_input_t; + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_INPUT_FLAGS_FORCE UINT32_C(0x1) + uint16_t unused_0; + uint32_t unused_1; +} hwrm_mfg_param_critical_data_finalize_input_t, *phwrm_mfg_param_critical_data_finalize_input_t; -/* hwrm_selftest_retrieve_serdes_data_output (size:192b/24B) */ +/* hwrm_mfg_param_critical_data_finalize_output (size:128b/16B) */ -typedef struct hwrm_selftest_retrieve_serdes_data_output { +typedef struct hwrm_mfg_param_critical_data_finalize_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -76447,69 +89532,36 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Total length of stored data. */ - uint16_t total_data_len; - /* - * Amount of data DMA'd to host by this call. The driver can use this - * field along with the total_data_len field above to determine the - * value to write to the resp_data_offset field in the next call - * if more than one call to these commands is required to retrieve all - * the stored data. - */ - uint16_t copied_data_len; - /* - * Percentage of completion of collection of BER values from the current - * eyescope operation in tenths of a percentage. 0 (0.0) to 1000 (100.0) - */ - uint16_t progress_percent; - /* Timeout in seconds for timeout of an individual BER point. */ - uint16_t timeout; - uint8_t flags; - /* - * This value indicates the structure of data returned by the firmware - * when DMA'ed to resp_data_addr - */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE UINT32_C(0x1) - /* - * Value 0 indicates that bit_count value is a raw total - * such that BER = error_count / bit_count. - */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_TOTAL UINT32_C(0x0) - /* - * Value 1 indicates that bit count is a power of - * 2 that bit_count is normalized to. A Value of 42 indicates - * that BER = error_count / 2^42 - */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_POW2 UINT32_C(0x1) - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_POW2 - /* Reserved for future. */ - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_RSVD_MASK UINT32_C(0xfe) - #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_RSVD_SFT 1 - uint8_t unused_0; - /* - * Size of header prepended to the bit_count and error_count array. - * Use this value to skip forward to the bit_count and error_count array. - */ - uint16_t hdr_size; - uint8_t unused_1[3]; + /* Total length of data finalized. */ + uint32_t total_data_len; + uint16_t error_status; + /* Critical data region was already locked */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_ALREADY_LOCKED UINT32_C(0x1) + /* Flash region was not entirely empty */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_NOT_EMPTY UINT32_C(0x2) + /* FACT_CFG was missing for write to critical cfg */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_MISSING_FACT_CFG UINT32_C(0x4) + /* VPD was missing for write to critical cfg */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_MISSING_VPD UINT32_C(0x8) + uint8_t unused_1; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_selftest_retrieve_serdes_data_output_t, *phwrm_selftest_retrieve_serdes_data_output_t; +} hwrm_mfg_param_critical_data_finalize_output_t, *phwrm_mfg_param_critical_data_finalize_output_t; -/****************************** - * hwrm_mfg_fru_write_control * - ******************************/ +/************************************* + * hwrm_mfg_param_critical_data_read * + *************************************/ -/* hwrm_mfg_fru_write_control_input (size:192b/24B) */ +/* hwrm_mfg_param_critical_data_read_input (size:256b/32B) */ -typedef struct hwrm_mfg_fru_write_control_input { +typedef struct hwrm_mfg_param_critical_data_read_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -76539,16 +89591,24 @@ */ uint64_t resp_addr; /* - * This field indicates the lock/unlock operation. 0 means Unlock and - * 1 means Lock. + * The host (DMA) buffer physical addr for the firmware to write to. + * This buffer is populated with data read from the + * critical data storage location. */ - uint32_t fru_lock; - uint32_t unused_0; -} hwrm_mfg_fru_write_control_input_t, *phwrm_mfg_fru_write_control_input_t; + uint64_t data_addr; + /* + * Size of the buffer pointed to by data_addr. The firmware may + * use this entire buffer or less than the entire buffer, but never + * more. + */ + uint32_t data_len; + /* The offset within the critical data to start reading. */ + uint32_t offset; +} hwrm_mfg_param_critical_data_read_input_t, *phwrm_mfg_param_critical_data_read_input_t; -/* hwrm_mfg_fru_write_control_output (size:128b/16B) */ +/* hwrm_mfg_param_critical_data_read_output (size:128b/16B) */ -typedef struct hwrm_mfg_fru_write_control_output { +typedef struct hwrm_mfg_param_critical_data_read_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -76557,25 +89617,28 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Total length of data written to the host memory. */ + uint32_t total_data_len; + uint16_t unused_0; + uint8_t unused_1; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_fru_write_control_output_t, *phwrm_mfg_fru_write_control_output_t; +} hwrm_mfg_param_critical_data_read_output_t, *phwrm_mfg_param_critical_data_read_output_t; -/************************* - * hwrm_mfg_timers_query * - *************************/ +/*************************************** + * hwrm_mfg_param_critical_data_health * + ***************************************/ -/* hwrm_mfg_timers_query_input (size:192b/24B) */ +/* hwrm_mfg_param_critical_data_health_input (size:192b/24B) */ -typedef struct hwrm_mfg_timers_query_input { +typedef struct hwrm_mfg_param_critical_data_health_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -76605,11 +89668,11 @@ */ uint64_t resp_addr; uint64_t unused_0; -} hwrm_mfg_timers_query_input_t, *phwrm_mfg_timers_query_input_t; +} hwrm_mfg_param_critical_data_health_input_t, *phwrm_mfg_param_critical_data_health_input_t; -/* hwrm_mfg_timers_query_output (size:192b/24B) */ +/* hwrm_mfg_param_critical_data_health_output (size:128b/16B) */ -typedef struct hwrm_mfg_timers_query_output { +typedef struct hwrm_mfg_param_critical_data_health_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -76618,43 +89681,35 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This is free running counter value running at 1 usec per tick. - * The value can wrap around. On error, a value of 0 on all ticks - * will be returned. - */ - uint32_t us_tick; - /* - * This is free running counter value running at 1 msec per tick. - * The value can wrap around. On error, a value of 0 on all ticks - * will be returned. - */ - uint32_t ms_tick; - /* - * This is free running counter value running at 100 msec per tick. - * The value can wrap around. On error, a value of 0 on all ticks - * will be returned. - */ - uint32_t ms100_tick; - uint8_t unused_0[3]; + uint32_t health_status; + /* region entirely empty */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_IS_EMPTY UINT32_C(0x1) + /* Data checksum fail */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_CHECKSUM_FAIL UINT32_C(0x2) + /* Malformed data (header/footer) */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_MALFORMED_DATA UINT32_C(0x4) + /* Critical data not locked */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_NOT_LOCKED UINT32_C(0x8) + uint16_t unused_1; + uint8_t unused_2; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_timers_query_output_t, *phwrm_mfg_timers_query_output_t; +} hwrm_mfg_param_critical_data_health_output_t, *phwrm_mfg_param_critical_data_health_output_t; -/******************** - * hwrm_mfg_otp_cfg * - ********************/ +/***************************** + * hwrm_mfg_prvsn_export_csr * + *****************************/ -/* hwrm_mfg_otp_cfg_input (size:256b/32B) */ +/* hwrm_mfg_prvsn_export_csr_input (size:256b/32B) */ -typedef struct hwrm_mfg_otp_cfg_input { +typedef struct hwrm_mfg_prvsn_export_csr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -76683,41 +89738,30 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t enables; - /* - * This bit must be '1' for the crid field to be - * configured. - */ - #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_CRID UINT32_C(0x1) - /* - * This bit must be '1' for the srt_rev_id field to be - * configured. - */ - #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_SRT_REV_ID UINT32_C(0x2) /* - * This bit must be '1' for the crt_rev_id field to be - * configured. + * 64-bit Host destination address. This is the host address where + * data will be written. */ - #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_CRT_REV_ID UINT32_C(0x4) + uint64_t host_dest_addr; + /* Provisioning slot number. 0-indexed. */ + uint8_t slot; + uint8_t unused_0; + /* Size in bytes of the available host buffer. */ + uint16_t host_buf_len; + uint8_t flags; /* - * This bit must be '1' for the sbi_rev_id field to be - * configured. + * This bit is only used when external secure SoC is used for + * secure boot. If this bit is set, export a certificate signing + * request (CSR) from the security SoC non-volatile storage on + * the device. */ - #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_SBI_REV_ID UINT32_C(0x8) - /* This field indicates the crid value to be set. */ - uint16_t crid_cfg_value; - /* This field indicates the srt rev id value to be set. */ - uint16_t srt_rev_id_cfg_value; - /* This field indicates the crt rev id value to be set. */ - uint16_t crt_rev_id_cfg_value; - /* This field indicates the sbi rev id value to be set. */ - uint16_t sbi_rev_id_cfg_value; - uint8_t unused_0[6]; -} hwrm_mfg_otp_cfg_input_t, *phwrm_mfg_otp_cfg_input_t; + #define HWRM_MFG_PRVSN_EXPORT_CSR_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1) + uint8_t unused_1[3]; +} hwrm_mfg_prvsn_export_csr_input_t, *phwrm_mfg_prvsn_export_csr_input_t; -/* hwrm_mfg_otp_cfg_output (size:128b/16B) */ +/* hwrm_mfg_prvsn_export_csr_output (size:128b/16B) */ -typedef struct hwrm_mfg_otp_cfg_output { +typedef struct hwrm_mfg_prvsn_export_csr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -76726,25 +89770,49 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Provisioning slot number. 0-indexed. */ + uint8_t slot; + uint8_t unused_0; + /* Size in bytes of the exported CSR. */ + uint16_t csr_len; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_mfg_otp_cfg_output_t, *phwrm_mfg_otp_cfg_output_t; +} hwrm_mfg_prvsn_export_csr_output_t, *phwrm_mfg_prvsn_export_csr_output_t; -/********************* - * hwrm_mfg_otp_qcfg * - *********************/ +/* hwrm_mfg_prvsn_export_csr_cmd_err (size:64b/8B) */ +typedef struct hwrm_mfg_prvsn_export_csr_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Slot invalid */ + #define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1) + /* Host provided buffer is too small */ + #define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_BUFFER_LENGTH UINT32_C(0x2) + #define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_LAST HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_BUFFER_LENGTH + uint8_t unused_0[7]; +} hwrm_mfg_prvsn_export_csr_cmd_err_t, *phwrm_mfg_prvsn_export_csr_cmd_err_t; -/* hwrm_mfg_otp_qcfg_input (size:192b/24B) */ +/****************************** + * hwrm_mfg_prvsn_import_cert * + ******************************/ -typedef struct hwrm_mfg_otp_qcfg_input { + +/* hwrm_mfg_prvsn_import_cert_input (size:256b/32B) */ + +typedef struct hwrm_mfg_prvsn_import_cert_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -76773,33 +89841,30 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t enables; - /* - * This bit must be '1' for the crid field to be - * queried. - */ - #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_CRID UINT32_C(0x1) - /* - * This bit must be '1' for the srt_rev_id field to be - * queried. - */ - #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_SRT_REV_ID UINT32_C(0x2) /* - * This bit must be '1' for the crt_rev_id field to be - * queried. + * 64-bit Host source address. This is the host address where + * source data is located. */ - #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_CRT_REV_ID UINT32_C(0x4) + uint64_t host_src_addr; + /* Provisioning slot number. 0-indexed. */ + uint8_t slot; + uint8_t unused_0; + /* Size in bytes of the certificate chain. */ + uint16_t cert_len; + uint8_t flags; /* - * This bit must be '1' for the sbi_rev_id field to be - * queried. + * This bit is only used when external secure SoC is used for + * secure boot. If this bit is set, then import a HSM-signed + * certificate chain to security SoC non-volatile storage on + * the device. */ - #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_SBI_REV_ID UINT32_C(0x8) - uint8_t unused_0[6]; -} hwrm_mfg_otp_qcfg_input_t, *phwrm_mfg_otp_qcfg_input_t; + #define HWRM_MFG_PRVSN_IMPORT_CERT_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1) + uint8_t unused_1[3]; +} hwrm_mfg_prvsn_import_cert_input_t, *phwrm_mfg_prvsn_import_cert_input_t; -/* hwrm_mfg_otp_qcfg_output (size:192b/24B) */ +/* hwrm_mfg_prvsn_import_cert_output (size:128b/16B) */ -typedef struct hwrm_mfg_otp_qcfg_output { +typedef struct hwrm_mfg_prvsn_import_cert_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -76808,38 +89873,59 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This field contains the value of current device type. The - * value indicates the current chip mode (Unassigned/AB_PROD). - */ - uint32_t enc_device_type; - /* This field indicates the current crid value. */ - uint16_t crid; - /* This field indicates the current srt rev id value. */ - uint16_t srt_rev_id; - /* This field indicates the current crt rev id value. */ - uint16_t crt_rev_id; - /* This field indicates the current sbi rev id value. */ - uint16_t sbi_rev_id; - uint8_t unused_0[3]; + /* Provisioning slot number. 0-indexed. */ + uint8_t slot; + /* Provisioned state */ + uint8_t state; + /* Certificate chain is not provisioned. */ + #define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_NOT_PROVISIONED UINT32_C(0x0) + /* Certificate chain successfully provisioned. */ + #define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_PROVISIONED UINT32_C(0x1) + #define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_LAST HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_PROVISIONED + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_mfg_otp_qcfg_output_t, *phwrm_mfg_otp_qcfg_output_t; +} hwrm_mfg_prvsn_import_cert_output_t, *phwrm_mfg_prvsn_import_cert_output_t; -/********************** - * hwrm_mfg_hdma_test * - **********************/ +/* hwrm_mfg_prvsn_import_cert_cmd_err (size:64b/8B) */ +typedef struct hwrm_mfg_prvsn_import_cert_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Slot invalid */ + #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1) + /* Slot is provisioned and locked */ + #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_SLOT_LOCKED UINT32_C(0x2) + /* Non-volatile storage is full or in error. */ + #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_STORAGE UINT32_C(0x3) + /* Certificate chain verification failed. */ + #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_CERT_VERIFY_FAIL UINT32_C(0x4) + /* There is no self-signed device id certificate on device */ + #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_SIGNED_DEVICE_CERT UINT32_C(0x5) + #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_LAST HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_SIGNED_DEVICE_CERT + uint8_t unused_0[7]; +} hwrm_mfg_prvsn_import_cert_cmd_err_t, *phwrm_mfg_prvsn_import_cert_cmd_err_t; -/* hwrm_mfg_hdma_test_input (size:384b/48B) */ +/**************************** + * hwrm_mfg_prvsn_get_state * + ****************************/ -typedef struct hwrm_mfg_hdma_test_input { + +/* hwrm_mfg_prvsn_get_state_input (size:128b/16B) */ + +typedef struct hwrm_mfg_prvsn_get_state_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -76868,35 +89954,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The host (DMA) buffer physical addr for the firmware to read from. */ - uint64_t host_src_data_addr; - /* The host (DMA) buffer physical addr for the firmware to write to. */ - uint64_t host_dst_data_addr; - /* - * The user provided data pattern which will be used in the DMA - * transfer. - */ - uint64_t user_data_pattern; - /* Timeout value to stop the test. */ - uint16_t timeout; - /* The number of DMA transfers to be done in the test. */ - uint16_t repeat_count; - /* Types can be any of "incremental", "fixed", or "random". */ - uint16_t subtype; - /* Test is run with the incremental data pattern. */ - #define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_INCREMENTAL UINT32_C(0x1) - /* Test is run with the fixed data pattern. */ - #define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_FIXED UINT32_C(0x2) - /* Test is run with a random data pattern. */ - #define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_RANDOM UINT32_C(0x3) - #define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_LAST HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_RANDOM - /* The length of the data used in the DMA transfers. */ - uint16_t data_len; -} hwrm_mfg_hdma_test_input_t, *phwrm_mfg_hdma_test_input_t; +} hwrm_mfg_prvsn_get_state_input_t, *phwrm_mfg_prvsn_get_state_input_t; -/* hwrm_mfg_hdma_test_output (size:128b/16B) */ +/* hwrm_mfg_prvsn_get_state_output (size:128b/16B) */ -typedef struct hwrm_mfg_hdma_test_output { +typedef struct hwrm_mfg_prvsn_get_state_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -76905,25 +89967,60 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Flag indicating if provision get state is valid. */ + uint8_t get_state_valid; + /* + * Provision get state is invalid. The attestation agent has not + * yet initialized and not completed verification of the + * provisioned certificate chain. + * The slot_status field is undetermined. + */ + #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_INVALID UINT32_C(0x0) + /* Provision get state is valid for SPDM. */ + #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_SPDM UINT32_C(0x1) + /* Provision get state is valid for Cerberus. */ + #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_CERBERUS UINT32_C(0x2) + /* Provision get state is valid. There is no attestation agent. */ + #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_NONE UINT32_C(0xff) + #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_LAST HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_NONE + /* + * An 8-bit mask returning the provisioned state of the imported + * certificate chain on the device for each available slot. + * Bit-N corresponding to slot N. + * The slot_status field is undetermined if get_state_valid = 0. + */ + uint8_t slot_status; + /* Slot N entries */ + #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_MASK UINT32_C(0xff) + #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_SFT 0 + /* Slot N is not provisioned. */ + #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_NOT_PROVISIONED UINT32_C(0x0) + /* + * Slot N is provisioned and certificate chain is loaded + * successfully by the attestation agent. + */ + #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_PROVISIONED UINT32_C(0x1) + #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_LAST HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_PROVISIONED + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_mfg_hdma_test_output_t, *phwrm_mfg_hdma_test_output_t; +} hwrm_mfg_prvsn_get_state_output_t, *phwrm_mfg_prvsn_get_state_output_t; -/***************************** - * hwrm_mfg_fru_eeprom_write * - *****************************/ +/****************************** + * hwrm_mfg_prvsn_export_cert * + ******************************/ -/* hwrm_mfg_fru_eeprom_write_input (size:256b/32B) */ +/* hwrm_mfg_prvsn_export_cert_input (size:256b/32B) */ -typedef struct hwrm_mfg_fru_eeprom_write_input { +typedef struct hwrm_mfg_prvsn_export_cert_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -76953,23 +90050,29 @@ */ uint64_t resp_addr; /* - * The host (DMA) buffer physical addr for the firmware to read from. - * This buffer is populated with the fru binary bits which is going - * to be programmed into the fru memory. + * 64-bit Host destination address. This is the host address where + * data will be written. */ - uint64_t data_addr; - /* i2c slave address. If set to 0xffff, fw will decide what to use. */ - uint16_t i2c_slave_addr; - /* Size of the buffer pointed to by data_addr. */ - uint16_t data_len; - /* The offset within the SEEPROM to start programming. */ - uint16_t offset; - uint8_t unused[2]; -} hwrm_mfg_fru_eeprom_write_input_t, *phwrm_mfg_fru_eeprom_write_input_t; + uint64_t host_dest_addr; + /* Provisioning slot number. 0-indexed. */ + uint8_t slot; + uint8_t unused_0; + /* Size in bytes of the available host buffer. */ + uint16_t host_buf_len; + uint8_t flags; + /* + * This bit is only used when external secure SoC is used + * for secure boot. If this bit is set, then export the + * provisioned certificate from the security SoC non-volatile + * storage device. + */ + #define HWRM_MFG_PRVSN_EXPORT_CERT_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1) + uint8_t unused_1[3]; +} hwrm_mfg_prvsn_export_cert_input_t, *phwrm_mfg_prvsn_export_cert_input_t; -/* hwrm_mfg_fru_eeprom_write_output (size:128b/16B) */ +/* hwrm_mfg_prvsn_export_cert_output (size:128b/16B) */ -typedef struct hwrm_mfg_fru_eeprom_write_output { +typedef struct hwrm_mfg_prvsn_export_cert_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -76978,28 +90081,58 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Total length of data written to the fru memory. */ - uint16_t total_data_len; - uint16_t unused_0; + /* Provisioning slot number. 0-indexed. */ + uint8_t slot; + uint8_t unused_0; + /* + * Size in bytes of the exported certificate chain. If there are no + * certificates provisioned for the specified slot, the device will + * return a successful response with cert_len equal to 0. + */ + uint16_t cert_len; uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_mfg_fru_eeprom_write_output_t, *phwrm_mfg_fru_eeprom_write_output_t; +} hwrm_mfg_prvsn_export_cert_output_t, *phwrm_mfg_prvsn_export_cert_output_t; -/**************************** - * hwrm_mfg_fru_eeprom_read * - ****************************/ +/* hwrm_mfg_prvsn_export_cert_cmd_err (size:64b/8B) */ + +typedef struct hwrm_mfg_prvsn_export_cert_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Slot invalid */ + #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1) + /* + * The provisioned certificates are invalid due to device ID change, + * NVRAM corruption or another reason. + */ + #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_CERT_INVALID UINT32_C(0x2) + /* Host provided buffer is too small */ + #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_BUFFER_LENGTH UINT32_C(0x3) + #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_LAST HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_BUFFER_LENGTH + uint8_t unused_0[7]; +} hwrm_mfg_prvsn_export_cert_cmd_err_t, *phwrm_mfg_prvsn_export_cert_cmd_err_t; +/******************************** + * hwrm_mfg_get_nvm_measurement * + ********************************/ -/* hwrm_mfg_fru_eeprom_read_input (size:256b/32B) */ -typedef struct hwrm_mfg_fru_eeprom_read_input { +/* hwrm_mfg_get_nvm_measurement_input (size:128b/16B) */ + +typedef struct hwrm_mfg_get_nvm_measurement_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77028,28 +90161,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * The host (DMA) buffer physical addr for the firmware to write to. - * This buffer is populated with the fru binary bits which is going - * to be read from the fru memory. - */ - uint64_t data_addr; - /* i2c slave address. If set to 0xffff, fw will decide what to use. */ - uint16_t i2c_slave_addr; - /* - * Size of the buffer pointed to by data_addr. The firmware may - * use this entire buffer or less than the entire buffer, but never - * more. - */ - uint16_t data_len; - /* The offset within the SEEPROM to start reading. */ - uint16_t offset; - uint8_t unused[2]; -} hwrm_mfg_fru_eeprom_read_input_t, *phwrm_mfg_fru_eeprom_read_input_t; +} hwrm_mfg_get_nvm_measurement_input_t, *phwrm_mfg_get_nvm_measurement_input_t; -/* hwrm_mfg_fru_eeprom_read_output (size:128b/16B) */ +/* hwrm_mfg_get_nvm_measurement_output (size:448b/56B) */ -typedef struct hwrm_mfg_fru_eeprom_read_output { +typedef struct hwrm_mfg_get_nvm_measurement_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77058,28 +90174,50 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Total length of data written to the host memory. */ - uint16_t total_data_len; - uint16_t unused_0; - uint8_t unused_1[3]; + /* Flag indicating if the hash returned is valid. */ + uint8_t hash_state; + /* + * Measurement hash is invalid. There was an error + * calculating the hash or firmware does not support NVM + * measurement. + */ + #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_INVALID UINT32_C(0x0) + /* Measurement hash is valid. */ + #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_VALID UINT32_C(0x1) + #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_LAST HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_VALID + /* + * Flag indicating whether the measurement was calculated + * in real time or calculated during bootup time. + */ + uint8_t calc_time; + /* Measurement was calculated during bootup time. */ + #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_BOOTUP UINT32_C(0x0) + /* Measurement is calculated in real time */ + #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_LIVE UINT32_C(0x1) + #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_LAST HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_LIVE + uint8_t unused_0[6]; + /* Thirty two bytes HMAC SHA256 hash of NVM configuration. */ + uint8_t hash[32]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} hwrm_mfg_fru_eeprom_read_output_t, *phwrm_mfg_fru_eeprom_read_output_t; +} hwrm_mfg_get_nvm_measurement_output_t, *phwrm_mfg_get_nvm_measurement_output_t; -/********************** - * hwrm_mfg_soc_image * - **********************/ +/************************* + * hwrm_mfg_psoc_qstatus * + *************************/ -/* hwrm_mfg_soc_image_input (size:512b/64B) */ +/* hwrm_mfg_psoc_qstatus_input (size:192b/24B) */ -typedef struct hwrm_mfg_soc_image_input { +typedef struct hwrm_mfg_psoc_qstatus_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77108,76 +90246,15 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * TBD. Work in progress. - * This field is the signature value used by SoC UEFI. - */ - uint32_t image_signature; - /* - * TBD. Work in progress. - * This field is unused for now. - */ - uint32_t image_type; - /* - * The offset within the image content that is being provided by the - * current invocation of this HWRM command. The primate firmware does - * not offer any score boarding services to ensure entire image - * content is transferred, it is the responsibility of the caller to - * ensure image consistency. - */ - uint32_t image_offset; - /* - * Size in bytes for the image content. The maximum value this field - * can specify is 4096. - */ - uint32_t image_length; - /* - * Address in host memory where the image content is located. This - * location should be 4KB aligned. - */ - uint64_t host_src_addr; - /* - * Address in SoC address space where the provided image content is - * to be copied. Primate firmware will copy the image content from - * host memory to this location. If the image size is more than the - * maximum size that can be transferred with each invocation of this - * command, then this address should be updated by the caller for - * each invocation to copy the full image. - */ - uint64_t soc_dest_addr; - /* - * Indicates the entrypoint in the image that should be used. This - * field is optional. When set to 0, the SoC will determine the - * entrypoint on its own. - */ - uint32_t entrypoint_offset; - uint32_t flags; - /* - * This bit should be set to '1' only when an image transfer is - * being initiated for each unique image_signature. - */ - #define HWRM_MFG_SOC_IMAGE_INPUT_FLAGS_START UINT32_C(0x1) - /* - * This bit should be set to '1' only when an image transfer for a - * given image_signature is complete. - */ - #define HWRM_MFG_SOC_IMAGE_INPUT_FLAGS_END UINT32_C(0x2) - /* - * An incrementing number starting with 1 for each invocation of this - * HWRM command for any given image_id. No two invocation of this - * command for a given image_id shall carry the same seq_number. Each - * consecutive invocation of this command for any given image_id - * shall increment this number by 1. The value 0 is used when - * seq_number is invalid when no image content is being moved. - */ - uint32_t seq_number; /* */ uint32_t reserved1; -} hwrm_mfg_soc_image_input_t, *phwrm_mfg_soc_image_input_t; + /* */ + uint32_t reserved2; +} hwrm_mfg_psoc_qstatus_input_t, *phwrm_mfg_psoc_qstatus_input_t; -/* hwrm_mfg_soc_image_output (size:128b/16B) */ +/* hwrm_mfg_psoc_qstatus_output (size:768b/96B) */ -typedef struct hwrm_mfg_soc_image_output { +typedef struct hwrm_mfg_psoc_qstatus_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77186,26 +90263,52 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_1[7]; + /* PBL version info. Start at 0, roll if change in structure */ + uint8_t pbl_info_version; + /* PBL info length. Counts all bytes. */ + uint8_t pbl_info_length; + /* + * Hardware generation major version. Rolled on incompatible hardware + * changes. + */ + uint8_t hw_generation_major; + /* Hardware generation minor version. Tracks minor changes. */ + uint8_t hw_generation_minor; + /* Reserved. */ + uint8_t feature_support; + /* Firmware version major. */ + uint8_t fw_version_major; + /* Firmware version minor. */ + uint8_t fw_version_minor; + /* Indicate which of the two firmware images is active. */ + uint8_t active_image; + /* Identifies PSoC specific part. */ + uint32_t silicon_id; + /* Length of part number string in bytes, including NULL terminator. */ + uint8_t part_number_string_length; + uint8_t unused_1[3]; + /* Part number string in ASCII. */ + uint8_t part_number_string[64]; + uint8_t unused_2[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is * written last. */ uint8_t valid; -} hwrm_mfg_soc_image_output_t, *phwrm_mfg_soc_image_output_t; +} hwrm_mfg_psoc_qstatus_output_t, *phwrm_mfg_psoc_qstatus_output_t; -/************************ - * hwrm_mfg_soc_qstatus * - ************************/ +/*************************** + * hwrm_mfg_selftest_qlist * + ***************************/ -/* hwrm_mfg_soc_qstatus_input (size:192b/24B) */ +/* hwrm_mfg_selftest_qlist_input (size:128b/16B) */ -typedef struct hwrm_mfg_soc_qstatus_input { +typedef struct hwrm_mfg_selftest_qlist_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77234,15 +90337,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* */ - uint32_t reserved1; - /* */ - uint32_t reserved2; -} hwrm_mfg_soc_qstatus_input_t, *phwrm_mfg_soc_qstatus_input_t; +} hwrm_mfg_selftest_qlist_input_t, *phwrm_mfg_selftest_qlist_input_t; -/* hwrm_mfg_soc_qstatus_output (size:576b/72B) */ +/* hwrm_mfg_selftest_qlist_output (size:192b/24B) */ -typedef struct hwrm_mfg_soc_qstatus_output { +typedef struct hwrm_mfg_selftest_qlist_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77252,56 +90351,62 @@ /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * This field describes capabilities of primate firmware for SoC - * image. - */ - uint32_t primate_flags; - /* */ - uint32_t reserved1; - /* This field contains the current content of the AP_STATUS register. */ - uint32_t ap_status; - /* - * This field contains the current content of the CRMU_STATUS - * register. + * This field represents the number of tests available to be + * requested by manufacturing tool. */ - uint32_t crmu_status; + uint8_t num_tests; + /* This field indicates which self-test is available to be run. */ + uint8_t available_tests; /* - * If an image provision operation is in process, this field will - * provide information on requested image signature else the contents - * are undefined. + * Can run the peripheral tests. Individual peripherals are + * specified in peripheral_tests field. */ - uint32_t image_signature; + #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PERIPHERAL_TEST UINT32_C(0x1) /* - * If an image provision operation is in process, this field will - * provide information on requested image command else the contents - * are undefined. + * This field represents the maximum timeout for all the + * tests to complete in milliseconds. */ - uint32_t image_command; + uint16_t test_timeout; /* - * If an image provision operation is in process, this field will - * provide the requested image name else the contents are undefined. + * This field is a 32 bits bitmap, each bit specifies a peripheral + * test. */ - uint8_t image_name[32]; - uint8_t unused_1[7]; + uint32_t peripheral_tests; + /* Can run memory test on Co-CPU peripheral */ + #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_CO_CPU_MEMORY UINT32_C(0x1) + /* Can run test on dpll eeprom peripheral */ + #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_DPLL_EEPROM UINT32_C(0x2) + /* Can run test on dpll mmcx connector peripheral */ + #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_DPLL_MMCX UINT32_C(0x4) + /* Can run test on gnss peripheral */ + #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_GNSS UINT32_C(0x8) + /* Can run pcie test on Co-CPU peripheral */ + #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_CO_CPU_PCIE UINT32_C(0x10) + /* Can run test on internal fabric peripheral */ + #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_INTERNAL_FABRIC UINT32_C(0x20) + /* Can run test on oven controlled crystal oscillator peripheral */ + #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_OCXO UINT32_C(0x40) + /* Can run test on telecom pll peripheral */ + #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_TELECOM_PLL UINT32_C(0x80) + uint8_t unused_2[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_soc_qstatus_output_t, *phwrm_mfg_soc_qstatus_output_t; +} hwrm_mfg_selftest_qlist_output_t, *phwrm_mfg_selftest_qlist_output_t; -/******************************* - * hwrm_mfg_param_seeprom_sync * - *******************************/ +/************************** + * hwrm_mfg_selftest_exec * + **************************/ -/* hwrm_mfg_param_seeprom_sync_input (size:640b/80B) */ +/* hwrm_mfg_selftest_exec_input (size:192b/24B) */ -typedef struct hwrm_mfg_param_seeprom_sync_input { +typedef struct hwrm_mfg_selftest_exec_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77330,34 +90435,40 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* This field indicates which self-test is being requested to run. */ + uint8_t flags; /* - * The host (DMA) buffer physical addr for the firmware to read from. - * This buffer is populated with the parameter binary bits which is - * going to be programmed into the seeprom memory. - */ - uint64_t data_addr; - /* Size of the buffer pointed to by data_addr. */ - uint16_t data_len; - /* The offset within the SEEPROM to start programming. */ - uint16_t offset; - uint32_t flags; - /* - * This bit must be '1' to sync the parameters available in factory - * config to seeprom binary before writing to seeprom + * Run the Peripheral tests specified in peripheral_tests + * field. */ - #define HWRM_MFG_PARAM_SEEPROM_SYNC_INPUT_FLAGS_FAC_CFG_SYNC UINT32_C(0x1) + #define HWRM_MFG_SELFTEST_EXEC_INPUT_FLAGS_PERIPHERAL_TEST UINT32_C(0x1) + uint8_t unused_0[3]; /* - * This bit must be '1' for the seeprom data to be written to - * a specified address with out any change in the binary + * This field is a 32 bits bitmap to specify which peripheral tests to + * run, each bit specifies a peripheral test. */ - #define HWRM_MFG_PARAM_SEEPROM_SYNC_INPUT_FLAGS_WRITE_BINARY_ONLY UINT32_C(0x80000000) - /* Reserved for future use. */ - uint8_t reserved[48]; -} hwrm_mfg_param_seeprom_sync_input_t, *phwrm_mfg_param_seeprom_sync_input_t; + uint32_t peripheral_tests; + /* Run memory test on Co-CPU peripheral */ + #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_CO_CPU_MEMORY UINT32_C(0x1) + /* Run test on dpll eeprom peripheral */ + #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_DPLL_EEPROM UINT32_C(0x2) + /* Run test on dpll mmcx connector peripheral */ + #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_DPLL_MMCX UINT32_C(0x4) + /* Run test on gnss peripheral */ + #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_GNSS UINT32_C(0x8) + /* Run pcie test on Co-CPU peripheral */ + #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_CO_CPU_PCIE UINT32_C(0x10) + /* Run test on internal fabric peripheral */ + #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_INTERNAL_FABRIC UINT32_C(0x20) + /* Run test on oven controlled crystal oscillator peripheral */ + #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_OCXO UINT32_C(0x40) + /* Run test on telecom pll peripheral */ + #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_TELECOM_PLL UINT32_C(0x80) +} hwrm_mfg_selftest_exec_input_t, *phwrm_mfg_selftest_exec_input_t; -/* hwrm_mfg_param_seeprom_sync_output (size:128b/16B) */ +/* hwrm_mfg_selftest_exec_output (size:192b/24B) */ -typedef struct hwrm_mfg_param_seeprom_sync_output { +typedef struct hwrm_mfg_selftest_exec_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77366,28 +90477,88 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Total length of data written to the seeprom memory. */ - uint16_t total_data_len; - uint16_t unused_0; + /* The following tests were requested to be run. */ + uint8_t requested_tests; + /* A request was made to run the peripheral tests. */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PERIPHERAL_TEST UINT32_C(0x1) + /* + * If a test was requested to be run as seen in the requested_tests + * field, this bit indicates whether the test was successful(1) or + * failed(0). + */ + uint8_t test_success; + /* + * If requested, a value of 1 indicates the peripheral tests + * completed successfully. + */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PERIPHERAL_TEST UINT32_C(0x1) + uint8_t unused_0[2]; + /* + * This field is a 32 bits bitmap for firmware to indicate which + * peripheral tests are specified by the host, each bit specifies + * a peripheral test. + */ + uint32_t peripheral_requested_tests; + /* Co-CPU peripheral test requested */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_CO_CPU_MEMORY UINT32_C(0x1) + /* dpll eeprom peripheral test requested */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_DPLL_EEPROM UINT32_C(0x2) + /* dpll mmcx connector peripheral test requested */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_DPLL_MMCX UINT32_C(0x4) + /* gnss peripheral test requested */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_GNSS UINT32_C(0x8) + /* pcie test on Co-CPU peripheral test requested */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_CO_CPU_PCIE UINT32_C(0x10) + /* internal fabric peripheral test requested */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_INTERNAL_FABRIC UINT32_C(0x20) + /* oven controlled crystal oscillator peripheral test requested */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_OCXO UINT32_C(0x40) + /* telecom pll peripheral test requested */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_TELECOM_PLL UINT32_C(0x80) + /* + * This field is a 32 bits bitmap for firmware to indicate which + * peripheral tests are successfully executed, each bit specifies + * a peripheral test. + */ + uint32_t peripheral_tests_success; + /* Co-CPU peripheral test is successfully executed */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_CO_CPU_MEMORY UINT32_C(0x1) + /* dpll eeprom peripheral test is successfully executed */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_DPLL_EEPROM UINT32_C(0x2) + /* dpll mmcx connector peripheral test is successfully executed */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_DPLL_MMCX UINT32_C(0x4) + /* gnss peripheral test is successfully executed */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_GNSS UINT32_C(0x8) + /* pcie test on Co-CPU peripheral test is successfully executed */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_CO_CPU_PCIE UINT32_C(0x10) + /* internal fabric peripheral test is successfully executed */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_INTERNAL_FABRIC UINT32_C(0x20) + /* + * oven controlled crystal oscillator peripheral test is successfully + * executed + */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_OCXO UINT32_C(0x40) + /* telecom pll peripheral test is successfully executed */ + #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_TELECOM_PLL UINT32_C(0x80) uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_param_seeprom_sync_output_t, *phwrm_mfg_param_seeprom_sync_output_t; +} hwrm_mfg_selftest_exec_output_t, *phwrm_mfg_selftest_exec_output_t; -/******************************* - * hwrm_mfg_param_seeprom_read * - *******************************/ +/**************** + * hwrm_oem_cmd * + ****************/ -/* hwrm_mfg_param_seeprom_read_input (size:256b/32B) */ +/* hwrm_oem_cmd_input (size:1024b/128B) */ -typedef struct hwrm_mfg_param_seeprom_read_input { +typedef struct hwrm_oem_cmd_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77417,25 +90588,35 @@ */ uint64_t resp_addr; /* - * The host (DMA) buffer physical addr for the firmware to write to. - * This buffer is populated with the parameter binary bits which is - * going to be read from the seeprom memory. - */ - uint64_t data_addr; - /* - * Size of the buffer pointed to by data_addr. The firmware may - * use this entire buffer or less than the entire buffer, but never - * more. - */ - uint16_t data_len; - /* The offset within the SEEPROM to start reading. */ - uint16_t offset; - uint8_t unused[4]; -} hwrm_mfg_param_seeprom_read_input_t, *phwrm_mfg_param_seeprom_read_input_t; + * The organization owning the message format. Set this field + * to 0x14e4 when used for Broadcom internal use when + * the naming authority is set to PCI_SIG. + */ + uint32_t oem_id; + /* The naming authority used for setting the oem_id. */ + uint8_t naming_authority; + /* Invalid naming authority */ + #define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_INVALID UINT32_C(0x0) + /* PCI_SIG naming authority numbering is used */ + #define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG UINT32_C(0x1) + #define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_LAST HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG + /* The message family within the organization. */ + uint8_t message_family; + /* Invalid message family */ + #define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_INVALID UINT32_C(0x0) + /* This message is targeted for Truflow */ + #define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW UINT32_C(0x1) + /* This message is targeted for RoCE */ + #define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_ROCE UINT32_C(0x2) + #define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_LAST HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_ROCE + uint16_t unused; + /* This field contains the vendor specific command data. */ + uint32_t oem_data[26]; +} hwrm_oem_cmd_input_t, *phwrm_oem_cmd_input_t; -/* hwrm_mfg_param_seeprom_read_output (size:128b/16B) */ +/* hwrm_oem_cmd_output (size:768b/96B) */ -typedef struct hwrm_mfg_param_seeprom_read_output { +typedef struct hwrm_oem_cmd_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77444,28 +90625,34 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Total length of data written to the host memory. */ - uint16_t total_data_len; - uint16_t unused_0[2]; + /* The organization owning the message format. */ + uint32_t oem_id; + /* The naming authority used for setting the oem_id. */ + uint8_t naming_authority; + /* The message family within the organization. */ + uint8_t message_family; + uint16_t unused; + /* This field contains the vendor specific response data. */ + uint32_t oem_data[18]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; - uint8_t unused_1; -} hwrm_mfg_param_seeprom_read_output_t, *phwrm_mfg_param_seeprom_read_output_t; +} hwrm_oem_cmd_output_t, *phwrm_oem_cmd_output_t; -/********************************* - * hwrm_mfg_param_seeprom_health * - *********************************/ +/*********** + * hwrm_sv * + ***********/ -/* hwrm_mfg_param_seeprom_health_input (size:192b/24B) */ +/* hwrm_sv_input (size:1152b/144B) */ -typedef struct hwrm_mfg_param_seeprom_health_input { +typedef struct hwrm_sv_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77494,61 +90681,31 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint64_t unused_0; -} hwrm_mfg_param_seeprom_health_input_t, *phwrm_mfg_param_seeprom_health_input_t; + uint32_t opaque[32]; +} hwrm_sv_input_t, *phwrm_sv_input_t; -/* hwrm_mfg_param_seeprom_health_output (size:128b/16B) */ +/* hwrm_sv_output (size:1088b/136B) */ -typedef struct hwrm_mfg_param_seeprom_health_output { +typedef struct hwrm_sv_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ uint16_t req_type; /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t health_status; - /* No response from the device */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_NO_RESPONSE UINT32_C(0x1) - /* Data checksum fail */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_CHECKSUM_FAIL UINT32_C(0x2) - /* Mac address not populated */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_NO_MAC_ADDRESS UINT32_C(0x4) - /* Part number not populated */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_NO_PART_NUMBER UINT32_C(0x8) - /* Serial number not populated */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_NO_SR_NUMBER UINT32_C(0x10) - /* Package description not populated */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_NO_PKG_DESCRIPTION UINT32_C(0x20) - uint16_t health_code; - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_SUCCESS UINT32_C(0x0) - /* No response from the device */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_NO_RESPONSE UINT32_C(0x1) - /* Data checksum fail */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_CHECKSUM_FAIL UINT32_C(0x2) - /* Mac address not populated */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_NO_MAC_ADDRESS UINT32_C(0x3) - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_LAST HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_NO_MAC_ADDRESS - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; - uint8_t unused_1; -} hwrm_mfg_param_seeprom_health_output_t, *phwrm_mfg_param_seeprom_health_output_t; + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t opaque[32]; +} hwrm_sv_output_t, *phwrm_sv_output_t; -/***************************** - * hwrm_mfg_prvsn_export_csr * - *****************************/ +/******************* + * hwrm_udcc_qcaps * + *******************/ -/* hwrm_mfg_prvsn_export_csr_input (size:256b/32B) */ +/* hwrm_udcc_qcaps_input (size:128b/16B) */ -typedef struct hwrm_mfg_prvsn_export_csr_input { +typedef struct hwrm_udcc_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77577,22 +90734,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * 64-bit Host destination address. This is the host address where - * data will be written. - */ - uint64_t host_dest_addr; - /* Provisioning slot number. 0-indexed. */ - uint8_t slot; - uint8_t unused_0; - /* Size in bytes of the available host buffer. */ - uint16_t host_buf_len; - uint32_t unused_1; -} hwrm_mfg_prvsn_export_csr_input_t, *phwrm_mfg_prvsn_export_csr_input_t; +} hwrm_udcc_qcaps_input_t, *phwrm_udcc_qcaps_input_t; -/* hwrm_mfg_prvsn_export_csr_output (size:128b/16B) */ +/* hwrm_udcc_qcaps_output (size:192b/24B) */ -typedef struct hwrm_mfg_prvsn_export_csr_output { +typedef struct hwrm_udcc_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77601,49 +90747,59 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Provisioning slot number. 0-indexed. */ - uint8_t slot; - uint8_t unused_0; - /* Size in bytes of the exported CSR. */ - uint16_t csr_len; + /* + * This field represents guaranteed minimum number of UDCC sessions + * available to the function. + */ + uint16_t min_sessions; + /* + * This field represents unguaranteed maximum number of UDCC sessions + * available to the function. + */ + uint16_t max_sessions; + /* + * This value indicates the type of session being modified by the + * UDCC. + */ + uint8_t session_type; + /* sessions are allocated on a per destination basis. */ + #define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_DESTINATION UINT32_C(0x0) + /* sessions are allocated on a per QP basis. */ + #define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_QP UINT32_C(0x1) + #define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_LAST HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_QP + uint8_t unused_0[3]; + /* + * This field represents the maximum number of bytes of UDCC program + * configuration data that one hwrm_udcc_comp_cfg request or + * hwrm_udcc_comp_qcfg response can transfer. + * The value is determined by the UDCC firmware. + */ + uint16_t max_comp_cfg_xfer; + /* + * This field represents the maximum number of bytes of UDCC program + * status or statistics data that one hwrm_udcc_comp_query response + * can transfer. The value is determined by the UDCC firmware. + */ + uint16_t max_comp_data_xfer; uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_prvsn_export_csr_output_t, *phwrm_mfg_prvsn_export_csr_output_t; - -/* hwrm_mfg_prvsn_export_csr_cmd_err (size:64b/8B) */ - -typedef struct hwrm_mfg_prvsn_export_csr_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error. */ - #define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* Slot invalid */ - #define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1) - /* Host provided buffer is too small */ - #define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_BUFFER_LENGTH UINT32_C(0x2) - #define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_LAST HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_BUFFER_LENGTH - uint8_t unused_0[7]; -} hwrm_mfg_prvsn_export_csr_cmd_err_t, *phwrm_mfg_prvsn_export_csr_cmd_err_t; +} hwrm_udcc_qcaps_output_t, *phwrm_udcc_qcaps_output_t; -/****************************** - * hwrm_mfg_prvsn_import_cert * - ******************************/ +/***************** + * hwrm_udcc_cfg * + *****************/ -/* hwrm_mfg_prvsn_import_cert_input (size:256b/32B) */ +/* hwrm_udcc_cfg_input (size:192b/24B) */ -typedef struct hwrm_mfg_prvsn_import_cert_input { +typedef struct hwrm_udcc_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77672,22 +90828,25 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; /* - * 64-bit Host source address. This is the host address where - * source data is located. + * This bit must be '1' for the udcc_mode field to be + * configured. */ - uint64_t host_src_addr; - /* Provisioning slot number. 0-indexed. */ - uint8_t slot; - uint8_t unused_0; - /* Size in bytes of the certificate chain. */ - uint16_t cert_len; - uint32_t unused_1; -} hwrm_mfg_prvsn_import_cert_input_t, *phwrm_mfg_prvsn_import_cert_input_t; + #define HWRM_UDCC_CFG_INPUT_ENABLES_UDCC_MODE UINT32_C(0x1) + /* UDCC mode for this function. */ + uint8_t udcc_mode; + /* UDCC is not enabled. */ + #define HWRM_UDCC_CFG_INPUT_UDCC_MODE_DISABLED UINT32_C(0x0) + /* UDCC is enabled. */ + #define HWRM_UDCC_CFG_INPUT_UDCC_MODE_ENABLED UINT32_C(0x1) + #define HWRM_UDCC_CFG_INPUT_UDCC_MODE_LAST HWRM_UDCC_CFG_INPUT_UDCC_MODE_ENABLED + uint8_t unused_1[3]; +} hwrm_udcc_cfg_input_t, *phwrm_udcc_cfg_input_t; -/* hwrm_mfg_prvsn_import_cert_output (size:128b/16B) */ +/* hwrm_udcc_cfg_output (size:128b/16B) */ -typedef struct hwrm_mfg_prvsn_import_cert_output { +typedef struct hwrm_udcc_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77696,59 +90855,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Provisioning slot number. 0-indexed. */ - uint8_t slot; - /* Provisioned state */ - uint8_t state; - /* Certificate chain is not provisioned. */ - #define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_NOT_PROVISIONED UINT32_C(0x0) - /* Certificate chain successfully provisioned. */ - #define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_PROVISIONED UINT32_C(0x1) - #define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_LAST HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_PROVISIONED - uint8_t unused_0[5]; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_prvsn_import_cert_output_t, *phwrm_mfg_prvsn_import_cert_output_t; - -/* hwrm_mfg_prvsn_import_cert_cmd_err (size:64b/8B) */ - -typedef struct hwrm_mfg_prvsn_import_cert_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error. */ - #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* Slot invalid */ - #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1) - /* Slot is provisioned and locked */ - #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_SLOT_LOCKED UINT32_C(0x2) - /* Non-volatile storage is full or in error. */ - #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_STORAGE UINT32_C(0x3) - /* Certificate chain verification failed. */ - #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_CERT_VERIFY_FAIL UINT32_C(0x4) - /* There is no self-signed device id certificate on device */ - #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_SIGNED_DEVICE_CERT UINT32_C(0x5) - #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_LAST HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_SIGNED_DEVICE_CERT - uint8_t unused_0[7]; -} hwrm_mfg_prvsn_import_cert_cmd_err_t, *phwrm_mfg_prvsn_import_cert_cmd_err_t; +} hwrm_udcc_cfg_output_t, *phwrm_udcc_cfg_output_t; -/**************************** - * hwrm_mfg_prvsn_get_state * - ****************************/ +/****************** + * hwrm_udcc_qcfg * + ******************/ -/* hwrm_mfg_prvsn_get_state_input (size:128b/16B) */ +/* hwrm_udcc_qcfg_input (size:128b/16B) */ -typedef struct hwrm_mfg_prvsn_get_state_input { +typedef struct hwrm_udcc_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77777,11 +90902,11 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_mfg_prvsn_get_state_input_t, *phwrm_mfg_prvsn_get_state_input_t; +} hwrm_udcc_qcfg_input_t, *phwrm_udcc_qcfg_input_t; -/* hwrm_mfg_prvsn_get_state_output (size:128b/16B) */ +/* hwrm_udcc_qcfg_output (size:128b/16B) */ -typedef struct hwrm_mfg_prvsn_get_state_output { +typedef struct hwrm_udcc_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77790,60 +90915,27 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Flag indicating if provision get state is valid. */ - uint8_t get_state_valid; - /* - * Provision get state is invalid. The attestation agent has not - * yet initialized and not completed verification of the - * provisioned certificate chain. - * The slot_status field is undetermined. - */ - #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_INVALID UINT32_C(0x0) - /* Provision get state is valid for SPDM. */ - #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_SPDM UINT32_C(0x1) - /* Provision get state is valid for Cerberus. */ - #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_CERBERUS UINT32_C(0x2) - /* Provision get state is valid. There is no attestation agent. */ - #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_NONE UINT32_C(0xff) - #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_LAST HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_NONE - /* - * An 8-bit mask returning the provisioned state of the imported - * certificate chain on the device for each available slot. - * Bit-N corresponding to slot N. - * The slot_status field is undetermined if get_state_valid = 0. - */ - uint8_t slot_status; - /* Slot N entries */ - #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_MASK UINT32_C(0xff) - #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_SFT 0 - /* Slot N is not provisioned. */ - #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_NOT_PROVISIONED UINT32_C(0x0) - /* - * Slot N is provisioned and certificate chain is loaded - * successfully by the attestation agent. - */ - #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_PROVISIONED UINT32_C(0x1) - #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_LAST HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_PROVISIONED - uint8_t unused_0[5]; + /* UDCC mode for this function. */ + uint8_t udcc_mode; + uint8_t unused_1[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_prvsn_get_state_output_t, *phwrm_mfg_prvsn_get_state_output_t; +} hwrm_udcc_qcfg_output_t, *phwrm_udcc_qcfg_output_t; -/******************************** - * hwrm_mfg_get_nvm_measurement * - ********************************/ +/************************* + * hwrm_udcc_session_cfg * + *************************/ -/* hwrm_mfg_get_nvm_measurement_input (size:128b/16B) */ +/* hwrm_udcc_session_cfg_input (size:384b/48B) */ -typedef struct hwrm_mfg_get_nvm_measurement_input { +typedef struct hwrm_udcc_session_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77872,11 +90964,53 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_mfg_get_nvm_measurement_input_t, *phwrm_mfg_get_nvm_measurement_input_t; + uint32_t enables; + /* This bit must be '1' for the session_state to be configured. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_SESSION_STATE UINT32_C(0x1) + /* This bit must be '1' for the dest_mac to be configured. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_DEST_MAC UINT32_C(0x2) + /* This bit must be '1' for the src_mac to be configured. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_SRC_MAC UINT32_C(0x4) + /* This bit must be '1' for the tx_stats_record to be configured. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_TX_STATS_RECORD UINT32_C(0x8) + /* This bit must be '1' for the rx_stats_record to be configured. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_RX_STATS_RECORD UINT32_C(0x10) + /* State to configure for the session. */ + uint8_t session_state; + /* + * This bit is set if the session is to be enabled and have firmware + * querying it for events. The bit is cleared if the session is to + * be disabled in firmware. + */ + #define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_ENABLED UINT32_C(0x1) + /* UDCC flow is not created in driver. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_FLOW_NOT_CREATED UINT32_C(0x2) + /* UDCC flow is now deleted in driver. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_FLOW_HAS_BEEN_DELETED UINT32_C(0x4) + uint8_t unused_1; + /* A handle for the session to be configured, if previously allocated. */ + uint16_t session_id; + /* destination mac address used for the session. */ + uint8_t dest_mac[6]; + uint16_t unused_2; + /* source mac address used for the session. */ + uint8_t src_mac[6]; + uint16_t unused_3; + /* + * address for the tx flow statistics record to be sampled by the + * UDCC firmware. Session must be disabled to take effect. + */ + uint32_t tx_stats_record; + /* + * address for the rx flow statistics record to be sampled by the + * UDCC firmware. Session must be disabled to take effect. + */ + uint32_t rx_stats_record; +} hwrm_udcc_session_cfg_input_t, *phwrm_udcc_session_cfg_input_t; -/* hwrm_mfg_get_nvm_measurement_output (size:448b/56B) */ +/* hwrm_udcc_session_cfg_output (size:128b/16B) */ -typedef struct hwrm_mfg_get_nvm_measurement_output { +typedef struct hwrm_udcc_session_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77885,50 +91019,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Flag indicating if the hash returned is valid. */ - uint8_t hash_state; - /* - * Measurement hash is invalid. There was an error - * calculating the hash or firmware does not support NVM - * measurement. - */ - #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_INVALID UINT32_C(0x0) - /* Measurement hash is valid. */ - #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_VALID UINT32_C(0x1) - #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_LAST HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_VALID - /* - * Flag indicating whether the measurement was calculated - * in real time or calculated during bootup time. - */ - uint8_t calc_time; - /* Measurement was calculated during bootup time. */ - #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_BOOTUP UINT32_C(0x0) - /* Measurement is calculated in real time */ - #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_LIVE UINT32_C(0x1) - #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_LAST HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_LIVE - uint8_t unused_0[6]; - /* Thirty two bytes HMAC SHA256 hash of NVM configuration. */ - uint8_t hash[32]; uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_get_nvm_measurement_output_t, *phwrm_mfg_get_nvm_measurement_output_t; +} hwrm_udcc_session_cfg_output_t, *phwrm_udcc_session_cfg_output_t; -/************************* - * hwrm_mfg_psoc_qstatus * - *************************/ +/************************** + * hwrm_udcc_session_qcfg * + **************************/ -/* hwrm_mfg_psoc_qstatus_input (size:192b/24B) */ +/* hwrm_udcc_session_qcfg_input (size:192b/24B) */ -typedef struct hwrm_mfg_psoc_qstatus_input { +typedef struct hwrm_udcc_session_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77957,15 +91066,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* */ - uint32_t reserved1; - /* */ - uint32_t reserved2; -} hwrm_mfg_psoc_qstatus_input_t, *phwrm_mfg_psoc_qstatus_input_t; + /* A handle for the session to be queried, if previously allocated. */ + uint16_t session_id; + uint8_t unused_0[6]; +} hwrm_udcc_session_qcfg_input_t, *phwrm_udcc_session_qcfg_input_t; -/* hwrm_mfg_psoc_qstatus_output (size:768b/96B) */ +/* hwrm_udcc_session_qcfg_output (size:512b/64B) */ -typedef struct hwrm_mfg_psoc_qstatus_output { +typedef struct hwrm_udcc_session_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77974,52 +91082,63 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* PBL version info. Start at 0, roll if change in structure */ - uint8_t pbl_info_version; - /* PBL info length. Counts all bytes. */ - uint8_t pbl_info_length; + /* session_state specifying configuration of the session. */ + uint8_t session_state; + /* + * This bit is set if the session is enabled and firmware is + * querying it for events. The bit is cleared if no querying + * should occur for this session. + */ + #define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_ENABLED UINT32_C(0x1) + /* UDCC flow is not created in driver. */ + #define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_FLOW_NOT_CREATED UINT32_C(0x2) + /* UDCC flow is now deleted in driver. */ + #define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_FLOW_HAS_BEEN_DELETED UINT32_C(0x4) + uint8_t unused_0; + /* destination mac address used for the session. */ + uint8_t dest_mac[6]; /* - * Hardware generation major version. Rolled on incompatible hardware - * changes. + * a 4 byte or 16 byte IP address, depending on whether the ip_type + * specifies IPv4 or IPv6. For IPv4 addresses, the first 4 bytes of the + * 16 byte field are used; the remaining 12 bytes are not used. */ - uint8_t hw_generation_major; - /* Hardware generation minor version. Tracks minor changes. */ - uint8_t hw_generation_minor; - /* Reserved. */ - uint8_t feature_support; - /* Firmware version major. */ - uint8_t fw_version_major; - /* Firmware version minor. */ - uint8_t fw_version_minor; - /* Indicate which of the two firmware images is active. */ - uint8_t active_image; - /* Identifies PSoC specific part. */ - uint32_t silicon_id; - /* Length of part number string in bytes, including NULL terminator. */ - uint8_t part_number_string_length; - uint8_t unused_1[3]; - /* Part number string in ASCII. */ - uint8_t part_number_string[64]; + uint32_t dest_ip[4]; + uint8_t unused_1[2]; + /* source mac address used for the session. */ + uint8_t src_mac[6]; + /* source QP number used for the session. */ + uint32_t src_qp_num; + /* destination QP number used for the session. */ + uint32_t dest_qp_num; + /* + * address for the tx flow statistics record to be sampled by the + * UDCC firmware. + */ + uint32_t tx_stats_record; + /* + * address for the rx flow statistics record to be sampled by the + * UDCC firmware. + */ + uint32_t rx_stats_record; uint8_t unused_2[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_psoc_qstatus_output_t, *phwrm_mfg_psoc_qstatus_output_t; +} hwrm_udcc_session_qcfg_output_t, *phwrm_udcc_session_qcfg_output_t; /*************************** - * hwrm_mfg_selftest_qlist * + * hwrm_udcc_session_query * ***************************/ -/* hwrm_mfg_selftest_qlist_input (size:128b/16B) */ +/* hwrm_udcc_session_query_input (size:192b/24B) */ -typedef struct hwrm_mfg_selftest_qlist_input { +typedef struct hwrm_udcc_session_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -78048,11 +91167,14 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} hwrm_mfg_selftest_qlist_input_t, *phwrm_mfg_selftest_qlist_input_t; + /* A handle for the session to be queried, if previously allocated. */ + uint16_t session_id; + uint8_t unused_0[6]; +} hwrm_udcc_session_query_input_t, *phwrm_udcc_session_query_input_t; -/* hwrm_mfg_selftest_qlist_output (size:192b/24B) */ +/* hwrm_udcc_session_query_output (size:576b/72B) */ -typedef struct hwrm_mfg_selftest_qlist_output { +typedef struct hwrm_udcc_session_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -78061,63 +91183,70 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This field represents the number of tests available to be - * requested by manufacturing tool. - */ - uint8_t num_tests; - /* This field indicates which self-test is available to be run. */ - uint8_t available_tests; - /* - * Can run the peripheral tests. Individual peripherals are - * specified in peripheral_tests field. - */ - #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PERIPHERAL_TEST UINT32_C(0x1) - /* - * This field represents the maximum timeout for all the - * tests to complete in milliseconds. - */ - uint16_t test_timeout; - /* - * This field is a 32 bits bitmap, each bit specifies a peripheral - * test. - */ - uint32_t peripheral_tests; - /* Can run memory test on Co-CPU peripheral */ - #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_CO_CPU_MEMORY UINT32_C(0x1) - /* Can run test on dpll eeprom peripheral */ - #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_DPLL_EEPROM UINT32_C(0x2) - /* Can run test on dpll mmcx connector peripheral */ - #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_DPLL_MMCX UINT32_C(0x4) - /* Can run test on gnss peripheral */ - #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_GNSS UINT32_C(0x8) - /* Can run pcie test on Co-CPU peripheral */ - #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_CO_CPU_PCIE UINT32_C(0x10) - /* Can run test on internal fabric peripheral */ - #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_INTERNAL_FABRIC UINT32_C(0x20) - /* Can run test on oven controlled crystal oscillator peripheral */ - #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_OCXO UINT32_C(0x40) - /* Can run test on telecom pll peripheral */ - #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_TELECOM_PLL UINT32_C(0x80) - uint8_t unused_2[7]; + /* field for the minimum RTT value (in ns) for the session. */ + uint32_t min_rtt_ns; + /* field for the maximum RTT value (in ns) for the session. */ + uint32_t max_rtt_ns; + /* + * field for the current configured rate (in Mbps) for the + * session. + */ + uint32_t cur_rate_mbps; + /* + * count for the number of events sent from FW to the UDCC + * program. + */ + uint32_t tx_event_count; + /* + * count for the number of CNP events sent from FW to the UDCC + * program. + */ + uint32_t cnp_rx_event_count; + /* + * count for the number of RTT request events received by the FW from + * the UDCC program. + */ + uint32_t rtt_req_count; + /* + * count for the number of RTT response events sent by the FW to the + * UDCC program. + */ + uint32_t rtt_resp_count; + /* count for the number of bytes transmitted for the session. */ + uint32_t tx_bytes_count; + /* count for the number of packets transmitted for the session. */ + uint32_t tx_packets_count; + /* count of initiator probes transmitted for the session. */ + uint32_t init_probes_sent; + /* count of terminator probes received for the session. */ + uint32_t term_probes_recv; + /* count of CNP packets received for the session. */ + uint32_t cnp_packets_recv; + /* count of retransmission timeout events received for the session. */ + uint32_t rto_event_recv; + /* count of sequence error NAK events received for the session. */ + uint32_t seq_err_nak_recv; + /* the current number of qps associated with the session. */ + uint32_t qp_count; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_selftest_qlist_output_t, *phwrm_mfg_selftest_qlist_output_t; +} hwrm_udcc_session_query_output_t, *phwrm_udcc_session_query_output_t; -/************************** - * hwrm_mfg_selftest_exec * - **************************/ +/********************** + * hwrm_udcc_comp_cfg * + **********************/ -/* hwrm_mfg_selftest_exec_input (size:192b/24B) */ +/* hwrm_udcc_comp_cfg_input (size:576b/72B) */ -typedef struct hwrm_mfg_selftest_exec_input { +typedef struct hwrm_udcc_comp_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -78146,40 +91275,38 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This field indicates which self-test is being requested to run. */ - uint8_t flags; /* - * Run the Peripheral tests specified in peripheral_tests - * field. + * This field holds the configuration arguments, which can be used + * to specify the context of the configuration data, e.g. type, + * session ID, etc. It is possible not all arg_buf are utilized. + * The format and meaning of the arguments are internal to + * the UDCC program. */ - #define HWRM_MFG_SELFTEST_EXEC_INPUT_FLAGS_PERIPHERAL_TEST UINT32_C(0x1) - uint8_t unused_0[3]; + uint8_t arg_buf[40]; /* - * This field is a 32 bits bitmap to specify which peripheral tests to - * run, each bit specifies a peripheral test. + * This field specifies the number of bytes in arg_buf that are + * configuration arguments. It can be zero if there are no arguments. */ - uint32_t peripheral_tests; - /* Run memory test on Co-CPU peripheral */ - #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_CO_CPU_MEMORY UINT32_C(0x1) - /* Run test on dpll eeprom peripheral */ - #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_DPLL_EEPROM UINT32_C(0x2) - /* Run test on dpll mmcx connector peripheral */ - #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_DPLL_MMCX UINT32_C(0x4) - /* Run test on gnss peripheral */ - #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_GNSS UINT32_C(0x8) - /* Run pcie test on Co-CPU peripheral */ - #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_CO_CPU_PCIE UINT32_C(0x10) - /* Run test on internal fabric peripheral */ - #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_INTERNAL_FABRIC UINT32_C(0x20) - /* Run test on oven controlled crystal oscillator peripheral */ - #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_OCXO UINT32_C(0x40) - /* Run test on telecom pll peripheral */ - #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_TELECOM_PLL UINT32_C(0x80) -} hwrm_mfg_selftest_exec_input_t, *phwrm_mfg_selftest_exec_input_t; + uint32_t arg_len; + /* + * This field specifies the length of the configuration data + * stored in the host memory. The host driver shall guarantee + * this number is not greater than the maximum configuration + * transfer size that is specified by the max_comp_cfg_xfer + * field of hwrm_udcc_qcaps_output. + */ + uint32_t cfg_len; + /* + * This field specifies the address of the host memory where + * the configuration data is stored. The format and meaning of + * the configuration data are internal to the UDCC program. + */ + uint64_t cfg_host_addr; +} hwrm_udcc_comp_cfg_input_t, *phwrm_udcc_comp_cfg_input_t; -/* hwrm_mfg_selftest_exec_output (size:192b/24B) */ +/* hwrm_udcc_comp_cfg_output (size:128b/16B) */ -typedef struct hwrm_mfg_selftest_exec_output { +typedef struct hwrm_udcc_comp_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -78188,88 +91315,25 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The following tests were requested to be run. */ - uint8_t requested_tests; - /* A request was made to run the peripheral tests. */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PERIPHERAL_TEST UINT32_C(0x1) - /* - * If a test was requested to be run as seen in the requested_tests - * field, this bit indicates whether the test was successful(1) or - * failed(0). - */ - uint8_t test_success; - /* - * If requested, a value of 1 indicates the peripheral tests - * completed successfully. - */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PERIPHERAL_TEST UINT32_C(0x1) - uint8_t unused_0[2]; - /* - * This field is a 32 bits bitmap for firmware to indicate which - * peripheral tests are specified by the host, each bit specifies - * a peripheral test. - */ - uint32_t peripheral_requested_tests; - /* Co-CPU peripheral test requested */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_CO_CPU_MEMORY UINT32_C(0x1) - /* dpll eeprom peripheral test requested */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_DPLL_EEPROM UINT32_C(0x2) - /* dpll mmcx connector peripheral test requested */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_DPLL_MMCX UINT32_C(0x4) - /* gnss peripheral test requested */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_GNSS UINT32_C(0x8) - /* pcie test on Co-CPU peripheral test requested */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_CO_CPU_PCIE UINT32_C(0x10) - /* internal fabric peripheral test requested */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_INTERNAL_FABRIC UINT32_C(0x20) - /* oven controlled crystal oscillator peripheral test requested */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_OCXO UINT32_C(0x40) - /* telecom pll peripheral test requested */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_TELECOM_PLL UINT32_C(0x80) - /* - * This field is a 32 bits bitmap for firmware to indicate which - * peripheral tests are successfully executed, each bit specifies - * a peripheral test. - */ - uint32_t peripheral_tests_success; - /* Co-CPU peripheral test is successfully executed */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_CO_CPU_MEMORY UINT32_C(0x1) - /* dpll eeprom peripheral test is successfully executed */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_DPLL_EEPROM UINT32_C(0x2) - /* dpll mmcx connector peripheral test is successfully executed */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_DPLL_MMCX UINT32_C(0x4) - /* gnss peripheral test is successfully executed */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_GNSS UINT32_C(0x8) - /* pcie test on Co-CPU peripheral test is successfully executed */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_CO_CPU_PCIE UINT32_C(0x10) - /* internal fabric peripheral test is successfully executed */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_INTERNAL_FABRIC UINT32_C(0x20) - /* - * oven controlled crystal oscillator peripheral test is successfully - * executed - */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_OCXO UINT32_C(0x40) - /* telecom pll peripheral test is successfully executed */ - #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_TELECOM_PLL UINT32_C(0x80) - uint8_t unused_1[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_selftest_exec_output_t, *phwrm_mfg_selftest_exec_output_t; +} hwrm_udcc_comp_cfg_output_t, *phwrm_udcc_comp_cfg_output_t; -/**************** - * hwrm_oem_cmd * - ****************/ +/*********************** + * hwrm_udcc_comp_qcfg * + ***********************/ -/* hwrm_oem_cmd_input (size:1024b/128B) */ +/* hwrm_udcc_comp_qcfg_input (size:576b/72B) */ -typedef struct hwrm_oem_cmd_input { +typedef struct hwrm_udcc_comp_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -78298,15 +91362,37 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t IANA; - uint32_t unused_0; - /* This field contains the vendor specific command data. */ - uint32_t oem_data[26]; -} hwrm_oem_cmd_input_t, *phwrm_oem_cmd_input_t; + /* + * This field holds the query arguments, which can be used to + * specify the context of the query, e.g. type, session ID, etc. + * It is possible not all arg_buf are utilized. + * The format and meaning of the arguments are internal to + * the UDCC program. + */ + uint8_t arg_buf[40]; + /* + * This field specifies the number of bytes in arg_buf that are + * query arguments. It can be zero if there are no arguments. + */ + uint32_t arg_len; + /* + * This field specifies the size of the buffer in the host memory + * for receiving the configuration data. The host driver shall + * guarantee the size of the buffer is not smaller than + * the maximum configuration transfer size that is specified by + * the max_comp_cfg_xfer field of hwrm_udcc_qcaps_output. + */ + uint32_t cfg_host_buf_size; + /* + * This field specifies the address of the host memory where + * the queried configuration to be stored. + */ + uint64_t cfg_host_addr; +} hwrm_udcc_comp_qcfg_input_t, *phwrm_udcc_comp_qcfg_input_t; -/* hwrm_oem_cmd_output (size:768b/96B) */ +/* hwrm_udcc_comp_qcfg_output (size:128b/16B) */ -typedef struct hwrm_oem_cmd_output { +typedef struct hwrm_udcc_comp_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -78315,29 +91401,32 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t IANA; - uint32_t unused_0; - /* This field contains the vendor specific response data. */ - uint32_t oem_data[18]; - uint8_t unused_1[7]; + /* + * This field specifies the length of configuration data transferred + * into the host memory. The amount of data transferred is up to + * the maximum configuration transfer size that is specified by + * the max_comp_cfg_xfer field of hwrm_udcc_qcaps_output. + */ + uint32_t cfg_len; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_oem_cmd_output_t, *phwrm_oem_cmd_output_t; +} hwrm_udcc_comp_qcfg_output_t, *phwrm_udcc_comp_qcfg_output_t; -/*********** - * hwrm_sv * - ***********/ +/************************ + * hwrm_udcc_comp_query * + ************************/ -/* hwrm_sv_input (size:1152b/144B) */ +/* hwrm_udcc_comp_query_input (size:576b/72B) */ -typedef struct hwrm_sv_input { +typedef struct hwrm_udcc_comp_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -78366,12 +91455,37 @@ * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t opaque[32]; -} hwrm_sv_input_t, *phwrm_sv_input_t; + /* + * This field holds the query arguments, which can be used to + * specify the context of the query, e.g. type, session ID, etc. + * It is possible not all arg_buf are utilized. + * The format and meaning of the arguments are internal to + * the UDCC program. + */ + uint8_t arg_buf[40]; + /* + * This field specifies the number of bytes in arg_buf that are + * query arguments. It can be zero if there are no arguments. + */ + uint32_t arg_len; + /* + * This field specifies the size of the buffer in the host memory + * for receiving the status or statistics data. The host driver + * shall guarantee the size of the buffer is not smaller than + * the maximum data transfer size that is specified by + * the max_comp_data_xfer field of hwrm_udcc_qcaps_output. + */ + uint32_t data_host_buf_size; + /* + * This field specifies the address of the host memory where + * the queried data to be stored. + */ + uint64_t data_host_addr; +} hwrm_udcc_comp_query_input_t, *phwrm_udcc_comp_query_input_t; -/* hwrm_sv_output (size:1088b/136B) */ +/* hwrm_udcc_comp_query_output (size:128b/16B) */ -typedef struct hwrm_sv_output { +typedef struct hwrm_udcc_comp_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -78380,7 +91494,22 @@ uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t opaque[32]; -} hwrm_sv_output_t, *phwrm_sv_output_t; + /* + * This field specifies the length of status or statistics data + * transferred into the host memory. The amount of data transferred + * is up to the maximum data transfer size that is specified by + * the max_comp_data_xfer field of hwrm_udcc_qcaps_output. + */ + uint32_t data_len; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_udcc_comp_query_output_t, *phwrm_udcc_comp_query_output_t; #endif /* _HSI_STRUCT_DEF_H_ */