diff --git a/sys/dev/mpi3mr/mpi3mr.h b/sys/dev/mpi3mr/mpi3mr.h
--- a/sys/dev/mpi3mr/mpi3mr.h
+++ b/sys/dev/mpi3mr/mpi3mr.h
@@ -123,6 +123,8 @@
 #define MPI3MR_OP_REP_Q_QD		1024
 #define MPI3MR_OP_REP_Q_QD_A0		4096
 
+#define MPI3MR_THRESHOLD_REPLY_COUNT	100
+
 #define MPI3MR_CHAINSGE_SIZE	MPI3MR_4K_PGSZ
 
 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST	\
diff --git a/sys/dev/mpi3mr/mpi3mr.c b/sys/dev/mpi3mr/mpi3mr.c
--- a/sys/dev/mpi3mr/mpi3mr.c
+++ b/sys/dev/mpi3mr/mpi3mr.c
@@ -4388,6 +4388,7 @@
 	U32 num_adm_reply = 0;
 	U64 reply_dma = 0;
 	Mpi3DefaultReplyDescriptor_t *reply_desc;
+	U16 threshold_comps = 0;
 	
 	mtx_lock_spin(&sc->admin_reply_lock);
 	if (sc->admin_in_use == false) {
@@ -4425,6 +4426,11 @@
 		if ((reply_desc->ReplyFlags &
 		     MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 			break;
+
+		if (++threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
+			mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET, adm_reply_ci);
+			threshold_comps = 0;
+		}
 	} while (1);
 
 	mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET, adm_reply_ci);
@@ -4837,7 +4843,7 @@
 	U32 num_op_replies = 0;
 	U64 reply_dma = 0;
 	Mpi3DefaultReplyDescriptor_t *reply_desc;
-	U16 req_qid = 0;
+	U16 req_qid = 0, threshold_comps = 0;
 
 	mtx_lock_spin(&op_reply_q->q_lock);
 	if (op_reply_q->in_use == false) {
@@ -4882,6 +4888,12 @@
 		if ((reply_desc->ReplyFlags &
 		     MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 			break;
+
+		if (++threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
+			mpi3mr_regwrite(sc, MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(op_reply_q->qid), reply_ci);
+			threshold_comps = 0;
+		}
+
 	} while (1);