diff --git a/sys/arm64/arm64/gicv3_its.c b/sys/arm64/arm64/gicv3_its.c
--- a/sys/arm64/arm64/gicv3_its.c
+++ b/sys/arm64/arm64/gicv3_its.c
@@ -45,6 +45,7 @@
 #include <sys/malloc.h>
 #include <sys/module.h>
 #include <sys/mutex.h>
+#include <sys/physmem.h>
 #include <sys/proc.h>
 #include <sys/taskqueue.h>
 #include <sys/tree.h>
@@ -292,6 +293,13 @@
 	vm_page_t ma; /* fake msi page */
 };
 
+/*
+ * The ITS page size is always 4k, even when the MMU size is different.
+ */
+#define GICV3_ITS_PAGE_SIZE		PAGE_SIZE_4K
+#define GICV3_ITS_MASK			((GICV3_ITS_PAGE_SIZE - 1) |	\
+	    GICR_PENDBASER_OUTER_CACHE_MASK)
+
 typedef void (its_quirk_func_t)(device_t);
 static its_quirk_func_t its_quirk_cavium_22375;
 
@@ -830,7 +838,17 @@
 
 		/* Make sure the GIC has seen everything */
 		dsb(sy);
-	}
+	} else {
+		KASSERT(sc->sc_pend_base[cpuid] == 0,
+		    ("PREALLOC too soon cpuid %d", cpuid));
+		tmp = gic_r_read_8(gicv3, GICR_PENDBASER);
+		tmp &= ~GICV3_ITS_MASK;
+		if (!physmem_excluded(tmp, LPI_PENDTAB_SIZE))
+			panic("gicv3 PENDBASER on cpu %d needs to reuse %#lx, but not reserved\n",
+			    cpuid, tmp);
+		sc->sc_pend_base[cpuid] = PHYS_TO_DMAP(tmp);
+        }
+
 
 	if (bootverbose)
 		device_printf(gicv3, "using %sPENDBASE of %#lx on cpu %d\n",