diff --git a/sys/amd64/pci/pci_cfgreg.c b/sys/amd64/pci/pci_cfgreg.c
--- a/sys/amd64/pci/pci_cfgreg.c
+++ b/sys/amd64/pci/pci_cfgreg.c
@@ -41,12 +41,12 @@
 #include <vm/pmap.h>
 #include <machine/pci_cfgreg.h>
 
-static uint32_t	pci_docfgregread(int bus, int slot, int func, int reg,
-		    int bytes);
-static int	pciereg_cfgread(int bus, unsigned slot, unsigned func,
-		    unsigned reg, unsigned bytes);
-static void	pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
-		    unsigned reg, int data, unsigned bytes);
+static uint32_t	pci_docfgregread(int domain, int bus, int slot, int func,
+		    int reg, int bytes);
+static int	pciereg_cfgread(int domain, int bus, unsigned slot,
+		    unsigned func, unsigned reg, unsigned bytes);
+static void	pciereg_cfgwrite(int domain, int bus, unsigned slot,
+		    unsigned func, unsigned reg, int data, unsigned bytes);
 static int	pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
 static void	pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
 
@@ -76,22 +76,25 @@
 }
 
 static uint32_t
-pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
+pci_docfgregread(int domain, int bus, int slot, int func, int reg, int bytes)
 {
+	if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0)
+		return (pcireg_cfgread(bus, slot, func, reg, bytes));
 
 	if (cfgmech == CFGMECH_PCIE &&
-	    (bus >= pcie_minbus && bus <= pcie_maxbus) &&
-	    (bus != 0 || !(1 << slot & pcie_badslots)))
-		return (pciereg_cfgread(bus, slot, func, reg, bytes));
-	else
+	    (bus >= pcie_minbus && bus <= pcie_maxbus))
+		return (pciereg_cfgread(domain, bus, slot, func, reg, bytes));
+	else if (domain == 0)
 		return (pcireg_cfgread(bus, slot, func, reg, bytes));
+	else
+		return (-1);
 }
 
 /* 
  * Read configuration space register
  */
 u_int32_t
-pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
+pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes)
 {
 	uint32_t line;
 
@@ -104,26 +107,31 @@
 	 * as an invalid IRQ.
 	 */
 	if (reg == PCIR_INTLINE && bytes == 1) {
-		line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
+		line = pci_docfgregread(domain, bus, slot, func, PCIR_INTLINE,
+		    1);
 		if (line == 0 || line >= 128)
 			line = PCI_INVALID_IRQ;
 		return (line);
 	}
-	return (pci_docfgregread(bus, slot, func, reg, bytes));
+	return (pci_docfgregread(domain, bus, slot, func, reg, bytes));
 }
 
 /* 
  * Write configuration space register 
  */
 void
-pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
+pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data,
+    int bytes)
 {
+	if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0) {
+		pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
+		return;
+	}
 
 	if (cfgmech == CFGMECH_PCIE &&
-	    (bus >= pcie_minbus && bus <= pcie_maxbus) &&
-	    (bus != 0 || !(1 << slot & pcie_badslots)))
-		pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
-	else
+	    (bus >= pcie_minbus && bus <= pcie_maxbus))
+		pciereg_cfgwrite(domain, bus, slot, func, reg, data, bytes);
+	else if (domain == 0)
 		pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
 }
 
@@ -242,7 +250,7 @@
 			if (val1 == 0xffffffff)
 				continue;
 
-			val2 = pciereg_cfgread(0, slot, 0, 0, 4);
+			val2 = pciereg_cfgread(0, 0, slot, 0, 0, 4);
 			if (val2 != val1)
 				pcie_badslots |= (1 << slot);
 		}
@@ -267,14 +275,14 @@
  */
 
 static int
-pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
+pciereg_cfgread(int domain, int bus, unsigned slot, unsigned func, unsigned reg,
     unsigned bytes)
 {
 	vm_offset_t va;
 	int data = -1;
 
-	if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
-	    func > PCI_FUNCMAX || reg > PCIE_REGMAX)
+	if (domain != 0 || bus < pcie_minbus || bus > pcie_maxbus ||
+	    slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
 		return (-1);
 
 	va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
@@ -298,13 +306,13 @@
 }
 
 static void
-pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
-    unsigned bytes)
+pciereg_cfgwrite(int domain, int bus, unsigned slot, unsigned func,
+    unsigned reg, int data, unsigned bytes)
 {
 	vm_offset_t va;
 
-	if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
-	    func > PCI_FUNCMAX || reg > PCIE_REGMAX)
+	if (domain != 0 || bus < pcie_minbus || bus > pcie_maxbus ||
+	    slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
 		return;
 
 	va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
diff --git a/sys/amd64/vmm/amd/amdvi_hw.c b/sys/amd64/vmm/amd/amdvi_hw.c
--- a/sys/amd64/vmm/amd/amdvi_hw.c
+++ b/sys/amd64/vmm/amd/amdvi_hw.c
@@ -124,7 +124,7 @@
 amdvi_pci_read(struct amdvi_softc *softc, int off)
 {
 
-	return (pci_cfgregread(PCI_RID2BUS(softc->pci_rid),
+	return (pci_cfgregread(softc->pci_seg, PCI_RID2BUS(softc->pci_rid),
 	    PCI_RID2SLOT(softc->pci_rid), PCI_RID2FUNC(softc->pci_rid),
 	    off, 4));
 }
diff --git a/sys/amd64/vmm/amd/ivrs_drv.c b/sys/amd64/vmm/amd/ivrs_drv.c
--- a/sys/amd64/vmm/amd/ivrs_drv.c
+++ b/sys/amd64/vmm/amd/ivrs_drv.c
@@ -649,7 +649,8 @@
 	softc->dev = dev;
 	ivhd = ivhd_hdrs[unit];
 	KASSERT(ivhd, ("ivhd is NULL"));
-	softc->pci_dev = pci_find_bsf(PCI_RID2BUS(ivhd->Header.DeviceId),
+	softc->pci_dev = pci_find_dbsf(ivhd->PciSegmentGroup,
+	    PCI_RID2BUS(ivhd->Header.DeviceId),
 	    PCI_RID2SLOT(ivhd->Header.DeviceId),
 	    PCI_RID2FUNC(ivhd->Header.DeviceId));
 
diff --git a/sys/arm64/acpica/pci_cfgreg.c b/sys/arm64/acpica/pci_cfgreg.c
--- a/sys/arm64/acpica/pci_cfgreg.c
+++ b/sys/arm64/acpica/pci_cfgreg.c
@@ -40,7 +40,7 @@
  * Read configuration space register
  */
 uint32_t
-pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
+pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes)
 {
 
 	/* ARM64TODO */
@@ -52,7 +52,8 @@
  * Write configuration space register
  */
 void
-pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
+pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data,
+    int bytes)
 {
 
 	/* ARM64TODO */
diff --git a/sys/arm64/include/pci_cfgreg.h b/sys/arm64/include/pci_cfgreg.h
--- a/sys/arm64/include/pci_cfgreg.h
+++ b/sys/arm64/include/pci_cfgreg.h
@@ -27,7 +27,7 @@
 #define	_MACHINE_PCI_CFGREG_H
 
 int pci_cfgregopen(void);
-uint32_t pci_cfgregread(int, int, int, int, int);
-void pci_cfgregwrite(int, int, int, int, u_int32_t, int);
+uint32_t pci_cfgregread(int, int, int, int, int, int);
+void pci_cfgregwrite(int, int, int, int, int, uint32_t, int);
 
 #endif /* !_MACHINE_PCI_CFGREG_H */
diff --git a/sys/dev/acpica/Osd/OsdHardware.c b/sys/dev/acpica/Osd/OsdHardware.c
--- a/sys/dev/acpica/Osd/OsdHardware.c
+++ b/sys/dev/acpica/Osd/OsdHardware.c
@@ -110,7 +110,7 @@
     if (!pci_cfgregopen())
 	return (AE_NOT_EXIST);
 
-    *(UINT64 *)Value = pci_cfgregread(PciId->Bus, PciId->Device,
+    *(UINT64 *)Value = pci_cfgregread(PciId->Segment, PciId->Bus, PciId->Device,
 	PciId->Function, Register, Width / 8);
 
     return (AE_OK);
@@ -132,8 +132,8 @@
     if (!pci_cfgregopen())
     	return (AE_NOT_EXIST);
 
-    pci_cfgregwrite(PciId->Bus, PciId->Device, PciId->Function, Register,
-	Value, Width / 8);
+    pci_cfgregwrite(PciId->Segment, PciId->Bus, PciId->Device, PciId->Function,
+	Register, Value, Width / 8);
 
     return (AE_OK);
 #endif
diff --git a/sys/dev/acpica/acpi_pci_link.c b/sys/dev/acpica/acpi_pci_link.c
--- a/sys/dev/acpica/acpi_pci_link.c
+++ b/sys/dev/acpica/acpi_pci_link.c
@@ -572,16 +572,16 @@
 
 /* XXX: Note that this is identical to pci_pir_search_irq(). */
 static uint8_t
-acpi_pci_link_search_irq(int bus, int device, int pin)
+acpi_pci_link_search_irq(int domain, int bus, int device, int pin)
 {
 	uint32_t value;
 	uint8_t func, maxfunc;
 
 	/* See if we have a valid device at function 0. */
-	value = pci_cfgregread(bus, device, 0, PCIR_VENDOR, 2);
+	value = pci_cfgregread(domain, bus, device, 0, PCIR_VENDOR, 2);
 	if (value == PCIV_INVALID)
 		return (PCI_INVALID_IRQ);
-	value = pci_cfgregread(bus, device, 0, PCIR_HDRTYPE, 1);
+	value = pci_cfgregread(domain, bus, device, 0, PCIR_HDRTYPE, 1);
 	if ((value & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
 		return (PCI_INVALID_IRQ);
 	if (value & PCIM_MFDEV)
@@ -591,10 +591,12 @@
 
 	/* Scan all possible functions at this device. */
 	for (func = 0; func <= maxfunc; func++) {
-		value = pci_cfgregread(bus, device, func, PCIR_VENDOR, 2);
+		value = pci_cfgregread(domain, bus, device, func, PCIR_VENDOR,
+		    2);
 		if (value == PCIV_INVALID)
 			continue;
-		value = pci_cfgregread(bus, device, func, PCIR_INTPIN, 1);
+		value = pci_cfgregread(domain, bus, device, func, PCIR_INTPIN,
+		    1);
 
 		/*
 		 * See if it uses the pin in question.  Note that the passed
@@ -603,7 +605,8 @@
 		 */
 		if (value != pin + 1)
 			continue;
-		value = pci_cfgregread(bus, device, func, PCIR_INTLINE, 1);
+		value = pci_cfgregread(domain, bus, device, func, PCIR_INTLINE,
+		    1);
 		if (bootverbose)
 			printf(
 		"ACPI: Found matching pin for %d.%d.INT%c at func %d: %d\n",
@@ -638,18 +641,22 @@
 {
 	struct link *link;
 	uint8_t bios_irq;
-	uintptr_t bus;
+	uintptr_t bus, domain;
 
 	/*
-	 * Look up the PCI bus for the specified PCI bridge device.  Note
-	 * that the PCI bridge device might not have any children yet.
-	 * However, looking up its bus number doesn't require a valid child
-	 * device, so we just pass NULL.
+	 * Look up the PCI domain and bus for the specified PCI bridge
+	 * device.  Note that the PCI bridge device might not have any
+	 * children yet.  However, looking up these IVARs doesn't
+	 * require a valid child device, so we just pass NULL.
 	 */
 	if (BUS_READ_IVAR(pcib, NULL, PCIB_IVAR_BUS, &bus) != 0) {
 		device_printf(pcib, "Unable to read PCI bus number");
 		panic("PCI bridge without a bus number");
 	}
+	if (BUS_READ_IVAR(pcib, NULL, PCIB_IVAR_DOMAIN, &domain) != 0) {
+		device_printf(pcib, "Unable to read PCI domain number");
+		panic("PCI bridge without a domain number");
+	}
 		
 	/* Bump the reference count. */
 	ACPI_SERIAL_BEGIN(pci_link);
@@ -667,7 +674,7 @@
 	 * The BIOS only routes interrupts via ISA IRQs using the ATPICs
 	 * (8259As).  Thus, if this link is routed via an ISA IRQ, go
 	 * look to see if the BIOS routed an IRQ for this link at the
-	 * indicated (bus, slot, pin).  If so, we prefer that IRQ for
+	 * indicated (domain, bus, slot, pin).  If so, we prefer that IRQ for
 	 * this link and add that IRQ to our list of known-good IRQs.
 	 * This provides a good work-around for link devices whose _CRS
 	 * method is either broken or bogus.  We only use the value
@@ -684,7 +691,7 @@
 	}
 
 	/* Try to find a BIOS IRQ setting from any matching devices. */
-	bios_irq = acpi_pci_link_search_irq(bus, slot, pin);
+	bios_irq = acpi_pci_link_search_irq(domain, bus, slot, pin);
 	if (!PCI_INTERRUPT_VALID(bios_irq)) {
 		ACPI_SERIAL_END(pci_link);
 		return;
diff --git a/sys/dev/acpica/acpi_pcib_acpi.c b/sys/dev/acpica/acpi_pcib_acpi.c
--- a/sys/dev/acpica/acpi_pcib_acpi.c
+++ b/sys/dev/acpica/acpi_pcib_acpi.c
@@ -629,14 +629,18 @@
 acpi_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
     u_int reg, int bytes)
 {
-    return (pci_cfgregread(bus, slot, func, reg, bytes));
+    struct acpi_hpcib_softc *sc = device_get_softc(dev);
+
+    return (pci_cfgregread(sc->ap_segment, bus, slot, func, reg, bytes));
 }
 
 static void
 acpi_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
     u_int reg, uint32_t data, int bytes)
 {
-    pci_cfgregwrite(bus, slot, func, reg, data, bytes);
+    struct acpi_hpcib_softc *sc = device_get_softc(dev);
+
+    pci_cfgregwrite(sc->ap_segment, bus, slot, func, reg, data, bytes);
 }
 
 static int
diff --git a/sys/dev/agp/agp_amd64.c b/sys/dev/agp/agp_amd64.c
--- a/sys/dev/agp/agp_amd64.c
+++ b/sys/dev/agp/agp_amd64.c
@@ -118,10 +118,10 @@
 agp_amd64_nvidia_match(uint16_t devid)
 {
 	/* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
-	if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
-	    pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
-	    pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
-	    pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
+	if (pci_cfgregread(0, 0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
+	    pci_cfgregread(0, 0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
+	    pci_cfgregread(0, 0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
+	    pci_cfgregread(0, 0, 11, 0, PCIR_DEVICE, 2) != devid)
 		return (ENXIO);
 
 	return (0);
@@ -131,11 +131,11 @@
 agp_amd64_via_match(void)
 {
 	/* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
-	if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
-	    pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
-	    pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
-	    pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
-	    (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
+	if (pci_cfgregread(0, 0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
+	    pci_cfgregread(0, 0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
+	    pci_cfgregread(0, 0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
+	    pci_cfgregread(0, 0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
+	    (pci_cfgregread(0, 0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
 		return (0);
 
 	return (1);
@@ -165,7 +165,7 @@
 	int i, n, error;
 
 	for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) {
-		devid = pci_cfgregread(0, i, 3, 0, 4);
+		devid = pci_cfgregread(0, 0, i, 3, 0, 4);
 		if (devid == 0x11031022 || devid == 0x12031022) {
 			sc->mctrl[n] = i;
 			n++;
@@ -227,11 +227,11 @@
 
 	/* Install the gatt and enable aperture. */
 	for (i = 0; i < sc->n_mctrl; i++) {
-		pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
+		pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
 		    (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
 		    4);
-		pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
-		    (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
+		pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
+		    (pci_cfgregread(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
 		    AGP_AMD64_APCTRL_GARTEN) &
 		    ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
 		    4);
@@ -249,8 +249,8 @@
 	agp_free_cdev(dev);
 
 	for (i = 0; i < sc->n_mctrl; i++)
-		pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
-		    pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
+		pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
+		    pci_cfgregread(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
 		    ~AGP_AMD64_APCTRL_GARTEN, 4);
 
 	AGP_SET_APERTURE(dev, sc->initial_aperture);
@@ -278,7 +278,7 @@
 	struct agp_amd64_softc *sc = device_get_softc(dev);
 	uint32_t i;
 
-	i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
+	i = (pci_cfgregread(0, 0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
 		AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
 
 	if (i >= AGP_AMD64_TABLE_SIZE)
@@ -301,8 +301,8 @@
 		return (EINVAL);
 
 	for (j = 0; j < sc->n_mctrl; j++)
-		pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
-		    (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
+		pci_cfgregwrite(0, 0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
+		    (pci_cfgregread(0, 0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
 		    ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
 
 	switch (pci_get_vendor(dev)) {
@@ -356,10 +356,15 @@
 	struct agp_amd64_softc *sc = device_get_softc(dev);
 	int i;
 
-	for (i = 0; i < sc->n_mctrl; i++)
-		pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
-		    pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
-		    AGP_AMD64_CACHECTRL_INVGART, 4);
+	for (i = 0; i < sc->n_mctrl; i++) {
+		uint32_t val;
+
+		val = pci_cfgregread(0, 0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
+		    4);
+		val |= AGP_AMD64_CACHECTRL_INVGART;
+		pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, val,
+		    4);
+	}
 }
 
 static void
@@ -372,7 +377,7 @@
 	sc->apbase = rman_get_start(sc->agp.as_aperture);
 	apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
 	for (i = 0; i < sc->n_mctrl; i++)
-		pci_cfgregwrite(0, sc->mctrl[i], 3,
+		pci_cfgregwrite(0, 0, sc->mctrl[i], 3,
 		    AGP_AMD64_APBASE, apbase, 4);
 }
 
@@ -418,8 +423,8 @@
 	pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
 	    (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
 	    sc->apbase, 4);
-	pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
-	pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
+	pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
+	pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
 }
 
 static int
@@ -438,12 +443,12 @@
 		return (EINVAL);
 	}
 
-	pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
-	    (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
+	pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
+	    (pci_cfgregread(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
 	    0xfffffff0) | apsize, 4);
-	pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
+	pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
 	    sc->apbase + aperture - 1, 4);
-	pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
+	pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
 	    sc->apbase + aperture - 1, 4);
 
 	return (0);
@@ -455,9 +460,9 @@
 	struct agp_amd64_softc *sc = device_get_softc(dev);
 
 	agp_amd64_apbase_fixup(dev);
-	pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
-	pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
-	    pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
+	pci_cfgregwrite(0, 0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
+	pci_cfgregwrite(0, 0, 1, 0, AGP3_VIA_GARTCTRL,
+	    pci_cfgregread(0, 0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
 }
 
 static int
@@ -468,7 +473,7 @@
 	apsize = ((aperture - 1) >> 20) ^ 0xff;
 	if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
 		return (EINVAL);
-	pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
+	pci_cfgregwrite(0, 0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
 
 	return (0);
 }
diff --git a/sys/dev/amdtemp/amdtemp.c b/sys/dev/amdtemp/amdtemp.c
--- a/sys/dev/amdtemp/amdtemp.c
+++ b/sys/dev/amdtemp/amdtemp.c
@@ -434,8 +434,9 @@
 			erratum319 = 1;
 			break;
 		case 1:	/* Socket AM2+ or AM3 */
-			if ((pci_cfgregread(pci_get_bus(dev),
-			    pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) &
+			if ((pci_cfgregread(pci_get_domain(dev),
+			    pci_get_bus(dev), pci_get_slot(dev), 2,
+			    AMDTEMP_DRAM_CONF_HIGH, 2) &
 			    AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 ||
 			    (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3))
 				break;
diff --git a/sys/dev/hpt27xx/hpt27xx_os_bsd.c b/sys/dev/hpt27xx/hpt27xx_os_bsd.c
--- a/sys/dev/hpt27xx/hpt27xx_os_bsd.c
+++ b/sys/dev/hpt27xx/hpt27xx_os_bsd.c
@@ -90,19 +90,19 @@
 /* PCI space access */
 HPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)
 {
-	return (HPT_U8)pci_cfgregread(bus, dev, func, reg, 1);
+	return (HPT_U8)pci_cfgregread(0, bus, dev, func, reg, 1);
 }
 HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)
 {
-	return (HPT_U32)pci_cfgregread(bus, dev, func, reg, 4);
+	return (HPT_U32)pci_cfgregread(0, bus, dev, func, reg, 4);
 }
 void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v)
 {
-	pci_cfgregwrite(bus, dev, func, reg, v, 1);
+	pci_cfgregwrite(0, bus, dev, func, reg, v, 1);
 }
 void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v)
 {
-	pci_cfgregwrite(bus, dev, func, reg, v, 4);
+	pci_cfgregwrite(0, bus, dev, func, reg, v, 4);
 }/* PCI space access */
 
 void *os_map_pci_bar(
diff --git a/sys/dev/hpt27xx/hpt27xx_osm_bsd.c b/sys/dev/hpt27xx/hpt27xx_osm_bsd.c
--- a/sys/dev/hpt27xx/hpt27xx_osm_bsd.c
+++ b/sys/dev/hpt27xx/hpt27xx_osm_bsd.c
@@ -75,6 +75,11 @@
 	PVBUS vbus;
 	PVBUS_EXT vbus_ext;
 	
+	if (pci_get_domain(dev) != 0) {
+		device_printf(dev, "does not support PCI domains\n");
+		return (ENXIO);
+	}
+
 	KdPrint(("hpt_attach(%d/%d/%d)", pci_get_bus(dev), pci_get_slot(dev), pci_get_function(dev)));
 
 	him = hpt_match(dev, 1);
diff --git a/sys/dev/hptnr/hptnr_os_bsd.c b/sys/dev/hptnr/hptnr_os_bsd.c
--- a/sys/dev/hptnr/hptnr_os_bsd.c
+++ b/sys/dev/hptnr/hptnr_os_bsd.c
@@ -88,7 +88,7 @@
 
 HPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg)
 {
-	return (HPT_U32)pci_cfgregread(bus, dev, func, reg, 4);
+	return (HPT_U32)pci_cfgregread(0, bus, dev, func, reg, 4);
 }/* PCI space access */
 
 void *os_map_pci_bar(
diff --git a/sys/dev/hptnr/hptnr_osm_bsd.c b/sys/dev/hptnr/hptnr_osm_bsd.c
--- a/sys/dev/hptnr/hptnr_osm_bsd.c
+++ b/sys/dev/hptnr/hptnr_osm_bsd.c
@@ -77,6 +77,11 @@
 	PVBUS vbus;
 	PVBUS_EXT vbus_ext;
 	
+	if (pci_get_domain(dev) != 0) {
+		device_printf(dev, "does not support PCI domains\n");
+		return (ENXIO);
+	}
+
 	KdPrint(("hpt_attach(%d/%d/%d)", pci_get_bus(dev), pci_get_slot(dev), pci_get_function(dev)));
 
 	him = hpt_match(dev, 1);
diff --git a/sys/dev/ichwd/ichwd.c b/sys/dev/ichwd/ichwd.c
--- a/sys/dev/ichwd/ichwd.c
+++ b/sys/dev/ichwd/ichwd.c
@@ -698,12 +698,12 @@
 		 * Space via the bridge's BAR.
 		 * Then hide back the bridge.
 		 */
-		pci_cfgregwrite(0, 31, 1, 0xe1, 0, 1);
-		base_address64 = pci_cfgregread(0, 31, 1, SBREG_BAR + 4, 4);
+		pci_cfgregwrite(0, 0, 31, 1, 0xe1, 0, 1);
+		base_address64 = pci_cfgregread(0, 0, 31, 1, SBREG_BAR + 4, 4);
 		base_address64 <<= 32;
-		base_address64 |= pci_cfgregread(0, 31, 1, SBREG_BAR, 4);
+		base_address64 |= pci_cfgregread(0, 0, 31, 1, SBREG_BAR, 4);
 		base_address64 &= ~0xfull;
-		pci_cfgregwrite(0, 31, 1, 0xe1, 1, 1);
+		pci_cfgregwrite(0, 0, 31, 1, 0xe1, 1, 1);
 
 		/*
 		 * No Reboot bit is in General Control register, offset 0xc,
diff --git a/sys/dev/ipmi/ipmi_isa.c b/sys/dev/ipmi/ipmi_isa.c
--- a/sys/dev/ipmi/ipmi_isa.c
+++ b/sys/dev/ipmi/ipmi_isa.c
@@ -66,7 +66,7 @@
 		 * create an isa ipmi device.  For now we hardcode the list
 		 * of bus, device, function tuples.
 		 */
-		devid = pci_cfgregread(0, 4, 2, PCIR_DEVVENDOR, 4);
+		devid = pci_cfgregread(0, 0, 4, 2, PCIR_DEVVENDOR, 4);
 		if (devid != 0xffffffff &&
 		    ipmi_pci_match(devid & 0xffff, devid >> 16) != NULL)
 			return;
diff --git a/sys/dev/pci/pci_subr.c b/sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c
+++ b/sys/dev/pci/pci_subr.c
@@ -53,7 +53,7 @@
 {
 	uint32_t id;
 
-	id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
+	id = read_config(0, bus, slot, func, PCIR_DEVVENDOR, 4);
 	if (id == 0xffffffff)
 		return (0);
 
@@ -61,12 +61,12 @@
 	case 0x12258086:
 		/* Intel 824?? */
 		/* XXX This is a guess */
-		/* *busnum = read_config(bus, slot, func, 0x41, 1); */
+		/* *busnum = read_config(0, bus, slot, func, 0x41, 1); */
 		*busnum = bus;
 		break;
 	case 0x84c48086:
 		/* Intel 82454KX/GX (Orion) */
-		*busnum = read_config(bus, slot, func, 0x4a, 1);
+		*busnum = read_config(0, bus, slot, func, 0x4a, 1);
 		break;
 	case 0x84ca8086:
 		/*
@@ -85,19 +85,19 @@
 		switch (slot) {
 		case 0x12:
 			/* Intel 82454NX PXB#0, Bus#A */
-			*busnum = read_config(bus, 0x10, func, 0xd0, 1);
+			*busnum = read_config(0, bus, 0x10, func, 0xd0, 1);
 			break;
 		case 0x13:
 			/* Intel 82454NX PXB#0, Bus#B */
-			*busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
+			*busnum = read_config(0, bus, 0x10, func, 0xd1, 1) + 1;
 			break;
 		case 0x14:
 			/* Intel 82454NX PXB#1, Bus#A */
-			*busnum = read_config(bus, 0x10, func, 0xd3, 1);
+			*busnum = read_config(0, bus, 0x10, func, 0xd3, 1);
 			break;
 		case 0x15:
 			/* Intel 82454NX PXB#1, Bus#B */
-			*busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
+			*busnum = read_config(0, bus, 0x10, func, 0xd4, 1) + 1;
 			break;
 		}
 		break;
@@ -116,12 +116,12 @@
 	case 0x02011166:
 	case 0x02251166:
 	case 0x03021014:
-		*busnum = read_config(bus, slot, func, 0x44, 1);
+		*busnum = read_config(0, bus, slot, func, 0x44, 1);
 		break;
 
 		/* Compaq/HP -- vendor 0x0e11 */
 	case 0x60100e11:
-		*busnum = read_config(bus, slot, func, 0xc8, 1);
+		*busnum = read_config(0, bus, slot, func, 0xc8, 1);
 		break;
 	default:
 		/* Don't know how to read bus number. */
diff --git a/sys/dev/pci/pcib_private.h b/sys/dev/pci/pcib_private.h
--- a/sys/dev/pci/pcib_private.h
+++ b/sys/dev/pci/pcib_private.h
@@ -148,7 +148,8 @@
 
 #define	PCIB_SUPPORTED_ARI_VER	1
 
-typedef uint32_t pci_read_config_fn(int b, int s, int f, int reg, int width);
+typedef uint32_t pci_read_config_fn(int d, int b, int s, int f, int reg,
+    int width);
 
 int		host_pcib_get_busno(pci_read_config_fn read_config, int bus,
     int slot, int func, uint8_t *busnum);
diff --git a/sys/i386/pci/pci_cfgreg.c b/sys/i386/pci/pci_cfgreg.c
--- a/sys/i386/pci/pci_cfgreg.c
+++ b/sys/i386/pci/pci_cfgreg.c
@@ -74,15 +74,15 @@
 SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
     "Enable support for PCI-e memory mapped config access");
 
-static uint32_t	pci_docfgregread(int bus, int slot, int func, int reg,
-		    int bytes);
+static uint32_t	pci_docfgregread(int domain, int bus, int slot, int func,
+		    int reg, int bytes);
 static int	pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
 static void	pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
 static int	pcireg_cfgopen(void);
-static int	pciereg_cfgread(int bus, unsigned slot, unsigned func,
-		    unsigned reg, unsigned bytes);
-static void	pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
-		    unsigned reg, int data, unsigned bytes);
+static int	pciereg_cfgread(int domain, int bus, unsigned slot,
+		    unsigned func, unsigned reg, unsigned bytes);
+static void	pciereg_cfgwrite(int domain, int bus, unsigned slot,
+		    unsigned func, unsigned reg, int data, unsigned bytes);
 
 /*
  * Some BIOS writers seem to want to ignore the spec and put
@@ -150,22 +150,25 @@
 }
 
 static uint32_t
-pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
+pci_docfgregread(int domain, int bus, int slot, int func, int reg, int bytes)
 {
+	if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0)
+		return (pcireg_cfgread(bus, slot, func, reg, bytes));
 
 	if (cfgmech == CFGMECH_PCIE &&
-	    (bus >= pcie_minbus && bus <= pcie_maxbus) &&
-	    (bus != 0 || !(1 << slot & pcie_badslots)))
-		return (pciereg_cfgread(bus, slot, func, reg, bytes));
-	else
+	    (bus >= pcie_minbus && bus <= pcie_maxbus))
+		return (pciereg_cfgread(domain, bus, slot, func, reg, bytes));
+	else if (domain == 0)
 		return (pcireg_cfgread(bus, slot, func, reg, bytes));
+	else
+		return (-1);
 }
 
 /* 
  * Read configuration space register
  */
 u_int32_t
-pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
+pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes)
 {
 	uint32_t line;
 
@@ -175,24 +178,29 @@
 	 * the code uses 255 as an invalid IRQ.
 	 */
 	if (reg == PCIR_INTLINE && bytes == 1) {
-		line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
+		line = pci_docfgregread(domain, bus, slot, func, PCIR_INTLINE,
+		    1);
 		return (pci_i386_map_intline(line));
 	}
-	return (pci_docfgregread(bus, slot, func, reg, bytes));
+	return (pci_docfgregread(domain, bus, slot, func, reg, bytes));
 }
 
 /* 
  * Write configuration space register 
  */
 void
-pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
+pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data,
+    int bytes)
 {
+	if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0) {
+		pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
+		return;
+	}
 
 	if (cfgmech == CFGMECH_PCIE &&
-	    (bus >= pcie_minbus && bus <= pcie_maxbus) &&
-	    (bus != 0 || !(1 << slot & pcie_badslots)))
-		pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
-	else
+	    (bus >= pcie_minbus && bus <= pcie_maxbus))
+		pciereg_cfgwrite(domain, bus, slot, func, reg, data, bytes);
+	else if (domain == 0)
 		pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
 }
 
@@ -505,7 +513,7 @@
 			if (val1 == 0xffffffff)
 				continue;
 
-			val2 = pciereg_cfgread(0, slot, 0, 0, 4);
+			val2 = pciereg_cfgread(0, 0, slot, 0, 0, 4);
 			if (val2 != val1)
 				pcie_badslots |= (1 << slot);
 		}
@@ -569,14 +577,14 @@
  */
 
 static int
-pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
+pciereg_cfgread(int domain, int bus, unsigned slot, unsigned func, unsigned reg,
     unsigned bytes)
 {
 	vm_offset_t va;
 	int data = -1;
 
-	if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
-	    func > PCI_FUNCMAX || reg > PCIE_REGMAX)
+	if (domain != 0 || bus < pcie_minbus || bus > pcie_maxbus ||
+	    slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
 		return (-1);
 
 	critical_enter();
@@ -602,13 +610,13 @@
 }
 
 static void
-pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
-    unsigned bytes)
+pciereg_cfgwrite(int domain, int bus, unsigned slot, unsigned func,
+    unsigned reg, int data, unsigned bytes)
 {
 	vm_offset_t va;
 
-	if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
-	    func > PCI_FUNCMAX || reg > PCIE_REGMAX)
+	if (domain != 0 || bus < pcie_minbus || bus > pcie_maxbus ||
+	    slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
 		return;
 
 	critical_enter();
diff --git a/sys/i386/pci/pci_pir.c b/sys/i386/pci/pci_pir.c
--- a/sys/i386/pci/pci_pir.c
+++ b/sys/i386/pci/pci_pir.c
@@ -264,10 +264,10 @@
 	uint8_t func, maxfunc;
 
 	/* See if we have a valid device at function 0. */
-	value = pci_cfgregread(bus, device, 0, PCIR_VENDOR, 2);
+	value = pci_cfgregread(0, bus, device, 0, PCIR_VENDOR, 2);
 	if (value == PCIV_INVALID)
 		return (PCI_INVALID_IRQ);
-	value = pci_cfgregread(bus, device, 0, PCIR_HDRTYPE, 1);
+	value = pci_cfgregread(0, bus, device, 0, PCIR_HDRTYPE, 1);
 	if ((value & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
 		return (PCI_INVALID_IRQ);
 	if (value & PCIM_MFDEV)
@@ -277,10 +277,10 @@
 
 	/* Scan all possible functions at this device. */
 	for (func = 0; func <= maxfunc; func++) {
-		value = pci_cfgregread(bus, device, func, PCIR_VENDOR, 2);
+		value = pci_cfgregread(0, bus, device, func, PCIR_VENDOR, 2);
 		if (value == PCIV_INVALID)
 			continue;
-		value = pci_cfgregread(bus, device, func, PCIR_INTPIN, 1);
+		value = pci_cfgregread(0, bus, device, func, PCIR_INTPIN, 1);
 
 		/*
 		 * See if it uses the pin in question.  Note that the passed
@@ -289,7 +289,7 @@
 		 */
 		if (value != pin + 1)
 			continue;
-		value = pci_cfgregread(bus, device, func, PCIR_INTLINE, 1);
+		value = pci_cfgregread(0, bus, device, func, PCIR_INTLINE, 1);
 		if (bootverbose)
 			printf(
 		"$PIR: Found matching pin for %d.%d.INT%c at func %d: %d\n",
diff --git a/sys/x86/include/pci_cfgreg.h b/sys/x86/include/pci_cfgreg.h
--- a/sys/x86/include/pci_cfgreg.h
+++ b/sys/x86/include/pci_cfgreg.h
@@ -58,8 +58,8 @@
 rman_res_t	hostb_alloc_start(int type, rman_res_t start, rman_res_t end, rman_res_t count);
 int		pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus);
 int		pci_cfgregopen(void);
-u_int32_t	pci_cfgregread(int bus, int slot, int func, int reg, int bytes);
-void		pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes);
+u_int32_t	pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes);
+void		pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, u_int32_t data, int bytes);
 #ifdef __HAVE_PIR
 void		pci_pir_open(void);
 int		pci_pir_probe(int bus, int require_parse);
diff --git a/sys/x86/iommu/intel_drv.c b/sys/x86/iommu/intel_drv.c
--- a/sys/x86/iommu/intel_drv.c
+++ b/sys/x86/iommu/intel_drv.c
@@ -969,7 +969,7 @@
 		dev = pci_find_dbsf(segment, busno, path->Device,
 		    path->Function);
 		if (i != path_len - 1) {
-			busno = pci_cfgregread(busno, path->Device,
+			busno = pci_cfgregread(segment, busno, path->Device,
 			    path->Function, PCIR_SECBUS_1, 1);
 			path++;
 		}
diff --git a/sys/x86/pci/pci_bus.c b/sys/x86/pci/pci_bus.c
--- a/sys/x86/pci/pci_bus.c
+++ b/sys/x86/pci/pci_bus.c
@@ -63,7 +63,7 @@
 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
 			u_int reg, int bytes)
 {
-	return(pci_cfgregread(bus, slot, func, reg, bytes));
+	return(pci_cfgregread(0, bus, slot, func, reg, bytes));
 }
 
 /* write configuration space register */
@@ -72,7 +72,7 @@
 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
 			 u_int reg, uint32_t data, int bytes)
 {
-	pci_cfgregwrite(bus, slot, func, reg, data, bytes);
+	pci_cfgregwrite(0, bus, slot, func, reg, data, bytes);
 }
 
 /* route interrupt */
diff --git a/sys/x86/pci/pci_early_quirks.c b/sys/x86/pci/pci_early_quirks.c
--- a/sys/x86/pci/pci_early_quirks.c
+++ b/sys/x86/pci/pci_early_quirks.c
@@ -67,36 +67,36 @@
  * Intel early quirks functions
  */
 static vm_paddr_t
-intel_stolen_base_gen3(int bus, int slot, int func)
+intel_stolen_base_gen3(int domain, int bus, int slot, int func)
 {
 	uint32_t ctrl;
 	vm_paddr_t val;
 
-	ctrl = pci_cfgregread(bus, slot, func, INTEL_BSM, 4);
+	ctrl = pci_cfgregread(domain, bus, slot, func, INTEL_BSM, 4);
 	val = ctrl & INTEL_BSM_MASK;
 	return (val);
 }
 
 static vm_paddr_t
-intel_stolen_base_gen11(int bus, int slot, int func)
+intel_stolen_base_gen11(int domain, int bus, int slot, int func)
 {
 	uint32_t ctrl;
 	vm_paddr_t val;
 
-	ctrl = pci_cfgregread(bus, slot, func, INTEL_GEN11_BSM_DW0, 4);
+	ctrl = pci_cfgregread(domain, bus, slot, func, INTEL_GEN11_BSM_DW0, 4);
 	val = ctrl & INTEL_BSM_MASK;
 	val |= (uint64_t)pci_cfgregread(
-	    bus, slot, func, INTEL_GEN11_BSM_DW1, 4) << 32;
+	    domain, bus, slot, func, INTEL_GEN11_BSM_DW1, 4) << 32;
 	return (val);
 }
 
 static vm_paddr_t
-intel_stolen_size_gen3(int bus, int slot, int func)
+intel_stolen_size_gen3(int domain, int bus, int slot, int func)
 {
 	uint32_t ctrl;
 	vm_paddr_t val;
 
-	ctrl = pci_cfgregread(0, 0, 0, I830_GMCH_CTRL, 2);
+	ctrl = pci_cfgregread(0, 0, 0, 0, I830_GMCH_CTRL, 2);
 	val = ctrl & I855_GMCH_GMS_MASK;
 
 	switch (val) {
@@ -131,34 +131,34 @@
 }
 
 static vm_paddr_t
-intel_stolen_size_gen6(int bus, int slot, int func)
+intel_stolen_size_gen6(int domain, int bus, int slot, int func)
 {
 	uint32_t ctrl;
 	vm_paddr_t val;
 
-	ctrl = pci_cfgregread(bus, slot, func, SNB_GMCH_CTRL, 2);
+	ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);
 	val = (ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
 	return (val * MiB(32));
 }
 
 static vm_paddr_t
-intel_stolen_size_gen8(int bus, int slot, int func)
+intel_stolen_size_gen8(int domain, int bus, int slot, int func)
 {
 	uint32_t ctrl;
 	vm_paddr_t val;
 
-	ctrl = pci_cfgregread(bus, slot, func, SNB_GMCH_CTRL, 2);
+	ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);
 	val = (ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
 	return (val * MiB(32));
 }
 
 static vm_paddr_t
-intel_stolen_size_chv(int bus, int slot, int func)
+intel_stolen_size_chv(int domain, int bus, int slot, int func)
 {
 	uint32_t ctrl;
 	vm_paddr_t val;
 
-	ctrl = pci_cfgregread(bus, slot, func, SNB_GMCH_CTRL, 2);
+	ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);
 	val = (ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
 
 	/*
@@ -175,12 +175,12 @@
 }
 
 static vm_paddr_t
-intel_stolen_size_gen9(int bus, int slot, int func)
+intel_stolen_size_gen9(int domain, int bus, int slot, int func)
 {
 	uint32_t ctrl;
 	vm_paddr_t val;
 
-	ctrl = pci_cfgregread(bus, slot, func, SNB_GMCH_CTRL, 2);
+	ctrl = pci_cfgregread(domain, bus, slot, func, SNB_GMCH_CTRL, 2);
 	val = (ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
 
 	/* 0x0  to 0xEF: 32MB increments starting at 0MB */
@@ -191,8 +191,8 @@
 }
 
 struct intel_stolen_ops {
-	vm_paddr_t (*base)(int bus, int slot, int func);
-	vm_paddr_t (*size)(int bus, int slot, int func);
+	vm_paddr_t (*base)(int domain, int bus, int slot, int func);
+	vm_paddr_t (*size)(int domain, int bus, int slot, int func);
 };
 
 static const struct intel_stolen_ops intel_stolen_ops_gen3 = {
@@ -277,7 +277,8 @@
 	uint32_t vendor, device, class;
 	int i;
 
-	/* XXX: Scan bus instead of assuming 0:2:0? */
+	/* XXX: Scan bus instead of assuming 0:0:2:0? */
+	const int domain = 0;
 	const int bus = 0;
 	const int slot = 2;
 	const int func = 0;
@@ -285,15 +286,15 @@
 	if (pci_cfgregopen() == 0)
 		return;
 
-	vendor = pci_cfgregread(bus, slot, func, PCIR_VENDOR, 2);
+	vendor = pci_cfgregread(domain, bus, slot, func, PCIR_VENDOR, 2);
 	if (vendor != PCI_VENDOR_INTEL)
 		return;
 
-	class = pci_cfgregread(bus, slot, func, PCIR_SUBCLASS, 2);
+	class = pci_cfgregread(domain, bus, slot, func, PCIR_SUBCLASS, 2);
 	if (class != PCI_CLASS_VGA)
 		return;
 
-	device = pci_cfgregread(bus, slot, func, PCIR_DEVICE, 2);
+	device = pci_cfgregread(domain, bus, slot, func, PCIR_DEVICE, 2);
 	if (device == 0xFFFF)
 		return;
 
@@ -301,8 +302,8 @@
 		if (intel_ids[i].device != device)
 			continue;
 		ops = intel_ids[i].data;
-		intel_graphics_stolen_base = ops->base(bus, slot, func);
-		intel_graphics_stolen_size = ops->size(bus, slot, func);
+		intel_graphics_stolen_base = ops->base(domain, bus, slot, func);
+		intel_graphics_stolen_size = ops->size(domain, bus, slot, func);
 		break;
 	}
 
diff --git a/sys/x86/pci/qpi.c b/sys/x86/pci/qpi.c
--- a/sys/x86/pci/qpi.c
+++ b/sys/x86/pci/qpi.c
@@ -117,7 +117,7 @@
 	 * the bus is not present.
 	 */
 	for (s = 0; s <= PCI_SLOTMAX; s++) {
-		devid = pci_cfgregread(bus, s, 0, PCIR_DEVVENDOR, 4);
+		devid = pci_cfgregread(0, bus, s, 0, PCIR_DEVVENDOR, 4);
 		if (devid != 0xffffffff)
 			break;
 	}
diff --git a/sys/x86/x86/legacy.c b/sys/x86/x86/legacy.c
--- a/sys/x86/x86/legacy.c
+++ b/sys/x86/x86/legacy.c
@@ -124,22 +124,22 @@
 		return;
 
 	/* Check for supported chipsets */
-	vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
-	did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
+	vid = pci_cfgregread(0, 0, 0, 0, PCIR_VENDOR, 2);
+	did = pci_cfgregread(0, 0, 0, 0, PCIR_DEVICE, 2);
 	switch (vid) {
 	case 0x8086:
 		switch (did) {
 		case 0x3590:
 		case 0x3592:
 			/* Intel 7520 or 7320 */
-			pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
+			pciebar = pci_cfgregread(0, 0, 0, 0, 0xce, 2) << 16;
 			pcie_cfgregopen(pciebar, 0, 255);
 			break;
 		case 0x2580:
 		case 0x2584:
 		case 0x2590:
 			/* Intel 915, 925, or 915GM */
-			pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
+			pciebar = pci_cfgregread(0, 0, 0, 0, 0x48, 4);
 			pcie_cfgregopen(pciebar, 0, 255);
 			break;
 		}