diff --git a/sys/dev/ic/ns16550.h b/sys/dev/ic/ns16550.h
--- a/sys/dev/ic/ns16550.h
+++ b/sys/dev/ic/ns16550.h
@@ -162,9 +162,6 @@
 #define	FIFO_XMT_RST	FCR_XMT_RST
 #define	FCR_DMA		0x08
 #define	FIFO_DMA_MODE	FCR_DMA
-#ifdef CPU_XBURST
-#define	FCR_UART_ON	0x10
-#endif
 #define	FCR_RX_LOW	0x00
 #define	FIFO_RX_LOW	FCR_RX_LOW
 #define	FCR_RX_MEDL	0x40
diff --git a/sys/dev/uart/uart_dev_ns8250.c b/sys/dev/uart/uart_dev_ns8250.c
--- a/sys/dev/uart/uart_dev_ns8250.c
+++ b/sys/dev/uart/uart_dev_ns8250.c
@@ -233,9 +233,6 @@
 	int drain = 0;
 
 	fcr = FCR_ENABLE;
-#ifdef CPU_XBURST
-	fcr |= FCR_UART_ON;
-#endif
 	if (what & UART_FLUSH_TRANSMITTER)
 		fcr |= FCR_XMT_RST;
 	if (what & UART_FLUSH_RECEIVER)
@@ -327,10 +324,6 @@
 {
 	u_char val;
 
-#ifdef CPU_XBURST
-	uart_setreg(bas, REG_FCR, FCR_UART_ON);
-#endif
-
 	/* Check known 0 bits that don't depend on DLAB. */
 	val = uart_getreg(bas, REG_IIR);
 	if (val & 0x30)
@@ -352,7 +345,7 @@
 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
     int parity)
 {
-	u_char ier, val;
+	u_char ier;
 
 	if (bas->rclk == 0)
 		bas->rclk = DEFAULT_RCLK;
@@ -369,11 +362,7 @@
 	uart_barrier(bas);
 
 	/* Disable the FIFO (if present). */
-	val = 0;
-#ifdef CPU_XBURST
-	val |= FCR_UART_ON;
-#endif
-	uart_setreg(bas, REG_FCR, val);
+	uart_setreg(bas, REG_FCR, 0);
 	uart_barrier(bas);
 
 	/* Set RTS & DTR. */
@@ -552,9 +541,6 @@
 	ns8250->busy_detect = bas->busy_detect;
 	ns8250->mcr = uart_getreg(bas, REG_MCR);
 	ns8250->fcr = FCR_ENABLE;
-#ifdef CPU_XBURST
-	ns8250->fcr |= FCR_UART_ON;
-#endif
 	if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
 	    &ivar)) {
 		if (UART_FLAGS_FCR_RX_LOW(ivar))
@@ -847,7 +833,6 @@
 	struct uart_bas *bas;
 	int count, delay, error, limit;
 	uint8_t lsr, mcr, ier;
-	uint8_t val;
 
 	bas = &sc->sc_bas;
 
@@ -880,11 +865,7 @@
 	 * done. Since this is the first time we enable the FIFOs, we reset
 	 * them.
 	 */
-	val = FCR_ENABLE;
-#ifdef CPU_XBURST
-	val |= FCR_UART_ON;
-#endif
-	uart_setreg(bas, REG_FCR, val);
+	uart_setreg(bas, REG_FCR, FCR_ENABLE);
 	uart_barrier(bas);
 	if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
 		/*
@@ -898,11 +879,7 @@
 		return (0);
 	}
 
-	val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST;
-#ifdef CPU_XBURST
-	val |= FCR_UART_ON;
-#endif
-	uart_setreg(bas, REG_FCR, val);
+	uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
 	uart_barrier(bas);
 
 	count = 0;
@@ -912,11 +889,7 @@
 	error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
 	if (error) {
 		uart_setreg(bas, REG_MCR, mcr);
-		val = 0;
-#ifdef CPU_XBURST
-		val |= FCR_UART_ON;
-#endif
-		uart_setreg(bas, REG_FCR, val);
+		uart_setreg(bas, REG_FCR, 0);
 		uart_barrier(bas);
 		goto describe;
 	}
@@ -947,11 +920,7 @@
 			ier = uart_getreg(bas, REG_IER) & 0xe0;
 			uart_setreg(bas, REG_IER, ier);
 			uart_setreg(bas, REG_MCR, mcr);
-			val = 0;
-#ifdef CPU_XBURST
-			val |= FCR_UART_ON;
-#endif
-			uart_setreg(bas, REG_FCR, val);
+			uart_setreg(bas, REG_FCR, 0);
 			uart_barrier(bas);
 			count = 0;
 			goto describe;