Index: sys/arm/mv/armada38x/armada38x.c
===================================================================
--- sys/arm/mv/armada38x/armada38x.c
+++ sys/arm/mv/armada38x/armada38x.c
@@ -39,6 +39,7 @@
 #include <arm/mv/mvvar.h>
 
 int armada38x_win_set_iosync_barrier(void);
+int armada38x_scu_enable(void);
 
 uint32_t
 get_tclk(void)
@@ -100,3 +101,30 @@
 
 	return (rv);
 }
+
+int
+armada38x_scu_enable(void)
+{
+	bus_space_handle_t vaddr_scu;
+	int rv;
+	uint32_t val;
+
+	rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE,
+	    MV_SCU_REGS_LEN, 0, &vaddr_scu);
+	if (rv)
+		return (rv);
+
+	/* ARM errata 764369 */
+	val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, 0x30);
+	if (!(val & 1))
+		bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0x30, val | 1);
+
+	/* Enable SCU */
+	val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CTRL);
+	if (!(val & MV_SCU_ENABLE))
+		bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0,
+		    val | MV_SCU_ENABLE);
+
+	bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);
+	return (0);
+}
Index: sys/arm/mv/mv_machdep.c
===================================================================
--- sys/arm/mv/mv_machdep.c
+++ sys/arm/mv/mv_machdep.c
@@ -68,6 +68,7 @@
 #endif
 #if defined(SOC_MV_ARMADA38X)
 int armada38x_win_set_iosync_barrier(void);
+int armada38x_scu_enable(void);
 #endif
 
 #define MPP_PIN_MAX		68
@@ -257,6 +258,8 @@
 	/* Set IO Sync Barrier bit for all Mbus devices */
 	if (armada38x_win_set_iosync_barrier() != 0)
 		printf("WARNING: could not map CPU Subsystem registers\n");
+	if (armada38x_scu_enable() != 0)
+		printf("WARNING: could not enable SCU\n");
 #endif
 }
 
Index: sys/arm/mv/mvreg.h
===================================================================
--- sys/arm/mv/mvreg.h
+++ sys/arm/mv/mvreg.h
@@ -34,6 +34,8 @@
 #ifndef _MVREG_H_
 #define _MVREG_H_
 
+#include <arm/mv/mvwin.h>
+
 #if defined(SOC_MV_DISCOVERY)
 #define IRQ_CAUSE_ERROR		0x0
 #define IRQ_CAUSE		0x4
@@ -452,4 +454,15 @@
 #define MV_DRBL_MASK(d,u)	(0x10 * (u) + 0x8 * (d) + 0x4)
 #define MV_DRBL_MSG(m,d,u)	(0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30)
 #endif
+
+/*
+ * SCU
+ */
+#if defined(SOC_MV_ARMADA38X)
+#define	MV_SCU_BASE		(MV_BASE + 0xc000)
+#define	MV_SCU_REGS_LEN		0x100
+#define	MV_SCU_REG_CTRL		0
+#define	MV_SCU_ENABLE		1
+#endif
+
 #endif /* _MVREG_H_ */