diff --git a/sys/arm/freescale/imx/files.imx5 b/sys/arm/freescale/imx/files.imx5 deleted file mode 100644 --- a/sys/arm/freescale/imx/files.imx5 +++ /dev/null @@ -1,54 +0,0 @@ - -# Init -arm/freescale/imx/imx_machdep.c standard -arm/freescale/imx/imx51_machdep.c optional soc_imx51 -arm/freescale/imx/imx53_machdep.c optional soc_imx53 - -# Special serial console for debuging early boot code -#arm/freescale/imx/imx_console.c standard - -# UART driver (includes serial console support) -dev/uart/uart_dev_imx.c optional uart - -# TrustZone Interrupt Controller -arm/freescale/imx/tzic.c standard - -# IOMUX - external pins multiplexor -arm/freescale/imx/imx_iomux.c standard - -# GPIO -arm/freescale/imx/imx_gpio.c optional gpio - -# Generic Periodic Timer -arm/freescale/imx/imx_gpt.c standard - -# Clock Configuration Manager -arm/freescale/imx/imx51_ccm.c standard - -# i.MX5xx PATA controller -dev/ata/chipsets/ata-fsl.c optional imxata - -# SDHCI/MMC -dev/sdhci/fsl_sdhci.c optional sdhci - -# USB OH3 controller (1 OTG, 3 EHCI) -arm/freescale/imx/imx_nop_usbphy.c optional ehci -dev/usb/controller/ehci_imx.c optional ehci - -# Watchdog -arm/freescale/imx/imx_wdog.c optional imxwdt - -# i2c -arm/freescale/imx/imx_i2c.c optional fsliic - -# IPU - Image Processing Unit (frame buffer also) -arm/freescale/imx/imx51_ipuv3.c optional sc -arm/freescale/imx/imx51_ipuv3_fbd.c optional vt -dev/vt/hw/fb/vt_early_fb.c optional vt - -# Fast Ethernet Controller -dev/ffec/if_ffec.c optional ffec - -# SPI -arm/freescale/imx/imx_spi.c optional imx_spi - diff --git a/sys/arm/freescale/imx/imx51_ccm.c b/sys/arm/freescale/imx/imx51_ccm.c deleted file mode 100644 --- a/sys/arm/freescale/imx/imx51_ccm.c +++ /dev/null @@ -1,656 +0,0 @@ -/* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved. - * Written by Hashimoto Kenichi for Genetec Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Clock Controller Module (CCM) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#define IMXCCMDEBUG -#undef IMXCCMDEBUG - -#ifndef IMX51_OSC_FREQ -#define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */ -#endif - -#ifndef IMX51_CKIL_FREQ -#define IMX51_CKIL_FREQ 32768 -#endif - -/* - * The fdt data does not provide reg properties describing the DPLL register - * blocks we need to access, presumably because the needed addresses are - * hard-coded within the linux driver. That leaves us with no choice but to do - * the same thing, if we want to run with vendor-supplied fdt data. So here we - * have tables of the physical addresses we need for each soc, and we'll use - * bus_space_map() at attach() time to get access to them. - */ -static uint32_t imx51_dpll_addrs[IMX51_N_DPLLS] = { - 0x83f80000, /* DPLL1 */ - 0x83f84000, /* DPLL2 */ - 0x83f88000, /* DPLL3 */ -}; - -static uint32_t imx53_dpll_addrs[IMX51_N_DPLLS] = { - 0x63f80000, /* DPLL1 */ - 0x63f84000, /* DPLL2 */ - 0x63f88000, /* DPLL3 */ -}; - -#define DPLL_REGS_SZ (16 * 1024) - -struct imxccm_softc { - device_t sc_dev; - struct resource *ccmregs; - u_int64_t pll_freq[IMX51_N_DPLLS]; - bus_space_tag_t pllbst; - bus_space_handle_t pllbsh[IMX51_N_DPLLS]; -}; - -struct imxccm_softc *ccm_softc = NULL; - -static uint64_t imx51_get_pll_freq(u_int); - -static int imxccm_match(device_t); -static int imxccm_attach(device_t); - -static device_method_t imxccm_methods[] = { - DEVMETHOD(device_probe, imxccm_match), - DEVMETHOD(device_attach, imxccm_attach), - - DEVMETHOD_END -}; - -static driver_t imxccm_driver = { - "imxccm", - imxccm_methods, - sizeof(struct imxccm_softc), -}; - -EARLY_DRIVER_MODULE(imxccm, simplebus, imxccm_driver, 0, 0, BUS_PASS_CPU); - -static inline uint32_t -pll_read_4(struct imxccm_softc *sc, int pll, int reg) -{ - - return (bus_space_read_4(sc->pllbst, sc->pllbsh[pll - 1], reg)); -} - -static inline uint32_t -ccm_read_4(struct imxccm_softc *sc, int reg) -{ - - return (bus_read_4(sc->ccmregs, reg)); -} - -static inline void -ccm_write_4(struct imxccm_softc *sc, int reg, uint32_t val) -{ - - bus_write_4(sc->ccmregs, reg, val); -} - -static int -imxccm_match(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (!ofw_bus_is_compatible(dev, "fsl,imx51-ccm") && - !ofw_bus_is_compatible(dev, "fsl,imx53-ccm")) - return (ENXIO); - - device_set_desc(dev, "Freescale Clock Control Module"); - return (BUS_PROBE_DEFAULT); -} - -static int -imxccm_attach(device_t dev) -{ - struct imxccm_softc *sc; - int idx; - u_int soc; - uint32_t *pll_addrs; - - sc = device_get_softc(dev); - sc->sc_dev = dev; - - switch ((soc = imx_soc_type())) { - case IMXSOC_51: - pll_addrs = imx51_dpll_addrs; - break; - case IMXSOC_53: - pll_addrs = imx53_dpll_addrs; - break; - default: - device_printf(dev, "No support for SoC type 0x%08x\n", soc); - goto noclocks; - } - - idx = 0; - sc->ccmregs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &idx, - RF_ACTIVE); - if (sc->ccmregs == NULL) { - device_printf(dev, "could not allocate resources\n"); - goto noclocks; - } - - sc->pllbst = fdtbus_bs_tag; - for (idx = 0; idx < IMX51_N_DPLLS; ++idx) { - if (bus_space_map(sc->pllbst, pll_addrs[idx], DPLL_REGS_SZ, 0, - &sc->pllbsh[idx]) != 0) { - device_printf(dev, "Cannot map DPLL registers\n"); - goto noclocks; - } - } - - ccm_softc = sc; - - imx51_get_pll_freq(1); - imx51_get_pll_freq(2); - imx51_get_pll_freq(3); - - device_printf(dev, "PLL1=%lluMHz, PLL2=%lluMHz, PLL3=%lluMHz\n", - sc->pll_freq[0] / 1000000, - sc->pll_freq[1] / 1000000, - sc->pll_freq[2] / 1000000); - device_printf(dev, "CPU clock=%d, UART clock=%d\n", - imx51_get_clock(IMX51CLK_ARM_ROOT), - imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); - device_printf(dev, - "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n", - imx51_get_clock(IMX51CLK_MAIN_BUS_CLK), - imx51_get_clock(IMX51CLK_AHB_CLK_ROOT), - imx51_get_clock(IMX51CLK_IPG_CLK_ROOT), - imx51_get_clock(IMX51CLK_PERCLK_ROOT)); - - return (0); - -noclocks: - - panic("Cannot continue without clock support"); -} - -u_int -imx51_get_clock(enum imx51_clock clk) -{ - u_int freq; - u_int sel; - uint32_t cacrr; /* ARM clock root register */ - uint32_t ccsr; - uint32_t cscdr1; - uint32_t cscmr1; - uint32_t cbcdr; - uint32_t cbcmr; - uint32_t cdcr; - - if (ccm_softc == NULL) - return (0); - - switch (clk) { - case IMX51CLK_PLL1: - case IMX51CLK_PLL2: - case IMX51CLK_PLL3: - return ccm_softc->pll_freq[clk-IMX51CLK_PLL1]; - case IMX51CLK_PLL1SW: - ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); - if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0) - return ccm_softc->pll_freq[1-1]; - /* step clock */ - /* FALLTHROUGH */ - case IMX51CLK_PLL1STEP: - ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); - switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) { - case 0: - return imx51_get_clock(IMX51CLK_LP_APM); - case 1: - return 0; /* XXX PLL bypass clock */ - case 2: - return ccm_softc->pll_freq[2-1] / - (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >> - CCSR_PLL2_DIV_PODF_SHIFT)); - case 3: - return ccm_softc->pll_freq[3-1] / - (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >> - CCSR_PLL3_DIV_PODF_SHIFT)); - } - /*NOTREACHED*/ - case IMX51CLK_PLL2SW: - ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); - if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0) - return imx51_get_clock(IMX51CLK_PLL2); - return 0; /* XXX PLL2 bypass clk */ - case IMX51CLK_PLL3SW: - ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); - if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0) - return imx51_get_clock(IMX51CLK_PLL3); - return 0; /* XXX PLL3 bypass clk */ - - case IMX51CLK_LP_APM: - ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); - return (ccsr & CCSR_LP_APM) ? - imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ; - - case IMX51CLK_ARM_ROOT: - freq = imx51_get_clock(IMX51CLK_PLL1SW); - cacrr = ccm_read_4(ccm_softc, CCMC_CACRR); - return freq / (cacrr + 1); - - /* ... */ - case IMX51CLK_MAIN_BUS_CLK_SRC: - cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); - if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0) - freq = imx51_get_clock(IMX51CLK_PLL2SW); - else { - freq = 0; - cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); - switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >> - CBCMR_PERIPH_APM_SEL_SHIFT) { - case 0: - freq = imx51_get_clock(IMX51CLK_PLL1SW); - break; - case 1: - freq = imx51_get_clock(IMX51CLK_PLL3SW); - break; - case 2: - freq = imx51_get_clock(IMX51CLK_LP_APM); - break; - case 3: - /* XXX: error */ - break; - } - } - return freq; - case IMX51CLK_MAIN_BUS_CLK: - freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); - cdcr = ccm_read_4(ccm_softc, CCMC_CDCR); - return freq / (1 + ((cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >> - CDCR_PERIPH_CLK_DVFS_PODF_SHIFT)); - case IMX51CLK_AHB_CLK_ROOT: - freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK); - cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); - return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >> - CBCDR_AHB_PODF_SHIFT)); - case IMX51CLK_IPG_CLK_ROOT: - freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); - cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); - return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >> - CBCDR_IPG_PODF_SHIFT)); - - case IMX51CLK_PERCLK_ROOT: - cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); - if (cbcmr & CBCMR_PERCLK_IPG_SEL) - return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT); - if (cbcmr & CBCMR_PERCLK_LP_APM_SEL) - freq = imx51_get_clock(IMX51CLK_LP_APM); - else - freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); - cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); - -#ifdef IMXCCMDEBUG - printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr); -#endif - - freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >> - CBCDR_PERCLK_PRED1_SHIFT); - freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >> - CBCDR_PERCLK_PRED2_SHIFT); - freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >> - CBCDR_PERCLK_PODF_SHIFT); - return freq; - case IMX51CLK_UART_CLK_ROOT: - cscdr1 = ccm_read_4(ccm_softc, CCMC_CSCDR1); - cscmr1 = ccm_read_4(ccm_softc, CCMC_CSCMR1); - -#ifdef IMXCCMDEBUG - printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1); -#endif - - sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >> - CSCMR1_UART_CLK_SEL_SHIFT; - - freq = 0; /* shut up GCC */ - switch (sel) { - case 0: - case 1: - case 2: - freq = imx51_get_clock(IMX51CLK_PLL1SW + sel); - break; - case 3: - freq = imx51_get_clock(IMX51CLK_LP_APM); - break; - } - - return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >> - CSCDR1_UART_CLK_PRED_SHIFT)) / - (1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >> - CSCDR1_UART_CLK_PODF_SHIFT)); - case IMX51CLK_IPU_HSP_CLK_ROOT: - freq = 0; - cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); - switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >> - CBCMR_IPU_HSP_CLK_SEL_SHIFT) { - case 0: - freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK); - break; - case 1: - freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK); - break; - case 2: - freq = imx51_get_clock( - IMX51CLK_EMI_SLOW_CLK_ROOT); - break; - case 3: - freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); - break; - } - return freq; - default: - device_printf(ccm_softc->sc_dev, - "clock %d: not supported yet\n", clk); - return 0; - } -} - -static uint64_t -imx51_get_pll_freq(u_int pll_no) -{ - uint32_t dp_ctrl; - uint32_t dp_op; - uint32_t dp_mfd; - uint32_t dp_mfn; - uint32_t mfi; - int32_t mfn; - uint32_t mfd; - uint32_t pdf; - uint32_t ccr; - uint64_t freq = 0; - u_int ref = 0; - - KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS, ("Wrong PLL id")); - - dp_ctrl = pll_read_4(ccm_softc, pll_no, DPLL_DP_CTL); - - if (dp_ctrl & DP_CTL_HFSM) { - dp_op = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_OP); - dp_mfd = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_MFD); - dp_mfn = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_MFN); - } else { - dp_op = pll_read_4(ccm_softc, pll_no, DPLL_DP_OP); - dp_mfd = pll_read_4(ccm_softc, pll_no, DPLL_DP_MFD); - dp_mfn = pll_read_4(ccm_softc, pll_no, DPLL_DP_MFN); - } - - pdf = dp_op & DP_OP_PDF_MASK; - mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT); - mfd = dp_mfd; - if (dp_mfn & 0x04000000) - /* 27bit signed value */ - mfn = (uint32_t)(0xf8000000 | dp_mfn); - else - mfn = dp_mfn; - - switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) { - case DP_CTL_REF_CLK_SEL_COSC: - /* Internal Oscillator */ - /* TODO: get from FDT "fsl,imx-osc" */ - ref = 24000000; /* IMX51_OSC_FREQ */ - break; - case DP_CTL_REF_CLK_SEL_FPM: - ccr = ccm_read_4(ccm_softc, CCMC_CCR); - if (ccr & CCR_FPM_MULT) - /* TODO: get from FDT "fsl,imx-ckil" */ - ref = 32768 * 1024; - else - /* TODO: get from FDT "fsl,imx-ckil" */ - ref = 32768 * 512; - break; - default: - ref = 0; - } - - if (dp_ctrl & DP_CTL_REF_CLK_DIV) - ref /= 2; - - ref *= 4; - freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1); - freq /= pdf + 1; - - if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN)) - freq /= 2; - -#ifdef IMXCCMDEBUG - printf("ref: %dKHz ", ref); - printf("dp_ctl: %08x ", dp_ctrl); - printf("pdf: %3d ", pdf); - printf("mfi: %3d ", mfi); - printf("mfd: %3d ", mfd); - printf("mfn: %3d ", mfn); - printf("pll: %d\n", (uint32_t)freq); -#endif - - ccm_softc->pll_freq[pll_no-1] = freq; - - return (freq); -} - -void -imx51_clk_gating(int clk_src, int mode) -{ - int field, group; - uint32_t reg; - - group = CCMR_CCGR_MODULE(clk_src); - field = clk_src % CCMR_CCGR_NSOURCE; - reg = ccm_read_4(ccm_softc, CCMC_CCGR(group)); - reg &= ~(0x03 << field * 2); - reg |= (mode << field * 2); - ccm_write_4(ccm_softc, CCMC_CCGR(group), reg); -} - -int -imx51_get_clk_gating(int clk_src) -{ - uint32_t reg; - - reg = ccm_read_4(ccm_softc, - CCMC_CCGR(CCMR_CCGR_MODULE(clk_src))); - return ((reg >> (clk_src % CCMR_CCGR_NSOURCE) * 2) & 0x03); -} - -/* - * Code from here down is temporary, in lieu of a SoC-independent clock API. - */ - -void -imx_ccm_usb_enable(device_t dev) -{ - uint32_t regval; - - /* - * Select PLL2 as the source for the USB clock. - * The default is PLL3, but U-boot changes it to PLL2. - */ - regval = ccm_read_4(ccm_softc, CCMC_CSCMR1); - regval &= ~CSCMR1_USBOH3_CLK_SEL_MASK; - regval |= 1 << CSCMR1_USBOH3_CLK_SEL_SHIFT; - ccm_write_4(ccm_softc, CCMC_CSCMR1, regval); - - /* - * Set the USB clock pre-divider to div-by-5, post-divider to div-by-2. - */ - regval = ccm_read_4(ccm_softc, CCMC_CSCDR1); - regval &= ~CSCDR1_USBOH3_CLK_PODF_MASK; - regval &= ~CSCDR1_USBOH3_CLK_PRED_MASK; - regval |= 4 << CSCDR1_USBOH3_CLK_PRED_SHIFT; - regval |= 1 << CSCDR1_USBOH3_CLK_PODF_SHIFT; - ccm_write_4(ccm_softc, CCMC_CSCDR1, regval); - - /* - * The same two clocks gates are used on imx51 and imx53. - */ - imx51_clk_gating(CCGR_USBOH3_IPG_AHB_CLK, CCGR_CLK_MODE_ALWAYS); - imx51_clk_gating(CCGR_USBOH3_60M_CLK, CCGR_CLK_MODE_ALWAYS); -} - -void -imx_ccm_usbphy_enable(device_t dev) -{ - uint32_t regval; - - /* - * Select PLL3 as the source for the USBPHY clock. U-boot does this - * only for imx53, but the bit exists on imx51. That seems a bit - * strange, but we'll go with it until more is known. - */ - if (imx_soc_type() == IMXSOC_53) { - regval = ccm_read_4(ccm_softc, CCMC_CSCMR1); - regval |= 1 << CSCMR1_USBPHY_CLK_SEL_SHIFT; - ccm_write_4(ccm_softc, CCMC_CSCMR1, regval); - } - - /* - * For the imx51 there's just one phy gate control, enable it. - */ - if (imx_soc_type() == IMXSOC_51) { - imx51_clk_gating(CCGR_USB_PHY_CLK, CCGR_CLK_MODE_ALWAYS); - return; - } - - /* - * For imx53 we don't have a full set of clock defines yet, but the - * datasheet says: - * gate reg 4, bits 13-12 usb ph2 clock (usb_phy2_clk_enable) - * gate reg 4, bits 11-10 usb ph1 clock (usb_phy1_clk_enable) - * - * We should use the fdt data for the device to figure out which of - * the two we're working on, but for now just turn them both on. - */ - if (imx_soc_type() == IMXSOC_53) { - imx51_clk_gating(__CCGR_NUM(4, 5), CCGR_CLK_MODE_ALWAYS); - imx51_clk_gating(__CCGR_NUM(4, 6), CCGR_CLK_MODE_ALWAYS); - return; - } -} - -uint32_t -imx_ccm_ecspi_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_CSPI_CLK_ROOT)); -} - -uint32_t -imx_ccm_ipg_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_IPG_CLK_ROOT)); -} - -uint32_t -imx_ccm_sdhci_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT)); -} - -uint32_t -imx_ccm_perclk_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_PERCLK_ROOT)); -} - -uint32_t -imx_ccm_uart_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); -} - -uint32_t -imx_ccm_ahb_hz(void) -{ - - return (imx51_get_clock(IMX51CLK_AHB_CLK_ROOT)); -} diff --git a/sys/arm/freescale/imx/imx51_ccmreg.h b/sys/arm/freescale/imx/imx51_ccmreg.h deleted file mode 100644 --- a/sys/arm/freescale/imx/imx51_ccmreg.h +++ /dev/null @@ -1,257 +0,0 @@ -/* $NetBSD: imx51_ccmreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. - * Written by Hashimoto Kenichi for Genetec Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _IMX51_CCMREG_H -#define _IMX51_CCMREG_H - -#include - -/* register offset address */ - -#define CCMC_BASE 0x73fd4000 -#define CCMC_CCR 0x0000 -#define CCR_FPM_MULT 0x00001000 -#define CCMC_CCDR 0x0004 -#define CCMC_CSR 0x0008 -#define CCMC_CCSR 0x000c -#define CCSR_LP_APM 0x00000200 -#define CCSR_STEP_SEL_SHIFT 7 -#define CCSR_STEP_SEL_MASK 0x00000180 -#define CCSR_PLL2_DIV_PODF_SHIFT 5 -#define CCSR_PLL2_DIV_PODF_MASK 0x00000060 -#define CCSR_PLL3_DIV_PODF_SHIFT 3 -#define CCSR_PLL3_DIV_PODF_MASK 0x00000030 -#define CCSR_PLL1_SW_CLK_SEL 0x00000004 -#define CCSR_PLL2_SW_CLK_SEL 0x00000002 -#define CCSR_PLL3_SW_CLK_SEL 0x00000001 -#define CCMC_CACRR 0x0010 -#define CCMC_CBCDR 0x0014 -#define CBCDR_DDR_HIGH_FREQ_CLK_SEL 0x40000000 -#define CBCDR_DDR_CLK_PODF_SHIFT 27 -#define CBCDR_DDR_CLK_PODF_MASK 0x38000000 -#define CBCDR_EMI_CLK_SEL 0x04000000 -#define CBCDR_PERIPH_CLK_SEL 0x02000000 -#define CBCDR_EMI_SLOW_PODF_SHIFT 22 -#define CBCDR_EMI_SLOW_PODF_MASK 0x01c00000 -#define CBCDR_AXI_B_PODF_SHIFT 19 -#define CBCDR_AXI_B_PODF_MASK 0x00380000 -#define CBCDR_AXI_A_PODF_SHIFT 16 -#define CBCDR_AXI_A_PODF_MASK 0x1fff0000 -#define CBCDR_NFC_PODF_SHIFT 13 -#define CBCDR_NFC_PODF_MASK 0x00018000 -#define CBCDR_AHB_PODF_SHIFT 10 -#define CBCDR_AHB_PODF_MASK 0x00001c00 -#define CBCDR_IPG_PODF_SHIFT 8 -#define CBCDR_IPG_PODF_MASK 0x00000300 -#define CBCDR_PERCLK_PRED1_SHIFT 6 -#define CBCDR_PERCLK_PRED1_MASK 0x000000c0 -#define CBCDR_PERCLK_PRED2_SHIFT 3 -#define CBCDR_PERCLK_PRED2_MASK 0x00000038 -#define CBCDR_PERCLK_PODF_SHIFT 0 -#define CBCDR_PERCLK_PODF_MASK 0x00000007 -#define CCMC_CBCMR 0x0018 -#define CBCMR_PERIPH_APM_SEL_SHIFT 12 -#define CBCMR_PERIPH_APM_SEL_MASK 0x00003000 -#define CBCMR_IPU_HSP_CLK_SEL_SHIFT 6 -#define CBCMR_IPU_HSP_CLK_SEL_MASK 0x000000c0 -#define CBCMR_PERCLK_LP_APM_SEL 0x00000002 -#define CBCMR_PERCLK_IPG_SEL 0x00000001 -#define CCMC_CSCMR1 0x001c -#define CSCMR1_UART_CLK_SEL_SHIFT 24 -#define CSCMR1_UART_CLK_SEL_MASK 0x03000000 -#define CSCMR1_USBPHY_CLK_SEL_SHIFT 26 -#define CSCMR1_USBPHY_CLK_SEL_MASK 0x04000000 -#define CSCMR1_USBOH3_CLK_SEL_SHIFT 22 -#define CSCMR1_USBOH3_CLK_SEL_MASK 0x00c00000 -#define CCMC_CSCMR2 0x0020 -#define CCMC_CSCDR1 0x0024 -#define CSCDR1_UART_CLK_PRED_SHIFT 3 -#define CSCDR1_UART_CLK_PRED_MASK 0x00000038 -#define CSCDR1_UART_CLK_PODF_SHIFT 0 -#define CSCDR1_UART_CLK_PODF_MASK 0x00000007 -#define CSCDR1_USBOH3_CLK_PRED_SHIFT 8 -#define CSCDR1_USBOH3_CLK_PRED_MASK 0x00000700 -#define CSCDR1_USBOH3_CLK_PODF_SHIFT 6 -#define CSCDR1_USBOH3_CLK_PODF_MASK 0x000000c0 -#define CCMC_CS1CDR 0x0028 -#define CCMC_CS2CDR 0x002c -#define CCMC_CDCDR 0x0030 -#define CCMC_CSCDR2 0x0038 -#define CCMC_CSCDR3 0x003c -#define CCMC_CSCDR4 0x0040 -#define CCMC_CWDR 0x0044 -#define CCMC_CDHIPR 0x0048 -#define CCMC_CDCR 0x004c -#define CDCR_PERIPH_CLK_DVFS_PODF_SHIFT 0 -#define CDCR_PERIPH_CLK_DVFS_PODF_MASK 0x00000003 -#define CCMC_CTOR 0x0050 -#define CCMC_CLPCR 0x0054 -#define CCMC_CISR 0x0058 -#define CCMC_CIMR 0x005c -#define CCMC_CCOSR 0x0060 -#define CCMC_CGPR 0x0064 -#define CCMC_CCGR(n) (0x0068 + (n) * 4) -#define CCMC_CMEOR 0x0084 - -#define CCMC_SIZE 0x88 - -/* CCGR Clock Gate Register */ - -#define CCMR_CCGR_NSOURCE 16 -#define CCMR_CCGR_NGROUPS 7 -#define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE) -#define __CCGR_NUM(a, b) ((a) * 16 + (b)) - -#define CCGR_ARM_BUS_CLK __CCGR_NUM(0, 0) -#define CCGR_ARM_AXI_CLK __CCGR_NUM(0, 1) -#define CCGR_ARM_DEBUG_CLK __CCGR_NUM(0, 2) -#define CCGR_TZIC_CLK __CCGR_NUM(0, 3) -#define CCGR_DAP_CLK __CCGR_NUM(0, 4) -#define CCGR_TPIU_CLK __CCGR_NUM(0, 5) -#define CCGR_CTI2_CLK __CCGR_NUM(0, 6) -#define CCGR_CTI3_CLK __CCGR_NUM(0, 7) -#define CCGR_AHBMUX1_CLK __CCGR_NUM(0, 8) -#define CCGR_AHBMUX2_CLK __CCGR_NUM(0, 9) -#define CCGR_ROMCP_CLK __CCGR_NUM(0, 10) -#define CCGR_ROM_CLK __CCGR_NUM(0, 11) -#define CCGR_AIPS_TZ1_CLK __CCGR_NUM(0, 12) -#define CCGR_AIPS_TZ2_CLK __CCGR_NUM(0, 13) -#define CCGR_AHB_MAX_CLK __CCGR_NUM(0, 14) -#define CCGR_IIM_CLK __CCGR_NUM(0, 15) -#define CCGR_TMAX1_CLK __CCGR_NUM(1, 0) -#define CCGR_TMAX2_CLK __CCGR_NUM(1, 1) -#define CCGR_TMAX3_CLK __CCGR_NUM(1, 2) -#define CCGR_UART1_CLK __CCGR_NUM(1, 3) -#define CCGR_UART1_SERIAL_CLK __CCGR_NUM(1, 4) -#define CCGR_UART2_CLK __CCGR_NUM(1, 5) -#define CCGR_UART2_SERIAL_CLK __CCGR_NUM(1, 6) -#define CCGR_UART3_CLK __CCGR_NUM(1, 7) -#define CCGR_UART3_SERIAL_CLK __CCGR_NUM(1, 8) -#define CCGR_I2C1_SERIAL_CLK __CCGR_NUM(1, 9) -#define CCGR_I2C2_SERIAL_CLK __CCGR_NUM(1, 10) -#define CCGR_HSI2C_CLK __CCGR_NUM(1, 11) -#define CCGR_HSI2C_SERIAL_CLK __CCGR_NUM(1, 12) -#define CCGR_FIRI_CLK __CCGR_NUM(1, 13) -#define CCGR_FIRI_SERIAL_CLK __CCGR_NUM(1, 14) -#define CCGR_SCC_CLK __CCGR_NUM(1, 15) - -#define CCGR_USB_PHY_CLK __CCGR_NUM(2, 0) -#define CCGR_EPIT1_CLK __CCGR_NUM(2, 1) -#define CCGR_EPIT1_SERIAL_CLK __CCGR_NUM(2, 2) -#define CCGR_EPIT2_CLK __CCGR_NUM(2, 3) -#define CCGR_EPIT2_SERIAL_CLK __CCGR_NUM(2, 4) -#define CCGR_PWM1_CLK __CCGR_NUM(2, 5) -#define CCGR_PWM1_SERIAL_CLK __CCGR_NUM(2, 6) -#define CCGR_PWM2_CLK __CCGR_NUM(2, 7) -#define CCGR_PWM2_SERIAL_CLK __CCGR_NUM(2, 8) -#define CCGR_GPT_CLK __CCGR_NUM(2, 9) -#define CCGR_GPT_SERIAL_CLK __CCGR_NUM(2, 10) -#define CCGR_OWIRE_CLK __CCGR_NUM(2, 11) -#define CCGR_FEC_CLK __CCGR_NUM(2, 12) -#define CCGR_USBOH3_IPG_AHB_CLK __CCGR_NUM(2, 13) -#define CCGR_USBOH3_60M_CLK __CCGR_NUM(2, 14) -#define CCGR_TVE_CLK __CCGR_NUM(2, 15) - -#define CCGR_ESDHC1_CLK __CCGR_NUM(3, 0) -#define CCGR_ESDHC1_SERIAL_CLK __CCGR_NUM(3, 1) -#define CCGR_ESDHC2_CLK __CCGR_NUM(3, 2) -#define CCGR_ESDHC2_SERIAL_CLK __CCGR_NUM(3, 3) -#define CCGR_ESDHC3_CLK __CCGR_NUM(3, 4) -#define CCGR_ESDHC3_SERIAL_CLK __CCGR_NUM(3, 5) -#define CCGR_ESDHC4_CLK __CCGR_NUM(3, 6) -#define CCGR_ESDHC4_SERIAL_CLK __CCGR_NUM(3, 7) -#define CCGR_SSI1_CLK __CCGR_NUM(3, 8) -#define CCGR_SSI1_SERIAL_CLK __CCGR_NUM(3, 9) -#define CCGR_SSI2_CLK __CCGR_NUM(3, 10) -#define CCGR_SSI2_SERIAL_CLK __CCGR_NUM(3, 11) -#define CCGR_SSI3_CLK __CCGR_NUM(3, 12) -#define CCGR_SSI3_SERIAL_CLK __CCGR_NUM(3, 13) -#define CCGR_SSI_EXT1_CLK __CCGR_NUM(3, 14) -#define CCGR_SSI_EXT2_CLK __CCGR_NUM(3, 15) - -#define CCGR_PATA_CLK __CCGR_NUM(4, 0) -#define CCGR_SIM_CLK __CCGR_NUM(4, 1) -#define CCGR_SIM_SERIAL_CLK __CCGR_NUM(4, 2) -#define CCGR_SAHARA_CLK __CCGR_NUM(4, 3) -#define CCGR_RTIC_CLK __CCGR_NUM(4, 4) -#define CCGR_ECSPI1_CLK __CCGR_NUM(4, 5) -#define CCGR_ECSPI1_SERIAL_CLK __CCGR_NUM(4, 6) -#define CCGR_ECSPI2_CLK __CCGR_NUM(4, 7) -#define CCGR_ECSPI2_SERIAL_CLK __CCGR_NUM(4, 8) -#define CCGR_CSPI_CLK __CCGR_NUM(4, 9) -#define CCGR_SRTC_CLK __CCGR_NUM(4, 10) -#define CCGR_SDMA_CLK __CCGR_NUM(4, 11) - -#define CCGR_SPBA_CLK __CCGR_NUM(5, 0) -#define CCGR_GPU_CLK __CCGR_NUM(5, 1) -#define CCGR_GARB_CLK __CCGR_NUM(5, 2) -#define CCGR_VPU_CLK __CCGR_NUM(5, 3) -#define CCGR_VPU_SERIAL_CLK __CCGR_NUM(5, 4) -#define CCGR_IPU_CLK __CCGR_NUM(5, 5) -#define CCGR_EMI_GARB_CLK __CCGR_NUM(6, 0) -#define CCGR_IPU_DI0_CLK __CCGR_NUM(6, 1) -#define CCGR_IPU_DI1_CLK __CCGR_NUM(6, 2) -#define CCGR_GPU2D_CLK __CCGR_NUM(6, 3) -#define CCGR_SLIMBUS_CLK __CCGR_NUM(6, 4) -#define CCGR_SLIMBUS_SERIAL_CLK __CCGR_NUM(6, 5) - -#define CCGR_CLK_MODE_OFF 0 -#define CCGR_CLK_MODE_RUNMODE 1 -#define CCGR_CLK_MODE_ALWAYS 3 - -#endif /* _IMX51_CCMREG_H */ diff --git a/sys/arm/freescale/imx/imx51_ccmvar.h b/sys/arm/freescale/imx/imx51_ccmvar.h deleted file mode 100644 --- a/sys/arm/freescale/imx/imx51_ccmvar.h +++ /dev/null @@ -1,110 +0,0 @@ -/* $NetBSD: imx51_ccmvar.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2012 Genetec Corporation. All rights reserved. - * Written by Hashimoto Kenichi for Genetec Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _ARM_IMX_IMX51_CCMVAR_H_ -#define _ARM_IMX_IMX51_CCMVAR_H_ - -enum imx51_clock { - IMX51CLK_FPM, - IMX51CLK_PLL1, - IMX51CLK_PLL2, - IMX51CLK_PLL3, - IMX51CLK_PLL1SW, - IMX51CLK_PLL2SW, - IMX51CLK_PLL3SW, - IMX51CLK_PLL1STEP, - IMX51CLK_LP_APM, - IMX51CLK_ARM_ROOT, - IMX51CLK_MAIN_BUS_CLK_SRC, /* XXX */ - IMX51CLK_MAIN_BUS_CLK, - IMX51CLK_EMI_SLOW_CLK_ROOT, - IMX51CLK_ENFC_CLK_ROOT, - IMX51CLK_AHB_CLK_ROOT, - IMX51CLK_IPG_CLK_ROOT, - IMX51CLK_PERCLK_ROOT, - IMX51CLK_DDR_CLK_ROOT, - IMX51CLK_ARM_AXI_CLK_ROOT, - IMX51CLK_ARM_AXI_A_CLK, - IMX51CLK_ARM_AXI_B_CLK, - IMX51CLK_IPU_HSP_CLK_ROOT, - IMX51CLK_CKIL_SYNC_CLK_ROOT, - IMX51CLK_USBOH3_CLK_ROOT, - IMX51CLK_ESDHC1_CLK_ROOT, - IMX51CLK_ESDHC2_CLK_ROOT, - IMX51CLK_ESDHC3_CLK_ROOT, - IMX51CLK_UART_CLK_ROOT, - IMX51CLK_SSI1_CLK_ROOT, - IMX51CLK_SSI2_CLK_ROOT, - IMX51CLK_SSI_EXT1_CLK_ROOT, - IMX51CLK_SSI_EXT2_CLK_ROOT, - IMX51CLK_USB_PHY_CLK_ROOT, - IMX51CLK_TVE_216_54_CLK_ROOT, - IMX51CLK_DI_CLK_ROOT, - IMX51CLK_SPDIF0_CLK_ROOT, - IMX51CLK_SPDIF1_CLK_ROOT, - IMX51CLK_CSPI_CLK_ROOT, - IMX51CLK_WRCK_CLK_ROOT, - IMX51CLK_LPSR_CLK_ROOT, - IMX51CLK_PGC_CLK_ROOT -}; - -u_int imx51_get_clock(enum imx51_clock); -void imx51_clk_gating(int, int); -int imx51_get_clk_gating(int); - -#endif /* _ARM_IMX_IMX51_CCMVAR_H_ */ diff --git a/sys/arm/freescale/imx/imx51_dpllreg.h b/sys/arm/freescale/imx/imx51_dpllreg.h deleted file mode 100644 --- a/sys/arm/freescale/imx/imx51_dpllreg.h +++ /dev/null @@ -1,105 +0,0 @@ -/* $NetBSD: imx51_dpllreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2012 Genetec Corporation. All rights reserved. - * Written by Hashimoto Kenichi for Genetec Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _IMX51_DPLLREG_H -#define _IMX51_DPLLREG_H - -#include - -/* register offset address */ - -#define IMX51_N_DPLLS 3 /* 1..3 */ - -#define DPLL_BASE(n) (0x83F80000 + (0x4000 * ((n)-1))) -#define DPLL_SIZE 0x100 - -#define DPLL_DP_CTL 0x0000 /* 0x1223 */ -#define DP_CTL_LRF 0x00000001 -#define DP_CTL_BRM 0x00000002 -#define DP_CTL_PLM 0x00000004 -#define DP_CTL_RCP 0x00000008 -#define DP_CTL_RST 0x00000010 -#define DP_CTL_UPEN 0x00000020 -#define DP_CTL_PRE 0x00000040 -#define DP_CTL_HFSM 0x00000080 -#define DP_CTL_REF_CLK_SEL_MASK 0x00000300 -#define DP_CTL_REF_CLK_SEL_COSC 0x00000200 -#define DP_CTL_REF_CLK_SEL_FPM 0x00000300 -#define DP_CTL_REF_CLK_DIV 0x00000400 -#define DP_CTL_DPDCK0_2_EN 0x00001000 -#define DP_CTL_HIGHCLK_EN DP_CTL_DPDCK0_2_EN -#define DP_CTL_MULCTRL 0x00002000 -#define DPLL_DP_CONFIG 0x0004 /* 2 */ -#define DPLL_DP_CONFIG_APEN 0x00000002 -#define DPLL_DP_CONFIG_LDREQ 0x00000001 -#define DPLL_DP_OP 0x0008 /* 0x80 */ -#define DP_OP_PDF_SHIFT 0 -#define DP_OP_PDF_MASK (0xf << DP_OP_PDF_SHIFT) -#define DP_OP_MFI_SHIFT 4 -#define DP_OP_MFI_MASK (0xf << DP_OP_MFI_SHIFT) -#define DPLL_DP_MFD 0x000C /* 2 */ -#define DPLL_DP_MFN 0x0010 /* 1 */ -#define DPLL_DP_MFNMINUS 0x0014 /* 0 */ -#define DPLL_DP_MFNPLUS 0x0018 /* 0 */ -#define DPLL_DP_HFS_OP 0x001C /* 0x80 */ -#define DPLL_DP_HFS_MFD 0x0020 /* 2 */ -#define DPLL_DP_HFS_MFN 0x0024 /* 1 */ -#define DPLL_DP_TOGC 0x0028 /* 0x20000 */ -#define DPLL_DP_DESTAT 0x002C /* 1 */ - -#endif /* _IMX51_DPLLREG_H */ diff --git a/sys/arm/freescale/imx/imx51_ipuv3.c b/sys/arm/freescale/imx/imx51_ipuv3.c deleted file mode 100644 --- a/sys/arm/freescale/imx/imx51_ipuv3.c +++ /dev/null @@ -1,872 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2012 Oleksandr Tymoshenko - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include - -#include - -#define IMX51_IPU_HSP_CLOCK 665000000 -#define IPU3FB_FONT_HEIGHT 16 - -struct ipu3sc_softc { - device_t dev; - bus_addr_t pbase; - bus_addr_t vbase; - - bus_space_tag_t iot; - bus_space_handle_t ioh; - bus_space_handle_t cm_ioh; - bus_space_handle_t dp_ioh; - bus_space_handle_t di0_ioh; - bus_space_handle_t di1_ioh; - bus_space_handle_t dctmpl_ioh; - bus_space_handle_t dc_ioh; - bus_space_handle_t dmfc_ioh; - bus_space_handle_t idmac_ioh; - bus_space_handle_t cpmem_ioh; -}; - -struct video_adapter_softc { - /* Videoadpater part */ - video_adapter_t va; - - intptr_t fb_addr; - intptr_t fb_paddr; - unsigned int fb_size; - - int bpp; - int depth; - unsigned int height; - unsigned int width; - unsigned int stride; - - unsigned int xmargin; - unsigned int ymargin; - - unsigned char *font; - int initialized; -}; - -static struct ipu3sc_softc *ipu3sc_softc; -static struct video_adapter_softc va_softc; - -/* FIXME: not only 2 bytes color supported */ -static uint16_t colors[16] = { - 0x0000, /* black */ - 0x001f, /* blue */ - 0x07e0, /* green */ - 0x07ff, /* cyan */ - 0xf800, /* red */ - 0xf81f, /* magenta */ - 0x3800, /* brown */ - 0xc618, /* light grey */ - 0xc618, /* XXX: dark grey */ - 0x001f, /* XXX: light blue */ - 0x07e0, /* XXX: light green */ - 0x07ff, /* XXX: light cyan */ - 0xf800, /* XXX: light red */ - 0xf81f, /* XXX: light magenta */ - 0xffe0, /* yellow */ - 0xffff, /* white */ -}; -static uint32_t colors_24[16] = { - 0x000000,/* Black */ - 0x000080,/* Blue */ - 0x008000,/* Green */ - 0x008080,/* Cyan */ - 0x800000,/* Red */ - 0x800080,/* Magenta */ - 0xcc6600,/* brown */ - 0xC0C0C0,/* Silver */ - 0x808080,/* Gray */ - 0x0000FF,/* Light Blue */ - 0x00FF00,/* Light Green */ - 0x00FFFF,/* Light Cyan */ - 0xFF0000,/* Light Red */ - 0xFF00FF,/* Light Magenta */ - 0xFFFF00,/* Yellow */ - 0xFFFFFF,/* White */ - -}; - -#define IPUV3_READ(ipuv3, module, reg) \ - bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg)) -#define IPUV3_WRITE(ipuv3, module, reg, val) \ - bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val)) - -#define CPMEM_CHANNEL_OFFSET(_c) ((_c) * 0x40) -#define CPMEM_WORD_OFFSET(_w) ((_w) * 0x20) -#define CPMEM_DP_OFFSET(_d) ((_d) * 0x10000) -#define IMX_IPU_DP0 0 -#define IMX_IPU_DP1 1 -#define CPMEM_CHANNEL(_dp, _ch, _w) \ - (CPMEM_DP_OFFSET(_dp) + CPMEM_CHANNEL_OFFSET(_ch) + \ - CPMEM_WORD_OFFSET(_w)) -#define CPMEM_OFFSET(_dp, _ch, _w, _o) \ - (CPMEM_CHANNEL((_dp), (_ch), (_w)) + (_o)) - -#define IPUV3_DEBUG 100 - -#ifdef IPUV3_DEBUG -#define SUBMOD_DUMP_REG(_sc, _m, _l) \ - { \ - int i; \ - printf("*** " #_m " ***\n"); \ - for (i = 0; i <= (_l); i += 4) { \ - if ((i % 32) == 0) \ - printf("%04x: ", i & 0xffff); \ - printf("0x%08x%c", IPUV3_READ((_sc), _m, i), \ - ((i + 4) % 32)?' ':'\n'); \ - } \ - printf("\n"); \ - } -#endif - -#ifdef IPUV3_DEBUG -int ipuv3_debug = IPUV3_DEBUG; -#define DPRINTFN(n,x) if (ipuv3_debug>(n)) printf x; else -#else -#define DPRINTFN(n,x) -#endif - -static int ipu3_fb_probe(device_t); -static int ipu3_fb_attach(device_t); - -static int -ipu3_fb_malloc(struct ipu3sc_softc *sc, size_t size) -{ - - sc->vbase = (uint32_t)contigmalloc(size, M_DEVBUF, M_ZERO, 0, ~0, - PAGE_SIZE, 0); - sc->pbase = vtophys(sc->vbase); - - return (0); -} - -static void -ipu3_fb_init(void *arg) -{ - struct ipu3sc_softc *sc = arg; - struct video_adapter_softc *va_sc = &va_softc; - uint64_t w0sh96; - uint32_t w1sh96; - - /* FW W0[137:125] - 96 = [41:29] */ - /* FH W0[149:138] - 96 = [53:42] */ - w0sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 16)); - w0sh96 <<= 32; - w0sh96 |= IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 12)); - - va_sc->width = ((w0sh96 >> 29) & 0x1fff) + 1; - va_sc->height = ((w0sh96 >> 42) & 0x0fff) + 1; - - /* SLY W1[115:102] - 96 = [19:6] */ - w1sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 12)); - va_sc->stride = ((w1sh96 >> 6) & 0x3fff) + 1; - - printf("%dx%d [%d]\n", va_sc->width, va_sc->height, va_sc->stride); - va_sc->fb_size = va_sc->height * va_sc->stride; - - ipu3_fb_malloc(sc, va_sc->fb_size); - - /* DP1 + config_ch_23 + word_2 */ - IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 0), - ((sc->pbase >> 3) | ((sc->pbase >> 3) << 29)) & 0xffffffff); - - IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 4), - ((sc->pbase >> 3) >> 3) & 0xffffffff); - - va_sc->fb_addr = (intptr_t)sc->vbase; - va_sc->fb_paddr = (intptr_t)sc->pbase; - va_sc->bpp = va_sc->stride / va_sc->width; - va_sc->depth = va_sc->bpp * 8; -} - -static int -ipu3_fb_probe(device_t dev) -{ - int error; - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (!ofw_bus_is_compatible(dev, "fsl,ipu3")) - return (ENXIO); - - device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)"); - - error = sc_probe_unit(device_get_unit(dev), - device_get_flags(dev) | SC_AUTODETECT_KBD); - - if (error != 0) - return (error); - - return (BUS_PROBE_DEFAULT); -} - -static int -ipu3_fb_attach(device_t dev) -{ - struct ipu3sc_softc *sc = device_get_softc(dev); - bus_space_tag_t iot; - bus_space_handle_t ioh; - phandle_t node; - pcell_t reg; - int err; - uintptr_t base; - - if (ipu3sc_softc) - return (ENXIO); - - ipu3sc_softc = sc; - - if (bootverbose) - device_printf(dev, "clock gate status is %d\n", - imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT)); - - sc->dev = dev; - - err = (sc_attach_unit(device_get_unit(dev), - device_get_flags(dev) | SC_AUTODETECT_KBD)); - - if (err) { - device_printf(dev, "failed to attach syscons\n"); - goto fail; - } - - sc = device_get_softc(dev); - sc->iot = iot = fdtbus_bs_tag; - - /* - * Retrieve the device address based on the start address in the - * DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register - * address, so we just subtract IPU_CM_BASE to get the offset at which - * the IPU device was memory mapped. - * On i.MX53, the offset is 0. - */ - node = ofw_bus_get_node(dev); - if ((OF_getencprop(node, "reg", ®, sizeof(reg))) <= 0) - base = 0; - else - base = reg - IPU_CM_BASE(0); - /* map controller registers */ - err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh); - if (err) - goto fail_retarn_cm; - sc->cm_ioh = ioh; - - /* map Display Multi FIFO Controller registers */ - err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh); - if (err) - goto fail_retarn_dmfc; - sc->dmfc_ioh = ioh; - - /* map Display Interface 0 registers */ - err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh); - if (err) - goto fail_retarn_di0; - sc->di0_ioh = ioh; - - /* map Display Interface 1 registers */ - err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh); - if (err) - goto fail_retarn_di1; - sc->di1_ioh = ioh; - - /* map Display Processor registers */ - err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh); - if (err) - goto fail_retarn_dp; - sc->dp_ioh = ioh; - - /* map Display Controller registers */ - err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh); - if (err) - goto fail_retarn_dc; - sc->dc_ioh = ioh; - - /* map Image DMA Controller registers */ - err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0, - &ioh); - if (err) - goto fail_retarn_idmac; - sc->idmac_ioh = ioh; - - /* map CPMEM registers */ - err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0, - &ioh); - if (err) - goto fail_retarn_cpmem; - sc->cpmem_ioh = ioh; - - /* map DCTEMPL registers */ - err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0, - &ioh); - if (err) - goto fail_retarn_dctmpl; - sc->dctmpl_ioh = ioh; - -#ifdef notyet - sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO, - ipuv3intr, sc); - if (sc->ih == NULL) { - device_printf(sc->dev, - "unable to establish interrupt at irq %d\n", - IMX51_INT_IPUV3); - return (ENXIO); - } -#endif - - /* - * We have to wait until interrupts are enabled. - * Mailbox relies on it to get data from VideoCore - */ - ipu3_fb_init(sc); - - return (0); - -fail: - return (ENXIO); -fail_retarn_dctmpl: - bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE); -fail_retarn_cpmem: - bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE); -fail_retarn_idmac: - bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE); -fail_retarn_dp: - bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE); -fail_retarn_dc: - bus_space_unmap(sc->iot, sc->di1_ioh, IPU_DI1_SIZE); -fail_retarn_di1: - bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE); -fail_retarn_di0: - bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE); -fail_retarn_dmfc: - bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE); -fail_retarn_cm: - device_printf(sc->dev, - "failed to map registers (errno=%d)\n", err); - return (err); -} - -static device_method_t ipu3_fb_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, ipu3_fb_probe), - DEVMETHOD(device_attach, ipu3_fb_attach), - { 0, 0 } -}; - -static driver_t ipu3_fb_driver = { - "fb", - ipu3_fb_methods, - sizeof(struct ipu3sc_softc), -}; - -DRIVER_MODULE(ipu3fb, simplebus, ipu3_fb_driver, 0, 0); - -/* - * Video driver routines and glue. - */ -static int ipu3fb_configure(int); -static vi_probe_t ipu3fb_probe; -static vi_init_t ipu3fb_init; -static vi_get_info_t ipu3fb_get_info; -static vi_query_mode_t ipu3fb_query_mode; -static vi_set_mode_t ipu3fb_set_mode; -static vi_save_font_t ipu3fb_save_font; -static vi_load_font_t ipu3fb_load_font; -static vi_show_font_t ipu3fb_show_font; -static vi_save_palette_t ipu3fb_save_palette; -static vi_load_palette_t ipu3fb_load_palette; -static vi_set_border_t ipu3fb_set_border; -static vi_save_state_t ipu3fb_save_state; -static vi_load_state_t ipu3fb_load_state; -static vi_set_win_org_t ipu3fb_set_win_org; -static vi_read_hw_cursor_t ipu3fb_read_hw_cursor; -static vi_set_hw_cursor_t ipu3fb_set_hw_cursor; -static vi_set_hw_cursor_shape_t ipu3fb_set_hw_cursor_shape; -static vi_blank_display_t ipu3fb_blank_display; -static vi_mmap_t ipu3fb_mmap; -static vi_ioctl_t ipu3fb_ioctl; -static vi_clear_t ipu3fb_clear; -static vi_fill_rect_t ipu3fb_fill_rect; -static vi_bitblt_t ipu3fb_bitblt; -static vi_diag_t ipu3fb_diag; -static vi_save_cursor_palette_t ipu3fb_save_cursor_palette; -static vi_load_cursor_palette_t ipu3fb_load_cursor_palette; -static vi_copy_t ipu3fb_copy; -static vi_putp_t ipu3fb_putp; -static vi_putc_t ipu3fb_putc; -static vi_puts_t ipu3fb_puts; -static vi_putm_t ipu3fb_putm; - -static video_switch_t ipu3fbvidsw = { - .probe = ipu3fb_probe, - .init = ipu3fb_init, - .get_info = ipu3fb_get_info, - .query_mode = ipu3fb_query_mode, - .set_mode = ipu3fb_set_mode, - .save_font = ipu3fb_save_font, - .load_font = ipu3fb_load_font, - .show_font = ipu3fb_show_font, - .save_palette = ipu3fb_save_palette, - .load_palette = ipu3fb_load_palette, - .set_border = ipu3fb_set_border, - .save_state = ipu3fb_save_state, - .load_state = ipu3fb_load_state, - .set_win_org = ipu3fb_set_win_org, - .read_hw_cursor = ipu3fb_read_hw_cursor, - .set_hw_cursor = ipu3fb_set_hw_cursor, - .set_hw_cursor_shape = ipu3fb_set_hw_cursor_shape, - .blank_display = ipu3fb_blank_display, - .mmap = ipu3fb_mmap, - .ioctl = ipu3fb_ioctl, - .clear = ipu3fb_clear, - .fill_rect = ipu3fb_fill_rect, - .bitblt = ipu3fb_bitblt, - .diag = ipu3fb_diag, - .save_cursor_palette = ipu3fb_save_cursor_palette, - .load_cursor_palette = ipu3fb_load_cursor_palette, - .copy = ipu3fb_copy, - .putp = ipu3fb_putp, - .putc = ipu3fb_putc, - .puts = ipu3fb_puts, - .putm = ipu3fb_putm, -}; - -VIDEO_DRIVER(ipu3fb, ipu3fbvidsw, ipu3fb_configure); - -extern sc_rndr_sw_t txtrndrsw; -RENDERER(ipu3fb, 0, txtrndrsw, gfb_set); -RENDERER_MODULE(ipu3fb, gfb_set); - -static uint16_t ipu3fb_static_window[ROW*COL]; -extern u_char dflt_font_16[]; - -static int -ipu3fb_configure(int flags) -{ - struct video_adapter_softc *sc; - - sc = &va_softc; - - if (sc->initialized) - return 0; - - sc->width = 640; - sc->height = 480; - sc->bpp = 2; - sc->stride = sc->width * sc->bpp; - - ipu3fb_init(0, &sc->va, 0); - - sc->initialized = 1; - - return (0); -} - -static int -ipu3fb_probe(int unit, video_adapter_t **adp, void *arg, int flags) -{ - - return (0); -} - -static int -ipu3fb_init(int unit, video_adapter_t *adp, int flags) -{ - struct video_adapter_softc *sc; - video_info_t *vi; - - sc = (struct video_adapter_softc *)adp; - vi = &adp->va_info; - - vid_init_struct(adp, "ipu3fb", -1, unit); - - sc->font = dflt_font_16; - vi->vi_cheight = IPU3FB_FONT_HEIGHT; - vi->vi_cwidth = 8; - vi->vi_width = sc->width/8; - vi->vi_height = sc->height/vi->vi_cheight; - - /* - * Clamp width/height to syscons maximums - */ - if (vi->vi_width > COL) - vi->vi_width = COL; - if (vi->vi_height > ROW) - vi->vi_height = ROW; - - sc->xmargin = (sc->width - (vi->vi_width * vi->vi_cwidth)) / 2; - sc->ymargin = (sc->height - (vi->vi_height * vi->vi_cheight))/2; - - adp->va_window = (vm_offset_t) ipu3fb_static_window; - adp->va_flags |= V_ADP_FONT /* | V_ADP_COLOR | V_ADP_MODECHANGE */; - adp->va_line_width = sc->stride; - adp->va_buffer_size = sc->fb_size; - - vid_register(&sc->va); - - return (0); -} - -static int -ipu3fb_get_info(video_adapter_t *adp, int mode, video_info_t *info) -{ - - bcopy(&adp->va_info, info, sizeof(*info)); - return (0); -} - -static int -ipu3fb_query_mode(video_adapter_t *adp, video_info_t *info) -{ - - return (0); -} - -static int -ipu3fb_set_mode(video_adapter_t *adp, int mode) -{ - - return (0); -} - -static int -ipu3fb_save_font(video_adapter_t *adp, int page, int size, int width, - u_char *data, int c, int count) -{ - - return (0); -} - -static int -ipu3fb_load_font(video_adapter_t *adp, int page, int size, int width, - u_char *data, int c, int count) -{ - struct video_adapter_softc *sc; - - sc = (struct video_adapter_softc *)adp; - sc->font = data; - - return (0); -} - -static int -ipu3fb_show_font(video_adapter_t *adp, int page) -{ - - return (0); -} - -static int -ipu3fb_save_palette(video_adapter_t *adp, u_char *palette) -{ - - return (0); -} - -static int -ipu3fb_load_palette(video_adapter_t *adp, u_char *palette) -{ - - return (0); -} - -static int -ipu3fb_set_border(video_adapter_t *adp, int border) -{ - - return (ipu3fb_blank_display(adp, border)); -} - -static int -ipu3fb_save_state(video_adapter_t *adp, void *p, size_t size) -{ - - return (0); -} - -static int -ipu3fb_load_state(video_adapter_t *adp, void *p) -{ - - return (0); -} - -static int -ipu3fb_set_win_org(video_adapter_t *adp, off_t offset) -{ - - return (0); -} - -static int -ipu3fb_read_hw_cursor(video_adapter_t *adp, int *col, int *row) -{ - - *col = *row = 0; - return (0); -} - -static int -ipu3fb_set_hw_cursor(video_adapter_t *adp, int col, int row) -{ - - return (0); -} - -static int -ipu3fb_set_hw_cursor_shape(video_adapter_t *adp, int base, int height, - int celsize, int blink) -{ - - return (0); -} - -static int -ipu3fb_blank_display(video_adapter_t *adp, int mode) -{ - - return (0); -} - -static int -ipu3fb_mmap(video_adapter_t *adp, vm_ooffset_t offset, vm_paddr_t *paddr, - int prot, vm_memattr_t *memattr) -{ - struct video_adapter_softc *sc; - - sc = (struct video_adapter_softc *)adp; - - /* - * This might be a legacy VGA mem request: if so, just point it at the - * framebuffer, since it shouldn't be touched - */ - if (offset < sc->stride * sc->height) { - *paddr = sc->fb_paddr + offset; - return (0); - } - - return (EINVAL); -} - -static int -ipu3fb_ioctl(video_adapter_t *adp, u_long cmd, caddr_t data) -{ - struct video_adapter_softc *sc; - struct fbtype *fb; - - sc = (struct video_adapter_softc *)adp; - - switch (cmd) { - case FBIOGTYPE: - fb = (struct fbtype *)data; - fb->fb_type = FBTYPE_PCIMISC; - fb->fb_height = sc->height; - fb->fb_width = sc->width; - fb->fb_depth = sc->depth; - if (sc->depth <= 1 || sc->depth > 8) - fb->fb_cmsize = 0; - else - fb->fb_cmsize = 1 << sc->depth; - fb->fb_size = sc->fb_size; - break; - default: - return (fb_commonioctl(adp, cmd, data)); - } - - return (0); -} - -static int -ipu3fb_clear(video_adapter_t *adp) -{ - - return (ipu3fb_blank_display(adp, 0)); -} - -static int -ipu3fb_fill_rect(video_adapter_t *adp, int val, int x, int y, int cx, int cy) -{ - - return (0); -} - -static int -ipu3fb_bitblt(video_adapter_t *adp, ...) -{ - - return (0); -} - -static int -ipu3fb_diag(video_adapter_t *adp, int level) -{ - - return (0); -} - -static int -ipu3fb_save_cursor_palette(video_adapter_t *adp, u_char *palette) -{ - - return (0); -} - -static int -ipu3fb_load_cursor_palette(video_adapter_t *adp, u_char *palette) -{ - - return (0); -} - -static int -ipu3fb_copy(video_adapter_t *adp, vm_offset_t src, vm_offset_t dst, int n) -{ - - return (0); -} - -static int -ipu3fb_putp(video_adapter_t *adp, vm_offset_t off, uint32_t p, uint32_t a, - int size, int bpp, int bit_ltor, int byte_ltor) -{ - - return (0); -} - -static int -ipu3fb_putc(video_adapter_t *adp, vm_offset_t off, uint8_t c, uint8_t a) -{ - struct video_adapter_softc *sc; - int col, row, bpp; - int b, i, j, k; - uint8_t *addr; - u_char *p; - uint32_t fg, bg, color; - - sc = (struct video_adapter_softc *)adp; - bpp = sc->bpp; - - if (sc->fb_addr == 0) - return (0); - row = (off / adp->va_info.vi_width) * adp->va_info.vi_cheight; - col = (off % adp->va_info.vi_width) * adp->va_info.vi_cwidth; - p = sc->font + c * IPU3FB_FONT_HEIGHT; - addr = (uint8_t *)sc->fb_addr - + (row + sc->ymargin) * (sc->stride) - + bpp * (col + sc->xmargin); - - if (bpp == 2) { - bg = colors[(a >> 4) & 0x0f]; - fg = colors[a & 0x0f]; - } else if (bpp == 3) { - bg = colors_24[(a >> 4) & 0x0f]; - fg = colors_24[a & 0x0f]; - } else { - return (ENXIO); - } - - for (i = 0; i < IPU3FB_FONT_HEIGHT; i++) { - for (j = 0, k = 7; j < 8; j++, k--) { - if ((p[i] & (1 << k)) == 0) - color = bg; - else - color = fg; - /* FIXME: BPP maybe different */ - for (b = 0; b < bpp; b ++) - addr[bpp * j + b] = - (color >> (b << 3)) & 0xff; - } - - addr += (sc->stride); - } - - return (0); -} - -static int -ipu3fb_puts(video_adapter_t *adp, vm_offset_t off, u_int16_t *s, int len) -{ - int i; - - for (i = 0; i < len; i++) - ipu3fb_putc(adp, off + i, s[i] & 0xff, (s[i] & 0xff00) >> 8); - - return (0); -} - -static int -ipu3fb_putm(video_adapter_t *adp, int x, int y, uint8_t *pixel_image, - uint32_t pixel_mask, int size, int width) -{ - - return (0); -} diff --git a/sys/arm/freescale/imx/imx51_ipuv3_fbd.c b/sys/arm/freescale/imx/imx51_ipuv3_fbd.c deleted file mode 100644 --- a/sys/arm/freescale/imx/imx51_ipuv3_fbd.c +++ /dev/null @@ -1,360 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2012 Oleksandr Tymoshenko - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include - -#include - -#include "fb_if.h" - -#define IMX51_IPU_HSP_CLOCK 665000000 - -struct ipu3sc_softc { - device_t dev; - device_t sc_fbd; /* fbd child */ - struct fb_info sc_info; - - bus_space_tag_t iot; - bus_space_handle_t ioh; - bus_space_handle_t cm_ioh; - bus_space_handle_t dp_ioh; - bus_space_handle_t di0_ioh; - bus_space_handle_t di1_ioh; - bus_space_handle_t dctmpl_ioh; - bus_space_handle_t dc_ioh; - bus_space_handle_t dmfc_ioh; - bus_space_handle_t idmac_ioh; - bus_space_handle_t cpmem_ioh; -}; - -static struct ipu3sc_softc *ipu3sc_softc; - -#define IPUV3_READ(ipuv3, module, reg) \ - bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg)) -#define IPUV3_WRITE(ipuv3, module, reg, val) \ - bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val)) - -#define CPMEM_CHANNEL_OFFSET(_c) ((_c) * 0x40) -#define CPMEM_WORD_OFFSET(_w) ((_w) * 0x20) -#define CPMEM_DP_OFFSET(_d) ((_d) * 0x10000) -#define IMX_IPU_DP0 0 -#define IMX_IPU_DP1 1 -#define CPMEM_CHANNEL(_dp, _ch, _w) \ - (CPMEM_DP_OFFSET(_dp) + CPMEM_CHANNEL_OFFSET(_ch) + \ - CPMEM_WORD_OFFSET(_w)) -#define CPMEM_OFFSET(_dp, _ch, _w, _o) \ - (CPMEM_CHANNEL((_dp), (_ch), (_w)) + (_o)) - -static int ipu3_fb_probe(device_t); -static int ipu3_fb_attach(device_t); - -static void -ipu3_fb_init(struct ipu3sc_softc *sc) -{ - uint64_t w0sh96; - uint32_t w1sh96; - - /* FW W0[137:125] - 96 = [41:29] */ - /* FH W0[149:138] - 96 = [53:42] */ - w0sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 16)); - w0sh96 <<= 32; - w0sh96 |= IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 12)); - - sc->sc_info.fb_width = ((w0sh96 >> 29) & 0x1fff) + 1; - sc->sc_info.fb_height = ((w0sh96 >> 42) & 0x0fff) + 1; - - /* SLY W1[115:102] - 96 = [19:6] */ - w1sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 12)); - sc->sc_info.fb_stride = ((w1sh96 >> 6) & 0x3fff) + 1; - - printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, - sc->sc_info.fb_stride); - sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; - - sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, - M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); - sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); - - /* DP1 + config_ch_23 + word_2 */ - IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 0), - (((uint32_t)sc->sc_info.fb_pbase >> 3) | - (((uint32_t)sc->sc_info.fb_pbase >> 3) << 29)) & 0xffffffff); - - IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 4), - (((uint32_t)sc->sc_info.fb_pbase >> 3) >> 3) & 0xffffffff); - - /* XXX: fetch or set it from/to IPU. */ - sc->sc_info.fb_bpp = sc->sc_info.fb_depth = sc->sc_info.fb_stride / - sc->sc_info.fb_width * 8; -} - -/* Use own color map, because of different RGB offset. */ -static int -ipu3_fb_init_colors(struct fb_info *info) -{ - - switch (info->fb_depth) { - case 8: - return (vt_config_cons_colors(info, COLOR_FORMAT_RGB, - 0x7, 5, 0x7, 2, 0x3, 0)); - case 15: - return (vt_config_cons_colors(info, COLOR_FORMAT_RGB, - 0x1f, 10, 0x1f, 5, 0x1f, 0)); - case 16: - return (vt_config_cons_colors(info, COLOR_FORMAT_RGB, - 0x1f, 11, 0x3f, 5, 0x1f, 0)); - case 24: - case 32: /* Ignore alpha. */ - return (vt_config_cons_colors(info, COLOR_FORMAT_RGB, - 0xff, 0, 0xff, 8, 0xff, 16)); - default: - return (1); - } -} - -static int -ipu3_fb_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (!ofw_bus_is_compatible(dev, "fsl,ipu3")) - return (ENXIO); - - device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)"); - - return (BUS_PROBE_DEFAULT); -} - -static int -ipu3_fb_attach(device_t dev) -{ - struct ipu3sc_softc *sc = device_get_softc(dev); - bus_space_tag_t iot; - bus_space_handle_t ioh; - phandle_t node; - pcell_t reg; - int err; - uintptr_t base; - - ipu3sc_softc = sc; - - if (bootverbose) - device_printf(dev, "clock gate status is %d\n", - imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT)); - - sc->dev = dev; - - sc = device_get_softc(dev); - sc->iot = iot = fdtbus_bs_tag; - - /* - * Retrieve the device address based on the start address in the - * DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register - * address, so we just subtract IPU_CM_BASE to get the offset at which - * the IPU device was memory mapped. - * On i.MX53, the offset is 0. - */ - node = ofw_bus_get_node(dev); - if ((OF_getencprop(node, "reg", ®, sizeof(reg))) <= 0) - base = 0; - else - base = reg - IPU_CM_BASE(0); - /* map controller registers */ - err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh); - if (err) - goto fail_retarn_cm; - sc->cm_ioh = ioh; - - /* map Display Multi FIFO Controller registers */ - err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh); - if (err) - goto fail_retarn_dmfc; - sc->dmfc_ioh = ioh; - - /* map Display Interface 0 registers */ - err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh); - if (err) - goto fail_retarn_di0; - sc->di0_ioh = ioh; - - /* map Display Interface 1 registers */ - err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh); - if (err) - goto fail_retarn_di1; - sc->di1_ioh = ioh; - - /* map Display Processor registers */ - err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh); - if (err) - goto fail_retarn_dp; - sc->dp_ioh = ioh; - - /* map Display Controller registers */ - err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh); - if (err) - goto fail_retarn_dc; - sc->dc_ioh = ioh; - - /* map Image DMA Controller registers */ - err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0, - &ioh); - if (err) - goto fail_retarn_idmac; - sc->idmac_ioh = ioh; - - /* map CPMEM registers */ - err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0, - &ioh); - if (err) - goto fail_retarn_cpmem; - sc->cpmem_ioh = ioh; - - /* map DCTEMPL registers */ - err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0, - &ioh); - if (err) - goto fail_retarn_dctmpl; - sc->dctmpl_ioh = ioh; - -#ifdef notyet - sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO, - ipuv3intr, sc); - if (sc->ih == NULL) { - device_printf(sc->dev, - "unable to establish interrupt at irq %d\n", - IMX51_INT_IPUV3); - return (ENXIO); - } -#endif - - /* - * We have to wait until interrupts are enabled. - * Mailbox relies on it to get data from VideoCore - */ - ipu3_fb_init(sc); - - sc->sc_info.fb_name = device_get_nameunit(dev); - - ipu3_fb_init_colors(&sc->sc_info); - sc->sc_info.fb_cmsize = 16; - - /* Ask newbus to attach framebuffer device to me. */ - sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); - if (sc->sc_fbd == NULL) - device_printf(dev, "Can't attach fbd device\n"); - - return (bus_generic_attach(dev)); - -fail_retarn_dctmpl: - bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE); -fail_retarn_cpmem: - bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE); -fail_retarn_idmac: - bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE); -fail_retarn_dp: - bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE); -fail_retarn_dc: - bus_space_unmap(sc->iot, sc->di1_ioh, IPU_DI1_SIZE); -fail_retarn_di1: - bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE); -fail_retarn_di0: - bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE); -fail_retarn_dmfc: - bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE); -fail_retarn_cm: - device_printf(sc->dev, - "failed to map registers (errno=%d)\n", err); - return (err); -} - -static struct fb_info * -ipu3_fb_getinfo(device_t dev) -{ - struct ipu3sc_softc *sc = device_get_softc(dev); - - return (&sc->sc_info); -} - -static device_method_t ipu3_fb_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, ipu3_fb_probe), - DEVMETHOD(device_attach, ipu3_fb_attach), - - /* Framebuffer service methods */ - DEVMETHOD(fb_getinfo, ipu3_fb_getinfo), - { 0, 0 } -}; - -static driver_t ipu3_fb_driver = { - "fb", - ipu3_fb_methods, - sizeof(struct ipu3sc_softc), -}; - -DRIVER_MODULE(fb, simplebus, ipu3_fb_driver, 0, 0); diff --git a/sys/arm/freescale/imx/imx51_ipuv3reg.h b/sys/arm/freescale/imx/imx51_ipuv3reg.h deleted file mode 100644 --- a/sys/arm/freescale/imx/imx51_ipuv3reg.h +++ /dev/null @@ -1,922 +0,0 @@ -/* $NetBSD: imx51_ipuv3reg.h,v 1.1 2012/04/17 10:19:57 bsh Exp $ */ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. - * Written by Hashimoto Kenichi for Genetec Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _ARM_IMX_IMX51_IPUV3REG_H -#define _ARM_IMX_IMX51_IPUV3REG_H - -/* register offset address */ - -/* - * CM - * Control Module - */ -#define IPU_CM_CONF 0x00000000 -#define CM_CONF_CSI_SEL 0x80000000 -#define CM_CONF_IC_INPUT 0x40000000 -#define CM_CONF_CSI1_DATA_SOURCE 0x20000000 -#define CM_CONF_CSI0_DATA_SOURCE 0x10000000 -#define CM_CONF_VDI_DMFC_SYNC 0x08000000 -#define CM_CONF_IC_DMFC_SYNC 0x04000000 -#define CM_CONF_IC_DMFC_SEL 0x02000000 -#define CM_CONF_ISP_DOUBLE_FLOW 0x01000000 -#define CM_CONF_IDMAC_DISABLE 0x00400000 -#define CM_CONF_IPU_DIAGBUS_ON 0x00200000 -#define CM_CONF_IPU_DIAGBUS_MODE 0x001f0000 -#define CM_CONF_VDI_EN 0x00001000 -#define CM_CONF_SISG_EN 0x00000800 -#define CM_CONF_DMFC_EN 0x00000400 -#define CM_CONF_DC_EN 0x00000200 -#define CM_CONF_SMFC_EN 0x00000100 -#define CM_CONF_DI1_EN 0x00000080 -#define CM_CONF_DI0_EN 0x00000040 -#define CM_CONF_DP_EN 0x00000020 -#define CM_CONF_ISP_EN 0x00000010 -#define CM_CONF_IRT_EN 0x00000008 -#define CM_CONF_IC_EN 0x00000004 -#define CM_CONF_CSI1_EN 0x00000002 -#define CM_CONF_CSI0_EN 0x00000001 -#define IPU_SISG_CTRL0 0x00000004 -#define IPU_SISG_CTRL1 0x00000008 -#define IPU_CM_INT_CTRL_1 0x0000003c -#define IPU_CM_INT_CTRL_2 0x00000040 -#define IPU_CM_INT_CTRL_3 0x00000044 -#define IPU_CM_INT_CTRL_4 0x00000048 -#define IPU_CM_INT_CTRL_5 0x0000004c -#define IPU_CM_INT_CTRL_6 0x00000050 -#define IPU_CM_INT_CTRL_7 0x00000054 -#define IPU_CM_INT_CTRL_8 0x00000058 -#define IPU_CM_INT_CTRL_9 0x0000005c -#define IPU_CM_INT_CTRL_10 0x00000060 -#define IPU_CM_INT_CTRL_11 0x00000064 -#define IPU_CM_INT_CTRL_12 0x00000068 -#define IPU_CM_INT_CTRL_13 0x0000006c -#define IPU_CM_INT_CTRL_14 0x00000070 -#define IPU_CM_INT_CTRL_15 0x00000074 -#define IPU_CM_SDMA_EVENT_1 0x00000078 -#define IPU_CM_SDMA_EVENT_2 0x0000007c -#define IPU_CM_SDMA_EVENT_3 0x00000080 -#define IPU_CM_SDMA_EVENT_4 0x00000084 -#define IPU_CM_SDMA_EVENT_7 0x00000088 -#define IPU_CM_SDMA_EVENT_8 0x0000008c -#define IPU_CM_SDMA_EVENT_11 0x00000090 -#define IPU_CM_SDMA_EVENT_12 0x00000094 -#define IPU_CM_SDMA_EVENT_13 0x00000098 -#define IPU_CM_SDMA_EVENT_14 0x0000009c -#define IPU_CM_SRM_PRI1 0x000000a0 -#define IPU_CM_SRM_PRI2 0x000000a4 -#define IPU_CM_FS_PROC_FLOW1 0x000000a8 -#define IPU_CM_FS_PROC_FLOW2 0x000000ac -#define IPU_CM_FS_PROC_FLOW3 0x000000b0 -#define IPU_CM_FS_DISP_FLOW1 0x000000b4 -#define IPU_CM_FS_DISP_FLOW2 0x000000b8 -#define IPU_CM_SKIP 0x000000bc -#define IPU_CM_DISP_ALT_CONF 0x000000c0 -#define IPU_CM_DISP_GEN 0x000000c4 -#define CM_DISP_GEN_DI0_COUNTER_RELEASE 0x01000000 -#define CM_DISP_GEN_DI1_COUNTER_RELEASE 0x00800000 -#define CM_DISP_GEN_MCU_MAX_BURST_STOP 0x00400000 -#define CM_DISP_GEN_MCU_T_SHIFT 18 -#define CM_DISP_GEN_MCU_T(n) ((n) << CM_DISP_GEN_MCU_T_SHIFT) -#define IPU_CM_DISP_ALT1 0x000000c8 -#define IPU_CM_DISP_ALT2 0x000000cc -#define IPU_CM_DISP_ALT3 0x000000d0 -#define IPU_CM_DISP_ALT4 0x000000d4 -#define IPU_CM_SNOOP 0x000000d8 -#define IPU_CM_MEM_RST 0x000000dc -#define CM_MEM_START 0x80000000 -#define CM_MEM_EN 0x007fffff -#define IPU_CM_PM 0x000000e0 -#define IPU_CM_GPR 0x000000e4 -#define CM_GPR_IPU_CH_BUF1_RDY1_CLR 0x80000000 -#define CM_GPR_IPU_CH_BUF1_RDY0_CLR 0x40000000 -#define CM_GPR_IPU_CH_BUF0_RDY1_CLR 0x20000000 -#define CM_GPR_IPU_CH_BUF0_RDY0_CLR 0x10000000 -#define CM_GPR_IPU_ALT_CH_BUF1_RDY1_CLR 0x08000000 -#define CM_GPR_IPU_ALT_CH_BUF1_RDY0_CLR 0x04000000 -#define CM_GPR_IPU_ALT_CH_BUF0_RDY1_CLR 0x02000000 -#define CM_GPR_IPU_ALT_CH_BUF0_RDY0_CLR 0x01000000 -#define CM_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS 0x00800000 -#define CM_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS 0x00400000 -#define CM_GPR_IPU_CH_BUF2_RDY1_CLR 0x00200000 -#define CM_GPR_IPU_CH_BUF2_RDY0_CLR 0x00100000 -#define CM_GPR_IPU_GP(n) __BIT((n)) -#define IPU_CM_CH_DB_MODE_SEL_0 0x00000150 -#define IPU_CM_CH_DB_MODE_SEL_1 0x00000154 -#define IPU_CM_ALT_CH_DB_MODE_SEL_0 0x00000168 -#define IPU_CM_ALT_CH_DB_MODE_SEL_1 0x0000016c -#define IPU_CM_CH_TRB_MODE_SEL_0 0x00000178 -#define IPU_CM_CH_TRB_MODE_SEL_1 0x0000017c -#define IPU_CM_INT_STAT_1 0x00000200 -#define IPU_CM_INT_STAT_2 0x00000204 -#define IPU_CM_INT_STAT_3 0x00000208 -#define IPU_CM_INT_STAT_4 0x0000020c -#define IPU_CM_INT_STAT_5 0x00000210 -#define IPU_CM_INT_STAT_6 0x00000214 -#define IPU_CM_INT_STAT_7 0x00000218 -#define IPU_CM_INT_STAT_8 0x0000021c -#define IPU_CM_INT_STAT_9 0x00000220 -#define IPU_CM_INT_STAT_10 0x00000224 -#define IPU_CM_INT_STAT_11 0x00000228 -#define IPU_CM_INT_STAT_12 0x0000022c -#define IPU_CM_INT_STAT_13 0x00000230 -#define IPU_CM_INT_STAT_14 0x00000234 -#define IPU_CM_INT_STAT_15 0x00000238 -#define IPU_CM_CUR_BUF_0 0x0000023c -#define IPU_CM_CUR_BUF_1 0x00000240 -#define IPU_CM_ALT_CUR_BUF_0 0x00000244 -#define IPU_CM_ALT_CUR_BUF_1 0x00000248 -#define IPU_CM_SRM_STAT 0x0000024c -#define IPU_CM_PROC_TASKS_STAT 0x00000250 -#define IPU_CM_DISP_TASKS_STAT 0x00000254 -#define IPU_CM_TRIPLE_CUR_BUF_0 0x00000258 -#define IPU_CM_TRIPLE_CUR_BUF_1 0x0000025c -#define IPU_CM_TRIPLE_CUR_BUF_2 0x00000260 -#define IPU_CM_TRIPLE_CUR_BUF_3 0x00000264 -#define IPU_CM_CH_BUF0_RDY0 0x00000268 -#define IPU_CM_CH_BUF0_RDY1 0x0000026c -#define IPU_CM_CH_BUF1_RDY0 0x00000270 -#define IPU_CM_CH_BUF1_RDY1 0x00000274 -#define IPU_CM_ALT_CH_BUF0_RDY0 0x00000278 -#define IPU_CM_ALT_CH_BUF0_RDY1 0x0000027c -#define IPU_CM_ALT_CH_BUF1_RDY0 0x00000280 -#define IPU_CM_ALT_CH_BUF1_RDY1 0x00000284 -#define IPU_CM_CH_BUF2_RDY0 0x00000288 -#define IPU_CM_CH_BUF2_RDY1 0x0000028c - -/* - * IDMAC - * Image DMA Controller - */ -#define IPU_IDMAC_CONF 0x00000000 -#define IPU_IDMAC_CH_EN_1 0x00000004 -#define IPU_IDMAC_CH_EN_2 0x00000008 -#define IPU_IDMAC_SEP_ALPHA 0x0000000c -#define IPU_IDMAC_ALT_SEP_ALPHA 0x00000010 -#define IPU_IDMAC_CH_PRI_1 0x00000014 -#define IPU_IDMAC_CH_PRI_2 0x00000018 -#define IPU_IDMAC_WM_EN_1 0x0000001c -#define IPU_IDMAC_WM_EN_2 0x00000020 -#define IPU_IDMAC_LOCK_EN_1 0x00000024 -#define IPU_IDMAC_LOCK_EN_2 0x00000028 -#define IPU_IDMAC_SUB_ADDR_0 0x0000002c -#define IPU_IDMAC_SUB_ADDR_1 0x00000030 -#define IPU_IDMAC_SUB_ADDR_2 0x00000034 -#define IPU_IDMAC_SUB_ADDR_3 0x00000038 -#define IPU_IDMAC_SUB_ADDR_4 0x0000003c -#define IPU_IDMAC_BNDM_EN_1 0x00000040 -#define IPU_IDMAC_BNDM_EN_2 0x00000044 -#define IPU_IDMAC_SC_CORD 0x00000048 -#define IPU_IDMAC_SC_CORD1 0x0000004c -#define IPU_IDMAC_CH_BUSY_1 0x00000100 -#define IPU_IDMAC_CH_BUSY_2 0x00000104 - -#define CH_PANNEL_BG 23 -#define CH_PANNEL_FG 27 - -/* - * DP - * Display Port - */ -#define IPU_DP_DEBUG_CNT 0x000000bc -#define IPU_DP_DEBUG_STAT 0x000000c0 - -/* - * IC - * Image Converter - */ -#define IPU_IC_CONF 0x00000000 -#define IPU_IC_PRP_ENC_RSC 0x00000004 -#define IPU_IC_PRP_VF_RSC 0x00000008 -#define IPU_IC_PP_RSC 0x0000000c -#define IPU_IC_CMBP_1 0x00000010 -#define IPU_IC_CMBP_2 0x00000014 -#define IPU_IC_IDMAC_1 0x00000018 -#define IPU_IC_IDMAC_2 0x0000001c -#define IPU_IC_IDMAC_3 0x00000020 -#define IPU_IC_IDMAC_4 0x00000024 - -/* - * CSI - * Camera Sensor Interface - */ -#define IPU_CSI0_SENS_CONF 0x00000000 -#define IPU_CSI0_SENS_FRM_SIZE 0x00000004 -#define IPU_CSI0_ACT_FRM_SIZE 0x00000008 -#define IPU_CSI0_OUT_FRM_CTRL 0x0000000c -#define IPU_CSI0_TST_CTRL 0x00000010 -#define IPU_CSI0_CCIR_CODE_1 0x00000014 -#define IPU_CSI0_CCIR_CODE_2 0x00000018 -#define IPU_CSI0_CCIR_CODE_3 0x0000001c -#define IPU_CSI0_DI 0x00000020 -#define IPU_CSI0_SKIP 0x00000024 -#define IPU_CSI0_CPD_CTRL 0x00000028 -#define IPU_CSI0_CPD_OFFSET1 0x000000ec -#define IPU_CSI0_CPD_OFFSET2 0x000000f0 - -#define IPU_CSI1_SENS_CONF 0x00000000 -#define IPU_CSI1_SENS_FRM_SIZE 0x00000004 -#define IPU_CSI1_ACT_FRM_SIZE 0x00000008 -#define IPU_CSI1_OUT_FRM_CTRL 0x0000000c -#define IPU_CSI1_TST_CTRL 0x00000010 -#define IPU_CSI1_CCIR_CODE_1 0x00000014 -#define IPU_CSI1_CCIR_CODE_2 0x00000018 -#define IPU_CSI1_CCIR_CODE_3 0x0000001c -#define IPU_CSI1_DI 0x00000020 -#define IPU_CSI1_SKIP 0x00000024 -#define IPU_CSI1_CPD_CTRL 0x00000028 -#define IPU_CSI1_CPD_OFFSET1 0x000000ec -#define IPU_CSI1_CPD_OFFSET2 0x000000f0 - -/* - * DI - * Display Interface - */ -#define IPU_DI_GENERAL 0x00000000 -#define DI_GENERAL_DISP_Y_SEL 0x70000000 -#define DI_GENERAL_CLOCK_STOP_MODE 0x0f000000 -#define DI_GENERAL_DISP_CLOCK_INIT 0x00800000 -#define DI_GENERAL_MASK_SEL 0x00400000 -#define DI_GENERAL_VSYNC_EXT 0x00200000 -#define DI_GENERAL_CLK_EXT 0x00100000 -#define DI_GENERAL_WATCHDOG_MODE 0x000c0000 -#define DI_GENERAL_POLARITY_DISP_CLK 0x00020000 -#define DI_GENERAL_SYNC_COUNT_SEL 0x0000f000 -#define DI_GENERAL_ERR_TREATMENT 0x00000800 -#define DI_GENERAL_ERM_VSYNC_SEL 0x00000400 -#define DI_GENERAL_POLARITY_CS(n) (1 << ((n) + 8)) -#define DI_GENERAL_POLARITY(n) (1 << ((n) - 1)) - -#define IPU_DI_BS_CLKGEN0 0x00000004 -#define DI_BS_CLKGEN0_OFFSET_SHIFT 16 -#define IPU_DI_BS_CLKGEN1 0x00000008 -#define DI_BS_CLKGEN1_DOWN_SHIFT 16 -#define DI_BS_CLKGEN1_UP_SHIFT 0 -#define IPU_DI_SW_GEN0(n) (0x0000000c + ((n) - 1) * 4) -#define DI_SW_GEN0_RUN_VAL 0x7ff80000 -#define DI_SW_GEN0_RUN_RESOL 0x00070000 -#define DI_SW_GEN0_OFFSET_VAL 0x00007ff8 -#define DI_SW_GEN0_OFFSET_RESOL 0x00000007 -#define __DI_SW_GEN0(run_val, run_resol, offset_val, offset_resol) \ - (((run_val) << 19) | ((run_resol) << 16) | \ - ((offset_val) << 3) | (offset_resol)) -#define IPU_DI_SW_GEN1(n) (0x00000030 + ((n) - 1) * 4) -#define DI_SW_GEN1_CNT_POL_GEN_EN 0x60000000 -#define DI_SW_GEN1_CNT_AUTO_RELOAD 0x10000000 -#define DI_SW_GEN1_CNT_CLR_SEL 0x0e000000 -#define DI_SW_GEN1_CNT_DOWN 0x01ff0000 -#define DI_SW_GEN1_CNT_POL_TRIG_SEL 0x00007000 -#define DI_SW_GEN1_CNT_POL_CLR_SEL 0x00000e00 -#define DI_SW_GEN1_CNT_UP 0x000001ff -#define __DI_SW_GEN1(pol_gen_en, auto_reload, clr_sel, down, pol_trig_sel, pol_clr_sel, up) \ - (((pol_gen_en) << 29) | ((auto_reload) << 28) | \ - ((clr_sel) << 25) | \ - ((down) << 16) | ((pol_trig_sel) << 12) | \ - ((pol_clr_sel) << 9) | (up)) -#define IPU_DI_SYNC_AS_GEN 0x00000054 -#define DI_SYNC_AS_GEN_SYNC_START_EN 0x10000000 -#define DI_SYNC_AS_GEN_VSYNC_SEL 0x0000e000 -#define DI_SYNC_AS_GEN_VSYNC_SEL_SHIFT 13 -#define DI_SYNC_AS_GEN_SYNC_STAR 0x00000fff -#define IPU_DI_DW_GEN(n) (0x00000058 + (n) * 4) -#define DI_DW_GEN_ACCESS_SIZE_SHIFT 24 -#define DI_DW_GEN_COMPONNENT_SIZE_SHIFT 16 -#define DI_DW_GEN_PIN_SHIFT(n) (((n) - 11) * 2) -#define DI_DW_GEN_PIN(n) __BITS(DI_DW_GEN_PIN_SHIFT(n) + 1, \ - DI_DW_GEN_PIN_SHIFT(n)) -#define IPU_DI_DW_SET(n, m) (0x00000088 + (n) * 4 + (m) * 0x30) -#define DI_DW_SET_DOWN_SHIFT 16 -#define DI_DW_SET_UP_SHIFT 0 -#define IPU_DI_STP_REP(n) (0x00000148 + ((n - 1) / 2) * 4) -#define DI_STP_REP_SHIFT(n) (((n - 1) % 2) * 16) -#define DI_STP_REP_MASK(n) (0x00000fff << DI_STP_REP_SHIFT((n))) -#define IPU_DI_SER_CONF 0x0000015c -#define IPU_DI_SSC 0x00000160 -#define IPU_DI_POL 0x00000164 -#define DI_POL_DRDY_POLARITY_17 0x00000040 -#define DI_POL_DRDY_POLARITY_16 0x00000020 -#define DI_POL_DRDY_POLARITY_15 0x00000010 -#define DI_POL_DRDY_POLARITY_14 0x00000008 -#define DI_POL_DRDY_POLARITY_13 0x00000004 -#define DI_POL_DRDY_POLARITY_12 0x00000002 -#define DI_POL_DRDY_POLARITY_11 0x00000001 -#define IPU_DI_AW0 0x00000168 -#define IPU_DI_AW1 0x0000016c -#define IPU_DI_SCR_CONF 0x00000170 -#define IPU_DI_STAT 0x00000174 - -/* - * SMFC - * Sensor Multi FIFO Controller - */ -#define IPU_SMFC_MAP 0x00000000 -#define IPU_SMFC_WMC 0x00000004 -#define IPU_SMFC_BS 0x00000008 - -/* - * DC - * Display Controller - */ -#define IPU_DC_READ_CH_CONF 0x00000000 -#define IPU_DC_READ_CH_ADDR 0x00000004 - -#define IPU_DC_RL0_CH_0 0x00000008 -#define IPU_DC_RL1_CH_0 0x0000000c -#define IPU_DC_RL2_CH_0 0x00000010 -#define IPU_DC_RL3_CH_0 0x00000014 -#define IPU_DC_RL4_CH_0 0x00000018 -#define IPU_DC_WR_CH_CONF_1 0x0000001c -#define IPU_DC_WR_CH_ADDR_1 0x00000020 -#define IPU_DC_RL0_CH_1 0x00000024 -#define IPU_DC_RL1_CH_1 0x00000028 -#define IPU_DC_RL2_CH_1 0x0000002c -#define IPU_DC_RL3_CH_1 0x00000030 -#define IPU_DC_RL4_CH_1 0x00000034 -#define IPU_DC_WR_CH_CONF_2 0x00000038 -#define IPU_DC_WR_CH_ADDR_2 0x0000003c -#define IPU_DC_RL0_CH_2 0x00000040 -#define IPU_DC_RL1_CH_2 0x00000044 -#define IPU_DC_RL2_CH_2 0x00000048 -#define IPU_DC_RL3_CH_2 0x0000004c -#define IPU_DC_RL4_CH_2 0x00000050 -#define IPU_DC_CMD_CH_CONF_3 0x00000054 -#define IPU_DC_CMD_CH_CONF_4 0x00000058 -#define IPU_DC_WR_CH_CONF_5 0x0000005c -#define IPU_DC_WR_CH_ADDR_5 0x00000060 -#define IPU_DC_RL0_CH_5 0x00000064 -#define IPU_DC_RL1_CH_5 0x00000068 -#define IPU_DC_RL2_CH_5 0x0000006c -#define IPU_DC_RL3_CH_5 0x00000070 -#define IPU_DC_RL4_CH_5 0x00000074 -#define IPU_DC_WR_CH_CONF_6 0x00000078 -#define IPU_DC_WR_CH_ADDR_6 0x0000007c -#define IPU_DC_RL0_CH_6 0x00000080 -#define IPU_DC_RL1_CH_6 0x00000084 -#define IPU_DC_RL2_CH_6 0x00000088 -#define IPU_DC_RL3_CH_6 0x0000008c -#define IPU_DC_RL4_CH_6 0x00000090 -#define IPU_DC_WR_CH_CONF1_8 0x00000094 -#define IPU_DC_WR_CH_CONF2_8 0x00000098 -#define IPU_DC_RL1_CH_8 0x0000009c -#define IPU_DC_RL2_CH_8 0x000000a0 -#define IPU_DC_RL3_CH_8 0x000000a4 -#define IPU_DC_RL4_CH_8 0x000000a8 -#define IPU_DC_RL5_CH_8 0x000000ac -#define IPU_DC_RL6_CH_8 0x000000b0 -#define IPU_DC_WR_CH_CONF1_9 0x000000b4 -#define IPU_DC_WR_CH_CONF2_9 0x000000b8 -#define IPU_DC_RL1_CH_9 0x000000bc -#define IPU_DC_RL2_CH_9 0x000000c0 -#define IPU_DC_RL3_CH_9 0x000000c4 -#define IPU_DC_RL4_CH_9 0x000000c8 -#define IPU_DC_RL5_CH_9 0x000000cc -#define IPU_DC_RL6_CH_9 0x000000d0 - -#define IPU_DC_RL(chan_base, evt) ((chan_base) + (evt / 2) *0x4) -#define DC_RL_CH_0 IPU_DC_RL0_CH_0 -#define DC_RL_CH_1 IPU_DC_RL0_CH_1 -#define DC_RL_CH_2 IPU_DC_RL0_CH_2 -#define DC_RL_CH_5 IPU_DC_RL0_CH_5 -#define DC_RL_CH_6 IPU_DC_RL0_CH_6 -#define DC_RL_CH_8 IPU_DC_RL0_CH_8 - -#define DC_RL_EVT_NF 0 -#define DC_RL_EVT_NL 1 -#define DC_RL_EVT_EOF 2 -#define DC_RL_EVT_NFIELD 3 -#define DC_RL_EVT_EOL 4 -#define DC_RL_EVT_EOFIELD 5 -#define DC_RL_EVT_NEW_ADDR 6 -#define DC_RL_EVT_NEW_CHAN 7 -#define DC_RL_EVT_NEW_DATA 8 - -#define IPU_DC_GEN 0x000000d4 -#define IPU_DC_DISP_CONF1_0 0x000000d8 -#define IPU_DC_DISP_CONF1_1 0x000000dc -#define IPU_DC_DISP_CONF1_2 0x000000e0 -#define IPU_DC_DISP_CONF1_3 0x000000e4 -#define IPU_DC_DISP_CONF2_0 0x000000e8 -#define IPU_DC_DISP_CONF2_1 0x000000ec -#define IPU_DC_DISP_CONF2_2 0x000000f0 -#define IPU_DC_DISP_CONF2_3 0x000000f4 -#define IPU_DC_DI0_CONF_1 0x000000f8 -#define IPU_DC_DI0_CONF_2 0x000000fc -#define IPU_DC_DI1_CONF_1 0x00000100 -#define IPU_DC_DI1_CONF_2 0x00000104 - -#define IPU_DC_MAP_CONF_PNTR(n) (0x00000108 + (n) * 4) -#define IPU_DC_MAP_CONF_0 0x00000108 -#define IPU_DC_MAP_CONF_1 0x0000010c -#define IPU_DC_MAP_CONF_2 0x00000110 -#define IPU_DC_MAP_CONF_3 0x00000114 -#define IPU_DC_MAP_CONF_4 0x00000118 -#define IPU_DC_MAP_CONF_5 0x0000011c -#define IPU_DC_MAP_CONF_6 0x00000120 -#define IPU_DC_MAP_CONF_7 0x00000124 -#define IPU_DC_MAP_CONF_8 0x00000128 -#define IPU_DC_MAP_CONF_9 0x0000012c -#define IPU_DC_MAP_CONF_10 0x00000130 -#define IPU_DC_MAP_CONF_11 0x00000134 -#define IPU_DC_MAP_CONF_12 0x00000138 -#define IPU_DC_MAP_CONF_13 0x0000013c -#define IPU_DC_MAP_CONF_14 0x00000140 - -#define IPU_DC_MAP_CONF_MASK(n) (0x00000144 + (n) * 4) -#define IPU_DC_MAP_CONF_15 0x00000144 -#define IPU_DC_MAP_CONF_16 0x00000148 -#define IPU_DC_MAP_CONF_17 0x0000014c -#define IPU_DC_MAP_CONF_18 0x00000150 -#define IPU_DC_MAP_CONF_19 0x00000154 -#define IPU_DC_MAP_CONF_20 0x00000158 -#define IPU_DC_MAP_CONF_21 0x0000015c -#define IPU_DC_MAP_CONF_22 0x00000160 -#define IPU_DC_MAP_CONF_23 0x00000164 -#define IPU_DC_MAP_CONF_24 0x00000168 -#define IPU_DC_MAP_CONF_25 0x0000016c -#define IPU_DC_MAP_CONF_26 0x00000170 - -#define IPU_DC_UGDE(m, n) (0x00000174 + (m) * 0x10 + (n) +4) -#define IPU_DC_UGDE0_0 0x00000174 -#define IPU_DC_UGDE0_1 0x00000178 -#define IPU_DC_UGDE0_2 0x0000017c -#define IPU_DC_UGDE0_3 0x00000180 -#define IPU_DC_UGDE1_0 0x00000184 -#define IPU_DC_UGDE1_1 0x00000188 -#define IPU_DC_UGDE1_2 0x0000018c -#define IPU_DC_UGDE1_3 0x00000190 -#define IPU_DC_UGDE2_0 0x00000194 -#define IPU_DC_UGDE2_1 0x00000198 -#define IPU_DC_UGDE2_2 0x0000019c -#define IPU_DC_UGDE2_3 0x000001a0 -#define IPU_DC_UGDE3_0 0x000001a4 -#define IPU_DC_UGDE3_1 0x000001a8 -#define IPU_DC_UGDE3_2 0x000001ac -#define IPU_DC_UGDE3_3 0x000001b0 -#define IPU_DC_LLA0 0x000001b4 -#define IPU_DC_LLA1 0x000001b8 -#define IPU_DC_R_LLA0 0x000001bc -#define IPU_DC_R_LLA1 0x000001c0 -#define IPU_DC_WR_CH_ADDR_5_ALT 0x000001c4 -#define IPU_DC_STAT 0x000001c8 - -/* - * DMFC - * Display Multi FIFO Controller - */ -#define IPU_DMFC_RD_CHAN 0x00000000 -#define DMFC_RD_CHAN_PPW_C 0x03000000 -#define DMFC_RD_CHAN_WM_DR_0 0x00e00000 -#define DMFC_RD_CHAN_WM_SET_0 0x001c0000 -#define DMFC_RD_CHAN_WM_EN_0 0x00020000 -#define DMFC_RD_CHAN_BURST_SIZE_0 0x000000c0 -#define IPU_DMFC_WR_CHAN 0x00000004 -#define DMFC_WR_CHAN_BUSRT_SIZE_2C 0xc0000000 -#define DMFC_WR_CHAN_FIFO_SIZE_2C 0x38000000 -#define DMFC_WR_CHAN_ST_ADDR_2C 0x07000000 -#define DMFC_WR_CHAN_BURST_SIZE_1C 0x00c00000 -#define DMFC_WR_CHAN_FIFO_SIZE_1C 0x00380000 -#define DMFC_WR_CHAN_ST_ADDR_1C 0x00070000 -#define DMFC_WR_CHAN_BURST_SIZE_2 0x0000c000 -#define DMFC_WR_CHAN_FIFO_SIZE_2 0x00003800 -#define DMFC_WR_CHAN_ST_ADDR_2 0x00000700 -#define DMFC_WR_CHAN_BURST_SIZE_1 0x000000c0 -#define DMFC_WR_CHAN_FIFO_SIZE_1 0x00000038 -#define DMFC_WR_CHAN_ST_ADDR_1 0x00000007 -#define IPU_DMFC_WR_CHAN_DEF 0x00000008 -#define DMFC_WR_CHAN_DEF_WM_CLR_2C 0xe0000000 -#define DMFC_WR_CHAN_DEF_WM_SET_2C 0x1c000000 -#define DMFC_WR_CHAN_DEF_WM_EN_2C 0x02000000 -#define DMFC_WR_CHAN_DEF_WM_CLR_1C 0x00e00000 -#define DMFC_WR_CHAN_DEF_WM_SET_1C 0x001c0000 -#define DMFC_WR_CHAN_DEF_WM_EN_1C 0x00020000 -#define DMFC_WR_CHAN_DEF_WM_CLR_2 0x0000e000 -#define DMFC_WR_CHAN_DEF_WM_SET_2 0x00001c00 -#define DMFC_WR_CHAN_DEF_WM_EN_2 0x00000200 -#define DMFC_WR_CHAN_DEF_WM_CLR_1 0x000000e0 -#define DMFC_WR_CHAN_DEF_WM_SET_1 0x0000000c -#define DMFC_WR_CHAN_DEF_WM_EN_1 0x00000002 -#define IPU_DMFC_DP_CHAN 0x0000000c -#define DMFC_DP_CHAN_BUSRT_SIZE_6F 0xc0000000 -#define DMFC_DP_CHAN_FIFO_SIZE_6F 0x38000000 -#define DMFC_DP_CHAN_ST_ADDR_6F 0x07000000 -#define DMFC_DP_CHAN_BURST_SIZE_6B 0x00c00000 -#define DMFC_DP_CHAN_FIFO_SIZE_6B 0x00380000 -#define DMFC_DP_CHAN_ST_ADDR_6B 0x00070000 -#define DMFC_DP_CHAN_BURST_SIZE_5F 0x0000c000 -#define DMFC_DP_CHAN_FIFO_SIZE_5F 0x00003800 -#define DMFC_DP_CHAN_ST_ADDR_5F 0x00000700 -#define DMFC_DP_CHAN_BURST_SIZE_5B 0x000000c0 -#define DMFC_DP_CHAN_FIFO_SIZE_5B 0x00000038 -#define DMFC_DP_CHAN_ST_ADDR_5B 0x00000007 -#define IPU_DMFC_DP_CHAN_DEF 0x00000010 -#define DMFC_DP_CHAN_DEF_WM_CLR_6F 0xe0000000 -#define DMFC_DP_CHAN_DEF_WM_SET_6F 0x1c000000 -#define DMFC_DP_CHAN_DEF_WM_EN_6F 0x02000000 -#define DMFC_DP_CHAN_DEF_WM_CLR_6B 0x00e00000 -#define DMFC_DP_CHAN_DEF_WM_SET_6B 0x001c0000 -#define DMFC_DP_CHAN_DEF_WM_EN_6B 0x00020000 -#define DMFC_DP_CHAN_DEF_WM_CLR_5F 0x0000e000 -#define DMFC_DP_CHAN_DEF_WM_SET_5F 0x00001c00 -#define DMFC_DP_CHAN_DEF_WM_EN_5F 0x00000200 -#define DMFC_DP_CHAN_DEF_WM_CLR_5B 0x000000e0 -#define DMFC_DP_CHAN_DEF_WM_SET_5B 0x0000001c -#define DMFC_DP_CHAN_DEF_WM_EN_5B 0x00000002 -#define IPU_DMFC_GENERAL1 0x00000014 -#define DMFC_GENERAL1_WAIT4EOT_9 0x01000000 -#define DMFC_GENERAL1_WAIT4EOT_6F 0x00800000 -#define DMFC_GENERAL1_WAIT4EOT_6B 0x00400000 -#define DMFC_GENERAL1_WAIT4EOT_5F 0x00200000 -#define DMFC_GENERAL1_WAIT4EOT_5B 0x00100000 -#define DMFC_GENERAL1_WAIT4EOT_4 0x00080000 -#define DMFC_GENERAL1_WAIT4EOT_3 0x00040000 -#define DMFC_GENERAL1_WAIT4EOT_2 0x00020000 -#define DMFC_GENERAL1_WAIT4EOT_1 0x00010000 -#define DMFC_GENERAL1_WM_CLR_9 0x0000e000 -#define DMFC_GENERAL1_WM_SET_9 0x00001c00 -#define DMFC_GENERAL1_BURST_SIZE_9 0x00000060 -#define DMFC_GENERAL1_DCDP_SYNC_PR 0x00000003 -#define DCDP_SYNC_PR_FORBIDDEN 0 -#define DCDP_SYNC_PR_DC_DP 1 -#define DCDP_SYNC_PR_DP_DC 2 -#define DCDP_SYNC_PR_ROUNDROBIN 3 -#define IPU_DMFC_GENERAL2 0x00000018 -#define DMFC_GENERAL2_FRAME_HEIGHT_RD 0x1fff0000 -#define DMFC_GENERAL2_FRAME_WIDTH_RD 0x00001fff -#define IPU_DMFC_IC_CTRL 0x0000001c -#define DMFC_IC_CTRL_IC_FRAME_HEIGHT_RD 0xfff80000 -#define DMFC_IC_CTRL_IC_FRAME_WIDTH_RD 0x0007ffc0 -#define DMFC_IC_CTRL_IC_PPW_C 0x00000030 -#define DMFC_IC_CTRL_IC_IN_PORT 0x00000007 -#define IC_IN_PORT_CH28 0 -#define IC_IN_PORT_CH41 1 -#define IC_IN_PORT_DISABLE 2 -#define IC_IN_PORT_CH23 4 -#define IC_IN_PORT_CH27 5 -#define IC_IN_PORT_CH24 6 -#define IC_IN_PORT_CH29 7 -#define IPU_DMFC_WR_CHAN_ALT 0x00000020 -#define IPU_DMFC_WR_CHAN_DEF_ALT 0x00000024 -#define IPU_DMFC_DP_CHAN_ALT 0x00000028 -#define IPU_DMFC_DP_CHAN_DEF_ALT 0x0000002c -#define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6F_ALT 0xe0000000 -#define DMFC_DP_CHAN_DEF_ALT_WM_SET_6F_ALT 0x1c000000 -#define DMFC_DP_CHAN_DEF_ALT_WM_EN_6F_ALT 0x02000000 -#define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6B_ALT 0x00e00000 -#define DMFC_DP_CHAN_DEF_ALT_WM_SET_6B_ALT 0x001c0000 -#define DMFC_DP_CHAN_DEF_ALT_WM_EN_6B_ALT 0x00020000 -#define DMFC_DP_CHAN_DEF_ALT_WM_CLR_5B_ALT 0x000000e0 -#define DMFC_DP_CHAN_DEF_ALT_WM_SET_5B_ALT 0x0000001c -#define DMFC_DP_CHAN_DEF_ALT_WM_EN_5B_ALT 0x00000002 -#define IPU_DMFC_GENERAL1_ALT 0x00000030 -#define DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT 0x00800000 -#define DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT 0x00400000 -#define DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT 0x00100000 -#define DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT 0x00020000 -#define IPU_DMFC_STAT 0x00000034 -#define DMFC_STAT_IC_BUFFER_EMPTY 0x02000000 -#define DMFC_STAT_IC_BUFFER_FULL 0x01000000 -#define DMFC_STAT_FIFO_EMPTY(n) __BIT(12 + (n)) -#define DMFC_STAT_FIFO_FULL(n) __BIT((n)) - -/* - * VCI - * Video De Interkacing Module - */ -#define IPU_VDI_FSIZE 0x00000000 -#define IPU_VDI_C 0x00000004 - -/* - * DP - * Display Processor - */ -#define IPU_DP_COM_CONF_SYNC 0x00000000 -#define DP_FG_EN_SYNC 0x00000001 -#define DP_DP_GWAM_SYNC 0x00000004 -#define IPU_DP_GRAPH_WIND_CTRL_SYNC 0x00000004 -#define IPU_DP_FG_POS_SYNC 0x00000008 -#define IPU_DP_CUR_POS_SYNC 0x0000000c -#define IPU_DP_CUR_MAP_SYNC 0x00000010 -#define IPU_DP_CSC_SYNC_0 0x00000054 -#define IPU_DP_CSC_SYNC_1 0x00000058 -#define IPU_DP_CUR_POS_ALT 0x0000005c -#define IPU_DP_COM_CONF_ASYNC0 0x00000060 -#define IPU_DP_GRAPH_WIND_CTRL_ASYNC0 0x00000064 -#define IPU_DP_FG_POS_ASYNC0 0x00000068 -#define IPU_DP_CUR_POS_ASYNC0 0x0000006c -#define IPU_DP_CUR_MAP_ASYNC0 0x00000070 -#define IPU_DP_CSC_ASYNC0_0 0x000000b4 -#define IPU_DP_CSC_ASYNC0_1 0x000000b8 -#define IPU_DP_COM_CONF_ASYNC1 0x000000bc -#define IPU_DP_GRAPH_WIND_CTRL_ASYNC1 0x000000c0 -#define IPU_DP_FG_POS_ASYNC1 0x000000c4 -#define IPU_DP_CUR_POS_ASYNC1 0x000000c8 -#define IPU_DP_CUR_MAP_ASYNC1 0x000000cc -#define IPU_DP_CSC_ASYNC1_0 0x00000110 -#define IPU_DP_CSC_ASYNC1_1 0x00000114 - -/* IDMA parameter */ - /* - * non-Interleaved parameter - * - * param 0: XV W0[ 9: 0] - * YV W0[18:10] - * XB W0[31:19] - * param 1: YB W0[43:32] - * NSB W0[44] - * CF W0[45] - * UBO W0[61:46] - * param 2: UBO W0[67:62] - * VBO W0[89:68] - * IOX W0[93:90] - * RDRW W0[94] - * Reserved W0[95] - * param 3: Reserved W0[112:96] - * S0 W0[113] - * BNDM W0[116:114] - * BM W0[118:117] - * ROT W0[119] - * HF W0[120] - * VF W0[121] - * THF W0[122] - * CAP W0[123] - * CAE W0[124] - * FW W0[127:125] - * param 4: FW W0[137:128] - * FH W0[149:138] - * param 5: EBA0 W1[28:0] - * EBA1 W1[31:29] - * param 6: EBA1 W1[57:32] - * ILO W1[63:58] - * param 7: ILO W1[77:64] - * NPB W1[84:78] - * PFS W1[88:85] - * ALU W1[89] - * ALBM W1[92:90] - * ID W1[94:93] - * TH W1[95] - * param 8: TH W1[101:96] - * SLY W1[115:102] - * WID3 W1[127:125] - * param 9: SLUV W1[141:128] - * CRE W1[149] - * - * Interleaved parameter - * - * param 0: XV W0[ 9: 0] - * YV W0[18:10] - * XB W0[31:19] - * param 1: YB W0[43:32] - * NSB W0[44] - * CF W0[45] - * SX W0[57:46] - * SY W0[61:58] - * param 2: SY W0[68:62] - * NS W0[78:69] - * SDX W0[85:79] - * SM W0[95:86] - * param 3: SCC W0[96] - * SCE W0[97] - * SDY W0[104:98] - * SDRX W0[105] - * SDRY W0[106] - * BPP W0[109:107] - * DEC_SEL W0[111:110] - * DIM W0[112] - * SO W0[113] - * BNDM W0[116:114] - * BM W0[118:117] - * ROT W0[119] - * HF W0[120] - * VF W0[121] - * THF W0[122] - * CAP W0[123] - * CAE W0[124] - * FW W0[127:125] - * param 4: FW W0[137:128] - * FH W0[149:138] - * param 5: EBA0 W1[28:0] - * EBA1 W1[31:29] - * param 6: EBA1 W1[57:32] - * ILO W1[63:58] - * param 7: ILO W1[77:64] - * NPB W1[84:78] - * PFS W1[88:85] - * ALU W1[89] - * ALBM W1[92:90] - * ID W1[94:93] - * TH W1[95] - * param 8: TH W1[101:96] - * SL W1[115:102] - * WID0 W1[118:116] - * WID1 W1[121:119] - * WID2 W1[124:122] - * WID3 W1[127:125] - * param 9: OFS0 W1[132:128] - * OFS1 W1[137:133] - * OFS2 W1[142:138] - * OFS3 W1[147:143] - * SXYS W1[148] - * CRE W1[149] - * DEC_SEL2 W1[150] - */ - -#define __IDMA_PARAM(word, shift, size) \ - ((((word) & 0xff) << 16) | (((shift) & 0xff) << 8) | ((size) & 0xff)) - -/* non-Interleaved parameter */ -/* W0 */ -#define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10) -#define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9) -#define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13) -#define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12) -#define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1) -#define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1) -#define IDMAC_Ch_PARAM_UBO __IDMA_PARAM(0, 46, 22) -#define IDMAC_Ch_PARAM_VBO __IDMA_PARAM(0, 68, 22) -#define IDMAC_Ch_PARAM_IOX __IDMA_PARAM(0, 90, 4) -#define IDMAC_Ch_PARAM_RDRW __IDMA_PARAM(0, 94, 1) -#define IDMAC_Ch_PARAM_S0 __IDMA_PARAM(0,113, 1) -#define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3) -#define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2) -#define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1) -#define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1) -#define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1) -#define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1) -#define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1) -#define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1) -#define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13) -#define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12) -/* W1 */ -#define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29) -#define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29) -#define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20) -#define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7) -#define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4) -#define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1) -#define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3) -#define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2) -#define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7) -#define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14) -#define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3) -#define IDMAC_Ch_PARAM_SLUV __IDMA_PARAM(1,128, 14) -#define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1) - -/* Interleaved parameter */ -/* W0 */ -#define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10) -#define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9) -#define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13) -#define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12) -#define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1) -#define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1) -#define IDMAC_Ch_PARAM_SX __IDMA_PARAM(0, 46, 12) -#define IDMAC_Ch_PARAM_SY __IDMA_PARAM(0, 58, 11) -#define IDMAC_Ch_PARAM_NS __IDMA_PARAM(0, 69, 10) -#define IDMAC_Ch_PARAM_SDX __IDMA_PARAM(0, 79, 7) -#define IDMAC_Ch_PARAM_SM __IDMA_PARAM(0, 86, 10) -#define IDMAC_Ch_PARAM_SCC __IDMA_PARAM(0, 96, 1) -#define IDMAC_Ch_PARAM_SCE __IDMA_PARAM(0, 97, 1) -#define IDMAC_Ch_PARAM_SDY __IDMA_PARAM(0, 98, 7) -#define IDMAC_Ch_PARAM_SDRX __IDMA_PARAM(0,105, 1) -#define IDMAC_Ch_PARAM_SDRY __IDMA_PARAM(0,106, 1) -#define IDMAC_Ch_PARAM_BPP __IDMA_PARAM(0,107, 3) -#define IDMAC_Ch_PARAM_DEC_SEL __IDMA_PARAM(0,110, 2) -#define IDMAC_Ch_PARAM_DIM __IDMA_PARAM(0,112, 1) -#define IDMAC_Ch_PARAM_SO __IDMA_PARAM(0,113, 1) -#define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3) -#define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2) -#define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1) -#define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1) -#define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1) -#define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1) -#define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1) -#define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1) -#define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13) -#define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12) -/* W1 */ -#define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29) -#define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29) -#define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20) -#define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7) -#define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4) -#define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1) -#define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3) -#define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2) -#define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7) -#define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14) -#define IDMAC_Ch_PARAM_WID0 __IDMA_PARAM(1,116, 3) -#define IDMAC_Ch_PARAM_WID1 __IDMA_PARAM(1,119, 3) -#define IDMAC_Ch_PARAM_WID2 __IDMA_PARAM(1,122, 3) -#define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3) -#define IDMAC_Ch_PARAM_OFS0 __IDMA_PARAM(1,128, 5) -#define IDMAC_Ch_PARAM_OFS1 __IDMA_PARAM(1,133, 5) -#define IDMAC_Ch_PARAM_OFS2 __IDMA_PARAM(1,138, 5) -#define IDMAC_Ch_PARAM_OFS3 __IDMA_PARAM(1,143, 5) -#define IDMAC_Ch_PARAM_SXYS __IDMA_PARAM(1,148, 1) -#define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1) -#define IDMAC_Ch_PARAM_DEC_SEL2 __IDMA_PARAM(1,150, 1) - -/* XXX Temp */ -#define GPUMEM_BASE 0x20000000 -#define GPUMEM_SIZE 0x20000 - -#define GPU_BASE 0x30000000 -#define GPU_SIZE 0x10000000 - -/* - * Image Processing Unit - * - * All addresses are relative to the base SoC address. - */ -#define IPU_CM_BASE(_base) ((_base) + 0x1e000000) -#define IPU_CM_SIZE 0x8000 -#define IPU_IDMAC_BASE(_base) ((_base) + 0x1e008000) -#define IPU_IDMAC_SIZE 0x8000 -#define IPU_DP_BASE(_base) ((_base) + 0x1e018000) -#define IPU_DP_SIZE 0x8000 -#define IPU_IC_BASE(_base) ((_base) + 0x1e020000) -#define IPU_IC_SIZE 0x8000 -#define IPU_IRT_BASE(_base) ((_base) + 0x1e028000) -#define IPU_IRT_SIZE 0x8000 -#define IPU_CSI0_BASE(_base) ((_base) + 0x1e030000) -#define IPU_CSI0_SIZE 0x8000 -#define IPU_CSI1_BASE(_base) ((_base) + 0x1e038000) -#define IPU_CSI1_SIZE 0x8000 -#define IPU_DI0_BASE(_base) ((_base) + 0x1e040000) -#define IPU_DI0_SIZE 0x8000 -#define IPU_DI1_BASE(_base) ((_base) + 0x1e048000) -#define IPU_DI1_SIZE 0x8000 -#define IPU_SMFC_BASE(_base) ((_base) + 0x1e050000) -#define IPU_SMFC_SIZE 0x8000 -#define IPU_DC_BASE(_base) ((_base) + 0x1e058000) -#define IPU_DC_SIZE 0x8000 -#define IPU_DMFC_BASE(_base) ((_base) + 0x1e060000) -#define IPU_DMFC_SIZE 0x8000 -#define IPU_VDI_BASE(_base) ((_base) + 0x1e068000) -#define IPU_VDI_SIZE 0x8000 -#define IPU_CPMEM_BASE(_base) ((_base) + 0x1f000000) -#define IPU_CPMEM_SIZE 0x20000 -#define IPU_LUT_BASE(_base) ((_base) + 0x1f020000) -#define IPU_LUT_SIZE 0x20000 -#define IPU_SRM_BASE(_base) ((_base) + 0x1f040000) -#define IPU_SRM_SIZE 0x20000 -#define IPU_TPM_BASE(_base) ((_base) + 0x1f060000) -#define IPU_TPM_SIZE 0x20000 -#define IPU_DCTMPL_BASE(_base) ((_base) + 0x1f080000) -#define IPU_DCTMPL_SIZE 0x20000 - -#endif /* _ARM_IMX_IMX51_IPUV3REG_H */ diff --git a/sys/arm/freescale/imx/imx51_machdep.c b/sys/arm/freescale/imx/imx51_machdep.c deleted file mode 100644 --- a/sys/arm/freescale/imx/imx51_machdep.c +++ /dev/null @@ -1,102 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2013 Ian Lepore - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include "opt_platform.h" - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include - -#include "platform_if.h" - -static platform_attach_t imx51_attach; -static platform_devmap_init_t imx51_devmap_init; -static platform_cpu_reset_t imx51_cpu_reset; - -static int -imx51_attach(platform_t plat) -{ - - /* XXX - Get rid of this stuff soon. */ - boothowto |= RB_VERBOSE|RB_MULTIPLE; - bootverbose = 1; - - return (0); -} - -/* - * Set up static device mappings. This is hand-optimized platform-specific - * config data which covers most of the common on-chip devices with a few 1MB - * section mappings. - * - * Notably missing are entries for GPU, IPU, in general anything video related. - */ -static int -imx51_devmap_init(platform_t plat) -{ - - devmap_add_entry(0x70000000, 0x00100000); - devmap_add_entry(0x73f00000, 0x00100000); - devmap_add_entry(0x83f00000, 0x00100000); - - return (0); -} - -static void -imx51_cpu_reset(platform_t plat) -{ - - imx_wdog_cpu_reset(0x73F98000); -} - -u_int -imx_soc_type(void) -{ - return (IMXSOC_51); -} - -static platform_method_t imx51_methods[] = { - PLATFORMMETHOD(platform_attach, imx51_attach), - PLATFORMMETHOD(platform_devmap_init, imx51_devmap_init), - PLATFORMMETHOD(platform_cpu_reset, imx51_cpu_reset), - - PLATFORMMETHOD_END, -}; - -FDT_PLATFORM_DEF(imx51, "i.MX51", 0, "fsl,imx51", 100); diff --git a/sys/arm/freescale/imx/imx51_sdmareg.h b/sys/arm/freescale/imx/imx51_sdmareg.h deleted file mode 100644 --- a/sys/arm/freescale/imx/imx51_sdmareg.h +++ /dev/null @@ -1,141 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * - * This software was developed by Oleksandr Rybalko under sponsorship - * from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* Internal Registers definition for Freescale i.MX515 SDMA Core */ - -/* SDMA Core Instruction Memory Space */ -#define SDMA_IBUS_ROM_ADDR_BASE 0x0000 -#define SDMA_IBUS_ROM_ADDR_SIZE 0x07ff -#define SDMA_IBUS_RAM_ADDR_BASE 0x1000 -#define SDMA_IBUS_RAM_ADDR_SIZE 0x1fff - -/* SDMA Core Internal Registers */ -#define SDMA_MC0PTR 0x7000 /* AP (MCU) Channel 0 Pointer R */ - -#define SDMA_CCPTR 0x7002 /* Current Channel Pointer R */ -#define SDMA_ECTL_CCPTR_MASK 0x0000ffff -#define SDMA_ECTL_CCPTR_SHIFT 0 - -#define SDMA_CCR 0x7003 /* Current Channel Register R */ -#define SDMA_ECTL_CCR_MASK 0x0000001f -#define SDMA_ECTL_CCR_SHIFT 0 - -#define SDMA_NCR 0x7004 /* Highest Pending Channel Register R */ -#define SDMA_ECTL_NCR_MASK 0x0000001f -#define SDMA_ECTL_NCR_SHIFT 0 - -#define SDMA_EVENTS 0x7005 /* External DMA Requests Mirror R */ - -#define SDMA_CCPRI 0x7006 /* Current Channel Priority R */ -#define SDMA_ECTL_CCPRI_MASK 0x00000007 -#define SDMA_ECTL_CCPRI_SHIFT 0 - -#define SDMA_NCPRI 0x7007 /* Next Channel Priority R */ -#define SDMA_ECTL_NCPRI_MASK 0x00000007 -#define SDMA_ECTL_NCPRI_SHIFT 0 - -#define SDMA_ECOUNT 0x7009 /* OnCE Event Cell Counter R/W */ -#define SDMA_ECTL_ECOUNT_MASK 0x0000ffff -#define SDMA_ECTL_ECOUNT_SHIFT 0 - -#define SDMA_ECTL 0x700A /* OnCE Event Cell Control Register R/W */ -#define SDMA_ECTL_EN (1 << 13) -#define SDMA_ECTL_CNT (1 << 12) -#define SDMA_ECTL_ECTC_MASK 0x00000c00 -#define SDMA_ECTL_ECTC_SHIFT 10 -#define SDMA_ECTL_DTC_MASK 0x00000300 -#define SDMA_ECTL_DTC_SHIFT 8 -#define SDMA_ECTL_ATC_MASK 0x000000c0 -#define SDMA_ECTL_ATC_SHIFT 6 -#define SDMA_ECTL_ABTC_MASK 0x00000030 -#define SDMA_ECTL_ABTC_SHIFT 4 -#define SDMA_ECTL_AATC_MASK 0x0000000c -#define SDMA_ECTL_AATC_SHIFT 2 -#define SDMA_ECTL_ATS_MASK 0x00000003 -#define SDMA_ECTL_ATS_SHIFT 0 - -#define SDMA_EAA 0x700B /* OnCE Event Address Register A R/W */ -#define SDMA_ECTL_EAA_MASK 0x0000ffff -#define SDMA_ECTL_EAA_SHIFT 0 - -#define SDMA_EAB 0x700C /* OnCE Event Cell Address Register B R/W */ -#define SDMA_ECTL_EAB_MASK 0x0000ffff -#define SDMA_ECTL_EAB_SHIFT 0 - -#define SDMA_EAM 0x700D /* OnCE Event Cell Address Mask R/W */ -#define SDMA_ECTL_EAM_MASK 0x0000ffff -#define SDMA_ECTL_EAM_SHIFT 0 - -#define SDMA_ED 0x700E /* OnCE Event Cell Data Register R/W */ -#define SDMA_EDM 0x700F /* OnCE Event Cell Data Mask R/W */ -#define SDMA_RTB 0x7018 /* OnCE Real-Time Buffer R/W */ - -#define SDMA_TB 0x7019 /* OnCE Trace Buffer R */ -#define SDMA_TB_TBF (1 << 28) -#define SDMA_TB_TADDR_MASK 0x0fffc000 -#define SDMA_TB_TADDR_SHIFT 14 -#define SDMA_TB_CHFADDR_MASK 0x00003fff -#define SDMA_TB_CHFADDR_SHIFT 0 - -#define SDMA_OSTAT 0x701A /* OnCE Status R */ -#define SDMA_OSTAT_PST_MASK 0x0000f000 -#define SDMA_OSTAT_PST_SHIFT 12 -#define SDMA_OSTAT_RCV (1 << 11) -#define SDMA_OSTAT_EDR (1 << 10) -#define SDMA_OSTAT_ODR (1 << 9) -#define SDMA_OSTAT_SWB (1 << 8) -#define SDMA_OSTAT_MST (1 << 7) -#define SDMA_OSTAT_ECDR_MASK 0x00000007 -#define SDMA_OSTAT_ECDR_SHIFT 0 - -#define SDMA_MCHN0ADDR 0x701C /* Channel 0 Boot Address R */ -#define SDMA_MCHN0ADDR_SMS_Z (1 << 14) -#define SDMA_MCHN0ADDR_CHN0ADDR_MASK 0x00003fff -#define SDMA_MCHN0ADDR_CHN0ADDR_SHIFT 0 - -#define SDMA_MODE 0x701D /* Mode Status Register R */ -#define SDMA_MODE_DSPCtrl (1 << 3) -#define SDMA_MODE_AP_END (1 << 0) - -#define SDMA_LOCK 0x701E /* Lock Status Register R */ -#define SDMA_LOCK_LOCK (1 << 0) - -#define SDMA_EVENTS2 0x701F /* External DMA Requests Mirror #2 R */ - -#define SDMA_HE 0x7020 /* AP Enable Register R */ -#define SDMA_PRIV 0x7022 /* Current Channel BP Privilege Register R */ -#define SDMA_PRIV_BPPRIV (1 << 0) -#define SDMA_PRF_CNT 0x7023 /* Profile Free Running Register R/W */ -#define SDMA_PRF_CNT_SEL_MASK 0xc0000000 -#define SDMA_PRF_CNT_SEL_SHIFT 30 -#define SDMA_PRF_CNT_EN (1 << 29) -#define SDMA_PRF_CNT_OFL (1 << 22) -#define SDMA_PRF_CNT_COUNTER_MASK 0x003fffff -#define SDMA_PRF_CNT_COUNTER_SHIFT 0 diff --git a/sys/arm/freescale/imx/imx51_ssireg.h b/sys/arm/freescale/imx/imx51_ssireg.h deleted file mode 100644 --- a/sys/arm/freescale/imx/imx51_ssireg.h +++ /dev/null @@ -1,179 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * - * This software was developed by Oleksandr Rybalko under sponsorship - * from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* Registers definition for Freescale i.MX515 Synchronous Serial Interface */ - -#define IMX51_SSI_STX0_REG 0x0000 /* SSI TX Data Register 0 */ -#define IMX51_SSI_STX1_REG 0x0004 /* SSI TX Data Register 1 */ -#define IMX51_SSI_SRX0_REG 0x0008 /* SSI RX Data Register 0 */ -#define IMX51_SSI_SRX1_REG 0x000C /* SSI RX Data Register 1 */ -#define IMX51_SSI_SCR_REG 0x0010 /* SSI Control Register */ -#define SSI_SCR_RFR_CLK_DIS (1 << 11) /* RX FC Disable */ -#define SSI_SCR_TFR_CLK_DIS (1 << 10) /* TX FC Disable */ -#define SSI_SCR_CLK_IST (1 << 9) /* Clock Idle */ -#define SSI_SCR_TCH_EN (1 << 8) /* 2Chan Enable */ -#define SSI_SCR_SYS_CLK_EN (1 << 7) /* System Clock En */ -#define SSI_SCR_MODE_NORMAL (0 << 5) -#define SSI_SCR_MODE_I2S_MASTER (1 << 5) -#define SSI_SCR_MODE_I2S_SLAVE (2 << 5) -#define SSI_SCR_MODE_MASK (3 << 5) -#define SSI_SCR_SYN (1 << 4) /* Sync Mode */ -#define SSI_SCR_NET (1 << 3) /* Network Mode */ -#define SSI_SCR_RE (1 << 2) /* RX Enable */ -#define SSI_SCR_TE (1 << 1) /* TX Enable */ -#define SSI_SCR_SSIEN (1 << 0) /* SSI Enable */ - -#define IMX51_SSI_SISR_REG 0x0014 /* SSI Interrupt Status Register */ -#define SSI_SISR_RFRC (1 << 24) /* RX Frame Complete */ -#define SSI_SIR_TFRC (1 << 23) /* TX Frame Complete */ -#define SSI_SIR_CMDAU (1 << 18) /* Command Address Updated */ -#define SSI_SIR_CMDDU (1 << 17) /* Command Data Updated */ -#define SSI_SIR_RXT (1 << 16) /* RX Tag Updated */ -#define SSI_SIR_RDR1 (1 << 15) /* RX Data Ready 1 */ -#define SSI_SIR_RDR0 (1 << 14) /* RX Data Ready 0 */ -#define SSI_SIR_TDE1 (1 << 13) /* TX Data Reg Empty 1 */ -#define SSI_SIR_TDE0 (1 << 12) /* TX Data Reg Empty 0 */ -#define SSI_SIR_ROE1 (1 << 11) /* RXer Overrun Error 1 */ -#define SSI_SIR_ROE0 (1 << 10) /* RXer Overrun Error 0 */ -#define SSI_SIR_TUE1 (1 << 9) /* TXer Underrun Error 1 */ -#define SSI_SIR_TUE0 (1 << 8) /* TXer Underrun Error 0 */ -#define SSI_SIR_TFS (1 << 7) /* TX Frame Sync */ -#define SSI_SIR_RFS (1 << 6) /* RX Frame Sync */ -#define SSI_SIR_TLS (1 << 5) /* TX Last Time Slot */ -#define SSI_SIR_RLS (1 << 4) /* RX Last Time Slot */ -#define SSI_SIR_RFF1 (1 << 3) /* RX FIFO Full 1 */ -#define SSI_SIR_RFF0 (1 << 2) /* RX FIFO Full 0 */ -#define SSI_SIR_TFE1 (1 << 1) /* TX FIFO Empty 1 */ -#define SSI_SIR_TFE0 (1 << 0) /* TX FIFO Empty 0 */ - -#define IMX51_SSI_SIER_REG 0x0018 /* SSI Interrupt Enable Register */ -/* 24-23 Enable Bit (See SISR) */ -#define SSI_SIER_RDMAE (1 << 22) /* RX DMA Enable */ -#define SSI_SIER_RIE (1 << 21) /* RX Interrupt Enable */ -#define SSI_SIER_TDMAE (1 << 20) /* TX DMA Enable */ -#define SSI_SIER_TIE (1 << 19) /* TX Interrupt Enable */ -/* 18-0 Enable Bits (See SISR) */ - -#define IMX51_SSI_STCR_REG 0x001C /* SSI TX Configuration Register */ -#define SSI_STCR_TXBIT0 (1 << 9) /* TX Bit 0 */ -#define SSI_STCR_TFEN1 (1 << 8) /* TX FIFO Enable 1 */ -#define SSI_STCR_TFEN0 (1 << 7) /* TX FIFO Enable 0 */ -#define SSI_STCR_TFDIR (1 << 6) /* TX Frame Direction */ -#define SSI_STCR_TXDIR (1 << 5) /* TX Clock Direction */ -#define SSI_STCR_TSHFD (1 << 4) /* TX Shift Direction */ -#define SSI_STCR_TSCKP (1 << 3) /* TX Clock Polarity */ -#define SSI_STCR_TFSI (1 << 2) /* TX Frame Sync Invert */ -#define SSI_STCR_TFSL (1 << 1) /* TX Frame Sync Length */ -#define SSI_STCR_TEFS (1 << 0) /* TX Early Frame Sync */ - -#define IMX51_SSI_SRCR_REG 0x0020 /* SSI RX Configuration Register */ -#define SSI_SRCR_RXEXT (1 << 10) /* RX Data Extension */ -#define SSI_SRCR_RXBIT0 (1 << 9) /* RX Bit 0 */ -#define SSI_SRCR_RFEN1 (1 << 8) /* RX FIFO Enable 1 */ -#define SSI_SRCR_RFEN0 (1 << 7) /* RX FIFO Enable 0 */ -#define SSI_SRCR_RFDIR (1 << 6) /* RX Frame Direction */ -#define SSI_SRCR_RXDIR (1 << 5) /* RX Clock Direction */ -#define SSI_SRCR_RSHFD (1 << 4) /* RX Shift Direction */ -#define SSI_SRCR_RSCKP (1 << 3) /* RX Clock Polarity */ -#define SSI_SRCR_RFSI (1 << 2) /* RX Frame Sync Invert */ -#define SSI_SRCR_RFSL (1 << 1) /* RX Frame Sync Length */ -#define SSI_SRCR_REFS (1 << 0) /* RX Early Frame Sync */ - -#define IMX51_SSI_STCCR_REG 0x0024 /* TX Clock Control */ -#define IMX51_SSI_SRCCR_REG 0x0028 /* RX Clock Control */ -#define SSI_SXCCR_DIV2 (1 << 18) /* Divide By 2 */ -#define SSI_SXCCR_PSR (1 << 17) /* Prescaler Range */ -#define SSI_SXCCR_WL_MASK 0x0001e000 -#define SSI_SXCCR_WL_SHIFT 13 /* Word Length Control */ -#define SSI_SXCCR_DC_MASK 0x00001f00 -#define SSI_SXCCR_DC_SHIFT 8 /* Frame Rate Divider */ -#define SSI_SXCCR_PM_MASK 0x000000ff -#define SSI_SXCCR_PM_SHIFT 0 /* Prescaler Modulus */ - -#define IMX51_SSI_SFCSR_REG 0x002C /* SSI FIFO Control/Status Register */ -#define SSI_SFCSR_RFCNT1_MASK 0xf0000000 -#define SSI_SFCSR_RFCNT1_SHIFT 28 /* RX FIFO Counter 1 */ -#define SSI_SFCSR_TFCNT1_MASK 0x0f000000 -#define SSI_SFCSR_TFCNT1_SHIFT 24 /* TX FIFO Counter 1 */ -#define SSI_SFCSR_RFWM1_MASK 0x00f00000 -#define SSI_SFCSR_RFWM1_SHIFT 20 /* RX FIFO Full WaterMark 1 */ -#define SSI_SFCSR_TFWM1_MASK 0x000f0000 -#define SSI_SFCSR_TFWM1_SHIFT 16 /* TX FIFO Empty WaterMark 1 */ -#define SSI_SFCSR_RFCNT0_MASK 0x0000f000 -#define SSI_SFCSR_RFCNT0_SHIFT 12 /* RX FIFO Counter 0 */ -#define SSI_SFCSR_TFCNT0_MASK 0x00000f00 -#define SSI_SFCSR_TFCNT0_SHIFT 8 /* TX FIFO Counter 0 */ -#define SSI_SFCSR_RFWM0_MASK 0x000000f0 -#define SSI_SFCSR_RFWM0_SHIFT 4 /* RX FIFO Full WaterMark 0 */ -#define SSI_SFCSR_TFWM0_MASK 0x0000000f -#define SSI_SFCSR_TFWM0_SHIFT 0 /* TX FIFO Empty WaterMark 0 */ - -#define IMX51_SSI_STR_REG 0x0030 /* SSI Test Register1 */ -#define SSI_STR_TEST (1 << 15) /* Test Mode */ -#define SSI_STR_RCK2TCK (1 << 14) /* RX<->TX Clock Loop Back */ -#define SSI_STR_RFS2TFS (1 << 13) /* RX<->TX Frame Loop Back */ -#define SSI_STR_RXSTATE_MASK 0x00001f00 -#define SSI_STR_RXSTATE_SHIFT 8 /* RXer State Machine Status */ -#define SSI_STR_TXD2RXD (1 << 7) /* TX<->RX Data Loop Back */ -#define SSI_STR_TCK2RCK (1 << 6) /* TX<->RX Clock Loop Back */ -#define SSI_STR_TFS2RFS (1 << 5) /* TX<->RX Frame Loop Back */ -#define SSI_STR_TXSTATE_MASK 0x0000001f -#define SSI_STR_TXSTATE_SHIFT 0 /* TXer State Machine Status */ - -#define IMX51_SSI_SOR_REG 0x0034 /* SSI Option Register2 */ -#define SSI_SOR_CLKOFF (1 << 6) /* Clock Off */ -#define SSI_SOR_RX_CLR (1 << 5) /* RXer Clear */ -#define SSI_SOR_TX_CLR (1 << 4) /* TXer Clear */ -#define SSI_SOR_INIT (1 << 3) /* Initialize */ -#define SSI_SOR_WAIT_MASK 0x00000006 -#define SSI_SOR_INIT_SHIFT 1 /* Wait */ -#define SSI_SOR_SYNRST (1 << 0) /* Frame Sync Reset */ - -#define IMX51_SSI_SACNT_REG 0x0038 /* SSI AC97 Control Register */ -#define SSI_SACNT_FRDIV_MASK 0x000007e0 -#define SSI_SACNT_FRDIV_SHIFT 5 /* Frame Rate Divider */ -#define SSI_SACNT_WR (1 << 4) /* Write Command */ -#define SSI_SACNT_RD (1 << 3) /* Read Command */ -#define SSI_SACNT_TIF (1 << 2) /* Tag in FIFO */ -#define SSI_SACNT_FV (1 << 1) /* Fixed/Variable Operation */ -#define SSI_SACNT_AC97EN (1 << 0) /* AC97 Mode Enable */ - -#define IMX51_SSI_SACADD_REG 0x003C /* SSI AC97 Command Address Register */ -#define SSI_SACADD_MASK 0x0007ffff -#define IMX51_SSI_SACDAT_REG 0x0040 /* SSI AC97 Command Data Register */ -#define SSI_SACDAT_MASK 0x000fffff -#define IMX51_SSI_SATAG_REG 0x0044 /* SSI AC97 Tag Register */ -#define SSI_SATAG_MASK 0x0000ffff -#define IMX51_SSI_STMSK_REG 0x0048 /* SSI TX Time Slot Mask Register */ -#define IMX51_SSI_SRMSK_REG 0x004C /* SSI RX Time Slot Mask Register */ -#define IMX51_SSI_SACCST_REG 0x0050 /* SSI AC97 Channel Status Register */ -#define IMX51_SSI_SACCEN_REG 0x0054 /* SSI AC97 Channel Enable Register */ -#define IMX51_SSI_SACCDIS_REG 0x0058 /* SSI AC97 Channel Disable Register */ -#define SSI_SAC_MASK 0x000003ff /* SACCST,SACCEN,SACCDIS */ diff --git a/sys/arm/freescale/imx/imx51_tzicreg.h b/sys/arm/freescale/imx/imx51_tzicreg.h deleted file mode 100644 --- a/sys/arm/freescale/imx/imx51_tzicreg.h +++ /dev/null @@ -1,85 +0,0 @@ -/* $NetBSD: imx51_tzicreg.h,v 1.1 2010/11/13 07:11:03 bsh Exp $ */ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2010 Genetec Corporation. All rights reserved. - * Written by Hashimoto Kenichi for Genetec Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Oleksandr Rybalko - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _IMX51_TZICREG_H_ -#define _IMX51_TZICREG_H_ - -#include - -#define TZIC_SIZE 0x4000 -#define TZIC_INTCNTL 0x0000 -#define INTCNTL_NSEN_MASK 0x80000000 -#define INTCNTL_NSEN 0x00010000 -#define INTCNTL_EN 0x00000001 -#define TZIC_INTTYPE 0x0004 -#define TZIC_PRIOMASK 0x000c -#define TZIC_SYNCCTRL 0x0010 -#define TZIC_DSMINT 0x0014 -#define TZIC_INTSEC(n) (0x0080 + 0x04 * (n)) -#define TZIC_ENSET(n) (0x0100 + 0x04 * (n)) -#define TZIC_ENCLEAR(n) (0x0180 + 0x04 * (n)) -#define TZIC_SRCSET(n) (0x0200 + 0x04 * (n)) -#define TZIC_SRCCLAR(n) (0x0280 + 0x04 * (n)) -#define TZIC_PRIORITY(n) (0x0400 + 0x04 * (n)) -#define TZIC_PND(n) (0x0d00 + 0x04 * (n)) -#define TZIC_HIPND(n) (0x0d80 + 0x04 * (n)) -#define TZIC_WAKEUP(n) (0x0e00 + 0x04 * (n)) -#define TZIC_SWINT 0x0f00 - -#define TZIC_INTNUM 128 -#endif /* _IMX51_TZICRREG_H_ */ diff --git a/sys/arm/freescale/imx/imx53_machdep.c b/sys/arm/freescale/imx/imx53_machdep.c deleted file mode 100644 --- a/sys/arm/freescale/imx/imx53_machdep.c +++ /dev/null @@ -1,98 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2013 Ian Lepore - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include "opt_platform.h" - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include - -#include "platform_if.h" - -static platform_attach_t imx53_attach; -static platform_devmap_init_t imx53_devmap_init; -static platform_cpu_reset_t imx53_cpu_reset; - -static int -imx53_attach(platform_t plat) -{ - - return (0); -} - -/* - * Set up static device mappings. This is hand-optimized platform-specific - * config data which covers most of the common on-chip devices with a few 1MB - * section mappings. - * - * Notably missing are entries for GPU, IPU, in general anything video related. - */ -static int -imx53_devmap_init(platform_t plat) -{ - - devmap_add_entry(0x50000000, 0x00100000); - devmap_add_entry(0x53f00000, 0x00100000); - devmap_add_entry(0x63f00000, 0x00100000); - - return (0); -} - -static void -imx53_cpu_reset(platform_t plat) -{ - - imx_wdog_cpu_reset(0x53F98000); -} - -u_int -imx_soc_type(void) -{ - return (IMXSOC_53); -} - -static platform_method_t imx53_methods[] = { - PLATFORMMETHOD(platform_attach, imx53_attach), - PLATFORMMETHOD(platform_devmap_init, imx53_devmap_init), - PLATFORMMETHOD(platform_cpu_reset, imx53_cpu_reset), - - PLATFORMMETHOD_END, -}; - -FDT_PLATFORM_DEF(imx53, "i.MX53", 0, "fsl,imx53", 100); diff --git a/sys/arm/freescale/imx/imx_nop_usbphy.c b/sys/arm/freescale/imx/imx_nop_usbphy.c deleted file mode 100644 --- a/sys/arm/freescale/imx/imx_nop_usbphy.c +++ /dev/null @@ -1,115 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2013 Ian Lepore - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -/* - * USBPHY "no-op" driver for Freescale family of SoCs. This driver is used on - * SoCs which have usbphy hardware whose clocks need to be enabled, but no other - * action has to be taken to make the hardware work. - */ - -#include "opt_bus.h" - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include - -/* - * Table of supported FDT compat strings. - */ -static struct ofw_compat_data compat_data[] = { - {"nop-usbphy", true}, - {"usb-nop-xceiv", true}, - {NULL, false}, -}; - -struct usbphy_softc { - device_t dev; - u_int phy_num; -}; - -static int -usbphy_detach(device_t dev) -{ - - return (0); -} - -static int -usbphy_attach(device_t dev) -{ - - /* - * Turn on the phy clocks. - */ - imx_ccm_usbphy_enable(dev); - - return (0); -} - -static int -usbphy_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { - device_set_desc(dev, "Freescale USB PHY"); - return (BUS_PROBE_DEFAULT); - } - - return (ENXIO); -} - -static device_method_t usbphy_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, usbphy_probe), - DEVMETHOD(device_attach, usbphy_attach), - DEVMETHOD(device_detach, usbphy_detach), - - DEVMETHOD_END -}; - -static driver_t usbphy_driver = { - "usbphy", - usbphy_methods, - sizeof(struct usbphy_softc) -}; - -DRIVER_MODULE(usbphy, simplebus, usbphy_driver, 0, 0); diff --git a/sys/arm/freescale/imx/std.imx51 b/sys/arm/freescale/imx/std.imx51 deleted file mode 100644 --- a/sys/arm/freescale/imx/std.imx51 +++ /dev/null @@ -1,5 +0,0 @@ -machine arm armv7 -cpu CPU_CORTEXA -makeoptions CONF_CFLAGS="-march=armv7a" - -files "../freescale/imx/files.imx5" diff --git a/sys/arm/freescale/imx/std.imx53 b/sys/arm/freescale/imx/std.imx53 deleted file mode 100644 --- a/sys/arm/freescale/imx/std.imx53 +++ /dev/null @@ -1,5 +0,0 @@ -machine arm armv7 -cpu CPU_CORTEXA -makeoptions CONF_CFLAGS="-march=armv7a" - -files "../freescale/imx/files.imx5" diff --git a/sys/arm/freescale/imx/tzic.c b/sys/arm/freescale/imx/tzic.c deleted file mode 100644 --- a/sys/arm/freescale/imx/tzic.c +++ /dev/null @@ -1,306 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2012, 2013 The FreeBSD Foundation - * - * This software was developed by Oleksandr Rybalko under sponsorship - * from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include - -#include "pic_if.h" - -#define TZIC_NIRQS 128 - -struct tzic_irqsrc { - struct intr_irqsrc isrc; - u_int irq; -}; - -struct tzic_softc { - device_t dev; - struct resource *tzicregs; - struct tzic_irqsrc isrcs[TZIC_NIRQS]; -}; - -static struct tzic_softc *tzic_sc; - -static inline uint32_t -tzic_read_4(struct tzic_softc *sc, int reg) -{ - - return (bus_read_4(sc->tzicregs, reg)); -} - -static inline void -tzic_write_4(struct tzic_softc *sc, int reg, uint32_t val) -{ - - bus_write_4(sc->tzicregs, reg, val); -} - -static inline void -tzic_irq_eoi(struct tzic_softc *sc) -{ - - tzic_write_4(sc, TZIC_PRIOMASK, 0xff); -} - -static inline void -tzic_irq_mask(struct tzic_softc *sc, u_int irq) -{ - - tzic_write_4(sc, TZIC_ENCLEAR(irq >> 5), (1u << (irq & 0x1f))); -} - -static inline void -tzic_irq_unmask(struct tzic_softc *sc, u_int irq) -{ - - tzic_write_4(sc, TZIC_ENSET(irq >> 5), (1u << (irq & 0x1f))); -} - -static int -tzic_intr(void *arg) -{ - struct tzic_softc *sc = arg; - int b, i, irq; - uint32_t pending; - - /* Get active interrupt */ - for (i = 0; i < TZIC_NIRQS / 32; ++i) { - pending = tzic_read_4(sc, TZIC_PND(i)); - if ((b = 31 - __builtin_clz(pending)) < 0) - continue; - irq = i * 32 + b; - tzic_write_4(sc, TZIC_PRIOMASK, 0); - if (intr_isrc_dispatch(&sc->isrcs[irq].isrc, - curthread->td_intr_frame) != 0) { - tzic_irq_mask(sc, irq); - tzic_irq_eoi(sc); - arm_irq_memory_barrier(irq); - if (bootverbose) { - device_printf(sc->dev, - "Stray irq %u disabled\n", irq); - } - } - return (FILTER_HANDLED); - } - - if (bootverbose) - device_printf(sc->dev, "Spurious interrupt detected\n"); - - return (FILTER_HANDLED); -} - -static void -tzic_enable_intr(device_t dev, struct intr_irqsrc *isrc) -{ - u_int irq = ((struct tzic_irqsrc *)isrc)->irq; - struct tzic_softc *sc = device_get_softc(dev); - - arm_irq_memory_barrier(irq); - tzic_irq_unmask(sc, irq); -} - -static void -tzic_disable_intr(device_t dev, struct intr_irqsrc *isrc) -{ - u_int irq = ((struct tzic_irqsrc *)isrc)->irq; - struct tzic_softc *sc = device_get_softc(dev); - - tzic_irq_mask(sc, irq); -} - -static int -tzic_map_intr(device_t dev, struct intr_map_data *data, - struct intr_irqsrc **isrcp) -{ - struct intr_map_data_fdt *daf; - struct tzic_softc *sc; - - if (data->type != INTR_MAP_DATA_FDT) - return (ENOTSUP); - - daf = (struct intr_map_data_fdt *)data; - if (daf->ncells != 1 || daf->cells[0] >= TZIC_NIRQS) - return (EINVAL); - - sc = device_get_softc(dev); - *isrcp = &sc->isrcs[daf->cells[0]].isrc; - - return (0); -} - -static void -tzic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) -{ - struct tzic_softc *sc = device_get_softc(dev); - - tzic_irq_mask(sc, ((struct tzic_irqsrc *)isrc)->irq); - tzic_irq_eoi(sc); -} - -static void -tzic_post_ithread(device_t dev, struct intr_irqsrc *isrc) -{ - - tzic_enable_intr(dev, isrc); -} - -static void -tzic_post_filter(device_t dev, struct intr_irqsrc *isrc) -{ - - tzic_irq_eoi(device_get_softc(dev)); -} - -static int -tzic_pic_attach(struct tzic_softc *sc) -{ - struct intr_pic *pic; - const char *name; - intptr_t xref; - int error; - u_int irq; - - name = device_get_nameunit(sc->dev); - for (irq = 0; irq < TZIC_NIRQS; irq++) { - sc->isrcs[irq].irq = irq; - error = intr_isrc_register(&sc->isrcs[irq].isrc, - sc->dev, 0, "%s,%u", name, irq); - if (error != 0) - return (error); - } - - xref = OF_xref_from_node(ofw_bus_get_node(sc->dev)); - pic = intr_pic_register(sc->dev, xref); - if (pic == NULL) - return (ENXIO); - - return (intr_pic_claim_root(sc->dev, xref, tzic_intr, sc, 0)); -} - -static int -tzic_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (ofw_bus_is_compatible(dev, "fsl,tzic")) { - device_set_desc(dev, "TrustZone Interrupt Controller"); - return (BUS_PROBE_DEFAULT); - } - return (ENXIO); -} - -static int -tzic_attach(device_t dev) -{ - struct tzic_softc *sc = device_get_softc(dev); - int i; - - if (tzic_sc) - return (ENXIO); - tzic_sc = sc; - sc->dev = dev; - - i = 0; - sc->tzicregs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, - RF_ACTIVE); - if (sc->tzicregs == NULL) { - device_printf(dev, "could not allocate resources\n"); - return (ENXIO); - } - - /* route all interrupts to IRQ. secure interrupts are for FIQ */ - for (i = 0; i < 4; i++) - tzic_write_4(sc, TZIC_INTSEC(i), 0xffffffff); - - /* disable all interrupts */ - for (i = 0; i < 4; i++) - tzic_write_4(sc, TZIC_ENCLEAR(i), 0xffffffff); - - /* Set all interrupts to priority 0 (max). */ - for (i = 0; i < 128 / 4; ++i) - tzic_write_4(sc, TZIC_PRIORITY(i), 0); - - /* - * Set priority mask to lowest (unmasked) prio, set synchronizer to - * low-latency mode (as opposed to low-power), enable the controller. - */ - tzic_write_4(sc, TZIC_PRIOMASK, 0xff); - tzic_write_4(sc, TZIC_SYNCCTRL, 0); - tzic_write_4(sc, TZIC_INTCNTL, INTCNTL_NSEN_MASK|INTCNTL_NSEN|INTCNTL_EN); - - /* Register as a root pic. */ - if (tzic_pic_attach(sc) != 0) { - device_printf(dev, "could not attach PIC\n"); - return (ENXIO); - } - - return (0); -} - -static device_method_t tzic_methods[] = { - DEVMETHOD(device_probe, tzic_probe), - DEVMETHOD(device_attach, tzic_attach), - - DEVMETHOD(pic_disable_intr, tzic_disable_intr), - DEVMETHOD(pic_enable_intr, tzic_enable_intr), - DEVMETHOD(pic_map_intr, tzic_map_intr), - DEVMETHOD(pic_post_filter, tzic_post_filter), - DEVMETHOD(pic_post_ithread, tzic_post_ithread), - DEVMETHOD(pic_pre_ithread, tzic_pre_ithread), - - DEVMETHOD_END -}; - -static driver_t tzic_driver = { - "tzic", - tzic_methods, - sizeof(struct tzic_softc), -}; - -EARLY_DRIVER_MODULE(tzic, ofwbus, tzic_driver, 0, 0, BUS_PASS_INTERRUPT); diff --git a/sys/conf/options.arm b/sys/conf/options.arm --- a/sys/conf/options.arm +++ b/sys/conf/options.arm @@ -36,8 +36,6 @@ SOC_BCM2835 opt_global.h SOC_BCM2836 opt_global.h SOC_BRCM_BCM2837 opt_global.h -SOC_IMX51 opt_global.h -SOC_IMX53 opt_global.h SOC_IMX6 opt_global.h SOC_MV_ARMADAXP opt_global.h SOC_MV_ARMADA38X opt_global.h diff --git a/sys/dev/ata/chipsets/ata-fsl.c b/sys/dev/ata/chipsets/ata-fsl.c deleted file mode 100644 --- a/sys/dev/ata/chipsets/ata-fsl.c +++ /dev/null @@ -1,234 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2012 The FreeBSD Foundation - * - * This software was developed by Oleksandr Rybalko under sponsorship - * from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -/* local prototypes */ -static int imx_ata_ch_attach(device_t dev); -static int imx_ata_setmode(device_t dev, int target, int mode); - -static int -imx_ata_probe(device_t dev) -{ - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (!ofw_bus_is_compatible(dev, "fsl,imx51-ata") && - !ofw_bus_is_compatible(dev, "fsl,imx53-ata")) - return (ENXIO); - - device_set_desc(dev, "Freescale Integrated PATA Controller"); - return (BUS_PROBE_LOW_PRIORITY); -} - -static void -imx_ata_intr(void *data) -{ - struct ata_pci_controller *ctrl = data; - - bus_write_2(ctrl->r_res1, 0x28, bus_read_2(ctrl->r_res1, 0x28)); - ctrl->interrupt[0].function(ctrl->interrupt[0].argument); -} - -static int -imx_ata_attach(device_t dev) -{ - struct ata_pci_controller *ctrl; - device_t child; - int unit; - - ctrl = device_get_softc(dev); - /* do chipset specific setups only needed once */ - ctrl->legacy = ata_legacy(dev); - ctrl->channels = 1; - ctrl->ichannels = -1; - ctrl->ch_attach = ata_pci_ch_attach; - ctrl->ch_detach = ata_pci_ch_detach; - ctrl->dev = dev; - - ctrl->r_type1 = SYS_RES_MEMORY; - ctrl->r_rid1 = 0; - ctrl->r_res1 = bus_alloc_resource_any(dev, ctrl->r_type1, - &ctrl->r_rid1, RF_ACTIVE); - - if (ata_setup_interrupt(dev, imx_ata_intr)) { - device_printf(dev, "failed to setup interrupt\n"); - return ENXIO; - } - - ctrl->channels = 1; - - ctrl->ch_attach = imx_ata_ch_attach; - ctrl->setmode = imx_ata_setmode; - - /* attach all channels on this controller */ - unit = 0; - child = device_add_child(dev, "ata", ((unit == 0) && ctrl->legacy) ? - unit : devclass_find_free_unit(ata_devclass, 2)); - if (child == NULL) - device_printf(dev, "failed to add ata child device\n"); - else - device_set_ivars(child, (void *)(intptr_t)unit); - - bus_generic_attach(dev); - return 0; -} - -static int -imx_ata_ch_attach(device_t dev) -{ - struct ata_pci_controller *ctrl; - struct ata_channel *ch; - int i; - - ctrl = device_get_softc(device_get_parent(dev)); - ch = device_get_softc(dev); - for (i = ATA_DATA; i < ATA_MAX_RES; i++) - ch->r_io[i].res = ctrl->r_res1; - - bus_write_2(ctrl->r_res1, 0x24, 0x80); - DELAY(100); - bus_write_2(ctrl->r_res1, 0x24, 0xc0); - DELAY(100); - - /* Write TIME_OFF/ON/1/2W */ - bus_write_1(ctrl->r_res1, 0x00, 3); - bus_write_1(ctrl->r_res1, 0x01, 3); - bus_write_1(ctrl->r_res1, 0x02, (25 + 15) / 15); - bus_write_1(ctrl->r_res1, 0x03, (70 + 15) / 15); - - /* Write TIME_2R/AX/RDX/4 */ - bus_write_1(ctrl->r_res1, 0x04, (70 + 15) / 15); - bus_write_1(ctrl->r_res1, 0x05, (50 + 15) / 15 + 2); - bus_write_1(ctrl->r_res1, 0x06, 1); - bus_write_1(ctrl->r_res1, 0x07, (10 + 15) / 15); - - /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */ - bus_write_1(ctrl->r_res1, 0x08, (10 + 15) / 15); - - bus_write_2(ctrl->r_res1, 0x24, 0xc1); - DELAY(30000); - - /* setup ATA registers */ - ch->r_io[ATA_DATA ].offset = 0xa0; - ch->r_io[ATA_FEATURE].offset = 0xa4; - ch->r_io[ATA_ERROR ].offset = 0xa4; - ch->r_io[ATA_COUNT ].offset = 0xa8; - ch->r_io[ATA_SECTOR ].offset = 0xac; - ch->r_io[ATA_CYL_LSB].offset = 0xb0; - ch->r_io[ATA_CYL_MSB].offset = 0xb4; - ch->r_io[ATA_DRIVE ].offset = 0xb8; - ch->r_io[ATA_COMMAND].offset = 0xbc; - - ch->r_io[ATA_STATUS ].offset = 0xbc; - ch->r_io[ATA_ALTSTAT].offset = 0xd8; - ch->r_io[ATA_CONTROL].offset = 0xd8; - - ata_pci_hw(dev); - - ch->flags |= ATA_NO_SLAVE; - ch->flags |= ATA_USE_16BIT; - ch->flags |= ATA_CHECKS_CABLE; - ch->flags |= ATA_KNOWN_PRESENCE; - - /* Clear pending interrupts. */ - bus_write_2(ctrl->r_res1, 0x28, 0xf8); - /* Enable all, but Idle interrupts. */ - bus_write_2(ctrl->r_res1, 0x2c, 0x88); - - return 0; -} - -static int -imx_ata_setmode(device_t dev, int target, int mode) -{ - - return (min(mode, ATA_PIO4)); -} - -static device_method_t imx_ata_methods[] = { - DEVMETHOD(device_probe, imx_ata_probe), - DEVMETHOD(device_attach, imx_ata_attach), - DEVMETHOD(device_detach, ata_pci_detach), - DEVMETHOD(device_suspend, ata_pci_suspend), - DEVMETHOD(device_resume, ata_pci_resume), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(bus_read_ivar, ata_pci_read_ivar), - DEVMETHOD(bus_write_ivar, ata_pci_write_ivar), - DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource), - DEVMETHOD(bus_release_resource, ata_pci_release_resource), - DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), - DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), - DEVMETHOD(bus_setup_intr, ata_pci_setup_intr), - DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr), - DEVMETHOD(pci_read_config, ata_pci_read_config), - DEVMETHOD(pci_write_config, ata_pci_write_config), - DEVMETHOD(bus_print_child, ata_pci_print_child), - DEVMETHOD(bus_child_location, ata_pci_child_location), - DEVMETHOD_END -}; -static driver_t imx_ata_driver = { - "atapci", - imx_ata_methods, - sizeof(struct ata_pci_controller) -}; -DRIVER_MODULE(imx_ata, simplebus, imx_ata_driver, NULL, NULL); -MODULE_VERSION(imx_ata, 1); -MODULE_DEPEND(imx_ata, ata, 1, 1, 1); -MODULE_DEPEND(imx_ata, atapci, 1, 1, 1);