diff --git a/sys/arm64/arm64/exception.S b/sys/arm64/arm64/exception.S
--- a/sys/arm64/arm64/exception.S
+++ b/sys/arm64/arm64/exception.S
@@ -27,6 +27,7 @@
 
 #include <machine/asm.h>
 #include <machine/armreg.h>
+#include <machine/intr.h>
 #include "assym.inc"
 
 	.text
@@ -167,7 +168,7 @@
 .macro	do_ast
 	mrs	x19, daif
 	/* Make sure the IRQs are enabled before calling ast() */
-	bic	x19, x19, #PSR_I
+	bic	x19, x19, #(PSR_I | PSR_F)
 1:
 	/*
 	 * Mask interrupts while checking the ast pending flag
@@ -210,6 +211,15 @@
 	ERET
 END(handle_el1h_irq)
 
+ENTRY(handle_el1h_fiq)
+	save_registers 1
+	mov	x0, sp
+	mov	x1, #INTR_TYPE_MD_FIQ
+	bl	intr_irq_handler_type
+	restore_registers 1
+	ERET
+END(handle_el1h_irq)
+
 ENTRY(handle_el0_sync)
 	save_registers 0
 	ldr	x0, [x18, #PC_CURTHREAD]
@@ -230,6 +240,16 @@
 	ERET
 END(handle_el0_irq)
 
+ENTRY(handle_el0_fiq)
+	save_registers 0
+	mov	x0, sp
+	mov	x1, #INTR_TYPE_MD_FIQ
+	bl	intr_irq_handler_type
+	do_ast
+	restore_registers 0
+	ERET
+END(handle_el0_fiq)
+
 ENTRY(handle_serror)
 	save_registers 0
 	mov	x0, sp
@@ -268,16 +288,16 @@
 
 	vector el1h_sync 1	/* Synchronous EL1h */
 	vector el1h_irq 1	/* IRQ EL1h */
-	vempty 1		/* FIQ EL1h */
+	vector el1h_fiq 1	/* FIQ EL1h */
 	vector serror 1		/* Error EL1h */
 
 	vector el0_sync 0	/* Synchronous 64-bit EL0 */
 	vector el0_irq 0	/* IRQ 64-bit EL0 */
-	vempty 0		/* FIQ 64-bit EL0 */
+	vector el0_fiq 0	/* FIQ 64-bit EL0 */
 	vector serror 0		/* Error 64-bit EL0 */
 
 	vector el0_sync 0	/* Synchronous 32-bit EL0 */
 	vector el0_irq 0	/* IRQ 32-bit EL0 */
-	vempty 0		/* FIQ 32-bit EL0 */
+	vector el0_fiq 0	/* FIQ 32-bit EL0 */
 	vector serror 0		/* Error 32-bit EL0 */
 
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -196,7 +196,7 @@
 #define	DAIF_I			(1 << 1)
 #define	DAIF_F			(1 << 0)
 #define	DAIF_ALL		(DAIF_D | DAIF_A | DAIF_I | DAIF_F)
-#define	DAIF_INTR		(DAIF_I)	/* All exceptions that pass */
+#define	DAIF_INTR		(DAIF_I | DAIF_F) /* All exceptions that pass */
 						/* through the intr framework */
 
 /* DBGBCR<n>_EL1 - Debug Breakpoint Control Registers */
@@ -2058,7 +2058,7 @@
 #define	PSR_D		0x00000200UL
 #define	PSR_DAIF	(PSR_D | PSR_A | PSR_I | PSR_F)
 /* The default DAIF mask. These bits are valid in spsr_el1 and daif */
-#define	PSR_DAIF_DEFAULT (PSR_F)
+#define	PSR_DAIF_DEFAULT (0)
 #define	PSR_IL		0x00100000UL
 #define	PSR_SS		0x00200000UL
 #define	PSR_V		0x10000000UL
diff --git a/sys/arm64/include/intr.h b/sys/arm64/include/intr.h
--- a/sys/arm64/include/intr.h
+++ b/sys/arm64/include/intr.h
@@ -27,16 +27,18 @@
 #ifndef _MACHINE_INTR_H_
 #define	_MACHINE_INTR_H_
 
+/*
+ * We basically only want to expose some interrupt types that must be kept in
+ * sync between assembly and C here.
+ */
+#ifndef LOCORE
+
 #ifdef FDT
 #include <dev/ofw/openfirm.h>
 #endif
 
 #include <sys/intr.h>
 
-#ifndef NIRQ
-#define	NIRQ		16384	/* XXX - It should be an option. */
-#endif
-
 static inline void
 arm_irq_memory_barrier(uintptr_t irq)
 {
@@ -46,10 +48,19 @@
 void intr_ipi_dispatch(u_int);
 #endif
 
+#endif	/* LOCORE */
+
+#ifndef NIRQ
+#define	NIRQ		16384	/* XXX - It should be an option. */
+#endif
+
 #ifdef DEV_ACPI
 #define	ACPI_INTR_XREF	1
 #define	ACPI_MSI_XREF	2
 #define	ACPI_GPIO_XREF	3
 #endif
 
+/* MD interrupt types */
+#define	INTR_TYPE_MD_FIQ		0x0001
+
 #endif	/* _MACHINE_INTR_H */