diff --git a/sys/arm64/arm64/cpu_errata.c b/sys/arm64/arm64/cpu_errata.c
--- a/sys/arm64/arm64/cpu_errata.c
+++ b/sys/arm64/arm64/cpu_errata.c
@@ -60,30 +60,10 @@
 static cpu_quirk_install install_thunderx_bcast_tlbi_workaround;
 
 static struct cpu_quirks cpu_quirks[] = {
+	/* Spectre-V2 */
 	{
-		.midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
-		.midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A57,0,0),
-		.quirk_install = install_psci_bp_hardening,
-	},
-	{
-		.midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
-		.midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A72,0,0),
-		.quirk_install = install_psci_bp_hardening,
-	},
-	{
-		.midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
-		.midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A73,0,0),
-		.quirk_install = install_psci_bp_hardening,
-	},
-	{
-		.midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
-		.midr_value = CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A75,0,0),
-		.quirk_install = install_psci_bp_hardening,
-	},
-	{
-		.midr_mask = CPU_IMPL_MASK | CPU_PART_MASK,
-		.midr_value =
-		    CPU_ID_RAW(CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0,0),
+		.midr_mask = 0,
+		.midr_value = 0,
 		.quirk_install = install_psci_bp_hardening,
 	},
 	{
@@ -105,9 +85,27 @@
 	},
 };
 
+/* Spectre Variant 2 */
 static void
-install_psci_bp_hardening(u_int midr __unused)
+install_psci_bp_hardening(u_int midr)
 {
+	static const u_int safe_list[] = {
+		CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A35, 0, 0),
+		CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A53, 0, 0),
+		CPU_ID_RAW(CPU_IMPL_ARM, CPU_PART_CORTEX_A55, 0, 0),
+	};
+	uint64_t pfr0;
+
+	/* If this CPU has CSV2 it's safe */
+	pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
+	if (ID_AA64PFR0_CSV2_VAL(pfr0) != ID_AA64PFR0_CSV2_NONE)
+		return;
+
+	/* Or is a known safe CPU */
+	for (int i = 0; i < nitems(safe_list); i++) {
+		if ((midr & (CPU_IMPL_MASK | CPU_PART_MASK)) == safe_list[i])
+			return;
+	}
 
 	if (smccc_arch_features(SMCCC_ARCH_WORKAROUND_1) != SMCCC_RET_SUCCESS)
 		return;