diff --git a/sys/arm64/arm64/elf32_machdep.c b/sys/arm64/arm64/elf32_machdep.c
--- a/sys/arm64/arm64/elf32_machdep.c
+++ b/sys/arm64/arm64/elf32_machdep.c
@@ -266,7 +266,7 @@
 	/* LR_usr is mapped to x14 */
 	tf->tf_x[14] = imgp->entry_addr;
 	tf->tf_elr = imgp->entry_addr;
-	tf->tf_spsr = PSR_M_32;
+	tf->tf_spsr = PSR_M4_32;
 	if ((uint32_t)imgp->entry_addr & 1)
 		tf->tf_spsr |= PSR_T;
 
diff --git a/sys/arm64/arm64/exec_machdep.c b/sys/arm64/arm64/exec_machdep.c
--- a/sys/arm64/arm64/exec_machdep.c
+++ b/sys/arm64/arm64/exec_machdep.c
@@ -478,7 +478,7 @@
 #endif
 
 	if ((spsr & PSR_M_MASK) != PSR_M_EL0t ||
-	    (spsr & PSR_AARCH32) != 0 ||
+	    (spsr & PSR_M4_MASK) != PSR_M4_64 ||
 	    (spsr & PSR_DAIF) != (td->td_frame->tf_spsr & PSR_DAIF))
 		return (EINVAL); 
 
diff --git a/sys/arm64/arm64/vm_machdep.c b/sys/arm64/arm64/vm_machdep.c
--- a/sys/arm64/arm64/vm_machdep.c
+++ b/sys/arm64/arm64/vm_machdep.c
@@ -98,7 +98,7 @@
 	bcopy(td1->td_frame, tf, sizeof(*tf));
 	tf->tf_x[0] = 0;
 	tf->tf_x[1] = 0;
-	tf->tf_spsr = td1->td_frame->tf_spsr & (PSR_M_32 | PSR_DAIF);
+	tf->tf_spsr = td1->td_frame->tf_spsr & (PSR_M4_MASK | PSR_DAIF);
 
 	td2->td_frame = tf;
 
@@ -213,7 +213,7 @@
 	struct trapframe *tf = td->td_frame;
 
 	/* 32bits processes use r13 for sp */
-	if (td->td_frame->tf_spsr & PSR_M_32) {
+	if ((td->td_frame->tf_spsr & PSR_M4_MASK) == PSR_M4_32) {
 		tf->tf_x[13] = STACKALIGN((uintptr_t)stack->ss_sp + stack->ss_size);
 		if ((register_t)entry & 1)
 			tf->tf_spsr |= PSR_T;
@@ -234,7 +234,7 @@
 		return (EINVAL);
 
 	pcb = td->td_pcb;
-	if (td->td_frame->tf_spsr & PSR_M_32) {
+	if ((td->td_frame->tf_spsr & PSR_M4_MASK) == PSR_M4_32) {
 		/* 32bits arm stores the user TLS into tpidrro */
 		pcb->pcb_tpidrro_el0 = (register_t)tls_base;
 		pcb->pcb_tpidr_el0 = (register_t)tls_base;
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -2040,35 +2040,38 @@
  *         0: always SP0
  *         1: current ELs SP
  */
-#define	PSR_M_EL0t	0x00000000UL
-#define	PSR_M_EL1t	0x00000004UL
-#define	PSR_M_EL1h	0x00000005UL
-#define	PSR_M_EL2t	0x00000008UL
-#define	PSR_M_EL2h	0x00000009UL
-#define	PSR_M_64	0x00000000UL
-#define	PSR_M_32	0x00000010UL
-#define	PSR_M_MASK	0x0000000fUL
-
-#define	PSR_T		0x00000020UL
-
-#define	PSR_AARCH32	0x00000010UL
-#define	PSR_F		0x00000040UL
-#define	PSR_I		0x00000080UL
-#define	PSR_A		0x00000100UL
-#define	PSR_D		0x00000200UL
-#define	PSR_DAIF	(PSR_D | PSR_A | PSR_I | PSR_F)
+#define	PSR_M_SHIFT		0
+#define	PSR_M_EL0t		(0x0UL << PSR_M_SHIFT)
+#define	PSR_M_MASK		(0xfUL << PSR_M_SHIFT)
+#define	PSR_M_EL1t		(0x4UL << PSR_M_SHIFT)
+#define	PSR_M_EL1h		(0x5UL << PSR_M_SHIFT)
+#define	PSR_M_EL2t		(0x8UL << PSR_M_SHIFT)
+#define	PSR_M_EL2h		(0x9UL << PSR_M_SHIFT)
+/* M[4] is used to decide to return to AArch32 or AArch64 */
+#define	PSR_M4_SHIFT		4
+#define	PSR_M4_MASK		(0x1UL << PSR_M4_SHIFT)
+#define	PSR_M4_64		(0x0UL << PSR_M4_SHIFT)
+#define	PSR_M4_32		(0x1UL << PSR_M4_SHIFT)
+
+#define	PSR_T			(0x1UL << 5)
+
+#define	PSR_F			(0x1UL << 6)
+#define	PSR_I			(0x1UL << 7)
+#define	PSR_A			(0x1UL << 8)
+#define	PSR_D			(0x1UL << 9)
+#define	PSR_DAIF		(PSR_D | PSR_A | PSR_I | PSR_F)
 /* The default DAIF mask. These bits are valid in spsr_el1 and daif */
-#define	PSR_DAIF_DEFAULT (PSR_F)
-#define	PSR_IL		0x00100000UL
-#define	PSR_SS		0x00200000UL
-#define	PSR_V		0x10000000UL
-#define	PSR_C		0x20000000UL
-#define	PSR_Z		0x40000000UL
-#define	PSR_N		0x80000000UL
-#define	PSR_FLAGS	0xf0000000UL
+#define	PSR_DAIF_DEFAULT	(PSR_F)
+#define	PSR_IL			(0x1UL << 20)
+#define	PSR_SS			(0x1UL << 21)
+#define	PSR_V			(0x1UL << 28)
+#define	PSR_C			(0x1UL << 29)
+#define	PSR_Z			(0x1UL << 30)
+#define	PSR_N			(0x1UL << 31)
+#define	PSR_FLAGS		(PSR_N | PSR_Z | PSR_C | PSR_V)
 /* PSR fields that can be set from 32-bit and 64-bit processes */
-#define	PSR_SETTABLE_32	PSR_FLAGS
-#define	PSR_SETTABLE_64	(PSR_FLAGS | PSR_SS)
+#define	PSR_SETTABLE_32		PSR_FLAGS
+#define	PSR_SETTABLE_64		(PSR_FLAGS | PSR_SS)
 
 /* REVIDR_EL1 - Revision ID Register */
 #define	REVIDR_EL1			MRS_REG(REVIDR_EL1)