Index: head/sys/arm/freescale/imx/imx6_ccm.c
===================================================================
--- head/sys/arm/freescale/imx/imx6_ccm.c
+++ head/sys/arm/freescale/imx/imx6_ccm.c
@@ -348,6 +348,43 @@
 	return (132000000);
 }
 
+void
+imx_ccm_ipu_enable(int ipu)
+{
+	struct ccm_softc *sc;
+	uint32_t reg;
+
+	sc = ccm_sc;
+	reg = RD4(sc, CCM_CCGR3);
+	if (ipu == 1)
+		reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0;
+	else
+		reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0;
+	WR4(sc, CCM_CCGR3, reg);
+}
+
+void
+imx_ccm_hdmi_enable(void)
+{
+	struct ccm_softc *sc;
+	uint32_t reg;
+
+	sc = ccm_sc;
+	reg = RD4(sc, CCM_CCGR2);
+	reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR;
+	WR4(sc, CCM_CCGR2, reg);
+
+	/* Set HDMI clock to 280MHz */
+	reg = RD4(sc, CCM_CHSCCDR);
+	reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
+	    CHSCCDR_IPU1_DI0_PODF_MASK | CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+	reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT);
+	reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT);
+	WR4(sc, CCM_CHSCCDR, reg);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT);
+	WR4(sc, CCM_CHSCCDR, reg);
+}
+
 uint32_t
 imx_ccm_get_cacrr(void)
 {
Index: head/sys/arm/freescale/imx/imx6_ccmreg.h
===================================================================
--- head/sys/arm/freescale/imx/imx6_ccmreg.h
+++ head/sys/arm/freescale/imx/imx6_ccmreg.h
@@ -30,6 +30,9 @@
 #define	IMX6_CCMREG_H
 
 #define	CCM_CACCR			0x010
+#define	CCM_CBCDR			0x014
+#define	    CBCDR_MMDC_CH1_AXI_PODF_SHIFT	3
+#define	    CBCDR_MMDC_CH1_AXI_PODF_MASK	(7 << 3)
 #define	CCM_CSCMR1			0x01C
 #define	  SSI1_CLK_SEL_S		  10
 #define	  SSI2_CLK_SEL_S		  12
@@ -39,6 +42,7 @@
 #define	  SSI_CLK_SEL_454_PFD		  1
 #define	  SSI_CLK_SEL_PLL4		  2
 #define	CCM_CSCMR2			0x020
+#define	  CSCMR2_LDB_DI0_IPU_DIV_SHIFT	  10
 #define	CCM_CS1CDR			0x028
 #define	  SSI1_CLK_PODF_SHIFT		  0
 #define	  SSI1_CLK_PRED_SHIFT		  6
@@ -49,6 +53,18 @@
 #define	CCM_CS2CDR			0x02C
 #define	  SSI2_CLK_PODF_SHIFT		  0
 #define	  SSI2_CLK_PRED_SHIFT		  6
+#define	  LDB_DI0_CLK_SEL_SHIFT		  9
+#define	  LDB_DI0_CLK_SEL_MASK		  (3 << LDB_DI0_CLK_SEL_SHIFT)
+#define	CCM_CHSCCDR			0x034
+#define	  CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
+#define	  CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT	6
+#define	  CHSCCDR_IPU1_DI0_PODF_MASK		(0x7 << 3)
+#define	  CHSCCDR_IPU1_DI0_PODF_SHIFT		3
+#define	  CHSCCDR_IPU1_DI0_CLK_SEL_MASK		(0x7)
+#define	  CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT	0
+#define	  CHSCCDR_CLK_SEL_LDB_DI0		3
+#define	  CHSCCDR_PODF_DIVIDE_BY_3		2
+#define	  CHSCCDR_IPU_PRE_CLK_540M_PFD		5
 #define	CCM_CSCDR2			0x038
 #define	CCM_CLPCR			0x054
 #define	  CCM_CLPCR_LPM_MASK		  0x03
Index: head/sys/arm/freescale/imx/imx_ccmvar.h
===================================================================
--- head/sys/arm/freescale/imx/imx_ccmvar.h
+++ head/sys/arm/freescale/imx/imx_ccmvar.h
@@ -52,6 +52,8 @@
 void imx_ccm_usb_enable(device_t _usbdev);
 void imx_ccm_usbphy_enable(device_t _phydev);
 void imx_ccm_ssi_configure(device_t _ssidev);
+void imx_ccm_hdmi_enable(void);
+void imx_ccm_ipu_enable(int ipu);
 
 /* Routines to get and set the arm clock root divisor register. */
 uint32_t imx_ccm_get_cacrr(void);