Index: head/sys/arm/include/atomic-v6.h
===================================================================
--- head/sys/arm/include/atomic-v6.h
+++ head/sys/arm/include/atomic-v6.h
@@ -593,6 +593,54 @@
 	*p = v;
 }
 
+static __inline int
+atomic_testandset_32(volatile uint32_t *p, u_int v)
+{
+	uint32_t tmp, tmp2, res, mask;
+
+	mask = 1u << (v & 0x1f);
+	tmp = tmp2 = 0;
+	__asm __volatile(
+	"1:	ldrex	%0, [%4]	\n"
+	"	orr	%1, %0, %3	\n"
+	"	strex	%2, %1, [%4]	\n"
+	"	cmp	%2, #0		\n"
+	"	it	ne		\n"
+	"	bne	1b		\n"
+	: "=&r" (res), "=&r" (tmp), "=&r" (tmp2)
+	: "r" (mask), "r" (p)
+	: "cc", "memory");
+	return ((res & mask) != 0);
+}
+
+static __inline int
+atomic_testandset_int(volatile u_int *p, u_int v)
+{
+
+	return (atomic_testandset_32((volatile uint32_t *)p, v));
+}
+
+static __inline int
+atomic_testandset_long(volatile u_long *p, u_int v)
+{
+
+	return (atomic_testandset_32((volatile uint32_t *)p, v));
+}
+
+static __inline int
+atomic_testandset_64(volatile uint64_t *p, u_int v)
+{
+	volatile uint32_t *p32;
+
+	p32 = (volatile uint32_t *)p;
+	/* Assume little-endian */
+	if (v >= 32) {
+		v &= 0x1f;
+		p32++;
+	}
+	return (atomic_testandset_32(p32, v));
+}
+
 #undef ATOMIC_ACQ_REL
 #undef ATOMIC_ACQ_REL_LONG