diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -1453,10 +1453,47 @@
 
 
 /* ID_AA64PFR1_EL1 */
+static const struct mrs_field_value id_aa64pfr1_nmi[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, NMI, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64pfr1_csv2_frac[] = {
+	MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p0, ""),
+	MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p1, "CSV2 p1"),
+	MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p2, "CSV2 p2"),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64pfr1_rndr_trap[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, RNDR_trap, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64pfr1_sme[] = {
+	MRS_FIELD_VALUE(ID_AA64PFR1_SME_NONE, ""),
+	MRS_FIELD_VALUE(ID_AA64PFR1_SME_SME, "SME"),
+	MRS_FIELD_VALUE(ID_AA64PFR1_SME_SME2, "SME2"),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64pfr1_mpam_frac[] = {
+	MRS_FIELD_VALUE(ID_AA64PFR1_MPAM_frac_p0, ""),
+	MRS_FIELD_VALUE(ID_AA64PFR1_MPAM_frac_p1, "MPAM p1"),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64pfr1_ras_frac[] = {
+	MRS_FIELD_VALUE(ID_AA64PFR1_RAS_frac_p0, ""),
+	MRS_FIELD_VALUE(ID_AA64PFR1_RAS_frac_p1, "RAS p1"),
+	MRS_FIELD_VALUE_END,
+};
+
 static const struct mrs_field_value id_aa64pfr1_mte[] = {
 	MRS_FIELD_VALUE(ID_AA64PFR1_MTE_NONE, ""),
-	MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL_EL0, "MTE EL0"),
-	MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL, "MTE"),
+	MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE, "MTE"),
+	MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE2, "MTE2"),
+	MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE3, "MTE3"),
 	MRS_FIELD_VALUE_END,
 };
 
@@ -1487,6 +1524,16 @@
 #endif
 
 static const struct mrs_field id_aa64pfr1_fields[] = {
+	MRS_FIELD(ID_AA64PFR1, NMI, false, MRS_EXACT, id_aa64pfr1_nmi),
+	MRS_FIELD(ID_AA64PFR1, CSV2_frac, false, MRS_EXACT,
+	    id_aa64pfr1_csv2_frac),
+	MRS_FIELD(ID_AA64PFR1, RNDR_trap, false, MRS_EXACT,
+	    id_aa64pfr1_rndr_trap),
+	MRS_FIELD(ID_AA64PFR1, SME, false, MRS_EXACT, id_aa64pfr1_sme),
+	MRS_FIELD(ID_AA64PFR1, MPAM_frac, false, MRS_EXACT,
+	    id_aa64pfr1_mpam_frac),
+	MRS_FIELD(ID_AA64PFR1, RAS_frac, false, MRS_EXACT,
+	    id_aa64pfr1_ras_frac),
 	MRS_FIELD(ID_AA64PFR1, MTE, false, MRS_EXACT, id_aa64pfr1_mte),
 	MRS_FIELD_HWCAP(ID_AA64PFR1, SSBS, false, MRS_LOWER, id_aa64pfr1_ssbs,
 	    id_aa64pfr1_ssbs_caps),
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -1202,11 +1202,11 @@
 
 /* ID_AA64PFR1_EL1 */
 #define	ID_AA64PFR1_EL1			MRS_REG(ID_AA64PFR1_EL1)
-#define	ID_AA64PFR1_EL1_op0		0x3
-#define	ID_AA64PFR1_EL1_op1		0x0
-#define	ID_AA64PFR1_EL1_CRn		0x0
-#define	ID_AA64PFR1_EL1_CRm		0x4
-#define	ID_AA64PFR1_EL1_op2		0x1
+#define	ID_AA64PFR1_EL1_op0		3
+#define	ID_AA64PFR1_EL1_op1		0
+#define	ID_AA64PFR1_EL1_CRn		0
+#define	ID_AA64PFR1_EL1_CRm		4
+#define	ID_AA64PFR1_EL1_op2		1
 #define	ID_AA64PFR1_BT_SHIFT		0
 #define	ID_AA64PFR1_BT_MASK		(UL(0xf) << ID_AA64PFR1_BT_SHIFT)
 #define	ID_AA64PFR1_BT_VAL(x)		((x) & ID_AA64PFR1_BT_MASK)
@@ -1222,13 +1222,41 @@
 #define	ID_AA64PFR1_MTE_MASK		(UL(0xf) << ID_AA64PFR1_MTE_SHIFT)
 #define	ID_AA64PFR1_MTE_VAL(x)		((x) & ID_AA64PFR1_MTE_MASK)
 #define	 ID_AA64PFR1_MTE_NONE		(UL(0x0) << ID_AA64PFR1_MTE_SHIFT)
-#define	 ID_AA64PFR1_MTE_IMPL_EL0	(UL(0x1) << ID_AA64PFR1_MTE_SHIFT)
-#define	 ID_AA64PFR1_MTE_IMPL		(UL(0x2) << ID_AA64PFR1_MTE_SHIFT)
+#define	 ID_AA64PFR1_MTE_MTE		(UL(0x1) << ID_AA64PFR1_MTE_SHIFT)
+#define	 ID_AA64PFR1_MTE_MTE2		(UL(0x2) << ID_AA64PFR1_MTE_SHIFT)
+#define	 ID_AA64PFR1_MTE_MTE3		(UL(0x3) << ID_AA64PFR1_MTE_SHIFT)
 #define	ID_AA64PFR1_RAS_frac_SHIFT	12
 #define	ID_AA64PFR1_RAS_frac_MASK	(UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT)
 #define	ID_AA64PFR1_RAS_frac_VAL(x)	((x) & ID_AA64PFR1_RAS_frac_MASK)
-#define	 ID_AA64PFR1_RAS_frac_V1	(UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
-#define	 ID_AA64PFR1_RAS_frac_V2	(UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
+#define	 ID_AA64PFR1_RAS_frac_p0	(UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
+#define	 ID_AA64PFR1_RAS_frac_p1	(UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
+#define	ID_AA64PFR1_MPAM_frac_SHIFT	16
+#define	ID_AA64PFR1_MPAM_frac_MASK	(UL(0xf) << ID_AA64PFR1_MPAM_frac_SHIFT)
+#define	ID_AA64PFR1_MPAM_frac_VAL(x)	((x) & ID_AA64PFR1_MPAM_frac_MASK)
+#define	 ID_AA64PFR1_MPAM_frac_p0	(UL(0x0) << ID_AA64PFR1_MPAM_frac_SHIFT)
+#define	 ID_AA64PFR1_MPAM_frac_p1	(UL(0x1) << ID_AA64PFR1_MPAM_frac_SHIFT)
+#define	ID_AA64PFR1_SME_SHIFT		24
+#define	ID_AA64PFR1_SME_MASK		(UL(0xf) << ID_AA64PFR1_SME_SHIFT)
+#define	ID_AA64PFR1_SME_VAL(x)		((x) & ID_AA64PFR1_SME_MASK)
+#define	 ID_AA64PFR1_SME_NONE		(UL(0x0) << ID_AA64PFR1_SME_SHIFT)
+#define	 ID_AA64PFR1_SME_SME		(UL(0x1) << ID_AA64PFR1_SME_SHIFT)
+#define	 ID_AA64PFR1_SME_SME2		(UL(0x2) << ID_AA64PFR1_SME_SHIFT)
+#define	ID_AA64PFR1_RNDR_trap_SHIFT	28
+#define	ID_AA64PFR1_RNDR_trap_MASK	(UL(0xf) << ID_AA64PFR1_RNDR_trap_SHIFT)
+#define	ID_AA64PFR1_RNDR_trap_VAL(x)	((x) & ID_AA64PFR1_RNDR_trap_MASK)
+#define	 ID_AA64PFR1_RNDR_trap_NONE	(UL(0x0) << ID_AA64PFR1_RNDR_trap_SHIFT)
+#define	 ID_AA64PFR1_RNDR_trap_IMPL	(UL(0x1) << ID_AA64PFR1_RNDR_trap_SHIFT)
+#define	ID_AA64PFR1_CSV2_frac_SHIFT	32
+#define	ID_AA64PFR1_CSV2_frac_MASK	(UL(0xf) << ID_AA64PFR1_CSV2_frac_SHIFT)
+#define	ID_AA64PFR1_CSV2_frac_VAL(x)	((x) & ID_AA64PFR1_CSV2_frac_MASK)
+#define	 ID_AA64PFR1_CSV2_frac_p0	(UL(0x0) << ID_AA64PFR1_CSV2_frac_SHIFT)
+#define	 ID_AA64PFR1_CSV2_frac_p1	(UL(0x1) << ID_AA64PFR1_CSV2_frac_SHIFT)
+#define	 ID_AA64PFR1_CSV2_frac_p2	(UL(0x2) << ID_AA64PFR1_CSV2_frac_SHIFT)
+#define	ID_AA64PFR1_NMI_SHIFT		36
+#define	ID_AA64PFR1_NMI_MASK		(UL(0xf) << ID_AA64PFR1_NMI_SHIFT)
+#define	ID_AA64PFR1_NMI_VAL(x)		((x) & ID_AA64PFR1_NMI_MASK)
+#define	 ID_AA64PFR1_NMI_NONE		(UL(0x0) << ID_AA64PFR1_NMI_SHIFT)
+#define	 ID_AA64PFR1_NMI_IMPL		(UL(0x1) << ID_AA64PFR1_NMI_SHIFT)
 
 /* ID_AA64ZFR0_EL1 */
 #define	ID_AA64ZFR0_EL1			MRS_REG(ID_AA64ZFR0_EL1)