diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -140,6 +140,7 @@
 	uint64_t	id_aa64mmfr1;
 	uint64_t	id_aa64mmfr2;
 	uint64_t	id_aa64mmfr3;
+	uint64_t	id_aa64mmfr4;
 	uint64_t	id_aa64pfr0;
 	uint64_t	id_aa64pfr1;
 	uint64_t	id_aa64zfr0;
@@ -1297,6 +1298,12 @@
 };
 
 
+/* ID_AA64MMFR4_EL1 */
+static const struct mrs_field id_aa64mmfr4_fields[] = {
+	MRS_FIELD_END,
+};
+
+
 /* ID_AA64PFR0_EL1 */
 static const struct mrs_field_value id_aa64pfr0_csv3[] = {
 	MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""),
@@ -1778,6 +1785,7 @@
 	USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1),
 	USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2),
 	USER_REG(ID_AA64MMFR3_EL1, id_aa64mmfr3),
+	USER_REG(ID_AA64MMFR4_EL1, id_aa64mmfr4),
 
 	USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0),
 	USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1),
@@ -2509,6 +2517,11 @@
 		print_id_register(sb, "Memory Model Features 3",
 		    desc->id_aa64mmfr3, id_aa64mmfr3_fields);
 
+	/* AArch64 Memory Model Feature Register 4 */
+	if (SHOULD_PRINT_REG(id_aa64mmfr4))
+		print_id_register(sb, "Memory Model Features 4",
+		    desc->id_aa64mmfr4, id_aa64mmfr4_fields);
+
 	/* AArch64 Debug Feature Register 0 */
 	if (SHOULD_PRINT_REG(id_aa64dfr0))
 		print_id_register(sb, "Debug Features 0",
@@ -2624,6 +2637,7 @@
 	desc->id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
 	desc->id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1);
 	desc->id_aa64mmfr3 = READ_SPECIALREG(id_aa64mmfr3_el1);
+	desc->id_aa64mmfr4 = READ_SPECIALREG(id_aa64mmfr4_el1);
 	desc->id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
 	desc->id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1);
 
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -1094,6 +1094,14 @@
 #define	 ID_AA64MMFR3_Spec_FPACC_NONE	(UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
 #define	 ID_AA64MMFR3_Spec_FPACC_IMPL	(UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
 
+/* ID_AA64MMFR4_EL1 */
+#define	ID_AA64MMFR4_EL1		MRS_REG(ID_AA64MMFR4_EL1)
+#define	ID_AA64MMFR4_EL1_op0		3
+#define	ID_AA64MMFR4_EL1_op1		0
+#define	ID_AA64MMFR4_EL1_CRn		0
+#define	ID_AA64MMFR4_EL1_CRm		7
+#define	ID_AA64MMFR4_EL1_op2		4
+
 /* ID_AA64PFR0_EL1 */
 #define	ID_AA64PFR0_EL1			MRS_REG(ID_AA64PFR0_EL1)
 #define	ID_AA64PFR0_EL1_op0		0x3