diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -139,6 +139,7 @@
 	uint64_t	id_aa64mmfr0;
 	uint64_t	id_aa64mmfr1;
 	uint64_t	id_aa64mmfr2;
+	uint64_t	id_aa64mmfr3;
 	uint64_t	id_aa64pfr0;
 	uint64_t	id_aa64pfr1;
 	uint64_t	id_aa64zfr0;
@@ -1265,6 +1266,37 @@
 };
 
 
+/* ID_AA64MMFR2_EL1 */
+static const struct mrs_field_value id_aa64mmfr3_spec_fpacc[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, Spec_FPACC, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64mmfr3_mec[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, MEC, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64mmfr3_sctlrx[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, SCTLRX, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64mmfr3_tcrx[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, TCRX, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field id_aa64mmfr3_fields[] = {
+	MRS_FIELD(ID_AA64MMFR3, Spec_FPACC, false, MRS_EXACT,
+	    id_aa64mmfr3_spec_fpacc),
+	MRS_FIELD(ID_AA64MMFR3, MEC, false, MRS_EXACT, id_aa64mmfr3_mec),
+	MRS_FIELD(ID_AA64MMFR3, SCTLRX, false, MRS_EXACT, id_aa64mmfr3_sctlrx),
+	MRS_FIELD(ID_AA64MMFR3, TCRX, false, MRS_EXACT, id_aa64mmfr3_tcrx),
+	MRS_FIELD_END,
+};
+
+
 /* ID_AA64PFR0_EL1 */
 static const struct mrs_field_value id_aa64pfr0_csv3[] = {
 	MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""),
@@ -1745,6 +1777,7 @@
 	USER_REG(ID_AA64MMFR0_EL1, id_aa64mmfr0),
 	USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1),
 	USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2),
+	USER_REG(ID_AA64MMFR3_EL1, id_aa64mmfr3),
 
 	USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0),
 	USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1),
@@ -2471,6 +2504,11 @@
 		print_id_register(sb, "Memory Model Features 2",
 		    desc->id_aa64mmfr2, id_aa64mmfr2_fields);
 
+	/* AArch64 Memory Model Feature Register 3 */
+	if (SHOULD_PRINT_REG(id_aa64mmfr3))
+		print_id_register(sb, "Memory Model Features 3",
+		    desc->id_aa64mmfr3, id_aa64mmfr3_fields);
+
 	/* AArch64 Debug Feature Register 0 */
 	if (SHOULD_PRINT_REG(id_aa64dfr0))
 		print_id_register(sb, "Debug Features 0",
@@ -2585,6 +2623,7 @@
 	desc->id_aa64mmfr0 = READ_SPECIALREG(id_aa64mmfr0_el1);
 	desc->id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
 	desc->id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1);
+	desc->id_aa64mmfr3 = READ_SPECIALREG(id_aa64mmfr3_el1);
 	desc->id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
 	desc->id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1);
 
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -1066,6 +1066,34 @@
 #define	 ID_AA64MMFR2_E0PD_NONE		(UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT)
 #define	 ID_AA64MMFR2_E0PD_IMPL		(UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT)
 
+/* ID_AA64MMFR3_EL1 */
+#define	ID_AA64MMFR3_EL1		MRS_REG(ID_AA64MMFR3_EL1)
+#define	ID_AA64MMFR3_EL1_op0		3
+#define	ID_AA64MMFR3_EL1_op1		0
+#define	ID_AA64MMFR3_EL1_CRn		0
+#define	ID_AA64MMFR3_EL1_CRm		7
+#define	ID_AA64MMFR3_EL1_op2		3
+#define	ID_AA64MMFR3_TCRX_SHIFT		0
+#define	ID_AA64MMFR3_TCRX_MASK		(UL(0xf) << ID_AA64MMFR3_TCRX_SHIFT)
+#define	ID_AA64MMFR3_TCRX_VAL(x)	((x) & ID_AA64MMFR3_TCRX_MASK)
+#define	 ID_AA64MMFR3_TCRX_NONE		(UL(0x0) << ID_AA64MMFR3_TCRX_SHIFT)
+#define	 ID_AA64MMFR3_TCRX_IMPL		(UL(0x1) << ID_AA64MMFR3_TCRX_SHIFT)
+#define	ID_AA64MMFR3_SCTLRX_SHIFT	4
+#define	ID_AA64MMFR3_SCTLRX_MASK	(UL(0xf) << ID_AA64MMFR3_SCTLRX_SHIFT)
+#define	ID_AA64MMFR3_SCTLRX_VAL(x)	((x) & ID_AA64MMFR3_SCTLRX_MASK)
+#define	 ID_AA64MMFR3_SCTLRX_NONE	(UL(0x0) << ID_AA64MMFR3_SCTLRX_SHIFT)
+#define	 ID_AA64MMFR3_SCTLRX_IMPL	(UL(0x1) << ID_AA64MMFR3_SCTLRX_SHIFT)
+#define	ID_AA64MMFR3_MEC_SHIFT		28
+#define	ID_AA64MMFR3_MEC_MASK		(UL(0xf) << ID_AA64MMFR3_MEC_SHIFT)
+#define	ID_AA64MMFR3_MEC_VAL(x)	((x) & ID_AA64MMFR3_MEC_MASK)
+#define	 ID_AA64MMFR3_MEC_NONE		(UL(0x0) << ID_AA64MMFR3_MEC_SHIFT)
+#define	 ID_AA64MMFR3_MEC_IMPL		(UL(0x1) << ID_AA64MMFR3_MEC_SHIFT)
+#define	ID_AA64MMFR3_Spec_FPACC_SHIFT	60
+#define	ID_AA64MMFR3_Spec_FPACC_MASK	(UL(0xf) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
+#define	ID_AA64MMFR3_Spec_FPACC_VAL(x)	((x) & ID_AA64MMFR3_Spec_FPACC_MASK)
+#define	 ID_AA64MMFR3_Spec_FPACC_NONE	(UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
+#define	 ID_AA64MMFR3_Spec_FPACC_IMPL	(UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
+
 /* ID_AA64PFR0_EL1 */
 #define	ID_AA64PFR0_EL1			MRS_REG(ID_AA64PFR0_EL1)
 #define	ID_AA64PFR0_EL1_op0		0x3