diff --git a/sys/dev/bxe/bxe_elink.c b/sys/dev/bxe/bxe_elink.c
--- a/sys/dev/bxe/bxe_elink.c
+++ b/sys/dev/bxe/bxe_elink.c
@@ -393,7 +393,8 @@
 #define MDIO_PMA_REG_8727_PCS_GP		0xc842
 #define MDIO_PMA_REG_8727_OPT_CFG_REG		0xc8e4
 
-#define MDIO_AN_REG_8727_MISC_CTRL		0x8309
+#define MDIO_AN_REG_8727_MISC_CTRL1		0x8308
+#define MDIO_AN_REG_8727_MISC_CTRL2		0x8309
 #define	MDIO_PMA_REG_8073_CHIP_REV			0xc801
 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS		0xc820
 #define MDIO_PMA_REG_8073_XAUI_WA 			0xc841
@@ -10164,6 +10165,7 @@
 	uint16_t tmp1, val;
 	/* Set option 1G speed */
 	if ((phy->req_line_speed == ELINK_SPEED_1000) ||
+	    (phy->req_line_speed == ELINK_SPEED_2500) ||
 	    (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
 		ELINK_DEBUG_P0(sc, "Setting 1G force\n");
 		elink_cl45_write(sc, phy,
@@ -10173,6 +10175,22 @@
 		elink_cl45_read(sc, phy,
 				MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
 		ELINK_DEBUG_P1(sc, "1.7 = 0x%x\n", tmp1);
+		if ((phy->req_line_speed == ELINK_SPEED_2500) &&
+		    (phy->speed_cap_mask &
+		     (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
+		      PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))) {
+			elink_cl45_read_and_write(sc, phy,
+						  MDIO_AN_DEVAD,
+						  MDIO_AN_REG_8727_MISC_CTRL2,
+						  ~(1<<5));
+			elink_cl45_write(sc, phy,
+					 MDIO_AN_DEVAD,
+					 MDIO_AN_REG_8727_MISC_CTRL1, 0x0010);
+		} else {
+			elink_cl45_write(sc, phy,
+					 MDIO_AN_DEVAD,
+					 MDIO_AN_REG_8727_MISC_CTRL1, 0x001C);
+		}
 		/* Power down the XAUI until link is up in case of dual-media
 		 * and 1G
 		 */
@@ -10194,7 +10212,7 @@
 
 		ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
 		elink_cl45_write(sc, phy,
-				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
+				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL2, 0);
 		elink_cl45_write(sc, phy,
 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
 	} else {
@@ -10202,8 +10220,11 @@
 		 * registers although it is default
 		 */
 		elink_cl45_write(sc, phy,
-				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
+				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL2,
 				 0x0020);
+		elink_cl45_write(sc, phy,
+				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL1,
+				 0x001C);
 		elink_cl45_write(sc, phy,
 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
 		elink_cl45_write(sc, phy,
@@ -10495,6 +10516,11 @@
 		vars->line_speed = ELINK_SPEED_10000;
 		ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
 			   params->port);
+	} else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
+		link_up = 1;
+		vars->line_speed = ELINK_SPEED_2500;
+		ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G\n",
+			   params->port);
 	} else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
 		link_up = 1;
 		vars->line_speed = ELINK_SPEED_1000;
@@ -10526,7 +10552,8 @@
 	}
 
 	if ((ELINK_DUAL_MEDIA(params)) &&
-	    (phy->req_line_speed == ELINK_SPEED_1000)) {
+	    ((phy->req_line_speed == ELINK_SPEED_1000) ||
+	     (phy->req_line_speed == ELINK_SPEED_2500))) {
 		elink_cl45_read(sc, phy,
 				MDIO_PMA_DEVAD,
 				MDIO_PMA_REG_8727_PCS_GP, &val1);
@@ -12703,6 +12730,7 @@
 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
 	.mdio_ctrl	= 0,
 	.supported	= (ELINK_SUPPORTED_10000baseT_Full |
+			   ELINK_SUPPORTED_2500baseX_Full |
 			   ELINK_SUPPORTED_1000baseT_Full |
 			   ELINK_SUPPORTED_Autoneg |
 			   ELINK_SUPPORTED_FIBRE |