diff --git a/sys/dev/bxe/bxe_elink.c b/sys/dev/bxe/bxe_elink.c
--- a/sys/dev/bxe/bxe_elink.c
+++ b/sys/dev/bxe/bxe_elink.c
@@ -5029,7 +5029,7 @@
 					   uint8_t always_autoneg)
 {
 	struct bxe_softc *sc = params->sc;
-	uint16_t val16, digctrl_kx1, digctrl_kx2;
+	uint16_t misc1_val, val16, digctrl_kx1, digctrl_kx2;
 
 	/* Clear XFI clock comp in non-10G single lane mode. */
 	elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
@@ -5044,6 +5044,20 @@
 					 0x1000);
 		ELINK_DEBUG_P0(sc, "set SGMII AUTONEG\n");
 	} else {
+		if (fiber_mode && (phy->req_line_speed == ELINK_SPEED_2500) &&
+		    (phy->speed_cap_mask &
+		     (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
+		      PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))) {
+			elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
+					MDIO_WC_REG_SERDESDIGITAL_MISC1,
+					&misc1_val);
+			misc1_val &= ~(0x1f);
+			misc1_val |= 0x10;
+			elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
+					 MDIO_WC_REG_SERDESDIGITAL_MISC1,
+					 misc1_val);
+		}
+
 		elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
 				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
 		val16 &= 0xcebf;
@@ -5054,6 +5068,7 @@
 			val16 |= 0x2000;
 			break;
 		case ELINK_SPEED_1000:
+		case ELINK_SPEED_2500:
 			val16 |= 0x0040;
 			break;
 		default:
@@ -12533,6 +12548,7 @@
 			   ELINK_SUPPORTED_100baseT_Full |
 			   ELINK_SUPPORTED_1000baseT_Full |
 			   ELINK_SUPPORTED_1000baseKX_Full |
+			   ELINK_SUPPORTED_2500baseX_Full |
 			   ELINK_SUPPORTED_10000baseT_Full |
 			   ELINK_SUPPORTED_10000baseKR_Full |
 			   ELINK_SUPPORTED_20000baseKR2_Full |