diff --git a/sys/riscv/include/cpu.h b/sys/riscv/include/cpu.h
--- a/sys/riscv/include/cpu.h
+++ b/sys/riscv/include/cpu.h
@@ -83,6 +83,14 @@
 /* SiFive marchid values */
 #define	MARCHID_SIFIVE_U7	MARCHID_COMMERCIAL(7)
 
+/*
+ * MMU virtual-addressing modes. Support for each level implies the previous,
+ * so Sv48-enabled systems MUST support Sv39, etc.
+ */
+#define	MMU_SV39	0x1	/* 3-level paging */
+#define	MMU_SV48	0x2	/* 4-level paging */
+#define	MMU_SV57	0x4	/* 5-level paging */
+
 extern char btext[];
 extern char etext[];
 
diff --git a/sys/riscv/include/md_var.h b/sys/riscv/include/md_var.h
--- a/sys/riscv/include/md_var.h
+++ b/sys/riscv/include/md_var.h
@@ -40,6 +40,7 @@
 extern register_t mvendorid;
 extern register_t marchid;
 extern register_t mimpid;
+extern u_int mmu_caps;
 
 struct dumperinfo;
 struct minidumpstate;
diff --git a/sys/riscv/riscv/identcpu.c b/sys/riscv/riscv/identcpu.c
--- a/sys/riscv/riscv/identcpu.c
+++ b/sys/riscv/riscv/identcpu.c
@@ -65,10 +65,13 @@
 register_t marchid;	/* The architecture ID */
 register_t mimpid;	/* The implementation ID */
 
+u_int mmu_caps;
+
 struct cpu_desc {
 	const char	*cpu_mvendor_name;
 	const char	*cpu_march_name;
 	u_int		isa_extensions;		/* Single-letter extensions. */
+	u_int		mmu_caps;
 };
 
 struct cpu_desc cpu_desc[MAXCPU];
@@ -269,6 +272,20 @@
 }
 
 #ifdef FDT
+static void
+parse_mmu_fdt(struct cpu_desc *desc, phandle_t node)
+{
+	char mmu[16];
+
+	desc->mmu_caps |= MMU_SV39;
+	if (OF_getprop(node, "mmu-type", mmu, sizeof(mmu)) > 0) {
+		if (strcmp(mmu, "riscv,sv48") == 0)
+			desc->mmu_caps |= MMU_SV48;
+		else if (strcmp(mmu, "riscv,sv57") == 0)
+			desc->mmu_caps |= MMU_SV48 | MMU_SV57;
+	}
+}
+
 static void
 identify_cpu_features_fdt(u_int cpu, struct cpu_desc *desc)
 {
@@ -317,6 +334,9 @@
 		if (parse_riscv_isa(desc, isa, len) != 0)
 			return;
 
+		/* Check MMU features. */
+		parse_mmu_fdt(desc, node);
+
 		/* We are done. */
 		break;
 	}
@@ -356,6 +376,11 @@
 	/* Update the capabilities exposed to userspace via AT_HWCAP. */
 	UPDATE_CAP(elf_hwcap, (u_long)desc->isa_extensions);
 
+	/*
+	 * MMU capabilities, e.g. Sv48.
+	 */
+	UPDATE_CAP(mmu_caps, desc->mmu_caps);
+
 #undef UPDATE_CAP
 }
 
@@ -429,6 +454,11 @@
 		    desc->cpu_mvendor_name, desc->cpu_march_name, hart);
 
 		printf("  marchid=%#lx, mimpid=%#lx\n", marchid, mimpid);
+		printf("  MMU: %#b\n", desc->mmu_caps,
+		    "\020"
+		    "\01Sv39"
+		    "\02Sv48"
+		    "\03Sv57");
 		printf("  ISA: %#b\n", desc->isa_extensions,
 		    "\020"
 		    "\01Atomic"
diff --git a/sys/riscv/riscv/pmap.c b/sys/riscv/riscv/pmap.c
--- a/sys/riscv/riscv/pmap.c
+++ b/sys/riscv/riscv/pmap.c
@@ -704,7 +704,7 @@
 
 	mode = 0;
 	TUNABLE_INT_FETCH("vm.pmap.mode", &mode);
-	if (mode == PMAP_MODE_SV48) {
+	if (mode == PMAP_MODE_SV48 && (mmu_caps & MMU_SV48) != 0) {
 		/*
 		 * Enable SV48 mode: allocate an L0 page and set SV48 mode in
 		 * SATP.  If the implementation does not provide SV48 mode,