diff --git a/sys/arm64/rockchip/rk_dwc3.c b/sys/arm64/rockchip/rk_dwc3.c
--- a/sys/arm64/rockchip/rk_dwc3.c
+++ b/sys/arm64/rockchip/rk_dwc3.c
@@ -141,11 +141,7 @@
 		    clk_get_name(sc->clk_bus));
 		return (ENXIO);
 	}
-	if (sc->type == RK3399) {
-		if (clk_get_by_ofw_name(dev, 0, "grf_clk", &sc->clk_grf) != 0) {
-			device_printf(dev, "Cannot get grf_clk clock\n");
-			return (ENXIO);
-		}
+	if (clk_get_by_ofw_name(dev, 0, "grf_clk", &sc->clk_grf) == 0) {
 		err = clk_enable(sc->clk_grf);
 		if (err != 0) {
 			device_printf(dev, "Could not enable clock %s\n",
diff --git a/sys/dev/usb/controller/dwc3.h b/sys/dev/usb/controller/dwc3.h
--- a/sys/dev/usb/controller/dwc3.h
+++ b/sys/dev/usb/controller/dwc3.h
@@ -49,6 +49,7 @@
 
 #define	DWC3_GUCTL1		0xc11c
 #define	 DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	(1 << 28)
+#define	 DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK (1 << 26)
 
 #define	DWC3_GSNPSID		0xc120
 #define	DWC3_GGPIO		0xc124
diff --git a/sys/dev/usb/controller/dwc3.c b/sys/dev/usb/controller/dwc3.c
--- a/sys/dev/usb/controller/dwc3.c
+++ b/sys/dev/usb/controller/dwc3.c
@@ -366,6 +366,7 @@
 #ifdef FDT
 	phandle_t node;
 	phy_t usb2_phy, usb3_phy;
+	uint32_t reg;
 #endif
 	int error, rid;
 
@@ -403,7 +404,13 @@
 	error = phy_get_by_ofw_name(dev, node, "usb3-phy", &usb3_phy);
 	if (error == 0 && usb3_phy != NULL)
 		phy_enable(usb3_phy);
-
+	else {
+		reg = DWC3_READ(sc, DWC3_GUCTL1);
+		if (bootverbose)
+			device_printf(dev, "Forcing USB2 clock only\n");
+		reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
+		DWC3_WRITE(sc, DWC3_GUCTL1, reg);
+	}
 	snps_dwc3_configure_phy(sc, node);
 skip_phys:
 #endif