Index: sys/arm64/conf/QUARTZ64 =================================================================== --- sys/arm64/conf/QUARTZ64 +++ sys/arm64/conf/QUARTZ64 @@ -0,0 +1,190 @@ +# $Id$ + +cpu ARM64 +ident QUARTZ64 + +options FDT +options FDT_DTB_STATIC +makeoptions FDT_DTS_FILE=rockchip/rk3566-quartz64-a.dts + +makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols +makeoptions WITH_CTF=1 # Run ctfconvert(1) for DTrace support +makeoptions MODULES_OVERRIDE="" + +options SCHED_ULE # ULE scheduler +options NUMA # NonUniform Memory Architecture support +options PREEMPTION # Enable kernel thread preemption +options INET # InterNETworking +#options VIMAGE # Subsystem virtualization, e.g. VNET +#options INET6 # IPv6 communications protocols +#options SCTP # Stream Control Transmission Protocol +options IPSEC_SUPPORT # Allow kldload of ipsec and tcpmd5 +options TCP_HHOOK # hhook(9) framework for TCP +options TCP_OFFLOAD # TCP offload +options TCP_RFC7413 # TCP Fast Open +options FFS # Berkeley Fast Filesystem +options SOFTUPDATES # Enable FFS soft updates support +options UFS_ACL # Support for access control lists +options UFS_DIRHASH # Improve performance on big directories +options UFS_GJOURNAL # Enable gjournal-based UFS journaling +options QUOTA # Enable disk quotas for UFS +options MSDOSFS # MSDOS Filesystem +options CD9660 # ISO 9660 Filesystem +options PROCFS # Process filesystem (requires PSEUDOFS) +options PSEUDOFS # Pseudo-filesystem framework +options GEOM_LABEL # Provides labelization +options COMPAT_FREEBSD32 # Compatible with FreeBSD/arm +options KTRACE # ktrace(1) support +options STACK # stack(9) support +options SYSVSHM # SYSV-style shared memory +options SYSVMSG # SYSV-style message queues +options SYSVSEM # SYSV-style semaphores +options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B realtime extensions +options PRINTF_BUFR_SIZE=128 # Prevent printf output interspersion +options KBD_INSTALL_CDEV # install a CDEV entry in /dev +options HWPMC_HOOKS # Necessary kernel hooks for hwpmc(4) +options KDTRACE_FRAME # Ensure frames are compiled in +options KDTRACE_HOOKS # Kernel DTrace hooks +options VFP # Floating-point support +options SMP +options INTRNG +options LINUX_BOOT_ABI # Boot using booti command from U-Boot + +# Debugging support. Always need this: +options KDB # Enable kernel debugger support. +options KDB_TRACE # Print a stack trace for a panic. +options DDB # Support DDB. + +options VERBOSE_SYSINIT=0 # Support debug.verbose_sysinit + +# SoC support +options SOC_ROCKCHIP_RK3568 + +# CPU frequency control +device cpufreq + +# Bus drivers +device pci +options PCI_HP # PCI-Express native HotPlug +options PCI_IOV # PCI SR-IOV support + +# PCI/PCI-X/PCIe Ethernet NICs that use iflib infrastructure +device mdio +device mii +device miibus +device iflib +device em # Intel Gig ethernet + +# NVM Express (NVMe) support +device nvme # base NVMe driver +device nvd # expose NVMe namespaces as disks + +# MMC/SD/SDIO Card slot support +device rk_dwmmc +device rk_emmcphy +device dwmmc +device mmc # mmc/sd bus +device mmcsd # mmc/sd flash cards +device sdhci + +# SCSI/CAM Block devices +device ahci +device scbus +device da +device cd +device umass + +# Serial (COM) ports +device uart # Generic UART driver +device uart_ns8250 # ns8250-type UART driver +device uart_snps + +# USB support +options USB_DEBUG # enable debug msgs +options USB_VERBOSE # print vendor names etc +device rk_usb2phy # Rockchip USB2PHY +device rk_typec_phy # Rockchip TypeC PHY +device rk_dwc3 # Rockchip DWC3 controller +device dwcotg # DWC OTG controller +device dwc3 # Synopsys DWC3 controller +device ohci # OHCI USB interface +device ehci # EHCI USB interface (USB 2.0) +device xhci # XHCI USB interface (USB 3.0) +device usb # USB Bus (required) +device ukbd # Keyboard +device ums # Moues + +# USB ethernet support +device axe +device muge +device smcphy +device smsc +device ure + +# GPIO / PINCTRL +device rk_gpio # RockChip GPIO Controller +device dwgpio # Synopsys DesignWare APB GPIO Controller +device gpio +device gpioled +device gpioregulator +device rk_pinctrl # RockChip Pinmux Controller +device fdt_pinctrl + +# I2C +device rk_i2c # RockChip I2C controller +device iicbus +device iic +device syr827 # Silergy SYR827 PMIC +device tcs4525 # TCS 4525 PMIC +device rk817 # RockChip RK817 PMIC + +# SPI +device rk_spi # RockChip SPI controller +device spibus + +# Flash devices +device mx25l # SPI flash device + +# PWM +device rk_pwm +device pwm + +# Power and IO Domains +device rk_iodomain + +# Sysopsys Designware watchdog +device dwwdt + +# Console +device vt +device vt_efifb +device kbdmux + +# Generic HID device +device hid + +# EVDEV support +device evdev # input event device support +device uinput # install /dev/uinput cdev +options EVDEV_SUPPORT # evdev support in legacy drivers + +# Pseudo devices. +device bpf # Berkeley packet filter +device crypto # core crypto support +device loop # Network loopback +device ether # Ethernet support +device vlan # 802.1Q VLAN support +device tuntap # Packet tunnel. +device md # Memory "disks" +device gif # IPv6 and IPv4 tunneling +device firmware # firmware assist module +options EFIRT # EFI Runtime Services + +# EXT_RESOURCES pseudo devices +device clk +device phy +device hwreset +device nvmem +device regulator +device syscon +device intrng Index: sys/arm64/rockchip/clk/rk3568_cru.c =================================================================== --- sys/arm64/rockchip/clk/rk3568_cru.c +++ sys/arm64/rockchip/clk/rk3568_cru.c @@ -0,0 +1,1067 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2021, 2022 Soren Schmidt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#include +#include + + +#define RK3568_PLLSEL_CON(x) ((x) * 0x20) +#define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400) + +#define PNAME(_name) static const char *_name[] + +#define RK_PLLRATE(_hz, _ref, _fb, _post1, _post2, _dspd) \ +{ \ + .freq = _hz, \ + .refdiv = _ref, \ + .fbdiv = _fb, \ + .postdiv1 = _post1, \ + .postdiv2 = _post2, \ + .dsmpd = _dspd, \ +} + +/* PLL clock */ +#define RK_PLL(_id, _name, _pnames, _off, _shift) \ +{ \ + .type = RK3328_CLK_PLL, \ + .clk.pll = &(struct rk_clk_pll_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pnames, \ + .clkdef.parent_cnt = nitems(_pnames), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .base_offset = RK3568_PLLSEL_CON(_off), \ + .mode_reg = 0xc0, \ + .mode_shift = _shift, \ + .rates = rk3568_pll_rates, \ + }, \ +} + +/* Clock for ARM core(s) */ +#define RK_ARMDIV(_id, _nm, _pn, _r, _off, _ds, _dw, _ms, _mw, _mp, _ap)\ +{ \ + .type = RK_CLK_ARMCLK, \ + .clk.armclk = &(struct rk_clk_armclk_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _nm, \ + .clkdef.parent_names = _pn, \ + .clkdef.parent_cnt = nitems(_pn), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .muxdiv_offset = RK3568_CLKSEL_CON(_off), \ + .mux_shift = _ms, \ + .mux_width = _mw, \ + .div_shift = _ds, \ + .div_width = _dw, \ + .main_parent = _mp, \ + .alt_parent = _ap, \ + .rates = _r, \ + .nrates = nitems(_r), \ + }, \ +} + +/* Composite */ +#define RK_COMPOSITE(_id, _name, _pnames, _o, _ms, _mw, _ds, _dw, _go, _gw,_f) \ +{ \ + .type = RK_CLK_COMPOSITE, \ + .clk.composite = &(struct rk_clk_composite_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pnames, \ + .clkdef.parent_cnt = nitems(_pnames), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ + .mux_shift = _ms, \ + .mux_width = _mw, \ + .div_shift = _ds, \ + .div_width = _dw, \ + .gate_offset = RK3568_CLKGATE_CON(_go), \ + .gate_shift = _gw, \ + .flags = RK_CLK_COMPOSITE_HAVE_MUX | \ + RK_CLK_COMPOSITE_HAVE_GATE | _f, \ + }, \ +} + +/* Composite no mux */ +#define RK_COMPNOMUX(_id, _name, _pname, _o, _ds, _dw, _go, _gw, _f) \ +{ \ + .type = RK_CLK_COMPOSITE, \ + .clk.composite = &(struct rk_clk_composite_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = (const char *[]){_pname}, \ + .clkdef.parent_cnt = 1, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ + .div_shift = _ds, \ + .div_width = _dw, \ + .gate_offset = RK3568_CLKGATE_CON(_go), \ + .gate_shift = _gw, \ + .flags = RK_CLK_COMPOSITE_HAVE_GATE | _f, \ + }, \ +} + +/* Composite no div */ +#define RK_COMPNODIV(_id, _name, _pnames, _o, _ms, _mw, _go, _gw, _f) \ +{ \ + .type = RK_CLK_COMPOSITE, \ + .clk.composite = &(struct rk_clk_composite_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pnames, \ + .clkdef.parent_cnt = nitems(_pnames), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ + .mux_shift = _ms, \ + .mux_width = _mw, \ + .gate_offset = RK3568_CLKGATE_CON(_go), \ + .gate_shift = _gw, \ + .flags = RK_CLK_COMPOSITE_HAVE_MUX | \ + RK_CLK_COMPOSITE_HAVE_GATE | _f, \ + }, \ +} + +/* Composite div only */ +#define RK_COMPDIV(_id, _name, _pname, _o, _ds, _dw, _f) \ +{ \ + .type = RK_CLK_COMPOSITE, \ + .clk.composite = &(struct rk_clk_composite_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = (const char *[]){_pname}, \ + .clkdef.parent_cnt = 1, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ + .div_shift = _ds, \ + .div_width = _dw, \ + .flags = _f, \ + }, \ +} + + +/* Fixed factor mux/div */ +#define RK_FACTOR(_id, _name, _pname, _mult, _div) \ +{ \ + .type = RK_CLK_FIXED, \ + .clk.fixed = &(struct clk_fixed_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = (const char *[]){_pname}, \ + .clkdef.parent_cnt = 1, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .mult = _mult, \ + .div = _div, \ + }, \ +} + +/* Fractional */ +#define RK_FRACTION(_id, _name, _pname, _o, _go, _gw, _f) \ +{ \ + .type = RK_CLK_FRACT, \ + .clk.fract = &(struct rk_clk_fract_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = (const char *[]){_pname}, \ + .clkdef.parent_cnt = 1, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .offset = RK3568_CLKSEL_CON(_o), \ + .gate_offset = RK3568_CLKGATE_CON(_go), \ + .gate_shift = _gw, \ + .flags = RK_CLK_FRACT_HAVE_GATE | _f, \ + }, \ +} + +/* Multiplexer */ +#define RK_MUX(_id, _name, _pnames, _o, _ms, _mw, _f) \ +{ \ + .type = RK_CLK_MUX, \ + .clk.mux = &(struct rk_clk_mux_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pnames, \ + .clkdef.parent_cnt = nitems(_pnames), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .offset = RK3568_CLKSEL_CON(_o), \ + .shift = _ms, \ + .width = _mw, \ + .mux_flags = _f, \ + }, \ +} + +#define RK_GATE(_id, _name, _pname, _o, _s) \ +{ \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .offset = RK3568_CLKGATE_CON(_o), \ + .shift = _s, \ +} + +struct rk_clk_pll_rate rk3568_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd */ + RK_PLLRATE(2208000000, 1, 92, 1, 1, 1), + RK_PLLRATE(2184000000, 1, 91, 1, 1, 1), + RK_PLLRATE(2160000000, 1, 90, 1, 1, 1), + RK_PLLRATE(2088000000, 1, 87, 1, 1, 1), + RK_PLLRATE(2064000000, 1, 86, 1, 1, 1), + RK_PLLRATE(2040000000, 1, 85, 1, 1, 1), + RK_PLLRATE(2016000000, 1, 84, 1, 1, 1), + RK_PLLRATE(1992000000, 1, 83, 1, 1, 1), + RK_PLLRATE(1920000000, 1, 80, 1, 1, 1), + RK_PLLRATE(1896000000, 1, 79, 1, 1, 1), + RK_PLLRATE(1800000000, 1, 75, 1, 1, 1), + RK_PLLRATE(1704000000, 1, 71, 1, 1, 1), + RK_PLLRATE(1608000000, 1, 67, 1, 1, 1), + RK_PLLRATE(1600000000, 3, 200, 1, 1, 1), + RK_PLLRATE(1584000000, 1, 132, 2, 1, 1), + RK_PLLRATE(1560000000, 1, 130, 2, 1, 1), + RK_PLLRATE(1536000000, 1, 128, 2, 1, 1), + RK_PLLRATE(1512000000, 1, 126, 2, 1, 1), + RK_PLLRATE(1488000000, 1, 124, 2, 1, 1), + RK_PLLRATE(1464000000, 1, 122, 2, 1, 1), + RK_PLLRATE(1440000000, 1, 120, 2, 1, 1), + RK_PLLRATE(1416000000, 1, 118, 2, 1, 1), + RK_PLLRATE(1400000000, 3, 350, 2, 1, 1), + RK_PLLRATE(1392000000, 1, 116, 2, 1, 1), + RK_PLLRATE(1368000000, 1, 114, 2, 1, 1), + RK_PLLRATE(1344000000, 1, 112, 2, 1, 1), + RK_PLLRATE(1320000000, 1, 110, 2, 1, 1), + RK_PLLRATE(1296000000, 1, 108, 2, 1, 1), + RK_PLLRATE(1272000000, 1, 106, 2, 1, 1), + RK_PLLRATE(1248000000, 1, 104, 2, 1, 1), + RK_PLLRATE(1200000000, 1, 100, 2, 1, 1), + RK_PLLRATE(1188000000, 1, 99, 2, 1, 1), + RK_PLLRATE(1104000000, 1, 92, 2, 1, 1), + RK_PLLRATE(1100000000, 3, 275, 2, 1, 1), + RK_PLLRATE(1008000000, 1, 84, 2, 1, 1), + RK_PLLRATE(1000000000, 3, 250, 2, 1, 1), + RK_PLLRATE(912000000, 1, 76, 2, 1, 1), + RK_PLLRATE(816000000, 1, 68, 2, 1, 1), + RK_PLLRATE(800000000, 3, 200, 2, 1, 1), + RK_PLLRATE(700000000, 3, 350, 4, 1, 1), + RK_PLLRATE(696000000, 1, 116, 4, 1, 1), + RK_PLLRATE(600000000, 1, 100, 4, 1, 1), + RK_PLLRATE(594000000, 1, 99, 4, 1, 1), + RK_PLLRATE(500000000, 1, 125, 6, 1, 1), + RK_PLLRATE(408000000, 1, 68, 2, 2, 1), + RK_PLLRATE(312000000, 1, 78, 6, 1, 1), + RK_PLLRATE(216000000, 1, 72, 4, 2, 1), + RK_PLLRATE(200000000, 1, 100, 3, 4, 1), + RK_PLLRATE(148500000, 1, 99, 4, 4, 1), + RK_PLLRATE(100000000, 1, 150, 6, 6, 1), + RK_PLLRATE(96000000, 1, 96, 6, 4, 1), + RK_PLLRATE(74250000, 2, 99, 4, 4, 1), + {}, +}; + +static struct rk_clk_armclk_rates rk3568_armclk_rates[] = { + {2208000000, 1}, + {2160000000, 1}, + {2064000000, 1}, + {2016000000, 1}, + {1992000000, 1}, + {1800000000, 1}, + {1704000000, 1}, + {1608000000, 1}, + {1512000000, 1}, + {1488000000, 1}, + {1416000000, 1}, + {1200000000, 1}, + {1104000000, 1}, + {1008000000, 1}, + { 816000000, 1}, + { 696000000, 1}, + { 600000000, 1}, + { 408000000, 1}, + { 312000000, 1}, + { 216000000, 1}, + { 96000000, 1}, + {}, +}; + +/* Parent clock defines */ +PNAME(mux_pll_p) = { "xin24m" }; +PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; +PNAME(mux_armclk_p) = { "apll", "gpll" }; +PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", + "i2s0_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", + "i2s0_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", + "i2s1_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", + "i2s1_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", + "xin_osc0_half"}; +PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", + "i2s3_mclkin", "xin_osc0_half" }; +PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", + "i2s3_mclkin", "xin_osc0_half" }; +PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" }; +PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" }; +PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; +PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; +PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" }; +PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" }; +PNAME(npll_gpll_p) = { "npll", "gpll" }; +PNAME(cpll_gpll_p) = { "cpll", "gpll" }; +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" }; +PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; +PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" }; +PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", + "xin24m" }; +PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" }; +PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"}; +PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" }; +PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; +PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; +PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", + "gpll_100m", "xin24m" }; +PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" }; +PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; +PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; +PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; +PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; +PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; +PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; +PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; +PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" }; +PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" }; +PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" }; +PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" }; +PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" }; +PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", + "gpll_150m" }; +PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" }; +PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", + "cpll_50m", "clk_osc0_div_375k" }; +PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; +PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" }; +PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", + "gpll_100m", "xin24m" }; +PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", + "cpll_50m", "clk_osc0_div_750k" }; +PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", + "xin24m" }; +PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" }; +PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" }; +PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; +PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" }; +PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", + "gpll_100m", "xin24m" }; +PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" }; +PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" }; +PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" }; +PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", + "xin24m" }; +PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" }; +PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; +PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" }; +PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" }; +PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; +PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", + "gpll_300m", "xin24m" }; +PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", + "gpll_200m", "xin24m" }; +PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" }; +PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" }; +PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", + "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" }; +PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" }; +PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", + "clk_gmac0_xpcs_mii" }; +PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" }; +PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", + "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" }; +PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" }; +PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", + "clk_gmac1_xpcs_mii" }; +PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" }; +PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; +PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "npll", "vpll" }; + +/* CLOCKS */ +static struct rk_clk clks[] = { + /* External clocks */ + LINK("xin24m"), + LINK("clk_rtc_32k"), + LINK("usb480m_phy"), + LINK("mpll"), // SOS SCRU + LINK("i2s0_mclkin"), + LINK("i2s1_mclkin"), + LINK("i2s2_mclkin"), + LINK("i2s3_mclkin"), + LINK("gpu_pvtpll_out"), + LINK("npu_pvtpll_out"), + LINK("gmac0_clkin"), + LINK("gmac1_clkin"), + LINK("clk_gmac0_xpcs_mii"), + LINK("clk_gmac1_xpcs_mii"), + LINK("dummy"), + + /* PLL's */ + RK_PLL(PLL_APLL, "apll", mux_pll_p, 0, 0), + RK_PLL(PLL_DPLL, "dpll", mux_pll_p, 1, 2), + RK_PLL(PLL_GPLL, "gpll", mux_pll_p, 2, 6), + RK_PLL(PLL_CPLL, "cpll", mux_pll_p, 3, 4), + RK_PLL(PLL_NPLL, "npll", mux_pll_p, 4, 10), + RK_PLL(PLL_VPLL, "vpll", mux_pll_p, 5, 12), + RK_ARMDIV(ARMCLK, "armclk", mux_armclk_p, rk3568_armclk_rates, 0, 0, 5, + 6, 2, 0, 1), + RK_FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 1, 2), + RK_FACTOR(0, "xin_osc0_half", "xin24m", 1, 2), + RK_MUX(USB480M, "usb480m", mux_usb480m_p, -16, 14, 2, 0), + + /* Clocks */ + RK_COMPNOMUX(0, "gpll_400m", "gpll", 75, 0, 5, 35, 0, 0), + RK_COMPNOMUX(0, "gpll_300m", "gpll", 75, 8, 5, 35, 1, 0), + RK_COMPNOMUX(0, "gpll_200m", "gpll", 76, 0, 5, 35, 2, 0), + RK_COMPNOMUX(0, "gpll_150m", "gpll", 76, 8, 5, 35, 3, 0), + RK_COMPNOMUX(0, "gpll_100m", "gpll", 77, 0, 5, 35, 4, 0), + RK_COMPNOMUX(0, "gpll_75m", "gpll", 77, 8, 5, 35, 5, 0), + RK_COMPNOMUX(0, "gpll_20m", "gpll", 78, 0, 6, 35, 6, 0), + RK_COMPNOMUX(CPLL_500M, "cpll_500m", "cpll", 78, 8, 5, 35, 7, 0), + RK_COMPNOMUX(CPLL_333M, "cpll_333m", "cpll", 79, 0, 5, 35, 8, 0), + RK_COMPNOMUX(CPLL_250M, "cpll_250m", "cpll", 79, 8, 5, 35, 9, 0), + RK_COMPNOMUX(CPLL_125M, "cpll_125m", "cpll", 80, 0, 5, 35, 10, 0), + RK_COMPNOMUX(CPLL_100M, "cpll_100m", "cpll", 82, 0, 5, 35, 11, 0), + RK_COMPNOMUX(CPLL_62P5M, "cpll_62p5", "cpll", 80, 8, 5, 35, 12, 0), + RK_COMPNOMUX(CPLL_50M, "cpll_50m", "cpll", 81, 0, 5, 35, 13, 0), + RK_COMPNOMUX(CPLL_25M, "cpll_25m", "cpll", 81, 8, 6, 35, 14, 0), + RK_COMPNOMUX(0, "clk_osc0_div_750k", "xin24m", 82, 8, 6, 35, 15, 0), + RK_COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, 2, 8, 2, 0, 4, 0, + 5, 0), + RK_COMPNODIV(0, "sclk_core", sclk_core_pre_p, 2, 15, 1, 0, 7, 0), + RK_COMPNOMUX(0, "atclk_core", "armclk", 3, 0, 5, 0, 8, 0), + RK_COMPNOMUX(0, "gicclk_core", "armclk", 3, 8, 5, 0, 9, 0), + RK_COMPNOMUX(0, "pclk_core_pre", "armclk", 4, 0, 5, 0, 10, 0), + RK_COMPNOMUX(0, "periphclk_core_pre", "armclk", 4, 8, 5, 0, 11, 0), + RK_COMPNOMUX(0, "tsclk_core", "periphclk_core_pre", 5, 0, 4, 0, 14, 0), + RK_COMPNOMUX(0, "cntclk_core", "periphclk_core_pre", 5, 4, 4, 0, 15, 0), + RK_COMPNOMUX(0, "aclk_core", "sclk_core", 5, 8, 5, 1, 0, 0), + RK_COMPNODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", + gpll150_gpll100_gpll75_xin24m_p, 5, 14, 2, 1, 2, 0), + RK_COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 6, 6, 2, + 0, 4, 2, 0, 0), + RK_MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, 6, 11, + 1, 0), + RK_COMPDIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 6, 8, 2, 0), + RK_COMPDIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 6, 12, 4, 0), + RK_COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 7, 6, 1, 0, 4, 3, + 0, 0), + RK_MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, 7, 8, 1, + 0 | 0), + RK_MUX(CLK_NPU, "clk_npu", clk_npu_p, 7, 15, 1, 0), + RK_COMPNOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 8, 0, 4, 3, 2, 0), + RK_COMPNOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 8, 4, 4, 3, 3, 0), + RK_COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, 9, + 6, 2, 0, 5, 4, 0, 0), + RK_MUX(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, 9, 15, 1, + RK_CLK_COMPOSITE_GRF), + RK_COMPNOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", 10, 0, 2, 4, 2, 0), + RK_COMPNODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", + gpll200_gpll150_gpll100_xin24m_p, 10, 8, 2, 5, 0, 0), + RK_COMPNODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", + gpll150_gpll100_gpll75_xin24m_p, 10, 10, 2, 5, 1, 0), + RK_COMPNODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", + gpll100_gpll75_gpll50_p, 10, 12, 2, 5, 9, 0), + RK_COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", + gpll_cpll_npll_p, 11, 8, 2, 0, 7, 6, 0, 0), + RK_MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, 11, 10, + 2, 0), + RK_FRACTION(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", + "clk_i2s0_8ch_tx_src", 12, 6, 1, 0), + RK_COMPNODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, 11, + 15, 1, 6, 3, 0), + RK_COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", + gpll_cpll_npll_p, 13, 8, 2, 0, 7, 6, 4, 0), + RK_MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, 13, 10, + 2, 0), + RK_FRACTION(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", + "clk_i2s0_8ch_rx_src", 14, 6, 5, 0), + RK_COMPNODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, 13, + 15, 1, 6, 7, 0), + RK_COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", + gpll_cpll_npll_p, 15, 8, 2, 0, 7, 6, 8, 0), + RK_MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, 15, 10, + 2, 0), + RK_FRACTION(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", + "clk_i2s1_8ch_tx_src", 16, 6, 9, 0), + RK_COMPNODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, 15, + 15, 1, 6, 11, 0), + RK_COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", + gpll_cpll_npll_p, 17, 8, 2, 0, 7, 6, 12, 0), + RK_MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, 17, 10, + 2, 0), + RK_FRACTION(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", + "clk_i2s1_8ch_rx_src", 18, 6, 13, 0), + RK_COMPNODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, 17, + 15, 1, 6, 15, 0), + RK_COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 19, + 8, 2, 0, 7, 7, 0, 0), + RK_MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, 19, 10, 2, 0), + RK_FRACTION(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", + 20, 7, 1, 0), + RK_COMPNODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, 19, 15, 1, 7, + 3, 0), + RK_COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", + gpll_cpll_npll_p, 21, 8, 2, 0, 7, 7, 4, 0), + RK_MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, 21, 10, + 2, 0), + RK_FRACTION(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", + "clk_i2s3_2ch_tx_src", 22, 7, 5, 0), + RK_COMPNODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, 21, + 15, 1, 7, 7, 0), + RK_COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", + gpll_cpll_npll_p, 83, 8, 2, 0, 7, 7, 8, 0), + RK_MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, 83, 10, + 2, 0), + RK_FRACTION(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", + "clk_i2s3_2ch_rx_src", 84, 7, 9, 0), + RK_COMPNODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, 83, + 15, 1, 7, 11, 0), + RK_COMPNODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 23, 8, 2, 5, 15, 0), + RK_COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 23, + 14, 1, 0, 7, 7, 14, 0), + RK_MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, 23, 15, 1, 0), + RK_FRACTION(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", + "mclk_spdif_8ch_src", 24, 7, 15, 0), + RK_COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 25, 14, 1, + 0, 6, 8, 1, 0), + RK_MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, 25, 15, 1, 0), + RK_FRACTION(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", 26, + 8, 2, 0), + RK_COMPNODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 23, 10, 2, + 8, 4, 0), + RK_COMPNODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", + gpll200_gpll150_gpll100_xin24m_p, 27, 0, 2, 8, 7, 0), + RK_COMPNODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", + gpll150_gpll100_gpll75_xin24m_p, 27, 2, 2, 8, 8, 0), + RK_COMPNODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", + gpll200_gpll150_gpll100_p, 27, 4, 2, 8, 13, 0), + RK_COMPNODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", + gpll300_gpll200_gpll100_p, 27, 6, 2, 8, 14, 0), + RK_COMPNODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 28, 0, 2, 9, 1, 0), + RK_COMPNODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 28, 4, 3, 9, 4, 0), + RK_COMPNODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 28, 8, + 2, 9, 7, 0), + RK_COMPNODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 28, 12, 3, 9, 8, 0), + RK_COMPNODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 29, 0, 2, 10, 0, 0), + RK_COMPNOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 29, 4, 4, 10, 1, 0), + RK_COMPNODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, + 29, 8, 1, 10, 10, 0), + RK_COMPNODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, + 29, 9, 1, 10, 14, 0), + RK_COMPNODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 29, 13, 1, + 10, 4, 0), + RK_COMPNODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 30, + 0, 2, 14, 8, 0), + RK_COMPNODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 30, + 2, 2, 14, 9, 0), + RK_COMPNOMUX(PCLK_PHP, "pclk_php", "aclk_php", 30, 4, 4, 14, 10, 0), + RK_COMPNODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 30, 8, 3, 15, 1, 0), + RK_COMPNODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 30, 12, 3, 15, 3, 0), + RK_COMPNODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 31, 8, 2, + 15, 7, 0), + RK_COMPNODIV(CLK_MAC0_OUT, "clk_mac0_out", + cpll125_cpll50_cpll25_xin24m_p, 31, 14, 2, 15, 8, 0), + RK_COMPNODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 31, + 12, 2, 15, 4, 0), + RK_MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, 31, 2, 1, 0), + RK_FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 1, 5), + RK_FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 1, 50), + RK_FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 1, 2), + RK_FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 1, 20), + RK_MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", + mux_gmac0_rgmii_speed_p, 31, 4, 2, 0), + RK_MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", + mux_gmac0_rmii_speed_p, 31, 3, 1, 0), + RK_MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, 31, 0, + 2, 0), + RK_COMPNODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 32, + 0, 2, 16, 0, 0), + RK_COMPNODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 32, + 2, 2, 16, 1, 0), + RK_COMPNOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 32, 4, 4, 16, 2, 0), + RK_COMPNODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 32, 8, 3, 17, 1, 0), + RK_COMPNODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 33, 8, 2, + 17, 5, 0), + RK_COMPNODIV(CLK_MAC1_OUT, "clk_mac1_out", + cpll125_cpll50_cpll25_xin24m_p, 33, 14, 2, 17, 6, 0), + RK_COMPNODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 33, + 12, 2, 17, 2, 0), + RK_MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, 33, 2, 1, 0), + RK_FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 1, 5), + RK_FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 1, 50), + RK_FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 1, 2), + RK_FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 1, 20), + RK_MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", + mux_gmac1_rgmii_speed_p, 33, 4, 2, 0), + RK_MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", + mux_gmac1_rmii_speed_p, 33, 3, 1, 0), + RK_MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, 33, 0, + 2, 0), + RK_COMPNODIV(ACLK_PERIMID, "aclk_perimid", + gpll300_gpll200_gpll100_xin24m_p, 10, 4, 2, 14, 0, 0), + RK_COMPNODIV(HCLK_PERIMID, "hclk_perimid", + gpll150_gpll100_gpll75_xin24m_p, 10, 6, 2, 14, 1, 0), + RK_COMPNODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 34, + 0, 2, 18, 0, 0), + RK_COMPNOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 34, 4, 4, 18, 1, 0), + RK_COMPNOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 34, 8, 4, 18, 2, 0), + RK_COMPNODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 34, + 14, 2, 18, 11, 0), + RK_COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 35, 6, 2, 0, 5, 19, + 2, 0), + RK_COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 35, 14, + 2, 8, 6, 19, 8, 0), + RK_COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 36, 6, + 2, 0, 6, 19, 9, 0), + RK_COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 36, + 14, 2, 8, 6, 19, 10, 0), + RK_COMPNODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 37, + 0, 2, 20, 0, 0), + RK_COMPNOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 37, 8, 4, 20, 1, 0), + RK_COMPNOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 37, 12, 4, 20, 2, 0), + RK_COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 38, 6, + 2, 0, 5, 20, 6, 0), + RK_COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, 39, 10, 2, + 0, 8, 20, 10, 0), + RK_COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, 40, 10, 2, + 0, 8, 20, 11, 0), + RK_COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 41, 10, 2, + 0, 8, 20, 12, 0), + RK_COMPNODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, + 38, 8, 2, 21, 9, 0), + RK_COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 42, 7, 1, 0, 5, + 22, 0, 0), + RK_COMPNOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 42, 8, 4, 22, + 1, 0), + RK_COMPNODIV(ACLK_RGA_PRE, "aclk_rga_pre", + gpll300_cpll250_gpll100_xin24m_p, 43, 0, 2, 23, 0, 0), + RK_COMPNOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 43, 8, 4, 23, + 1, 0), + RK_COMPNOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 43, 12, 4, + 22, 12, 0), + RK_COMPNODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, + 43, 2, 2, 23, 6, 0), + RK_COMPNODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, + 43, 4, 2, 23, 9, 0), + RK_COMPNODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 43, 6, 2, + 23, 11, 0), + RK_COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 44, + 6, 2, 0, 5, 24, 0, 0), + RK_COMPNOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 44, + 8, 4, 24, 1, 0), + RK_COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, + 45, 14, 2, 0, 5, 24, 8, 0), + RK_COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, 47, + 7, 1, 0, 5, 25, 0, 0), + RK_COMPNOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 47, + 8, 4, 25, 1, 0), + RK_COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 48, + 6, 2, 0, 5, 25, 6, 0), + RK_COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, 49, + 14, 2, 8, 5, 25, 7, 0), + RK_COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", + gpll_cpll_npll_vpll_p, 49, 6, 2, 0, 5, 25, 8, 0), + RK_COMPNODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 50, + 0, 2, 26, 0, 0), + RK_COMPNODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 50, + 4, 2, 26, 1, 0), + RK_COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, + 51, 4, 2, 0, 3, 26, 5, 0), + RK_COMPNOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 51, 8, 7, 26, + 6, 0), + RK_COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 52, 8, + 2, 0, 7, 27, 13, 0), + RK_FRACTION(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", 53, 27, + 14, 0), + RK_MUX(0, "sclk_uart1_mux", sclk_uart1_p, 52, 12, 2, 0), + RK_COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 54, 8, + 2, 0, 7, 28, 1, 0), + RK_FRACTION(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", 55, 28, + 2, 0), + RK_MUX(0, "sclk_uart2_mux", sclk_uart2_p, 54, 12, 2, 0), + RK_COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 56, 8, + 2, 0, 7, 28, 5, 0), + RK_FRACTION(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", 57, 28, + 6, 0), + RK_MUX(0, "sclk_uart3_mux", sclk_uart3_p, 56, 12, 2, 0), + RK_COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 58, 8, + 2, 0, 7, 28, 9, 0), + RK_FRACTION(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", 59, 28, + 10, 0), + RK_MUX(0, "sclk_uart4_mux", sclk_uart4_p, 58, 12, 2, 0), + RK_COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 60, 8, + 2, 0, 7, 28, 13, 0), + RK_FRACTION(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", 61, 28, + 14, 0), + RK_MUX(0, "sclk_uart5_mux", sclk_uart5_p, 60, 12, 2, 0), + RK_COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 62, 8, + 2, 0, 7, 29, 1, 0), + RK_FRACTION(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", 63, 29, + 2, 0), + RK_MUX(0, "sclk_uart6_mux", sclk_uart6_p, 62, 12, 2, 0), + RK_COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 64, 8, + 2, 0, 7, 29, 5, 0), + RK_FRACTION(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", 65, 29, + 6, 0), + RK_MUX(0, "sclk_uart7_mux", sclk_uart7_p, 64, 12, 2, 0), + RK_COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 66, 8, + 2, 0, 7, 29, 9, 0), + RK_FRACTION(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", 67, 29, + 10, 0), + RK_MUX(0, "sclk_uart8_mux", sclk_uart8_p, 66, 12, 2, 0), + RK_COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 68, 8, + 2, 0, 7, 29, 13, 0), + RK_FRACTION(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", 69, 29, + 14, 0), + RK_MUX(0, "sclk_uart9_mux", sclk_uart9_p, 68, 12, 2, 0), + RK_COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 70, 7, 1, 0, 5, 27, + 6, 0), + RK_COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 70, 15, 1, 8, 5, 27, + 8, 0), + RK_COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 71, 7, 1, 0, 5, 27, + 10, 0), + RK_COMPNODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 71, 8, 2, 32, 10, 0), + RK_COMPNODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 72, 0, 1, + 30, 11, 0), + RK_COMPNODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 72, 2, 1, + 30, 13, 0), + RK_COMPNODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 72, 4, 1, + 30, 15, 0), + RK_COMPNODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 72, 6, 1, + 31, 1, 0), + RK_COMPNODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 72, 8, 1, + 31, 11, 0), + RK_COMPNODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 72, 10, 1, + 31, 14, 0), + RK_COMPNODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 72, 12, 1, + 32, 1, 0), + RK_COMPNODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 72, 14, 1, 32, + 11, 0), + RK_COMPNODIV(ACLK_TOP_HIGH, "aclk_top_high", + cpll500_gpll400_gpll300_xin24m_p, 73, 0, 2, 33, 0, 0), + RK_COMPNODIV(ACLK_TOP_LOW, "aclk_top_low", + gpll400_gpll300_gpll200_xin24m_p, 73, 4, 2, 33, 1, 0), + RK_COMPNODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 73, + 8, 2, 33, 2, 0), + RK_COMPNODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 73, + 12, 2, 33, 3, 0), + RK_COMPNODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 73, 15, 1, + 33, 9, 0), +}; + +/* GATES */ +static struct rk_cru_gate gates[] = { + RK_GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 1, 10), + RK_GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 1, 11), + RK_GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", 1, 12), + RK_GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 1, 9), + RK_GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 2, 3), + RK_GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 2, 6), + RK_GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 2, 7), + RK_GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 2, 8), + RK_GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", 2, 9), + RK_GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 3, 4), + RK_GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 3, 7), + RK_GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 3, 8), + RK_GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 3, 9), + RK_GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 3, 10), + RK_GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", + 3, 11), + RK_GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", 3, 12), + RK_GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", 4, 15), + RK_GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 5, 8), + RK_GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", 5, 4), + RK_GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", 5, 7), + RK_GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 5, 10), + RK_GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 5, 11), + RK_GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 5, 12), + RK_GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 5, 13), + RK_GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 6, 2), + RK_GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 6, 6), + RK_GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 6, 10), + RK_GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 6, 14), + RK_GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 7, 2), + RK_GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 7, 6), + RK_GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 7, 10), + RK_GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 5, 14), + RK_GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 7, 12), + RK_GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 7, 13), + RK_GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 8, 0), + RK_GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 8, 3), + RK_GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 8, 5), + RK_GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 8, 6), + RK_GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 8, 11), + RK_GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 8, 12), + RK_GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", + 8, 15), + RK_GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", 9, 10), + RK_GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", 9, 11), + RK_GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 26, 9), + RK_GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 26, 10), + RK_GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 26, 11), + RK_GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 9, 0), + RK_GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 9, 2), + RK_GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 9, 3), + RK_GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 9, 5), + RK_GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 9, 6), + RK_GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 9, 9), + RK_GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 12, 0), + RK_GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 12, 1), + RK_GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 12, 2), + RK_GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 12, 3), + RK_GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 12, 4), + RK_GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 12, 8), + RK_GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 12, 9), + RK_GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 12, 10), + RK_GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 12, 11), + RK_GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", + 12, 12), + RK_GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 13, 0), + RK_GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 13, 1), + RK_GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 13, 2), + RK_GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 13, 3), + RK_GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", + 13, 4), + RK_GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 11, 0), + RK_GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 11, 1), + RK_GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 11, 2), + RK_GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 11, 4), + RK_GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 11, 5), + RK_GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 11, 6), + RK_GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 11, 8), + RK_GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 11, 9), + RK_GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 11, 10), + RK_GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 10, 8), + RK_GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 10, 9), + RK_GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 10, 12), + RK_GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 10, 13), + RK_GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 13, 6), + RK_GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 15, 0), + RK_GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 15, 2), + RK_GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 15, 5), + RK_GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 15, 6), + RK_GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 15, 12), + RK_GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 16, 12), + RK_GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 16, 13), + RK_GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 16, 14), + RK_GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 16, 15), + RK_GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 17, 0), + RK_GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 17, 3), + RK_GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 17, 4), + RK_GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 17, 10), + RK_GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 18, 9), + RK_GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 18, 10), + RK_GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 19, 0), + RK_GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 19, 1), + RK_GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 19, 4), + RK_GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 20, 8), + RK_GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 20, 9), + RK_GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 20, 13), + RK_GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 21, 0), + RK_GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 21, 1), + RK_GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 21, 2), + RK_GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 21, 3), + RK_GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 21, 4), + RK_GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 21, 5), + RK_GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 21, 6), + RK_GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 21, 7), + RK_GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 21, 8), + RK_GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 22, 4), + RK_GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 22, 5), + RK_GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 23, 4), + RK_GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 23, 5), + RK_GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 23, 7), + RK_GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 23, 8), + RK_GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 23, 10), + RK_GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 23, 12), + RK_GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 23, 13), + RK_GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 23, 14), + RK_GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 23, 15), + RK_GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 22, 14), + RK_GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 22, 15), + RK_GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 24, 6), + RK_GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 24, 7), + RK_GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 25, 4), + RK_GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 25, 5), + RK_GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 26, 4), + RK_GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 26, 7), + RK_GATE(CLK_SARADC, "clk_saradc", "xin24m", 26, 8), + RK_GATE(PCLK_SCR, "pclk_scr", "pclk_bus", 26, 12), + RK_GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 26, 13), + RK_GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 26, 14), + RK_GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", 32, 13), + RK_GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", 32, 14), + RK_GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 32, 15), + RK_GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 27, 12), + RK_GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 27, 15), + RK_GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 28, 0), + RK_GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 28, 3), + RK_GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 28, 4), + RK_GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 28, 7), + RK_GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 28, 8), + RK_GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 28, 11), + RK_GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 28, 12), + RK_GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 28, 15), + RK_GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 29, 0), + RK_GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 29, 3), + RK_GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 29, 4), + RK_GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 29, 7), + RK_GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 29, 8), + RK_GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 29, 11), + RK_GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 29, 12), + RK_GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 29, 15), + RK_GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 27, 5), + RK_GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 27, 7), + RK_GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 27, 9), + RK_GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 30, 0), + RK_GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 30, 1), + RK_GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 30, 2), + RK_GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 30, 3), + RK_GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 30, 4), + RK_GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 30, 5), + RK_GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 30, 6), + RK_GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 30, 7), + RK_GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 30, 8), + RK_GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 30, 9), + RK_GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 30, 10), + RK_GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 30, 12), + RK_GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 30, 14), + RK_GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 31, 0), + RK_GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 31, 10), + RK_GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 31, 12), + RK_GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 31, 13), + RK_GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 31, 15), + RK_GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 32, 0), + RK_GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 32, 2), + RK_GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 31, 2), + RK_GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 31, 3), + RK_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 31, 4), + RK_GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 31, 5), + RK_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 31, 6), + RK_GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 31, 7), + RK_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 31, 8), + RK_GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 31, 9), + RK_GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 32, 3), + RK_GATE(CLK_TIMER0, "clk_timer0", "xin24m", 32, 4), + RK_GATE(CLK_TIMER1, "clk_timer1", "xin24m", 32, 5), + RK_GATE(CLK_TIMER2, "clk_timer2", "xin24m", 32, 6), + RK_GATE(CLK_TIMER3, "clk_timer3", "xin24m", 32, 7), + RK_GATE(CLK_TIMER4, "clk_timer4", "xin24m", 32, 8), + RK_GATE(CLK_TIMER5, "clk_timer5", "xin24m", 32, 9), + RK_GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 33, 8), + RK_GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 33, 13), + RK_GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 33, 14), + RK_GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 33, 15), + RK_GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 34, 4), + RK_GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 34, 5), + RK_GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 34, 6), + RK_GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 34, 11), + RK_GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 34, 12), + RK_GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 34, 13), + RK_GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 34, 14), +}; + + +static int +probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "rockchip,rk3568-cru")) { + device_set_desc(dev, "Rockchip RK3568 Clock and Reset Unit"); + return (BUS_PROBE_DEFAULT); + } + return (ENXIO); +} + +static int +attach(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + sc->dev = dev; + sc->clks = clks; + sc->nclks = nitems(clks); + sc->gates = gates; + sc->ngates = nitems(gates); + sc->reset_offset = 0x400; + sc->reset_num = 478; + + return (rk_cru_attach(dev)); +} + +static device_method_t methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, probe), + DEVMETHOD(device_attach, attach), + + DEVMETHOD_END +}; + +static devclass_t devclass; + +DEFINE_CLASS_1(rk3568_cru, rk3568_cru_driver, methods, + sizeof(struct rk_cru_softc), rk_cru_driver); + +EARLY_DRIVER_MODULE(rk3568_cru, simplebus, rk3568_cru_driver, + devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Index: sys/arm64/rockchip/clk/rk3568_pmucru.c =================================================================== --- sys/arm64/rockchip/clk/rk3568_pmucru.c +++ sys/arm64/rockchip/clk/rk3568_pmucru.c @@ -0,0 +1,329 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2021, 2022 Soren Schmidt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#include +#include + + +#define RK3568_PLLSEL_CON(x) ((x) * 0x20) +#define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x180) +#define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x200) + +#define PNAME(_name) static const char *_name[] + +/* PLL clock */ +#define RK_PLL(_id, _name, _pnames, _off, _shift) \ +{ \ + .type = RK3328_CLK_PLL, \ + .clk.pll = &(struct rk_clk_pll_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pnames, \ + .clkdef.parent_cnt = nitems(_pnames), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .base_offset = RK3568_PLLSEL_CON(_off), \ + .mode_reg = 0x80, \ + .mode_shift = _shift, \ + .rates = rk3568_pll_rates, \ + }, \ +} + +/* Composite */ +#define RK_COMPOSITE(_id, _name, _pnames, _o, _ms, _mw, _ds, _dw, _go, _gw, _f) \ +{ \ + .type = RK_CLK_COMPOSITE, \ + .clk.composite = &(struct rk_clk_composite_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pnames, \ + .clkdef.parent_cnt = nitems(_pnames), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ + .mux_shift = _ms, \ + .mux_width = _mw, \ + .div_shift = _ds, \ + .div_width = _dw, \ + .gate_offset = RK3568_CLKGATE_CON(_go), \ + .gate_shift = _gw, \ + .flags = RK_CLK_COMPOSITE_HAVE_MUX | \ + RK_CLK_COMPOSITE_HAVE_GATE | _f, \ + }, \ +} + +/* Composite no mux */ +#define RK_COMPNOMUX(_id, _name, _pname, _o, _ds, _dw, _go, _gw, _f) \ +{ \ + .type = RK_CLK_COMPOSITE, \ + .clk.composite = &(struct rk_clk_composite_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = (const char *[]){_pname}, \ + .clkdef.parent_cnt = 1, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ + .div_shift = _ds, \ + .div_width = _dw, \ + .gate_offset = RK3568_CLKGATE_CON(_go), \ + .gate_shift = _gw, \ + .flags = RK_CLK_COMPOSITE_HAVE_GATE | _f, \ + }, \ +} + +/* Fixed factor mux/div */ +#define RK_FACTOR(_id, _name, _pname, _mult, _div) \ +{ \ + .type = RK_CLK_FIXED, \ + .clk.fixed = &(struct clk_fixed_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = (const char *[]){_pname}, \ + .clkdef.parent_cnt = 1, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .mult = _mult, \ + .div = _div, \ + }, \ +} + +/* Fractional */ +#define RK_FRACTION(_id, _name, _pname, _o, _go, _gw, _f) \ +{ \ + .type = RK_CLK_FRACT, \ + .clk.fract = &(struct rk_clk_fract_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = (const char *[]){_pname}, \ + .clkdef.parent_cnt = 1, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .offset = RK3568_CLKSEL_CON(_o), \ + .gate_offset = RK3568_CLKGATE_CON(_go), \ + .gate_shift = _gw, \ + .flags = RK_CLK_FRACT_HAVE_GATE | _f, \ + }, \ +} + +/* Multiplexer */ +#define RK_MUX(_id, _name, _pnames, _o, _ms, _mw, _f) \ +{ \ + .type = RK_CLK_MUX, \ + .clk.mux = &(struct rk_clk_mux_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pnames, \ + .clkdef.parent_cnt = nitems(_pnames), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .offset = RK3568_CLKSEL_CON(_o), \ + .shift = _ms, \ + .width = _mw, \ + .mux_flags = _f, \ + }, \ +} + +#define RK_GATE(_id, _name, _pname, _o, _s) \ +{ \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .offset = RK3568_CLKGATE_CON(_o), \ + .shift = _s, \ +} + +extern struct rk_clk_pll_rate rk3568_pll_rates[]; + +/* Parent clock defines */ +PNAME(mux_pll_p) = { "xin24m" }; +PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; +PNAME(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" }; +PNAME(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" }; +PNAME(ppll_usb480m_cpll_gpll_p) = { "ppll", "usb480m", "cpll", "gpll"}; +PNAME(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" }; +PNAME(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" }; +PNAME(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" }; +PNAME(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" }; +PNAME(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" }; +PNAME(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" }; +PNAME(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" }; +PNAME(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" }; +PNAME(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" }; +PNAME(clk_pdpmu_p) = { "ppll", "gpll" }; +PNAME(clk_pwm0_p) = { "xin24m", "clk_pdpmu" }; + +/* CLOCKS */ +static struct rk_clk clks[] = { + /* External clocks */ + LINK("xin24m"), + LINK("cpll"), + LINK("gpll"), + LINK("usb480m"), + LINK("clk_32k_pvtm"), + + /* SRC_CLK */ + RK_MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, 0, 6, 2, 0), + RK_MUX(0, "sclk_uart0_mux", sclk_uart0_p, 4, 10, 2, 0), + + /* PLL's */ + RK_PLL(PLL_PPLL, "ppll", mux_pll_p, 0, 0), + RK_PLL(PLL_HPLL, "hpll", mux_pll_p, 2, 2), + + /* PD_PMU */ + RK_FACTOR(0, "ppll_ph0", "ppll", 1, 2), + RK_FACTOR(0, "ppll_ph180", "ppll", 1, 2), + RK_FACTOR(0, "hpll_ph0", "hpll", 1, 2), + RK_MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 2, 15, 1, 0), + RK_COMPNOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 2, 0, 5, 0, 2, 0), + RK_COMPNOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 3, 0, 7, 1, 1, 0), + RK_FRACTION(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", 1, 0, 1, 0), + RK_COMPNOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0, 0, 5, 0, 0, 0), + RK_COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", + ppll_usb480m_cpll_gpll_p, 4, 8, 2, 0, 7, 1, 3, 0), + RK_FRACTION(CLK_UART0_FRAC, "sclk_uart0_frac", + "sclk_uart0_div", 5, 1, 4, 0), + RK_MUX(DBCLK_GPIO0, "dbclk_gpio0_c", xin24m_32k_p, 6, 15, 1, 0), + RK_COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 6, 7, 1, 0, 7, 1, 7, 0), + RK_COMPNOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 7, 0, 6, 2, 0, 0), + RK_MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", + clk_usbphy0_ref_p, 8, 0, 1, 0), + RK_MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", + clk_usbphy1_ref_p, 8, 1, 1, 0), + RK_MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", + clk_mipidsiphy0_ref_p, 8, 2, 1, 0), + RK_MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", + clk_mipidsiphy1_ref_p, 8, 3, 1, 0), + RK_COMPNOMUX(CLK_WIFI_DIV, "clk_wifi_div", + "clk_pdpmu", 8, 8, 6, 2, 5, 0), + RK_MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, 8, 15, 1, 0), + RK_COMPNOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", + "ppll_ph0", 9, 0, 3, 2, 7, 0), + RK_MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", + clk_pciephy0_ref_p, 9, 3, 1, 0), + RK_COMPNOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", + "ppll_ph0", 9, 4, 3, 2, 9, 0), + RK_MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", + clk_pciephy1_ref_p, 9, 7, 1, 0), + RK_COMPNOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", + "ppll_ph0", 9, 8, 3, 2, 11, 0), + RK_MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", + clk_pciephy2_ref_p, 9, 11, 1, 0), + RK_MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 8, 7, 1, 0), +}; + +/* GATES */ +static struct rk_cru_gate gates[] = { + RK_GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, 6), + RK_GATE(DBCLK_GPIO0, "dbclk_gpio0", "dbclk_gpio0_c", 1, 10), + RK_GATE(CLK_PMU, "clk_pmu", "xin24m", 0, 7), + RK_GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 1, 0), + RK_GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 1, 2), + RK_GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 1, 5), + RK_GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 1, 9), + RK_GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 1, 6), + RK_GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 1, 8), + RK_GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 1, 11), + RK_GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 1, 12), + RK_GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 1, 13), + RK_GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 2, 1), + RK_GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 2, 2), + RK_GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", + "xin24m", 2, 3), + RK_GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", + "xin24m", 2, 4), + RK_GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 2, 6), + RK_GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 2, 8), + RK_GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 2, 10), + RK_GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 2, 12), + RK_GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 2, 13), + RK_GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 2, 14), + RK_GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 2, 15), +}; + +static int +probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "rockchip,rk3568-pmucru")) { + device_set_desc(dev, "Rockchip RK3568 PMU Clock and Reset Unit"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +attach(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + sc->gates = gates; + sc->ngates = nitems(gates); + sc->dev = dev; + sc->clks = clks; + sc->nclks = nitems(clks); + sc->reset_offset = 0x200; + sc->reset_num = 4; + + return (rk_cru_attach(dev)); +} + +static device_method_t methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, probe), + DEVMETHOD(device_attach, attach), + + DEVMETHOD_END +}; + +static devclass_t devclass; + +DEFINE_CLASS_1(rk3568_pmucru, rk3568_pmucru_driver, methods, + sizeof(struct rk_cru_softc), rk_cru_driver); + +EARLY_DRIVER_MODULE(rk3568_pmucru, simplebus, rk3568_pmucru_driver, + devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Index: sys/arm64/rockchip/clk/rk_clk_fract.c =================================================================== --- sys/arm64/rockchip/clk/rk_clk_fract.c +++ sys/arm64/rockchip/clk/rk_clk_fract.c @@ -186,10 +186,8 @@ sc = clknode_get_softc(clk); if (sc->denominator == 0) { - printf("%s: %s denominator is zero!\n", clknode_get_name(clk), - __func__); *freq = 0; - return(EINVAL); + return (0); } *freq *= sc->numerator; Index: sys/arm64/rockchip/clk/rk_clk_pll.h =================================================================== --- sys/arm64/rockchip/clk/rk_clk_pll.h +++ sys/arm64/rockchip/clk/rk_clk_pll.h @@ -64,5 +64,6 @@ int rk3066_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef); int rk3328_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef); int rk3399_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef); +int rk3568_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef); #endif /* _RK_CLK_PLL_H_ */ Index: sys/arm64/rockchip/clk/rk_clk_pll.c =================================================================== --- sys/arm64/rockchip/clk/rk_clk_pll.c +++ sys/arm64/rockchip/clk/rk_clk_pll.c @@ -777,3 +777,204 @@ return (0); } + +#define RK3568_CLK_PLL_FBDIV_SHIFT 0 +#define RK3568_CLK_PLL_FBDIV_MASK 0xFFF + +#define RK3568_CLK_PLL_POSTDIV1_SHIFT 12 +#define RK3568_CLK_PLL_POSTDIV1_MASK 0x7000 + +#define RK3568_CLK_PLL_DSMPD_SHIFT 12 +#define RK3568_CLK_PLL_DSMPD_MASK 0x1000 + +#define RK3568_CLK_PLL_REFDIV_SHIFT 0 +#define RK3568_CLK_PLL_REFDIV_MASK 0x3F + +#define RK3568_CLK_PLL_POSTDIV2_SHIFT 6 +#define RK3568_CLK_PLL_POSTDIV2_MASK 0x1C0 + +#define RK3568_CLK_PLL_FRAC_SHIFT 0 +#define RK3568_CLK_PLL_FRAC_MASK 0xFFFFFF + +#define RK3568_CLK_PLL_LOCK_MASK 0x400 + +#define RK3568_CLK_PLL_MODE_NORMAL 1 +#define RK3568_CLK_PLL_MODE_MASK 0x1 + +static int +rk3568_clk_pll_init(struct clknode *clk, device_t dev) +{ + + clknode_init_parent_idx(clk, 0); + + return (0); +} + +static int +rk3568_clk_pll_recalc(struct clknode *clk, uint64_t *freq) +{ + struct rk_clk_pll_sc *sc; + uint64_t rate; + uint32_t dsmpd, refdiv, fbdiv; + uint32_t postdiv1, postdiv2, frac; + uint32_t raw1, raw2, raw3; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(clk); + + READ4(clk, sc->base_offset, &raw1); + READ4(clk, sc->base_offset + 4, &raw2); + READ4(clk, sc->base_offset + 8, &raw3); + + fbdiv = (raw1 & RK3568_CLK_PLL_FBDIV_MASK) >> + RK3568_CLK_PLL_FBDIV_SHIFT; + postdiv1 = (raw1 & RK3568_CLK_PLL_POSTDIV1_MASK) >> + RK3568_CLK_PLL_POSTDIV1_SHIFT; + + dsmpd = (raw2 & RK3568_CLK_PLL_DSMPD_MASK) >> + RK3568_CLK_PLL_DSMPD_SHIFT; + refdiv = (raw2 & RK3568_CLK_PLL_REFDIV_MASK) >> + RK3568_CLK_PLL_REFDIV_SHIFT; + postdiv2 = (raw2 & RK3568_CLK_PLL_POSTDIV2_MASK) >> + RK3568_CLK_PLL_POSTDIV2_SHIFT; + + frac = (raw3 & RK3568_CLK_PLL_FRAC_MASK) >> RK3568_CLK_PLL_FRAC_SHIFT; + + DEVICE_UNLOCK(clk); + + rate = *freq * fbdiv / refdiv; + if (dsmpd == 0) { + /* Fractional mode */ + uint64_t frac_rate; + + frac_rate = *freq * frac / refdiv; + rate += frac_rate >> 24; + } + + *freq = rate / postdiv1 / postdiv2; + + if (*freq % 2) + *freq = *freq + 1; + + return (0); +} + +static int +rk3568_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, + int flags, int *stop) +{ + struct rk_clk_pll_rate *rates; + struct rk_clk_pll_sc *sc; + uint32_t reg; + int timeout; + + sc = clknode_get_softc(clk); + + if (sc->rates) + rates = sc->rates; + else if (sc->frac_rates) + rates = sc->frac_rates; + else + return (EINVAL); + + for (; rates->freq; rates++) { + if (rates->freq == *fout) + break; + } + if (rates->freq == 0) { + *stop = 1; + return (EINVAL); + } + + DEVICE_LOCK(clk); + + /* Setting to slow mode during frequency change */ + reg = (RK3568_CLK_PLL_MODE_MASK << sc->mode_shift) << + RK_CLK_PLL_MASK_SHIFT; + dprintf("Set PLL_MODEREG to %x\n", reg); + WRITE4(clk, sc->mode_reg, reg); + + /* Setting postdiv1 and fbdiv */ + reg = (rates->postdiv1 << RK3568_CLK_PLL_POSTDIV1_SHIFT) | + (rates->fbdiv << RK3568_CLK_PLL_FBDIV_SHIFT); + reg |= (RK3568_CLK_PLL_POSTDIV1_MASK | RK3568_CLK_PLL_FBDIV_MASK) << 16; + dprintf("Set PLL_CON0 to %x\n", reg); + WRITE4(clk, sc->base_offset, reg); + + /* Setting dsmpd, postdiv2 and refdiv */ + reg = (rates->dsmpd << RK3568_CLK_PLL_DSMPD_SHIFT) | + (rates->postdiv2 << RK3568_CLK_PLL_POSTDIV2_SHIFT) | + (rates->refdiv << RK3568_CLK_PLL_REFDIV_SHIFT); + reg |= (RK3568_CLK_PLL_DSMPD_MASK | + RK3568_CLK_PLL_POSTDIV2_MASK | + RK3568_CLK_PLL_REFDIV_MASK) << RK_CLK_PLL_MASK_SHIFT; + dprintf("Set PLL_CON1 to %x\n", reg); + WRITE4(clk, sc->base_offset + 0x4, reg); + + /* Setting frac */ + READ4(clk, sc->base_offset + 0x8, ®); + reg &= ~RK3568_CLK_PLL_FRAC_MASK; + reg |= rates->frac << RK3568_CLK_PLL_FRAC_SHIFT; + dprintf("Set PLL_CON2 to %x\n", reg); + WRITE4(clk, sc->base_offset + 0x8, reg); + + /* Reading lock */ + for (timeout = 1000; timeout; timeout--) { + READ4(clk, sc->base_offset + 0x4, ®); + if ((reg & RK3568_CLK_PLL_LOCK_MASK) == 0) + break; + DELAY(1); + } + + /* Set back to normal mode */ + reg = (RK3568_CLK_PLL_MODE_NORMAL << sc->mode_shift); + reg |= (RK3568_CLK_PLL_MODE_MASK << sc->mode_shift) << + RK_CLK_PLL_MASK_SHIFT; + dprintf("Set PLL_MODEREG to %x\n", reg); + WRITE4(clk, sc->mode_reg, reg); + + DEVICE_UNLOCK(clk); + + *stop = 1; + return (0); +} + +static clknode_method_t rk3568_clk_pll_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, rk3568_clk_pll_init), + CLKNODEMETHOD(clknode_set_gate, rk_clk_pll_set_gate), + CLKNODEMETHOD(clknode_recalc_freq, rk3568_clk_pll_recalc), + CLKNODEMETHOD(clknode_set_freq, rk3568_clk_pll_set_freq), + CLKNODEMETHOD_END +}; + +DEFINE_CLASS_1(rk3568_clk_pll_clknode, rk3568_clk_pll_clknode_class, + rk3568_clk_pll_clknode_methods, sizeof(struct rk_clk_pll_sc), clknode_class); + +int +rk3568_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef) +{ + struct clknode *clk; + struct rk_clk_pll_sc *sc; + + clk = clknode_create(clkdom, &rk3568_clk_pll_clknode_class, + &clkdef->clkdef); + if (clk == NULL) + return (1); + + sc = clknode_get_softc(clk); + + sc->base_offset = clkdef->base_offset; + sc->gate_offset = clkdef->gate_offset; + sc->gate_shift = clkdef->gate_shift; + sc->mode_reg = clkdef->mode_reg; + sc->mode_shift = clkdef->mode_shift; + sc->flags = clkdef->flags; + sc->rates = clkdef->rates; + sc->frac_rates = clkdef->frac_rates; + + clknode_register(clkdom, clk); + + return (0); +} Index: sys/arm64/rockchip/clk/rk_cru.h =================================================================== --- sys/arm64/rockchip/clk/rk_cru.h +++ sys/arm64/rockchip/clk/rk_cru.h @@ -228,6 +228,7 @@ RK3066_CLK_PLL, RK3328_CLK_PLL, RK3399_CLK_PLL, + RK3568_CLK_PLL, RK_CLK_COMPOSITE, RK_CLK_FIXED, RK_CLK_FRACT, Index: sys/arm64/rockchip/clk/rk_cru.c =================================================================== --- sys/arm64/rockchip/clk/rk_cru.c +++ sys/arm64/rockchip/clk/rk_cru.c @@ -245,6 +245,10 @@ rk3399_clk_pll_register(sc->clkdom, sc->clks[i].clk.pll); break; + case RK3568_CLK_PLL: + rk3568_clk_pll_register(sc->clkdom, + sc->clks[i].clk.pll); + break; case RK_CLK_COMPOSITE: rk_clk_composite_register(sc->clkdom, sc->clks[i].clk.composite); Index: sys/arm64/rockchip/rk3568_iodomain.c =================================================================== --- sys/arm64/rockchip/rk3568_iodomain.c +++ sys/arm64/rockchip/rk3568_iodomain.c @@ -0,0 +1,162 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2021, 2022 Soren Schmidt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: rk3568_iodomain.c 893 2022-07-26 09:47:22Z sos $ + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "syscon_if.h" + +#define RK3568_PMU_GRF_IO_VSEL0 0x0140 +#define RK3568_PMU_GRF_IO_VSEL1 0x0144 +#define RK3568_PMU_GRF_IO_VSEL2 0x0148 + +#define MAX_1V8 1850000 + +struct rk3568_iodomain_supply { + char *name; + uint32_t bit; +}; + +static struct rk3568_iodomain_supply rk3568_pmu_supply[] = { + {"pmuio1-supply", 0}, + {"pmuio2-supply", 1}, + {"vccio1-supply", 1}, + {"vccio2-supply", 2}, + {"vccio3-supply", 3}, + {"vccio4-supply", 4}, + {"vccio5-supply", 5}, + {"vccio6-supply", 6}, + {"vccio7-supply", 7}, +}; + +static struct ofw_compat_data compat_data[] = { + {"rockchip,rk3568-pmu-io-voltage-domain", 1}, + {NULL, 0} +}; + + +static int +rk3568_iodomain_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + device_set_desc(dev, "RockChip IO Voltage Domain"); + return (BUS_PROBE_DEFAULT); +} + +static int +rk3568_iodomain_attach(device_t dev) +{ + phandle_t node = ofw_bus_get_node(dev); + struct syscon *grf; + regulator_t supply; + int uvolt, i; + + if (syscon_get_handle_default(dev, &grf)) { + device_printf(dev, "Cannot get grf handle\n"); + return (ENXIO); + } + + for (i = 0; i < nitems(rk3568_pmu_supply); i++) { + if (regulator_get_by_ofw_property(dev, node, + rk3568_pmu_supply[i].name, &supply)) + return (ENXIO); + + if (regulator_get_voltage(supply, &uvolt)) { + device_printf(dev, + "Cannot get voltage for regulator %s\n", + rk3568_pmu_supply[i].name); + } else { + if (bootverbose) + device_printf(dev, + "Setting regulator %s voltage=%duV\n", + rk3568_pmu_supply[i].name, uvolt); + switch (i) { + case 1: + SYSCON_WRITE_4(grf, RK3568_PMU_GRF_IO_VSEL2, + (1 << (rk3568_pmu_supply[i].bit + 16)) | + (uvolt > MAX_1V8 ? + 0 : 1 << rk3568_pmu_supply[i].bit)); + SYSCON_WRITE_4(grf, RK3568_PMU_GRF_IO_VSEL2, + (1 << (rk3568_pmu_supply[i].bit + 4 + 16)) | + (uvolt > MAX_1V8 ? + 1 << (rk3568_pmu_supply[i].bit + 4) : 0)); + break; + + case 2: case 4: case 5: case 6: case 7: case 8: + SYSCON_WRITE_4(grf, RK3568_PMU_GRF_IO_VSEL0, + (1 << (rk3568_pmu_supply[i].bit + 16)) | + (uvolt > MAX_1V8 ? + 0 : 1 << rk3568_pmu_supply[i].bit)); + SYSCON_WRITE_4(grf, RK3568_PMU_GRF_IO_VSEL1, + (1 << (rk3568_pmu_supply[i].bit + 16)) | + (uvolt > MAX_1V8 ? + 1 << rk3568_pmu_supply[i].bit : 0)); + break; + + case 0: case 3: + break; + + default: + device_printf(dev, "Index out of range\n"); + }; + } + } + return (0); +} + +static device_method_t rk3568_iodomain_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk3568_iodomain_probe), + DEVMETHOD(device_attach, rk3568_iodomain_attach), + + DEVMETHOD_END +}; + +static driver_t rk3568_iodomain_driver = { + "rk3568_iodomain", rk3568_iodomain_methods, 0, +}; + +static devclass_t rk3568_iodomain_devclass; + +EARLY_DRIVER_MODULE(rk3568_iodomain, simplebus, rk3568_iodomain_driver, + rk3568_iodomain_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); Index: sys/arm64/rockchip/rk_dwc3.c =================================================================== --- sys/arm64/rockchip/rk_dwc3.c +++ sys/arm64/rockchip/rk_dwc3.c @@ -141,11 +141,8 @@ clk_get_name(sc->clk_bus)); return (ENXIO); } - if (sc->type == RK3399) { - if (clk_get_by_ofw_name(dev, 0, "grf_clk", &sc->clk_grf) != 0) { - device_printf(dev, "Cannot get grf_clk clock\n"); - return (ENXIO); - } + /* Optional clocks */ + if (clk_get_by_ofw_name(dev, 0, "grf_clk", &sc->clk_grf) == 0) { err = clk_enable(sc->clk_grf); if (err != 0) { device_printf(dev, "Could not enable clock %s\n", @@ -153,7 +150,6 @@ return (ENXIO); } } - /* Optional clocks */ if (clk_get_by_ofw_name(dev, 0, "aclk_usb3_rksoc_axi_perf", &sc->clk_axi_perf) == 0) { err = clk_enable(sc->clk_axi_perf); if (err != 0) { Index: sys/arm64/rockchip/rk_gpio.c =================================================================== --- sys/arm64/rockchip/rk_gpio.c +++ sys/arm64/rockchip/rk_gpio.c @@ -2,6 +2,7 @@ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot + * Copyright (c) 2021 Soren Schmidt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -35,6 +36,7 @@ #include #include +#include #include #include #include @@ -50,149 +52,302 @@ #include #include "gpio_if.h" +#include "pic_if.h" -#include "fdt_pinctrl_if.h" +enum gpio_regs { + RK_GPIO_SWPORTA_DR = 1, /* Data register */ + RK_GPIO_SWPORTA_DDR, /* Data direction register */ + RK_GPIO_INTEN, /* Interrupt enable register */ + RK_GPIO_INTMASK, /* Interrupt mask register */ + RK_GPIO_INTTYPE_LEVEL, /* Interrupt level register */ + RK_GPIO_INTTYPE_BOTH, /* Both rise and falling edge */ + RK_GPIO_INT_POLARITY, /* Interrupt polarity register */ + RK_GPIO_INT_STATUS, /* Interrupt status register */ + RK_GPIO_INT_RAWSTATUS, /* Raw Interrupt status register */ + RK_GPIO_DEBOUNCE, /* Debounce enable register */ + RK_GPIO_PORTA_EOI, /* Clear interrupt register */ + RK_GPIO_EXT_PORTA, /* External port register */ + RK_GPIO_REGNUM +}; -#define RK_GPIO_SWPORTA_DR 0x00 /* Data register */ -#define RK_GPIO_SWPORTA_DDR 0x04 /* Data direction register */ +#define RK_GPIO_COUNT 32 -#define RK_GPIO_INTEN 0x30 /* Interrupt enable register */ -#define RK_GPIO_INTMASK 0x34 /* Interrupt mask register */ -#define RK_GPIO_INTTYPE_LEVEL 0x38 /* Interrupt level register */ -#define RK_GPIO_INT_POLARITY 0x3C /* Interrupt polarity register */ -#define RK_GPIO_INT_STATUS 0x40 /* Interrupt status register */ -#define RK_GPIO_INT_RAWSTATUS 0x44 /* Raw Interrupt status register */ +static struct resource_spec rk_gpio_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { -1, 0 } +}; -#define RK_GPIO_DEBOUNCE 0x48 /* Debounce enable register */ +struct rk_pin_irqsrc { + struct intr_irqsrc isrc; + uint32_t irq; + uint32_t mode; +}; -#define RK_GPIO_PORTA_EOI 0x4C /* Clear interrupt register */ -#define RK_GPIO_EXT_PORTA 0x50 /* External port register */ - -#define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */ - -#define RK_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ - GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) - struct rk_gpio_softc { - device_t sc_dev; - device_t sc_busdev; - struct mtx sc_mtx; - struct resource *sc_res[2]; - bus_space_tag_t sc_bst; - bus_space_handle_t sc_bsh; + device_t dev; + device_t busdev; + device_t pinctrl; + uint32_t version; + struct mtx mtx; clk_t clk; - device_t pinctrl; + struct resource *res[nitems(rk_gpio_spec)]; + void *ihandle; + uint8_t regs[RK_GPIO_REGNUM]; + struct rk_pin_irqsrc isrcs[RK_GPIO_COUNT]; }; static struct ofw_compat_data compat_data[] = { - {"rockchip,gpio-bank", 1}, - {NULL, 0} + {"rockchip,gpio-bank", 1}, + {NULL, 0} }; -static struct resource_spec rk_gpio_spec[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE }, - { SYS_RES_IRQ, 0, RF_ACTIVE }, - { -1, 0 } -}; +#define RK_GPIO_VERSION 0x78 +#define RK_GPIO_TYPE_V1 0x00000000 +#define RK_GPIO_TYPE_V2 0x01000c2b +#define RK_GPIO_ISRC(sc, irq) (&(sc->isrcs[irq].isrc)) -static int rk_gpio_detach(device_t dev); -#define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) -#define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) -#define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) +static int +rk_gpio_read_bit(struct rk_gpio_softc *sc, int reg, int bit) +{ + int offset = sc->regs[reg]; + uint32_t value; -#define RK_GPIO_WRITE(_sc, _off, _val) \ - bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) -#define RK_GPIO_READ(_sc, _off) \ - bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) + mtx_lock_spin(&sc->mtx); + if (sc->version == RK_GPIO_TYPE_V1) { + value = bus_read_4(sc->res[0], offset); + value >>= bit; + } else { + value = bus_read_4(sc->res[0], bit > 15 ? offset + 4 : offset); + value >>= (bit % 16); + } + mtx_unlock_spin(&sc->mtx); + return (value & 1); +} +static void +rk_gpio_write_bit(struct rk_gpio_softc *sc, int reg, int bit, int data) +{ + int offset = sc->regs[reg]; + uint32_t value; + + mtx_lock_spin(&sc->mtx); + if (sc->version == RK_GPIO_TYPE_V1) { + value = bus_read_4(sc->res[0], offset); + if (data) + value |= (1 << bit); + else + value &= ~(1 << bit); + bus_write_4(sc->res[0], offset, value); + } else { + if (data) + value = (1 << (bit % 16)); + else + value = 0; + value |= (1 << ((bit % 16) + 16)); + bus_write_4(sc->res[0], bit > 15 ? offset + 4 : offset, value); + } + mtx_unlock_spin(&sc->mtx); +} + +static uint32_t +rk_gpio_read_4(struct rk_gpio_softc *sc, int reg) +{ + int offset = sc->regs[reg]; + uint32_t value; + + mtx_lock_spin(&sc->mtx); + if (sc->version == RK_GPIO_TYPE_V1) + value = bus_read_4(sc->res[0], offset); + else + value = (bus_read_4(sc->res[0], offset) & 0xffff) | + (bus_read_4(sc->res[0], offset + 4) << 16); + mtx_unlock_spin(&sc->mtx); + return (value); +} + +static void +rk_gpio_write_4(struct rk_gpio_softc *sc, int reg, uint32_t value) +{ + int offset = sc->regs[reg]; + + mtx_lock_spin(&sc->mtx); + if (sc->version == RK_GPIO_TYPE_V1) + bus_write_4(sc->res[0], offset, value); + else { + bus_write_4(sc->res[0], offset, (value & 0xffff) | 0xffff0000); + bus_write_4(sc->res[0], offset + 4, (value >> 16) | 0xffff0000); + } + mtx_unlock_spin(&sc->mtx); +} + static int +rk_gpio_intr(void *arg) +{ + struct rk_gpio_softc *sc = (struct rk_gpio_softc *)arg;; + struct trapframe *tf = curthread->td_intr_frame; + uint32_t status; + + status = rk_gpio_read_4(sc, RK_GPIO_INT_STATUS); + rk_gpio_write_4(sc, RK_GPIO_PORTA_EOI, status); + while (status) { + int pin = ffs(status) - 1; + + status &= ~(1 << pin); + if (intr_isrc_dispatch(RK_GPIO_ISRC(sc, pin), tf)) { + device_printf(sc->dev, "Interrupt pin=%d unhandled\n", + pin); + continue; + } + + if ((sc->version == RK_GPIO_TYPE_V1) && + (sc->isrcs[pin].mode & GPIO_INTR_EDGE_BOTH)) { + if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) + rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, + (1 << pin), 0); + else + rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, + (1 << pin), 1); + } + } + return (FILTER_HANDLED); +} + +static int rk_gpio_probe(device_t dev) { - if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); - - device_set_desc(dev, "RockChip GPIO Bank controller"); + device_set_desc(dev, "RockChip GPIO controller"); return (BUS_PROBE_DEFAULT); } static int +rk_gpio_detach(device_t dev) +{ + struct rk_gpio_softc *sc = device_get_softc(dev); + + if (sc->busdev) + gpiobus_detach_bus(dev); + bus_release_resources(dev, rk_gpio_spec, sc->res); + mtx_destroy(&sc->mtx); + clk_disable(sc->clk); + return (0); +} + +static int rk_gpio_attach(device_t dev) { struct rk_gpio_softc *sc; phandle_t node; - int err; + int irq, err; sc = device_get_softc(dev); - sc->sc_dev = dev; + sc->dev = dev; sc->pinctrl = device_get_parent(dev); - node = ofw_bus_get_node(sc->sc_dev); + node = ofw_bus_get_node(sc->dev); if (!OF_hasprop(node, "gpio-controller")) return (ENXIO); - mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN); + mtx_init(&sc->mtx, "rk gpio", "gpio", MTX_SPIN); - if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) { - device_printf(dev, "could not allocate resources\n"); - bus_release_resources(dev, rk_gpio_spec, sc->sc_res); - mtx_destroy(&sc->sc_mtx); + if (bus_alloc_resources(dev, rk_gpio_spec, sc->res)) { + device_printf(dev, "Could not allocate resources\n"); + bus_release_resources(dev, rk_gpio_spec, sc->res); + mtx_destroy(&sc->mtx); return (ENXIO); } - sc->sc_bst = rman_get_bustag(sc->sc_res[0]); - sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); - if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) { - device_printf(dev, "Cannot get clock\n"); - rk_gpio_detach(dev); + device_printf(dev, "Can not get clock\n"); + bus_release_resources(dev, rk_gpio_spec, sc->res); + mtx_destroy(&sc->mtx); return (ENXIO); } - err = clk_enable(sc->clk); - if (err != 0) { + if ((err = clk_enable(sc->clk))) { device_printf(dev, "Could not enable clock %s\n", clk_get_name(sc->clk)); + bus_release_resources(dev, rk_gpio_spec, sc->res); + mtx_destroy(&sc->mtx); + return (ENXIO); + } + + if ((err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE, + rk_gpio_intr, NULL, sc, &sc->ihandle))) { + device_printf(dev, "Can not setup IRQ\n"); rk_gpio_detach(dev); return (ENXIO); } - sc->sc_busdev = gpiobus_attach_bus(dev); - if (sc->sc_busdev == NULL) { + switch ((sc->version = bus_read_4(sc->res[0], RK_GPIO_VERSION))) { + case RK_GPIO_TYPE_V1: + sc->regs[RK_GPIO_SWPORTA_DR] = 0x00; + sc->regs[RK_GPIO_SWPORTA_DDR] = 0x04; + sc->regs[RK_GPIO_INTEN] = 0x30; + sc->regs[RK_GPIO_INTMASK] = 0x34; + sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x38; + sc->regs[RK_GPIO_INT_POLARITY] = 0x3c; + sc->regs[RK_GPIO_INT_STATUS] = 0x40; + sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x44; + sc->regs[RK_GPIO_DEBOUNCE] = 0x48; + sc->regs[RK_GPIO_PORTA_EOI] = 0x4c; + sc->regs[RK_GPIO_EXT_PORTA] = 0x50; + break; + case RK_GPIO_TYPE_V2: + sc->regs[RK_GPIO_SWPORTA_DR] = 0x00; + sc->regs[RK_GPIO_SWPORTA_DDR] = 0x08; + sc->regs[RK_GPIO_INTEN] = 0x10; + sc->regs[RK_GPIO_INTMASK] = 0x18; + sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x20; + sc->regs[RK_GPIO_INTTYPE_BOTH] = 0x30; + sc->regs[RK_GPIO_INT_POLARITY] = 0x28; + sc->regs[RK_GPIO_INT_STATUS] = 0x50; + sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x58; + sc->regs[RK_GPIO_DEBOUNCE] = 0x38; + sc->regs[RK_GPIO_PORTA_EOI] = 0x60; + sc->regs[RK_GPIO_EXT_PORTA] = 0x70; + break; + default: + device_printf(dev, "Unknown gpio version %08x\n", sc->version); rk_gpio_detach(dev); return (ENXIO); } - return (0); -} + for (irq = 0; irq < RK_GPIO_COUNT; irq++) { + sc->isrcs[irq].irq = irq; + sc->isrcs[irq].mode = GPIO_INTR_CONFORM; + if ((err = intr_isrc_register(RK_GPIO_ISRC(sc, irq), + dev, 0, "%s", device_get_nameunit(dev)))) { + device_printf(dev, "Can not register isrc %d\n", err); + rk_gpio_detach(dev); + return (ENXIO); + } + } -static int -rk_gpio_detach(device_t dev) -{ - struct rk_gpio_softc *sc; + if (!intr_pic_register(dev, OF_xref_from_node(node))) { + device_printf(dev, "Can not register pic\n"); + rk_gpio_detach(dev); + return (ENXIO); + } - sc = device_get_softc(dev); - - if (sc->sc_busdev) - gpiobus_detach_bus(dev); - bus_release_resources(dev, rk_gpio_spec, sc->sc_res); - mtx_destroy(&sc->sc_mtx); - clk_disable(sc->clk); - - return(0); + if (!(sc->busdev = gpiobus_attach_bus(dev))) { + device_printf(dev, "Can not attach bus\n"); + rk_gpio_detach(dev); + return (ENXIO); + } + return (0); } static device_t rk_gpio_get_bus(device_t dev) { - struct rk_gpio_softc *sc; + struct rk_gpio_softc *sc = device_get_softc(dev); - sc = device_get_softc(dev); - - return (sc->sc_busdev); + return (sc->busdev); } static int @@ -199,9 +354,7 @@ rk_gpio_pin_max(device_t dev, int *maxpin) { - /* Each bank have always 32 pins */ - /* XXX not true*/ - *maxpin = 31; + *maxpin = RK_GPIO_COUNT - 1; return (0); } @@ -208,61 +361,40 @@ static int rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) { - struct rk_gpio_softc *sc; - uint32_t bank; - sc = device_get_softc(dev); + if (pin >= RK_GPIO_COUNT) + return EINVAL; - if (pin >= 32) - return (EINVAL); - - bank = pin / 8; - pin = pin - (bank * 8); - RK_GPIO_LOCK(sc); - snprintf(name, GPIOMAXNAME, "P%c%d", bank + 'A', pin); - RK_GPIO_UNLOCK(sc); - + snprintf(name, GPIOMAXNAME, "gpio%d", pin); return (0); } static int -rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) +rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { - struct rk_gpio_softc *sc; - uint32_t reg; - int rv; - bool is_gpio; - sc = device_get_softc(dev); + if (pin >= RK_GPIO_COUNT) + return EINVAL; - rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, &is_gpio); - if (rv != 0) - return (rv); - if (!is_gpio) - return (EINVAL); - - *flags = 0; - rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags); - if (rv != 0) - return (rv); - - RK_GPIO_LOCK(sc); - reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); - RK_GPIO_UNLOCK(sc); - - if (reg & (1 << pin)) - *flags |= GPIO_PIN_OUTPUT; - else - *flags |= GPIO_PIN_INPUT; - + *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ + GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_EDGE_BOTH | \ + GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | \ + GPIO_INTR_LEVEL_HIGH | GPIO_INTR_LEVEL_LOW); return (0); } static int -rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) +rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { + struct rk_gpio_softc *sc = device_get_softc(dev); - *caps = RK_GPIO_DEFAULT_CAPS; + if (pin >= RK_GPIO_COUNT) + return (EINVAL); + + if (rk_gpio_read_bit(sc, RK_GPIO_SWPORTA_DDR, pin)) + *flags = GPIO_PIN_OUTPUT; + else + *flags = GPIO_PIN_INPUT; return (0); } @@ -269,34 +401,13 @@ static int rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { - struct rk_gpio_softc *sc; - uint32_t reg; - int rv; - bool is_gpio; + struct rk_gpio_softc *sc = device_get_softc(dev); - sc = device_get_softc(dev); - - rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, &is_gpio); - if (rv != 0) - return (rv); - if (!is_gpio) + if (pin >= RK_GPIO_COUNT) return (EINVAL); - rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags); - if (rv != 0) - return (rv); - - RK_GPIO_LOCK(sc); - - reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); - if (flags & GPIO_PIN_INPUT) - reg &= ~(1 << pin); - else if (flags & GPIO_PIN_OUTPUT) - reg |= (1 << pin); - - RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg); - RK_GPIO_UNLOCK(sc); - + rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, + (flags & GPIO_PIN_OUTPUT ? 1 : 0)); return (0); } @@ -303,17 +414,12 @@ static int rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) { - struct rk_gpio_softc *sc; - uint32_t reg; + struct rk_gpio_softc *sc = device_get_softc(dev); - sc = device_get_softc(dev); + if (pin >= RK_GPIO_COUNT) + return (EINVAL); - RK_GPIO_LOCK(sc); - reg = RK_GPIO_READ(sc, RK_GPIO_EXT_PORTA); - RK_GPIO_UNLOCK(sc); - - *val = reg & (1 << pin) ? 1 : 0; - + *val = rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin); return (0); } @@ -320,20 +426,12 @@ static int rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { - struct rk_gpio_softc *sc; - uint32_t reg; + struct rk_gpio_softc *sc = device_get_softc(dev); - sc = device_get_softc(dev); + if (pin >= RK_GPIO_COUNT) + return (EINVAL); - RK_GPIO_LOCK(sc); - reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); - if (value) - reg |= (1 << pin); - else - reg &= ~(1 << pin); - RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); - RK_GPIO_UNLOCK(sc); - + rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DR, pin, value); return (0); } @@ -340,100 +438,149 @@ static int rk_gpio_pin_toggle(device_t dev, uint32_t pin) { - struct rk_gpio_softc *sc; - uint32_t reg; + struct rk_gpio_softc *sc = device_get_softc(dev); + int value; - sc = device_get_softc(dev); + if (pin >= RK_GPIO_COUNT) + return (EINVAL); - RK_GPIO_LOCK(sc); - reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); - if (reg & (1 << pin)) - reg &= ~(1 << pin); - else - reg |= (1 << pin); - RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); - RK_GPIO_UNLOCK(sc); - + value = rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin); + rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DR, pin, !value); return (0); } static int -rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, - uint32_t change_pins, uint32_t *orig_pins) +rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, + pcell_t *gpios, uint32_t *pin, uint32_t *flags) { - struct rk_gpio_softc *sc; - uint32_t reg; - sc = device_get_softc(dev); + *pin = gpios[0]; + *flags = gpios[1]; + return (0); +} - RK_GPIO_LOCK(sc); - reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); - if (orig_pins) - *orig_pins = reg; +static phandle_t +rk_gpio_get_node(device_t bus, device_t dev) +{ - if ((clear_pins | change_pins) != 0) { - reg = (reg & ~clear_pins) ^ change_pins; - RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); + return (ofw_bus_get_node(bus)); +} + +static int +rk_pic_map_intr(device_t dev, struct intr_map_data *data, + struct intr_irqsrc **isrcp) +{ + struct rk_gpio_softc *sc = device_get_softc(dev); + struct intr_map_data_gpio *gdata; + uint32_t irq; + + if (data->type != INTR_MAP_DATA_GPIO) { + device_printf(dev, "Wrong type\n"); + return (ENOTSUP); } - RK_GPIO_UNLOCK(sc); - + gdata = (struct intr_map_data_gpio *)data; + irq = gdata->gpio_pin_num; + if (irq >= RK_GPIO_COUNT) { + device_printf(dev, "Invalid interrupt %u\n", irq); + return (EINVAL); + } + *isrcp = RK_GPIO_ISRC(sc, irq); return (0); } static int -rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, - uint32_t *pin_flags) +rk_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, + struct resource *res, struct intr_map_data *data) { - struct rk_gpio_softc *sc; - uint32_t reg, set, mask, flags; - int i; + struct rk_gpio_softc *sc = device_get_softc(dev); + struct rk_pin_irqsrc *rkisrc = (struct rk_pin_irqsrc *)isrc; + struct intr_map_data_gpio *gdata; + uint32_t mode; + uint8_t pin; - sc = device_get_softc(dev); + if (!data) { + device_printf(dev, "No map data\n"); + return (ENOTSUP); + } + gdata = (struct intr_map_data_gpio *)data; + mode = gdata->gpio_intr_mode; + pin = gdata->gpio_pin_num; - if (first_pin != 0 || num_pins > 32) + if (rkisrc->irq != gdata->gpio_pin_num) { + device_printf(dev, "Interrupts don't match\n"); return (EINVAL); + } - set = 0; - mask = 0; - for (i = 0; i < num_pins; i++) { - mask = (mask << 1) | 1; - flags = pin_flags[i]; - if (flags & GPIO_PIN_INPUT) { - set &= ~(1 << i); - } else if (flags & GPIO_PIN_OUTPUT) { - set |= (1 << i); - } + if (isrc->isrc_handlers != 0) { + device_printf(dev, "Handler already attached\n"); + return (rkisrc->mode == mode ? 0 : EINVAL); } + rkisrc->mode = mode; - RK_GPIO_LOCK(sc); - reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); - reg &= ~mask; - reg |= set; - RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg); - RK_GPIO_UNLOCK(sc); - + switch (mode & GPIO_INTR_MASK) { + case GPIO_INTR_EDGE_RISING: + rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); + rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); + rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); + break; + case GPIO_INTR_EDGE_FALLING: + rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); + rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); + rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); + break; + case GPIO_INTR_EDGE_BOTH: + rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); + rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); + if (sc->version == RK_GPIO_TYPE_V1) { + if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) + rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, + pin, 0); + else + rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, + pin, 1); + } else + rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_BOTH, pin, 1); + break; + case GPIO_INTR_LEVEL_HIGH: + rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); + rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); + rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); + break; + case GPIO_INTR_LEVEL_LOW: + rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); + rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); + rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); + break; + default: + rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 1); + rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 0); + return (EINVAL); + } + rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, pin, 1); + rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 0); + rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 1); return (0); } static int -rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, - pcell_t *gpios, uint32_t *pin, uint32_t *flags) +rk_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, + struct resource *res, struct intr_map_data *data) { + struct rk_gpio_softc *sc = device_get_softc(dev); + struct rk_pin_irqsrc *irqsrc; - /* The gpios are mapped as */ - *pin = gpios[0]; - *flags = gpios[1]; + irqsrc = (struct rk_pin_irqsrc *)isrc; + + if (isrc->isrc_handlers == 0) { + irqsrc->mode = GPIO_INTR_CONFORM; + rk_gpio_write_bit(sc, RK_GPIO_INTEN, irqsrc->irq, 0); + rk_gpio_write_bit(sc, RK_GPIO_INTMASK, irqsrc->irq, 0); + rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, irqsrc->irq, 0); + } return (0); } -static phandle_t -rk_gpio_get_node(device_t bus, device_t dev) -{ - /* We only have one child, the GPIO bus, which needs our own node. */ - return (ofw_bus_get_node(bus)); -} - static device_method_t rk_gpio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rk_gpio_probe), @@ -444,17 +591,20 @@ DEVMETHOD(gpio_get_bus, rk_gpio_get_bus), DEVMETHOD(gpio_pin_max, rk_gpio_pin_max), DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname), + DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps), DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags), - DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps), DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags), DEVMETHOD(gpio_pin_get, rk_gpio_pin_get), DEVMETHOD(gpio_pin_set, rk_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle), - DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32), - DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32), DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios), - /* ofw_bus interface */ + /* Interrupt controller interface */ + DEVMETHOD(pic_map_intr, rk_pic_map_intr), + DEVMETHOD(pic_setup_intr, rk_pic_setup_intr), + DEVMETHOD(pic_teardown_intr, rk_pic_teardown_intr), + + /* OFW bus interface */ DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node), DEVMETHOD_END Index: sys/arm64/rockchip/rk_grf.c =================================================================== --- sys/arm64/rockchip/rk_grf.c +++ sys/arm64/rockchip/rk_grf.c @@ -48,6 +48,12 @@ {"rockchip,rk3328-grf", 1}, {"rockchip,rk3399-grf", 1}, {"rockchip,rk3399-pmugrf", 1}, + {"rockchip,rk3568-grf", 1}, + {"rockchip,rk3568-pmugrf", 1}, + {"rockchip,rk3568-usb2phy-grf", 1}, + {"rockchip,rk3566-pipegrf", 1}, + {"rockchip,rk3568-pipegrf", 1}, + {"rockchip,pipe-phy-grf", 1}, {NULL, 0} }; Index: sys/arm64/rockchip/rk_pinctrl.c =================================================================== --- sys/arm64/rockchip/rk_pinctrl.c +++ sys/arm64/rockchip/rk_pinctrl.c @@ -1171,11 +1171,31 @@ } /* Then drive strength */ - rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®); - if (rv == 0) { - bit = (pin % 8) * 2; - mask = (0x3 << bit); - SYSCON_MODIFY_4(syscon, reg, mask, drive << bit | (mask << 16)); + if (ofw_bus_node_is_compatible(ofw_bus_get_node(sc->dev), + "rockchip,rk3568-pinctrl")) { + uint32_t value; + if (OF_getencprop(pin_conf, "drive-strength", &value, + sizeof(value)) == 0) { + if (bank) + reg = 0x01c0 + (bank * 0x40) + (pin / 2 * 4); + else + reg = 0x0070 + (pin / 2 * 4); + + drive = ((1 << (value + 1)) - 1) << (pin % 2); + + mask = 0x3f << (pin % 2);; + + SYSCON_WRITE_4(syscon, reg, drive | (mask << 16)); + } + } else { + rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, + ®); + if (rv == 0) { + bit = (pin % 8) * 2; + mask = (0x3 << bit); + SYSCON_MODIFY_4(syscon, reg, mask, + drive << bit | (mask << 16)); + } } /* Finally set the pin function */ @@ -1183,7 +1203,7 @@ switch (sc->conf->iomux_conf[i].nbits) { case 4: if ((pin % 8) >= 4) - reg += 0x4; + reg += 4; bit = (pin % 4) * 4; mask = (0xF << bit); break; @@ -1267,7 +1287,7 @@ switch (sc->conf->iomux_conf[i].nbits) { case 4: if ((pin % 8) >= 4) - reg += 0x4; + reg += 4; bit = (pin % 4) * 4; mask = (0xF << bit); break; @@ -1423,7 +1443,7 @@ { int i; - for(i = 0; i < sc->conf->ngpio_bank; i++) { + for (i = 0; i < sc->conf->ngpio_bank; i++) { if (strcmp(gpio_name, sc->conf->gpio_bank[i].gpio_name) != 0) continue; sc->conf->gpio_bank[i].gpio_dev = gpio_dev; Index: sys/arm64/rockchip/rk_spi.c =================================================================== --- sys/arm64/rockchip/rk_spi.c +++ sys/arm64/rockchip/rk_spi.c @@ -92,6 +92,7 @@ static struct ofw_compat_data compat_data[] = { { "rockchip,rk3328-spi", 1 }, { "rockchip,rk3399-spi", 1 }, + { "rockchip,rk3568-spi", 1 }, { NULL, 0 } }; Index: sys/arm64/rockchip/rk_tsadc.c =================================================================== --- sys/arm64/rockchip/rk_tsadc.c +++ sys/arm64/rockchip/rk_tsadc.c @@ -55,6 +55,11 @@ #include "syscon_if.h" #include "rk_tsadc_if.h" +/* Version of HW */ +#define TSADC_V2 1 +#define TSADC_V3 2 +#define TSADC_V7 3 + /* Global registers */ #define TSADC_USER_CON 0x000 #define TSADC_AUTO_CON 0x004 @@ -78,7 +83,7 @@ #define TSADC_COMP0_LOW_INT 0x080 /* V3 only */ #define TSADC_COMP1_LOW_INT 0x084 /* V3 only */ -/* GFR Bits */ +/* V3 GFR registers */ #define GRF_SARADC_TESTBIT 0x0e644 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) #define GRF_TSADC_TESTBIT_L 0x0e648 @@ -87,6 +92,13 @@ #define GRF_TSADC_VCM_EN_H (0x10001 << 7) #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) +/* V7 GRF register */ +#define GRF_TSADC_CON 0x0600 +#define GRF_TSADC_ANA_REG0 (0x10001 << 0) +#define GRF_TSADC_ANA_REG1 (0x10001 << 1) +#define GRF_TSADC_ANA_REG2 (0x10001 << 2) +#define GRF_TSADC_TSEN (0x10001 << 8) + #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) @@ -109,7 +121,7 @@ }; struct tsadc_conf { - int use_syscon; + int version; int q_sel_ntc; int shutdown_temp; int shutdown_mode; @@ -124,18 +136,14 @@ struct resource *mem_res; struct resource *irq_res; void *irq_ih; - clk_t tsadc_clk; clk_t apb_pclk_clk; hwreset_t hwreset; struct syscon *grf; - struct tsadc_conf *conf; - int shutdown_temp; int shutdown_mode; int shutdown_pol; - int alarm_temp; }; @@ -183,7 +191,7 @@ }; struct tsadc_conf rk3288_tsadc_conf = { - .use_syscon = 0, + .version = TSADC_V2, .q_sel_ntc = 0, .shutdown_temp = 95000, .shutdown_mode = 1, /* GPIO */ @@ -237,7 +245,7 @@ }; static struct tsadc_conf rk3328_tsadc_conf = { - .use_syscon = 0, + .version = TSADC_V2, .q_sel_ntc = 1, .shutdown_temp = 95000, .shutdown_mode = 0, /* CRU */ @@ -293,7 +301,7 @@ }; static struct tsadc_conf rk3399_tsadc_conf = { - .use_syscon = 1, + .version = TSADC_V3, .q_sel_ntc = 1, .shutdown_temp = 95000, .shutdown_mode = 1, /* GPIO */ @@ -306,10 +314,68 @@ } }; +static struct rk_calib_entry rk3568_calib_data[] = { + {0, -40000}, + {1584, -40000}, + {1620, -35000}, + {1652, -30000}, + {1688, -25000}, + {1720, -20000}, + {1756, -15000}, + {1788, -10000}, + {1824, -5000}, + {1856, 0}, + {1892, 5000}, + {1924, 10000}, + {1956, 15000}, + {1992, 20000}, + {2024, 25000}, + {2060, 30000}, + {2092, 35000}, + {2128, 40000}, + {2160, 45000}, + {2196, 50000}, + {2228, 55000}, + {2264, 60000}, + {2300, 65000}, + {2332, 70000}, + {2368, 75000}, + {2400, 80000}, + {2436, 85000}, + {2468, 90000}, + {2500, 95000}, + {2536, 100000}, + {2572, 105000}, + {2604, 110000}, + {2636, 115000}, + {2672, 120000}, + {2704, 125000}, +}; + +static struct tsensor rk3568_tsensors[] = { + { .channel = 0, .id = 0, .name = "CPU"}, + { .channel = 1, .id = 1, .name = "GPU"}, +}; + +static struct tsadc_conf rk3568_tsadc_conf = { + .version = TSADC_V7, + .q_sel_ntc = 1, + .shutdown_temp = 95000, + .shutdown_mode = 1, /* GPIO */ + .shutdown_pol = 0, /* Low */ + .tsensors = rk3568_tsensors, + .ntsensors = nitems(rk3568_tsensors), + .calib_info = { + .table = rk3568_calib_data, + .nentries = nitems(rk3568_calib_data), + } +}; + static struct ofw_compat_data compat_data[] = { {"rockchip,rk3288-tsadc", (uintptr_t)&rk3288_tsadc_conf}, {"rockchip,rk3328-tsadc", (uintptr_t)&rk3328_tsadc_conf}, {"rockchip,rk3399-tsadc", (uintptr_t)&rk3399_tsadc_conf}, + {"rockchip,rk3568-tsadc", (uintptr_t)&rk3568_tsadc_conf}, {NULL, 0} }; @@ -433,11 +499,9 @@ static void tsadc_init(struct tsadc_softc *sc) { - uint32_t val; + uint32_t val = 0; - /* Common part */ - val = 0; /* XXX Is this right? */ - if (sc->shutdown_pol != 0) + if (sc->shutdown_pol) val |= TSADC_AUTO_CON_POL_HI; else val &= ~TSADC_AUTO_CON_POL_HI; @@ -445,34 +509,50 @@ val |= TSADC_AUTO_Q_SEL; WR4(sc, TSADC_AUTO_CON, val); - if (!sc->conf->use_syscon) { - /* V2 init */ + switch (sc->conf->version) { + case TSADC_V2: WR4(sc, TSADC_AUTO_PERIOD, 250); /* 250 ms */ WR4(sc, TSADC_AUTO_PERIOD_HT, 50); /* 50 ms */ WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4); WR4(sc, TSADC_HIGHT_TSHUT_DEBOUNCE, 4); - } else { - /* V3 init */ - if (sc->grf == NULL) { - /* Errata: adjust interleave to working value */ - WR4(sc, TSADC_USER_CON, 13 << 6); /* 13 clks */ - } else { + break; + case TSADC_V3: + if (sc->grf) { SYSCON_WRITE_4(sc->grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L); SYSCON_WRITE_4(sc->grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H); DELAY(30); /* 15 usec min */ - SYSCON_WRITE_4(sc->grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON); SYSCON_WRITE_4(sc->grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON); DELAY(180); /* 90 usec min */ - } + } else + WR4(sc, TSADC_USER_CON, 13 << 6);/* 13 clks */ WR4(sc, TSADC_AUTO_PERIOD, 1875); /* 2.5 ms */ WR4(sc, TSADC_AUTO_PERIOD_HT, 1875); /* 2.5 ms */ WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4); WR4(sc, TSADC_HIGHT_TSHUT_DEBOUNCE, 4); + break; + case TSADC_V7: + WR4(sc, TSADC_USER_CON, 0xfc0); /* 97us, at least 90us */ + WR4(sc, TSADC_AUTO_PERIOD, 1622); /* 2.5ms */ + WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4); + WR4(sc, TSADC_AUTO_PERIOD_HT, 1622); /* 2.5ms */ + WR4(sc, TSADC_HIGHT_TSHUT_DEBOUNCE, 4); + if (sc->grf) { + SYSCON_WRITE_4(sc->grf, GRF_TSADC_CON, GRF_TSADC_TSEN); + DELAY(15); /* 10 usec min */ + SYSCON_WRITE_4(sc->grf, GRF_TSADC_CON, + GRF_TSADC_ANA_REG0); + SYSCON_WRITE_4(sc->grf, GRF_TSADC_CON, + GRF_TSADC_ANA_REG1); + SYSCON_WRITE_4(sc->grf, GRF_TSADC_CON, + GRF_TSADC_ANA_REG2); + DELAY(100); /* 90 usec min */ + } + break; } } @@ -485,13 +565,11 @@ *temp = tsadc_raw_to_temp(sc, val); #ifdef DEBUG - printf("%s: Sensor(id: %d, ch: %d), temp: %d\n", __func__, - sensor->id, sensor->channel, *temp); - printf(" status: 0x%08X, 0x%08X\n", - RD4(sc, TSADC_USER_CON), - RD4(sc, TSADC_AUTO_CON)); - printf(" Data: 0x%08X, 0x%08X, 0x%08X\n", - RD4(sc, TSADC_DATA(sensor->channel)), + device_printf(sc->dev, "%s: Sensor(id: %d, ch: %d), val: %d temp: %d\n", + __func__, sensor->id, sensor->channel, val, *temp); + device_printf(sc->dev, "%s: user_con=0x%08x auto_con=0x%08x " + "comp_int=0x%08x comp_shut=0x%08x\n", + __func__, RD4(sc, TSADC_USER_CON), RD4(sc, TSADC_AUTO_CON), RD4(sc, TSADC_COMP_INT(sensor->channel)), RD4(sc, TSADC_COMP_SHUT(sensor->channel))); #endif @@ -511,7 +589,7 @@ for (i = 0; i < sc->conf->ntsensors; i++) { if (sc->conf->tsensors->id == id) { - rv =tsadc_read_temp(sc, sc->conf->tsensors + id, val); + rv = tsadc_read_temp(sc, sc->conf->tsensors + id, val); return (rv); } } @@ -552,6 +630,7 @@ struct sysctl_oid *oid, *tmp; sysctl_ctx_init(&tsadc_sysctl_ctx); + /* create node for hw.temp */ oid = SYSCTL_ADD_NODE(&tsadc_sysctl_ctx, SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, "temperature", Index: sys/arm64/rockchip/rk_usb2phy.c =================================================================== --- sys/arm64/rockchip/rk_usb2phy.c +++ sys/arm64/rockchip/rk_usb2phy.c @@ -54,10 +54,8 @@ #include "clkdev_if.h" #include "syscon_if.h" -#define RK3399_GRF_USB20_PHY0_CON0 0x0 -#define RK3399_GRF_USB20_PHY0_CON1 0x4 -#define RK3399_GRF_USB20_PHY0_CON2 0x8 -#define RK3399_GRF_USB20_PHY0_CON3 0xC +#define USBPHY_USB2_GRF_CON0 0x0 +#define USBPHY_USB2_GRF_CON1 0x4 struct rk_usb2phy_reg { uint32_t offset; @@ -72,16 +70,32 @@ struct rk_usb2phy_regs rk3399_regs = { .clk_ctl = { /* bit 4 put pll in suspend */ + .offset = 0x0000, .enable_mask = 0x100000, .disable_mask = 0x100010, } }; +struct rk_usb2phy_regs rk3568_regs = { + .clk_ctl = { + .offset = 0x0008, + .enable_mask = 0x100000, + .disable_mask = 0x100010, + } +}; + static struct ofw_compat_data compat_data[] = { { "rockchip,rk3399-usb2phy", (uintptr_t)&rk3399_regs }, + { "rockchip,rk3568-usb2phy", (uintptr_t)&rk3568_regs }, { NULL, 0 } }; +struct rk_usb2phy_clk_softc { + device_t clkdev; + struct syscon *grf; + struct rk_usb2phy_regs *regs; +}; + struct rk_usb2phy_softc { device_t dev; struct syscon *grf; @@ -106,9 +120,9 @@ rk_usb2phy_phynode_methods, sizeof(struct phynode_usb_sc), phynode_usb_class); -enum RK3399_USBPHY { - RK3399_USBPHY_HOST = 0, - RK3399_USBPHY_OTG, +enum RK_USBPHY { + RK_USBPHY_HOST = 0, + RK_USBPHY_OTG, }; static int @@ -116,15 +130,22 @@ { struct rk_usb2phy_softc *sc; device_t dev; - intptr_t phy; + uint32_t write_mask, write_val; int error; dev = phynode_get_device(phynode); - phy = phynode_get_id(phynode); sc = device_get_softc(dev); - if (phy != RK3399_USBPHY_HOST) + switch (sc->mode) { + case PHY_USB_MODE_HOST: + write_mask = 0x0003 << 16; + write_val = enable ? 0x0000 : 0x0002; + break; + + case PHY_USB_MODE_OTG: + default: return (ERANGE); + } if (sc->phy_supply) { if (enable) @@ -134,13 +155,15 @@ if (error != 0) { device_printf(dev, "Cannot %sable the regulator\n", enable ? "En" : "Dis"); - goto fail; + return (ENXIO); } } + /* we have one PHY with two ports adjust both */ + SYSCON_WRITE_4(sc->grf, USBPHY_USB2_GRF_CON0, write_mask | write_val); + SYSCON_WRITE_4(sc->grf, USBPHY_USB2_GRF_CON1, write_mask | write_val); + return (0); -fail: - return (ENXIO); } static int @@ -154,7 +177,7 @@ phy = phynode_get_id(phynode); sc = device_get_softc(dev); - if (phy != RK3399_USBPHY_HOST) + if (phy != RK_USBPHY_HOST) return (ERANGE); *mode = sc->mode; @@ -173,7 +196,7 @@ phy = phynode_get_id(phynode); sc = device_get_softc(dev); - if (phy != RK3399_USBPHY_HOST) + if (phy != RK_USBPHY_HOST) return (ERANGE); sc->mode = mode; @@ -274,7 +297,7 @@ nclocks = ofw_bus_string_list_to_array(node, "clock-output-names", &clknames); if (nclocks != 1) - return (ENXIO); + return (0); clkdom = clkdom_create(devsc->dev); clkdom_set_ofw_mapper(clkdom, rk_usb2phy_clk_ofw_map); @@ -304,8 +327,10 @@ sc->clkdev = device_get_parent(devsc->dev); sc->grf = devsc->grf; sc->regs = (struct rk_usb2phy_regs *)ofw_bus_search_compatible(devsc->dev, compat_data)->ocd_data; - OF_getencprop(node, "reg", regs, sizeof(regs)); - sc->regs->clk_ctl.offset = regs[0]; + if (!sc->regs->clk_ctl.offset) { + OF_getencprop(node, "reg", regs, sizeof(regs)); + sc->regs->clk_ctl.offset = regs[0]; + } clknode_register(clkdom, clk); if (clkdom_finit(clkdom) != 0) { @@ -329,7 +354,7 @@ if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); - device_set_desc(dev, "Rockchip RK3399 USB2PHY"); + device_set_desc(dev, "Rockchip USB2PHY"); return (BUS_PROBE_DEFAULT); } @@ -346,9 +371,17 @@ sc->dev = dev; node = ofw_bus_get_node(dev); - if (syscon_get_handle_default(dev, &sc->grf) != 0) { - device_printf(dev, "Cannot get syscon handle\n"); - return (ENXIO); + if (OF_hasprop(node, "rockchip,usbgrf")) { + if (syscon_get_by_ofw_property(dev, node, "rockchip,usbgrf", + &sc->grf)) { + device_printf(dev, "Cannot get syscon handle\n"); + return (ENXIO); + } + } else { + if (syscon_get_handle_default(dev, &sc->grf)) { + device_printf(dev, "Cannot get syscon handle\n"); + return (ENXIO); + } } if (clk_get_by_ofw_name(dev, 0, "phyclk", &sc->clk) != 0) { @@ -380,7 +413,7 @@ } regulator_get_by_ofw_property(dev, host, "phy-supply", &sc->phy_supply); - phy_init.id = RK3399_USBPHY_HOST; + phy_init.id = RK_USBPHY_HOST; phy_init.ofw_node = host; phynode = phynode_create(dev, &rk_usb2phy_phynode_class, &phy_init); if (phynode == NULL) { Index: sys/conf/files =================================================================== --- sys/conf/files +++ sys/conf/files @@ -1630,6 +1630,7 @@ dev/drm2/ttm/ttm_memory.c optional drm2 dev/drm2/ttm/ttm_page_alloc.c optional drm2 dev/drm2/ttm/ttm_bo_vm.c optional drm2 +dev/dwwdt/dwwdt.c optional dwwdt dev/efidev/efidev.c optional efirt dev/efidev/efirt.c optional efirt dev/efidev/efirtc.c optional efirt @@ -1869,6 +1870,7 @@ dev/iicbus/ofw_iicbus_if.m optional fdt iicbus dev/iicbus/pcf8574.c optional pcf8574 dev/iicbus/pcf8591.c optional pcf8591 +dev/iicbus/pmic/fan53555.c optional fan53555 | tcs4525 fdt dev/iicbus/rtc8583.c optional rtc8583 dev/iicbus/rtc/pcf85063.c optional pcf85063 iicbus fdt dev/iicbus/rtc/rx8803.c optional rx8803 iicbus fdt Index: sys/conf/files.arm64 =================================================================== --- sys/conf/files.arm64 +++ sys/conf/files.arm64 @@ -272,7 +272,7 @@ dev/mbox/mbox_if.m optional soc_brcm_bcm2837 -dev/mmc/host/dwmmc.c optional dwmmc fdt +dev/mmc/host/dwmmc.c optional dwmmc acpi | fdt dev/mmc/host/dwmmc_altera.c optional dwmmc dwmmc_altera fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc dwmmc_hisi fdt dev/mmc/host/dwmmc_rockchip.c optional dwmmc rk_dwmmc fdt @@ -569,8 +569,9 @@ # RockChip Drivers arm64/rockchip/rk3328_codec.c optional fdt rk3328codec soc_rockchip_rk3328 arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 -arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399 -arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 +arm64/rockchip/rk3568_iodomain.c optional fdt rk_iodomain soc_rockchip_rk3568 +arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399 | fdt rk_dwc3 soc_rockchip_rk3568 +arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 | fdt rk_i2c soc_rockchip_rk3568 arm64/rockchip/rk_i2s.c optional fdt sound soc_rockchip_rk3328 | fdt sound soc_rockchip_rk3399 dev/iicbus/pmic/rockchip/rk8xx.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 dev/iicbus/pmic/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 @@ -578,31 +579,34 @@ dev/iicbus/pmic/rockchip/rk8xx_clocks.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 dev/iicbus/pmic/rockchip/rk8xx_regulators.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 dev/iicbus/pmic/rockchip/rk8xx_rtc.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 -arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 -arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 -arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 -arm64/rockchip/rk_iodomain.c optional fdt rk_iodomain +dev/iicbus/pmic/rockchip/rk817.c optional fdt rk817 soc_rockchip_rk3568 +arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 +arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 +arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 +arm64/rockchip/rk_iodomain.c optional fdt rk_iodomain !soc_rockchip_rk3568 arm64/rockchip/rk_spi.c optional fdt rk_spi -arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399 +arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 -arm64/rockchip/rk_tsadc_if.m optional fdt soc_rockchip_rk3399 -arm64/rockchip/rk_tsadc.c optional fdt soc_rockchip_rk3399 +arm64/rockchip/rk_tsadc_if.m optional fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 +arm64/rockchip/rk_tsadc.c optional fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 arm64/rockchip/rk_pwm.c optional fdt rk_pwm arm64/rockchip/rk_pcie.c optional fdt pci soc_rockchip_rk3399 arm64/rockchip/rk_pcie_phy.c optional fdt pci soc_rockchip_rk3399 # RockChip Clock support -arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 -arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 -arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 -arm64/rockchip/clk/rk_clk_fract.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 -arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 -arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 -arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 +arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 +arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 +arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 +arm64/rockchip/clk/rk_clk_fract.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 +arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 +arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 +arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 +arm64/rockchip/clk/rk3568_cru.c optional fdt soc_rockchip_rk3568 +arm64/rockchip/clk/rk3568_pmucru.c optional fdt soc_rockchip_rk3568 # Xilinx arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq Index: sys/conf/options.arm64 =================================================================== --- sys/conf/options.arm64 +++ sys/conf/options.arm64 @@ -34,4 +34,5 @@ SOC_NXP_LS opt_soc.h SOC_ROCKCHIP_RK3328 opt_soc.h SOC_ROCKCHIP_RK3399 opt_soc.h +SOC_ROCKCHIP_RK3568 opt_soc.h SOC_XILINX_ZYNQ opt_soc.h Index: sys/contrib/device-tree/include/dt-bindings/power/rk3568-power.h =================================================================== --- sys/contrib/device-tree/include/dt-bindings/power/rk3568-power.h +++ sys/contrib/device-tree/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_0 0 +#define RK3568_PD_CPU_1 1 +#define RK3568_PD_CPU_2 2 +#define RK3568_PD_CPU_3 3 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif Index: sys/contrib/device-tree/src/arm64/rockchip/rk3566-quartz64-a.dts =================================================================== --- sys/contrib/device-tree/src/arm64/rockchip/rk3566-quartz64-a.dts +++ sys/contrib/device-tree/src/arm64/rockchip/rk3566-quartz64-a.dts @@ -0,0 +1,864 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Pine64 RK3566 Quartz64-A Board"; + compatible = "pine64,quartz64-a", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + battery_cell: battery-cell { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <2500000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <180000>; + voltage-max-design-microvolt = <4106000>; + voltage-min-design-microvolt = <3625000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4106000 100>, <4071000 95>, <4018000 90>, <3975000 85>, + <3946000 80>, <3908000 75>, <3877000 70>, <3853000 65>, + <3834000 60>, <3816000 55>, <3802000 50>, <3788000 45>, + <3774000 40>, <3760000 35>, <3748000 30>, <3735000 25>, + <3718000 20>, <3697000 15>, <3685000 10>, <3625000 0>; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + fan: gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 4500 1>; + pinctrl-names = "default"; + pinctrl-0 = <&fan_en_h>; + #cooling-cells = <2>; + }; + + leds { + compatible = "gpio-leds"; + + led-work { + label = "work-led"; + default-state = "off"; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_enable_h>; + retain-state-suspended; + }; + + led-diy { + label = "diy-led"; + default-state = "on"; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&diy_led_enable_h>; + retain-state-suspended; + }; + }; + + rk817-sound { + compatible = "simple-audio-card"; + // SOS pinctrl-names = "default"; + // SOS pinctrl-0 = <&hp_det_h>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + simple-audio-card,name = "Analog RK817"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker", "SPKO"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc12v_dcin: vcc12v_dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* vbus feeds the rk817 usb input. + * With no battery attached, also feeds vcc_bat+ + * via ON/OFF_BAT jumper + */ + vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0_usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + /* all four ports are controlled by one gpio + * the host ports are sourced from vcc5v0_usb + * the otg port is sourced from vcc5v0_midu + */ + vcc5v0_usb20_host: vcc5v0_usb20_host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb20_host"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb20_host_en_h>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb20_otg: vcc5v0_usb20_otg { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb20_otg"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dcdc_boost>; + }; + + vcc3v3_pcie_p: vcc3v3_pcie_p { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie_p"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc3v3_sd: vcc3v3_sd { + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + /* sourced from vbus and vcc_bat+ via rk817 sw5 */ + vcc_sys: vcc_sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <4400000>; + vin-supply = <&vbus>; + }; + + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ + vcc_wl: vcc_wl { + compatible = "regulator-fixed"; + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; +}; + +&combphy1_usq { + status = "okay"; + rockchip,enable-ssc; +}; + +&combphy2_psq { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; + clocks = <&cru ARMCLK>; +}; + +&cpu_thermal { + trips { + cpu_hot: cpu_hot { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_hot>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcc_1v8>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk817_battery: battery { + monitored-battery = <&battery_cell>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + }; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + vpcie3v3-supply = <&vcc3v3_pcie_p>; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fan { + fan_en_h: fan-en-h { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_enable_h: work-led-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_enable_h: diy-led-enable-h { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hp_det_h: hp-det-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + vcc5v0_usb20_host_en_h: vcc5v0-usb20-host-en_h { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; +}; + +/* sata1 is muxed with the usb3 port */ +&sata1 { + status = "okay"; +}; + +/* sata2 is muxed with the pcie2 slot*/ +&sata2 { + status = "disabled"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <108000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; + status = "okay"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk817 1>; + clock-names = "lpo"; + device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_usb20_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +/* usb3 controller is muxed with sata1 */ +&usbhost_dwc3 { + status = "disabled"; +}; + +/* usb3 controller is muxed with sata1 */ +&usbhost30 { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0_out_hdmi { + status = "okay"; +}; Index: sys/contrib/device-tree/src/arm64/rockchip/rk3566.dtsi =================================================================== --- sys/contrib/device-tree/src/arm64/rockchip/rk3566.dtsi +++ sys/contrib/device-tree/src/arm64/rockchip/rk3566.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x.dtsi" + +/ { + compatible = "rockchip,rk3566"; +}; + +&pipegrf { + compatible = "rockchip,rk3566-pipegrf", "syscon"; +}; + +&power { + power-domain@RK3568_PD_PIPE { + reg = ; + clocks = <&cru PCLK_PIPE>; + pm_qos = <&qos_pcie2x1>, + <&qos_sata1>, + <&qos_sata2>, + <&qos_usb3_0>, + <&qos_usb3_1>; + #power-domain-cells = <0>; + }; +}; + +&usbdrd_dwc3 { + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; +}; Index: sys/contrib/device-tree/src/arm64/rockchip/rk3568-pinctrl.dtsi =================================================================== --- sys/contrib/device-tree/src/arm64/rockchip/rk3568-pinctrl.dtsi +++ sys/contrib/device-tree/src/arm64/rockchip/rk3568-pinctrl.dtsi @@ -0,0 +1,3120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + acodec { + /omit-if-no-ref/ + acodec_pins: acodec-pins { + rockchip,pins = + /* acodec_adc_sync */ + <1 RK_PB1 5 &pcfg_pull_none>, + /* acodec_adcclk */ + <1 RK_PA1 5 &pcfg_pull_none>, + /* acodec_adcdata */ + <1 RK_PA0 5 &pcfg_pull_none>, + /* acodec_dac_datal */ + <1 RK_PA7 5 &pcfg_pull_none>, + /* acodec_dac_datar */ + <1 RK_PB0 5 &pcfg_pull_none>, + /* acodec_dacclk */ + <1 RK_PA3 5 &pcfg_pull_none>, + /* acodec_dacsync */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + audiopwm { + /omit-if-no-ref/ + audiopwm_lout: audiopwm-lout { + rockchip,pins = + /* audiopwm_lout */ + <1 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutn: audiopwm-loutn { + rockchip,pins = + /* audiopwm_loutn */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutp: audiopwm-loutp { + rockchip,pins = + /* audiopwm_loutp */ + <1 RK_PA0 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_rout: audiopwm-rout { + rockchip,pins = + /* audiopwm_rout */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routn: audiopwm-routn { + rockchip,pins = + /* audiopwm_routn */ + <1 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routp: audiopwm-routp { + rockchip,pins = + /* audiopwm_routp */ + <1 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + bt656 { + /omit-if-no-ref/ + bt656m0_pins: bt656m0-pins { + rockchip,pins = + /* bt656_clkm0 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* bt656_d0m0 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* bt656_d1m0 */ + <2 RK_PD1 2 &pcfg_pull_none>, + /* bt656_d2m0 */ + <2 RK_PD2 2 &pcfg_pull_none>, + /* bt656_d3m0 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* bt656_d4m0 */ + <2 RK_PD4 2 &pcfg_pull_none>, + /* bt656_d5m0 */ + <2 RK_PD5 2 &pcfg_pull_none>, + /* bt656_d6m0 */ + <2 RK_PD6 2 &pcfg_pull_none>, + /* bt656_d7m0 */ + <2 RK_PD7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + bt656m1_pins: bt656m1-pins { + rockchip,pins = + /* bt656_clkm1 */ + <4 RK_PB4 5 &pcfg_pull_none>, + /* bt656_d0m1 */ + <3 RK_PC6 5 &pcfg_pull_none>, + /* bt656_d1m1 */ + <3 RK_PC7 5 &pcfg_pull_none>, + /* bt656_d2m1 */ + <3 RK_PD0 5 &pcfg_pull_none>, + /* bt656_d3m1 */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* bt656_d4m1 */ + <3 RK_PD2 5 &pcfg_pull_none>, + /* bt656_d5m1 */ + <3 RK_PD3 5 &pcfg_pull_none>, + /* bt656_d6m1 */ + <3 RK_PD4 5 &pcfg_pull_none>, + /* bt656_d7m1 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clk */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <3 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <3 RK_PB1 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <3 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <3 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <3 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <3 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <3 RK_PC2 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + cam { + /omit-if-no-ref/ + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clkout1: cam-clkout1 { + rockchip,pins = + /* cam_clkout1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rxm0 */ + <0 RK_PB4 2 &pcfg_pull_none>, + /* can0_txm0 */ + <0 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rxm1 */ + <2 RK_PA2 4 &pcfg_pull_none>, + /* can0_txm1 */ + <2 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rxm0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* can1_txm0 */ + <1 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rxm1 */ + <4 RK_PC2 3 &pcfg_pull_none>, + /* can1_txm1 */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rxm0 */ + <4 RK_PB4 3 &pcfg_pull_none>, + /* can2_txm0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rxm1 */ + <2 RK_PB1 4 &pcfg_pull_none>, + /* can2_txm1 */ + <2 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins = + /* cif_clkout */ + <4 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + /* cif_clkin */ + <4 RK_PC1 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + /* cif_d8 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* cif_d10 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d11 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d12 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d13 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d14 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d15 */ + <4 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + /* cif_d0 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d1 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d2 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d3 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d4 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d5 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* cif_d6 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* cif_d7 */ + <3 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins = + /* clk32k_out0 */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins = + /* clk32k_out1 */ + <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + ebc { + /omit-if-no-ref/ + ebc_extern: ebc-extern { + rockchip,pins = + /* ebc_sdce1 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* ebc_sdce2 */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* ebc_sdce3 */ + <4 RK_PB1 2 &pcfg_pull_none>, + /* ebc_sdshr */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* ebc_vcom */ + <4 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ebc_pins: ebc-pins { + rockchip,pins = + /* ebc_gdclk */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* ebc_gdoe */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* ebc_gdsp */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* ebc_sdce0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* ebc_sdclk */ + <4 RK_PC1 2 &pcfg_pull_none>, + /* ebc_sddo0 */ + <3 RK_PC6 2 &pcfg_pull_none>, + /* ebc_sddo1 */ + <3 RK_PC7 2 &pcfg_pull_none>, + /* ebc_sddo2 */ + <3 RK_PD0 2 &pcfg_pull_none>, + /* ebc_sddo3 */ + <3 RK_PD1 2 &pcfg_pull_none>, + /* ebc_sddo4 */ + <3 RK_PD2 2 &pcfg_pull_none>, + /* ebc_sddo5 */ + <3 RK_PD3 2 &pcfg_pull_none>, + /* ebc_sddo6 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* ebc_sddo7 */ + <3 RK_PD5 2 &pcfg_pull_none>, + /* ebc_sddo8 */ + <3 RK_PD6 2 &pcfg_pull_none>, + /* ebc_sddo9 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* ebc_sddo10 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* ebc_sddo11 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* ebc_sddo12 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* ebc_sddo13 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* ebc_sddo14 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* ebc_sddo15 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* ebc_sdle */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* ebc_sdoe */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + edpdp { + /omit-if-no-ref/ + edpdpm0_pins: edpdpm0-pins { + rockchip,pins = + /* edpdp_hpdinm0 */ + <4 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + edpdpm1_pins: edpdpm1-pins { + rockchip,pins = + /* edpdp_hpdinm1 */ + <0 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_datastrobe: emmc-datastrobe { + rockchip,pins = + /* emmc_datastrobe */ + <1 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko25m */ + <2 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1m0_pins: eth1m0-pins { + rockchip,pins = + /* eth1_refclko25mm0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth1m1_pins: eth1m1-pins { + rockchip,pins = + /* eth1_refclko25mm1 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + flash { + /omit-if-no-ref/ + flash_pins: flash-pins { + rockchip,pins = + /* flash_ale */ + <1 RK_PD0 2 &pcfg_pull_none>, + /* flash_cle */ + <1 RK_PC6 3 &pcfg_pull_none>, + /* flash_cs0n */ + <1 RK_PD3 2 &pcfg_pull_none>, + /* flash_cs1n */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* flash_d0 */ + <1 RK_PB4 2 &pcfg_pull_none>, + /* flash_d1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* flash_d2 */ + <1 RK_PB6 2 &pcfg_pull_none>, + /* flash_d3 */ + <1 RK_PB7 2 &pcfg_pull_none>, + /* flash_d4 */ + <1 RK_PC0 2 &pcfg_pull_none>, + /* flash_d5 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* flash_d6 */ + <1 RK_PC2 2 &pcfg_pull_none>, + /* flash_d7 */ + <1 RK_PC3 2 &pcfg_pull_none>, + /* flash_dqs */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* flash_rdn */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* flash_rdy */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* flash_volsel */ + <0 RK_PA7 1 &pcfg_pull_none>, + /* flash_wpn */ + <1 RK_PC7 3 &pcfg_pull_none>, + /* flash_wrn */ + <1 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_cs1: fspi-cs1 { + rockchip,pins = + /* fspi_cs1n */ + <1 RK_PC6 2 &pcfg_pull_up>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins = + /* gmac0_mdc */ + <2 RK_PC3 2 &pcfg_pull_none>, + /* gmac0_mdio */ + <2 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + /* gmac0_mclkinout */ + <2 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_er: gmac0-rx-er { + rockchip,pins = + /* gmac0_rxer */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + /* gmac0_rxd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PB7 2 &pcfg_pull_none>, + /* gmac0_rxdvcrs */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1m0_miim: gmac1m0-miim { + rockchip,pins = + /* gmac1_mdcm0 */ + <3 RK_PC4 3 &pcfg_pull_none>, + /* gmac1_mdiom0 */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_clkinout: gmac1m0-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm0 */ + <3 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_er: gmac1m0-rx-er { + rockchip,pins = + /* gmac1_rxerm0 */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_bus2: gmac1m0-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* gmac1_rxd1m0 */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm0 */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2: gmac1m0-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_miim: gmac1m1-miim { + rockchip,pins = + /* gmac1_mdcm1 */ + <4 RK_PB6 3 &pcfg_pull_none>, + /* gmac1_mdiom1 */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_clkinout: gmac1m1-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm1 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_er: gmac1m1-rx-er { + rockchip,pins = + /* gmac1_rxerm1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_bus2: gmac1m1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m1 */ + <4 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_rxd1m1 */ + <4 RK_PB0 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2: gmac1m1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC0 2 &pcfg_pull_none>, + /* gpu_pwren */ + <0 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + hdmitx { + /omit-if-no-ref/ + hdmitxm0_cec: hdmitxm0-cec { + rockchip,pins = + /* hdmitxm0_cec */ + <4 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitxm1_cec: hdmitxm1-cec { + rockchip,pins = + /* hdmitxm1_cec */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_scl: hdmitx-scl { + rockchip,pins = + /* hdmitx_scl */ + <4 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_sda: hdmitx-sda { + rockchip,pins = + /* hdmitx_sda */ + <4 RK_PD0 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1_xfer: i2c1-xfer { + rockchip,pins = + /* i2c1_scl */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_sclm0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_sclm1 */ + <4 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam1 */ + <4 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_sclm0 */ + <1 RK_PA1 1 &pcfg_pull_none_smt>, + /* i2c3_sdam0 */ + <1 RK_PA0 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_sclm1 */ + <3 RK_PB5 4 &pcfg_pull_none_smt>, + /* i2c3_sdam1 */ + <3 RK_PB6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_sclm0 */ + <4 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c4_sdam0 */ + <4 RK_PB2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_sclm1 */ + <2 RK_PB2 2 &pcfg_pull_none_smt>, + /* i2c4_sdam1 */ + <2 RK_PB1 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_sclm0 */ + <3 RK_PB3 4 &pcfg_pull_none_smt>, + /* i2c5_sdam0 */ + <3 RK_PB4 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_sclm1 */ + <4 RK_PC7 2 &pcfg_pull_none_smt>, + /* i2c5_sdam1 */ + <4 RK_PD0 2 &pcfg_pull_none_smt>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrckrx: i2s1m0-lrckrx { + rockchip,pins = + /* i2s1m0_lrckrx */ + <1 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_lrcktx: i2s1m0-lrcktx { + rockchip,pins = + /* i2s1m0_lrcktx */ + <1 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <1 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclkrx: i2s1m0-sclkrx { + rockchip,pins = + /* i2s1m0_sclkrx */ + <1 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclktx: i2s1m0-sclktx { + rockchip,pins = + /* i2s1m0_sclktx */ + <1 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1m0_sdo1 */ + <1 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1m0_sdo2 */ + <1 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1m0_sdo3 */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrckrx: i2s1m1-lrckrx { + rockchip,pins = + /* i2s1m1_lrckrx */ + <4 RK_PA7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrcktx: i2s1m1-lrcktx { + rockchip,pins = + /* i2s1m1_lrcktx */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1m1_mclk */ + <3 RK_PC6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclkrx: i2s1m1-sclkrx { + rockchip,pins = + /* i2s1m1_sclkrx */ + <4 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclktx: i2s1m1-sclktx { + rockchip,pins = + /* i2s1m1_sclktx */ + <3 RK_PC7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1m1_sdi0 */ + <3 RK_PD2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1m1_sdi1 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1m1_sdi2 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1m1_sdi3 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1m1_sdo0 */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1m1_sdo1 */ + <4 RK_PB0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1m1_sdo2 */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1m1_sdo3 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrckrx: i2s1m2-lrckrx { + rockchip,pins = + /* i2s1m2_lrckrx */ + <3 RK_PC5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrcktx: i2s1m2-lrcktx { + rockchip,pins = + /* i2s1m2_lrcktx */ + <2 RK_PD2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_mclk: i2s1m2-mclk { + rockchip,pins = + /* i2s1m2_mclk */ + <2 RK_PD0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclkrx: i2s1m2-sclkrx { + rockchip,pins = + /* i2s1m2_sclkrx */ + <3 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclktx: i2s1m2-sclktx { + rockchip,pins = + /* i2s1m2_sclktx */ + <2 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi0: i2s1m2-sdi0 { + rockchip,pins = + /* i2s1m2_sdi0 */ + <2 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi1: i2s1m2-sdi1 { + rockchip,pins = + /* i2s1m2_sdi1 */ + <2 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi2: i2s1m2-sdi2 { + rockchip,pins = + /* i2s1m2_sdi2 */ + <2 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi3: i2s1m2-sdi3 { + rockchip,pins = + /* i2s1m2_sdi3 */ + <2 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo0: i2s1m2-sdo0 { + rockchip,pins = + /* i2s1m2_sdo0 */ + <2 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo1: i2s1m2-sdo1 { + rockchip,pins = + /* i2s1m2_sdo1 */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo2: i2s1m2-sdo2 { + rockchip,pins = + /* i2s1m2_sdo2 */ + <3 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo3: i2s1m2-sdo3 { + rockchip,pins = + /* i2s1m2_sdo3 */ + <3 RK_PC2 5 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrckrx: i2s2m0-lrckrx { + rockchip,pins = + /* i2s2m0_lrckrx */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_lrcktx: i2s2m0-lrcktx { + rockchip,pins = + /* i2s2m0_lrcktx */ + <2 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclkrx: i2s2m0-sclkrx { + rockchip,pins = + /* i2s2m0_sclkrx */ + <2 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclktx: i2s2m0-sclktx { + rockchip,pins = + /* i2s2m0_sclktx */ + <2 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrckrx: i2s2m1-lrckrx { + rockchip,pins = + /* i2s2m1_lrckrx */ + <4 RK_PA5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrcktx: i2s2m1-lrcktx { + rockchip,pins = + /* i2s2m1_lrcktx */ + <4 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2m1_mclk */ + <4 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclkrx: i2s2m1-sclkrx { + rockchip,pins = + /* i2s2m1_sclkrx */ + <4 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclktx: i2s2m1-sclktx { + rockchip,pins = + /* i2s2m1_sclktx */ + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2m1_sdi */ + <4 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2m1_sdo */ + <4 RK_PB3 5 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3m0_lrck: i2s3m0-lrck { + rockchip,pins = + /* i2s3m0_lrck */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_mclk: i2s3m0-mclk { + rockchip,pins = + /* i2s3m0_mclk */ + <3 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sclk: i2s3m0-sclk { + rockchip,pins = + /* i2s3m0_sclk */ + <3 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdi: i2s3m0-sdi { + rockchip,pins = + /* i2s3m0_sdi */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdo: i2s3m0-sdo { + rockchip,pins = + /* i2s3m0_sdo */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_lrck: i2s3m1-lrck { + rockchip,pins = + /* i2s3m1_lrck */ + <4 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_mclk: i2s3m1-mclk { + rockchip,pins = + /* i2s3m1_mclk */ + <4 RK_PC2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sclk: i2s3m1-sclk { + rockchip,pins = + /* i2s3m1_sclk */ + <4 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdi: i2s3m1-sdi { + rockchip,pins = + /* i2s3m1_sdi */ + <4 RK_PC6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdo: i2s3m1-sdo { + rockchip,pins = + /* i2s3m1_sdo */ + <4 RK_PC5 5 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins = + /* isp_flashtrigin */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* isp_flashtrigout */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* isp_prelighttrig */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtag_pins: jtag-pins { + rockchip,pins = + /* jtag_tck */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* jtag_tms */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + lcdc { + /omit-if-no-ref/ + lcdc_ctl: lcdc-ctl { + rockchip,pins = + /* lcdc_clk */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* lcdc_d0 */ + <2 RK_PD0 1 &pcfg_pull_none>, + /* lcdc_d1 */ + <2 RK_PD1 1 &pcfg_pull_none>, + /* lcdc_d2 */ + <2 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d8 */ + <3 RK_PA1 1 &pcfg_pull_none>, + /* lcdc_d9 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d16 */ + <3 RK_PB1 1 &pcfg_pull_none>, + /* lcdc_d17 */ + <3 RK_PB2 1 &pcfg_pull_none>, + /* lcdc_d18 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>, + /* lcdc_den */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_hsync */ + <3 RK_PC1 1 &pcfg_pull_none>, + /* lcdc_vsync */ + <3 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcu_pins: mcu-pins { + rockchip,pins = + /* mcu_jtagtck */ + <0 RK_PB4 4 &pcfg_pull_none>, + /* mcu_jtagtdi */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* mcu_jtagtdo */ + <0 RK_PB3 4 &pcfg_pull_none>, + /* mcu_jtagtms */ + <0 RK_PC2 4 &pcfg_pull_none>, + /* mcu_jtagtrstn */ + <0 RK_PC3 4 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins = + /* pcie20_clkreqnm0 */ + <0 RK_PA5 3 &pcfg_pull_none>, + /* pcie20_perstnm0 */ + <0 RK_PB6 3 &pcfg_pull_none>, + /* pcie20_wakenm0 */ + <0 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + /* pcie20_clkreqnm1 */ + <2 RK_PD0 4 &pcfg_pull_none>, + /* pcie20_perstnm1 */ + <3 RK_PC1 4 &pcfg_pull_none>, + /* pcie20_wakenm1 */ + <2 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m2_pins: pcie20m2-pins { + rockchip,pins = + /* pcie20_clkreqnm2 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_perstnm2 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie20_wakenm2 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins = + /* pcie20_buttonrstn */ + <0 RK_PB4 3 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_clkreqnm0 */ + <0 RK_PA4 3 &pcfg_pull_none>, + /* pcie30x1_perstnm0 */ + <0 RK_PC3 3 &pcfg_pull_none>, + /* pcie30x1_wakenm0 */ + <0 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_clkreqnm1 */ + <2 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x1_perstnm1 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* pcie30x1_wakenm1 */ + <2 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_clkreqnm2 */ + <1 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_perstnm2 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_wakenm2 */ + <1 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_buttonrstn: pcie30x1-buttonrstn { + rockchip,pins = + /* pcie30x1_buttonrstn */ + <0 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqnm0 */ + <0 RK_PA6 2 &pcfg_pull_none>, + /* pcie30x2_perstnm0 */ + <0 RK_PC6 3 &pcfg_pull_none>, + /* pcie30x2_wakenm0 */ + <0 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqnm1 */ + <2 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_perstnm1 */ + <2 RK_PD6 4 &pcfg_pull_none>, + /* pcie30x2_wakenm1 */ + <2 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqnm2 */ + <4 RK_PC2 4 &pcfg_pull_none>, + /* pcie30x2_perstnm2 */ + <4 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x2_wakenm2 */ + <4 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_buttonrstn: pcie30x2-buttonrstn { + rockchip,pins = + /* pcie30x2_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk: pdmm0-clk { + rockchip,pins = + /* pdm_clk0m0 */ + <1 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins = + /* pdmm0_clk1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = + /* pdmm0_sdi0 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = + /* pdmm0_sdi1 */ + <1 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = + /* pdmm0_sdi2 */ + <1 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = + /* pdmm0_sdi3 */ + <1 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk: pdmm1-clk { + rockchip,pins = + /* pdm_clk0m1 */ + <3 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins = + /* pdmm1_clk1 */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins = + /* pdmm1_sdi0 */ + <3 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins = + /* pdmm1_sdi1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins = + /* pdmm1_sdi2 */ + <4 RK_PA2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins = + /* pdmm1_sdi3 */ + <4 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_clk1: pdmm2-clk1 { + rockchip,pins = + /* pdmm2_clk1 */ + <3 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi0: pdmm2-sdi0 { + rockchip,pins = + /* pdmm2_sdi0 */ + <3 RK_PB3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi1: pdmm2-sdi1 { + rockchip,pins = + /* pdmm2_sdi1 */ + <3 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi2: pdmm2-sdi2 { + rockchip,pins = + /* pdmm2_sdi2 */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi3: pdmm2-sdi3 { + rockchip,pins = + /* pdmm2_sdi3 */ + <3 RK_PC0 5 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_sleep */ + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug0 */ + <0 RK_PA5 4 &pcfg_pull_none>, + /* pmu_debug1 */ + <0 RK_PA6 3 &pcfg_pull_none>, + /* pmu_debug2 */ + <0 RK_PC4 4 &pcfg_pull_none>, + /* pmu_debug3 */ + <0 RK_PC5 4 &pcfg_pull_none>, + /* pmu_debug4 */ + <0 RK_PC6 4 &pcfg_pull_none>, + /* pmu_debug5 */ + <0 RK_PC7 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <0 RK_PB5 4 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <0 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3_pins: pwm3-pins { + rockchip,pins = + /* pwm3_ir */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4_pins: pwm4-pins { + rockchip,pins = + /* pwm4 */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5_pins: pwm5-pins { + rockchip,pins = + /* pwm5 */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6_pins: pwm6-pins { + rockchip,pins = + /* pwm6 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7_pins: pwm7-pins { + rockchip,pins = + /* pwm7_ir */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <1 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <1 RK_PD6 4 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_irm0 */ + <3 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_irm1 */ + <4 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_irm0 */ + <3 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_irm1 */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_ou */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + /* sata_cpdet */ + <0 RK_PA4 2 &pcfg_pull_none>, + /* sata_cppod */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* sata_mpswitch */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0_pins: sata0-pins { + rockchip,pins = + /* sata0_actled */ + <4 RK_PC6 3 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1_pins: sata1-pins { + rockchip,pins = + /* sata1_actled */ + <4 RK_PC5 3 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2_pins: sata2-pins { + rockchip,pins = + /* sata2_actled */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scr_pins: scr-pins { + rockchip,pins = + /* scr_clk */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_det */ + <1 RK_PA7 3 &pcfg_pull_up>, + /* scr_io */ + <1 RK_PA3 3 &pcfg_pull_up>, + /* scr_rst */ + <1 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_det */ + <2 RK_PB2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <2 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + sdmmc2 { + /omit-if-no-ref/ + sdmmc2m0_bus4: sdmmc2m0-bus4 { + rockchip,pins = + /* sdmmc2_d0m0 */ + <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m0 */ + <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m0 */ + <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m0 */ + <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_clk: sdmmc2m0-clk { + rockchip,pins = + /* sdmmc2_clkm0 */ + <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_cmd: sdmmc2m0-cmd { + rockchip,pins = + /* sdmmc2_cmdm0 */ + <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_det: sdmmc2m0-det { + rockchip,pins = + /* sdmmc2_detm0 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m0_pwren: sdmmc2m0-pwren { + rockchip,pins = + /* sdmmc2m0_pwren */ + <3 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sdmmc2m1_bus4: sdmmc2m1-bus4 { + rockchip,pins = + /* sdmmc2_d0m1 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m1 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m1 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m1 */ + <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_clk: sdmmc2m1-clk { + rockchip,pins = + /* sdmmc2_clkm1 */ + <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_cmd: sdmmc2m1-cmd { + rockchip,pins = + /* sdmmc2_cmdm1 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_det: sdmmc2m1-det { + rockchip,pins = + /* sdmmc2_detm1 */ + <3 RK_PA7 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m1_pwren: sdmmc2m1-pwren { + rockchip,pins = + /* sdmmc2m1_pwren */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_tx: spdifm0-tx { + rockchip,pins = + /* spdifm0_tx */ + <1 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_tx: spdifm1-tx { + rockchip,pins = + /* spdifm1_tx */ + <3 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_tx: spdifm2-tx { + rockchip,pins = + /* spdifm2_tx */ + <4 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_none>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_none>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_none>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_none>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_none>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_none>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_none>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_none>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_none>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_none>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_none>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_none>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_none>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_shut: tsadcm0-shut { + rockchip,pins = + /* tsadcm0_shut */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shutorg: tsadc-shutorg { + rockchip,pins = + /* tsadc_shutorg */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <0 RK_PC0 3 &pcfg_pull_up>, + /* uart0_tx */ + <0 RK_PC1 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + /* uart0_ctsn */ + <0 RK_PC7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + /* uart0_rtsn */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rxm0 */ + <2 RK_PB3 2 &pcfg_pull_up>, + /* uart1_txm0 */ + <2 RK_PB4 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <2 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rxm1 */ + <3 RK_PD7 4 &pcfg_pull_up>, + /* uart1_txm1 */ + <3 RK_PD6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <4 RK_PC1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <4 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rxm0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart2_txm0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rxm1 */ + <1 RK_PD6 2 &pcfg_pull_up>, + /* uart2_txm1 */ + <1 RK_PD5 2 &pcfg_pull_up>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rxm0 */ + <1 RK_PA0 2 &pcfg_pull_up>, + /* uart3_txm0 */ + <1 RK_PA1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins = + /* uart3m0_ctsn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins = + /* uart3m0_rtsn */ + <1 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rxm1 */ + <3 RK_PC0 4 &pcfg_pull_up>, + /* uart3_txm1 */ + <3 RK_PB7 4 &pcfg_pull_up>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rxm0 */ + <1 RK_PA4 2 &pcfg_pull_up>, + /* uart4_txm0 */ + <1 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins = + /* uart4m0_ctsn */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins = + /* uart4m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rxm1 */ + <3 RK_PB1 4 &pcfg_pull_up>, + /* uart4_txm1 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rxm0 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_txm0 */ + <2 RK_PA2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rxm1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart5_txm1 */ + <3 RK_PC2 4 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rxm0 */ + <2 RK_PA3 3 &pcfg_pull_up>, + /* uart6_txm0 */ + <2 RK_PA4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <2 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <2 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rxm1 */ + <1 RK_PD6 3 &pcfg_pull_up>, + /* uart6_txm1 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rxm0 */ + <2 RK_PA5 3 &pcfg_pull_up>, + /* uart7_txm0 */ + <2 RK_PA6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <2 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <2 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rxm1 */ + <3 RK_PC5 4 &pcfg_pull_up>, + /* uart7_txm1 */ + <3 RK_PC4 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rxm2 */ + <4 RK_PA3 4 &pcfg_pull_up>, + /* uart7_txm2 */ + <4 RK_PA2 4 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rxm0 */ + <2 RK_PC6 2 &pcfg_pull_up>, + /* uart8_txm0 */ + <2 RK_PC5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <2 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <2 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rxm1 */ + <3 RK_PA0 4 &pcfg_pull_up>, + /* uart8_txm1 */ + <2 RK_PD7 4 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rxm0 */ + <2 RK_PA7 3 &pcfg_pull_up>, + /* uart9_txm0 */ + <2 RK_PB0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <2 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <2 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rxm1 */ + <4 RK_PC6 4 &pcfg_pull_up>, + /* uart9_txm1 */ + <4 RK_PC5 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rxm2 */ + <4 RK_PA5 4 &pcfg_pull_up>, + /* uart9_txm2 */ + <4 RK_PA4 4 &pcfg_pull_up>; + }; + }; + + vop { + /omit-if-no-ref/ + vopm0_pins: vopm0-pins { + rockchip,pins = + /* vop_pwmm0 */ + <0 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + vopm1_pins: vopm1-pins { + rockchip,pins = + /* vop_pwmm1 */ + <3 RK_PC4 2 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + spi0-hs { + /omit-if-no-ref/ + spi0m0_pins_hs: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs0_hs: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs1_hs: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_pins_hs: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs0_hs: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi1-hs { + /omit-if-no-ref/ + spi1m0_pins_hs: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0_hs: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1_hs: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_pins_hs: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs0_hs: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi2-hs { + /omit-if-no-ref/ + spi2m0_pins_hs: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs0_hs: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs1_hs: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_pins_hs: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs0_hs: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs1_hs: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3-hs { + /omit-if-no-ref/ + spi3m0_pins_hs: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0_hs: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1_hs: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_pins_hs: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs0_hs: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs1_hs: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>; + }; + }; + + gmac-txd-level3 { + /omit-if-no-ref/ + gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>; + }; + }; + + gmac-txc-level2 { + /omit-if-no-ref/ + gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadc_pin: tsadc-pin { + rockchip,pins = + /* tsadc_pin */ + <0 RK_PA1 0 &pcfg_pull_none>; + }; + }; +}; Index: sys/contrib/device-tree/src/arm64/rockchip/rk3568.dtsi =================================================================== --- sys/contrib/device-tree/src/arm64/rockchip/rk3568.dtsi +++ sys/contrib/device-tree/src/arm64/rockchip/rk3568.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "rk356x.dtsi" + +/ { + compatible = "rockchip,rk3568"; + + sata0: sata@fc000000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfc000000 0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, + <&cru CLK_SATA0_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy0_us PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + qos_pcie3x1: qos@fe190080 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190080 0x0 0x20>; + }; + + qos_pcie3x2: qos@fe190100 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190100 0x0 0x20>; + }; + + qos_sata0: qos@fe190200 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190200 0x0 0x20>; + }; + + gmac0: ethernet@fe2a0000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe2a0000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, + <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, + <&cru PCLK_XPCS>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref", + "pclk_xpcs"; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <8>; + snps,wr_osr_lmt = <4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + combphy0_us: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + #phy-cells = <1>; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + status = "disabled"; + }; +}; + +&cpu0_opp_table { + opp-1992000000 { + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1150000 1150000 1150000>; + }; +}; + +&pipegrf { + compatible = "rockchip,rk3568-pipegrf", "syscon"; +}; + +&power { + power-domain@RK3568_PD_PIPE { + reg = ; + clocks = <&cru PCLK_PIPE>; + pm_qos = <&qos_pcie2x1>, + <&qos_pcie3x1>, + <&qos_pcie3x2>, + <&qos_sata0>, + <&qos_sata1>, + <&qos_sata2>, + <&qos_usb3_0>, + <&qos_usb3_1>; + #power-domain-cells = <0>; + }; +}; + +&usbdrd_dwc3 { + phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; +}; Index: sys/contrib/device-tree/src/arm64/rockchip/rk356x.dtsi =================================================================== --- sys/contrib/device-tree/src/arm64/rockchip/rk356x.dtsi +++ sys/contrib/device-tree/src/arm64/rockchip/rk356x.dtsi @@ -0,0 +1,1640 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&scmi_clk 0>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000 900000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000 900000 1150000>; + opp-suspend; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <900000 900000 1150000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <975000 975000 1150000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1050000 1050000 1150000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1150000 1150000 1150000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1150000 1150000 1150000>; + }; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <825000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <900000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + arm,no-tick-in-suspend; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + pinctrl-0 = <&clk32k_out0>; + pinctrl-names = "default"; + #clock-cells = <0>; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0010f000 0x100>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + sata1: sata@fc400000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfc400000 0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, + <&cru CLK_SATA1_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy1_usq PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + sata2: sata@fc800000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfc800000 0 0x1000>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, + <&cru CLK_SATA2_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy2_psq PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + usbdrd30: usbdrd { + compatible = "rockchip,rk3399-dwc3", "snps,dwc3"; + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "pipe_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: dwc3@fcc00000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfcc00000 0x0 0x400000>; + interrupts = ; + dr_mode = "host"; + phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG0>; + reset-names = "usb3-otg"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,xhci-trb-ent-quirk; + status = "disabled"; + }; + }; + + usbhost30: usbhost { + compatible = "rockchip,rk3399-dwc3", "snps,dwc3"; + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "pipe_clk"; + #address-cells = <2>; + #size-cells = <2>; + assigned-clocks = <&cru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <25000000>; + ranges; + status = "disabled"; + + usbhost_dwc3: dwc3@fd000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfd000000 0x0 0x400000>; + interrupts = ; + dr_mode = "host"; + phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG1>; + reset-names = "usb3-host"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + }; + + gic: interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ + <0x0 0xfd460000 0 0x80000>; /* GICR */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + mbi-alias = <0x0 0xfd410000>; + mbi-ranges = <296 24>; + msi-controller; + }; + + usb_host0_ehci: usb@fd800000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd800000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>; + phys = <&u2phy1_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ohci: usb@fd840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd840000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>; + phys = <&u2phy1_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host1_ehci: usb@fd880000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd880000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>; + phys = <&u2phy1_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host1_ohci: usb@fd8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd8c0000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>; + phys = <&u2phy1_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc20000 0x0 0x10000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3568-pmu-io-voltage-domain"; + status = "disabled"; + }; + }; + + pipegrf: syscon@fdc50000 { + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + + grf: syscon@fdc60000 { + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc60000 0x0 0x10000>; + }; + + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + + usb2phy0_grf: syscon@fdca0000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca0000 0x0 0x8000>; + }; + + usb2phy1_grf: syscon@fdca8000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca8000 0x0 0x8000>; + }; + + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x0 0xfdd00000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x0 0xfdd20000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; + assigned-clock-rates = <1200000000>, <200000000>; + rockchip,grf = <&grf>; + }; + + i2c0: i2c@fdd40000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfdd40000 0x0 0x1000>; + interrupts = ; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fdd50000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfdd50000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pwm0: pwm@fdd70000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70000 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm0m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@fdd70010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70010 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm1m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@fdd70020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70020 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm2m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@fdd70030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70030 0x0 0x10>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm3_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmu: power-management@fdd90000 { + compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xfdd90000 0x0 0x1000>; + + power: power-controller { + compatible = "rockchip,rk3568-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* These power domains are grouped by VD_GPU */ + power-domain@RK3568_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU_PRE>, + <&cru PCLK_GPU_PRE>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3568_PD_VI { + reg = ; + clocks = <&cru HCLK_VI>, + <&cru PCLK_VI>; + pm_qos = <&qos_isp>, + <&qos_vicap0>, + <&qos_vicap1>; + #power-domain-cells = <0>; + }; + + power-domain@RK3568_PD_VO { + reg = ; + clocks = <&cru HCLK_VO>, + <&cru PCLK_VO>, + <&cru ACLK_VOP_PRE>; + pm_qos = <&qos_hdcp>, + <&qos_vop_m0>, + <&qos_vop_m1>; + #power-domain-cells = <0>; + }; + + power-domain@RK3568_PD_RGA { + reg = ; + clocks = <&cru HCLK_RGA_PRE>, + <&cru PCLK_RGA_PRE>; + pm_qos = <&qos_ebc>, + <&qos_iep>, + <&qos_jpeg_dec>, + <&qos_jpeg_enc>, + <&qos_rga_rd>, + <&qos_rga_wr>; + #power-domain-cells = <0>; + }; + + power-domain@RK3568_PD_VPU { + reg = ; + clocks = <&cru HCLK_VPU_PRE>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3568_PD_RKVDEC { + clocks = <&cru HCLK_RKVDEC_PRE>; + reg = ; + pm_qos = <&qos_rkvdec>; + #power-domain-cells = <0>; + }; + + power-domain@RK3568_PD_RKVENC { + reg = ; + clocks = <&cru HCLK_RKVENC_PRE>; + pm_qos = <&qos_rkvenc_rd_m0>, + <&qos_rkvenc_rd_m1>, + <&qos_rkvenc_wr_m0>; + #power-domain-cells = <0>; + }; + }; + }; + + gpu: gpu@fde60000 { + compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; + reg = <0x0 0xfde60000 0x0 0x4000>; + + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&scmi_clk 1>, <&cru CLK_GPU>; + clock-names = "core", "bus"; + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; + power-domains = <&power RK3568_PD_GPU>; + status = "disabled"; + }; + + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, + <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC2>; + reset-names = "reset"; + status = "disabled"; + }; + + gmac1: ethernet@fe010000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe010000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, + <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <8>; + snps,wr_osr_lmt = <4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + + vop: vop@fe040000 { + compatible = "rockchip,rk3568-vop"; + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; + reg-names = "regs", "gamma_lut"; + rockchip,grf = <&grf>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; + clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; + iommus = <&vop_mmu>; + power-domains = <&power RK3568_PD_VO>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vp0_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vp0>; + status = "disabled"; + }; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + vp1_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vp1>; + status = "disabled"; + }; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + vp2_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vp2>; + status = "disabled"; + }; + }; + }; + }; + + vop_mmu: iommu@fe043e00 { + compatible = "rockchip,rk3568-iommu"; + reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + hdmi: hdmi@fe0a0000 { + compatible = "rockchip,rk3568-dw-hdmi"; + reg = <0x0 0xfe0a0000 0x0 0x20000>; + interrupts = ; + clocks = <&cru PCLK_HDMI_HOST>, + <&cru CLK_HDMI_SFR>, + <&cru CLK_HDMI_CEC>, + <&cru HCLK_VOP>; + clock-names = "iahb", "isfr", "cec", "hclk"; + power-domains = <&power RK3568_PD_VO>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_hdmi>; + status = "disabled"; + }; + + hdmi_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_hdmi>; + status = "disabled"; + }; + + hdmi_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_hdmi>; + status = "disabled"; + }; + }; + }; + }; + + qos_gpu: qos@fe128000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe128000 0x0 0x20>; + }; + + qos_rkvenc_rd_m0: qos@fe138080 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe138080 0x0 0x20>; + }; + + qos_rkvenc_rd_m1: qos@fe138100 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe138100 0x0 0x20>; + }; + + qos_rkvenc_wr_m0: qos@fe138180 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe138180 0x0 0x20>; + }; + + qos_isp: qos@fe148000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe148000 0x0 0x20>; + }; + + qos_vicap0: qos@fe148080 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe148080 0x0 0x20>; + }; + + qos_vicap1: qos@fe148100 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe148100 0x0 0x20>; + }; + + qos_vpu: qos@fe150000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe150000 0x0 0x20>; + }; + + qos_ebc: qos@fe158000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158000 0x0 0x20>; + }; + + qos_iep: qos@fe158100 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158100 0x0 0x20>; + }; + + qos_jpeg_dec: qos@fe158180 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158180 0x0 0x20>; + }; + + qos_jpeg_enc: qos@fe158200 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158200 0x0 0x20>; + }; + + qos_rga_rd: qos@fe158280 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158280 0x0 0x20>; + }; + + qos_rga_wr: qos@fe158300 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe158300 0x0 0x20>; + }; + + qos_npu: qos@fe180000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe180000 0x0 0x20>; + }; + + qos_pcie2x1: qos@fe190000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190000 0x0 0x20>; + }; + + qos_sata1: qos@fe190280 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190280 0x0 0x20>; + }; + + qos_sata2: qos@fe190300 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190300 0x0 0x20>; + }; + + qos_usb3_0: qos@fe190380 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190380 0x0 0x20>; + }; + + qos_usb3_1: qos@fe190400 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190400 0x0 0x20>; + }; + + qos_rkvdec: qos@fe198000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe198000 0x0 0x20>; + }; + + qos_hdcp: qos@fe1a8000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe1a8000 0x0 0x20>; + }; + + qos_vop_m0: qos@fe1a8080 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe1a8080 0x0 0x20>; + }; + + qos_vop_m1: qos@fe1a8100 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe1a8100 0x0 0x20>; + }; + + pcie2x1: pcie@fe260000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msi", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <2>; + msi-map = <0x0 &gic 0x0 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psq PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0000000 0x0 0x400000>, + <0x0 0xfe260000 0x0 0x10000>, + <0x3 0x3f800000 0x0 0x800000>; + ranges = <0x1000000 0x0 0x7f700000 0x3 0x3f700000 0x0 0x00100000 + 0x2000000 0x0 0x40000000 0x3 0x00000000 0x0 0x3f700000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + status = "disabled"; + + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = ; + }; + + }; + + sdmmc0: mmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc1: mmc@fe2c0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC1>; + reset-names = "reset"; + status = "disabled"; + }; + + sfc: spi@fe300000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe300000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-0 = <&fspi_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sdhci: mmc@fe310000 { + compatible = "rockchip,rk3568-dwcmshc"; + reg = <0x0 0xfe310000 0x0 0x10000>; + interrupts = ; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + spdif: spdif@fe460000 { + compatible = "rockchip,rk3568-spdif"; + reg = <0x0 0xfe460000 0x0 0x1000>; + interrupts = ; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; + dmas = <&dmac1 1>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe410000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe410000 0x0 0x1000>; + interrupts = ; + assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; + assigned-clock-rates = <1188000000>, <1188000000>; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, + <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 3>, <&dmac1 2>; + dma-names = "rx", "tx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx + &i2s1m0_lrcktx &i2s1m0_lrckrx + &i2s1m0_sdi0 &i2s1m0_sdi1 + &i2s1m0_sdi2 &i2s1m0_sdi3 + &i2s1m0_sdo0 &i2s1m0_sdo1 + &i2s1m0_sdo2 &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + dmac0: dmac@fe530000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe530000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + dmac1: dmac@fe550000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe550000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + i2c1: i2c@fe5a0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5a0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c1_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe5b0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5b0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c2m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe5c0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5c0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c3m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe5d0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5d0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c4m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fe5e0000 { + compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5e0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wdt: watchdog@fe600000 { + compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; + reg = <0x0 0xfe600000 0x0 0x100>; + interrupts = ; + clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; + clock-names = "tclk", "pclk"; + }; + + uart1: serial@fe650000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe650000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart1m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@fe660000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe660000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 4>, <&dmac0 5>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@fe670000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe670000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 6>, <&dmac0 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart3m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@fe680000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe680000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 8>, <&dmac0 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart4m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@fe690000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe690000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 10>, <&dmac0 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart5m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart6: serial@fe6a0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 12>, <&dmac0 13>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart6m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart7: serial@fe6b0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart7m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart8: serial@fe6c0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart8m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart9: serial@fe6d0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6d0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 18>, <&dmac0 19>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart9m0_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + thermal_zones: thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + }; + }; + + tsadc: tsadc@fe710000 { + compatible = "rockchip,rk3568-tsadc"; + reg = <0x0 0xfe710000 0x0 0x100>; + interrupts = ; + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; + assigned-clock-rates = <17000000>, <700000>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, + <&cru SRST_TSADCPHY>; + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <95000>; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&tsadc_pin>; + pinctrl-1 = <&tsadc_shutorg>; + pinctrl-2 = <&tsadc_pin>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + saradc: saradc@fe720000 { + compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xfe720000 0x0 0x100>; + interrupts = ; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + pwm4: pwm@fe6e0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0000 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm4_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@fe6e0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0010 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm5_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@fe6e0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0020 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm6_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@fe6e0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0030 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm7_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@fe6f0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0000 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm8m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@fe6f0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0010 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm9m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@fe6f0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0020 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm10m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@fe6f0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0030 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@fe700000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700000 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm12m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@fe700010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700010 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm13m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@fe700020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700020 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm14m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@fe700030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700030 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm15m0_pins>; + pinctrl-names = "active"; + #pwm-cells = <3>; + status = "disabled"; + }; + + combphy1_usq: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + #phy-cells = <1>; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + status = "disabled"; + }; + + combphy2_psq: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + #phy-cells = <1>; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + status = "disabled"; + }; + + usb2phy0: usb2-phy@fe8a0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8a0000 0x0 0x10000>; + clocks = <&pmucru CLK_USBPHY0_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "usb480m_phy0"; + interrupts = ; + rockchip,usbgrf = <&usb2phy0_grf>; + status = "disabled"; + + u2phy0_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + usb2phy1: usb2-phy@fe8b0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8b0000 0x0 0x10000>; + clocks = <&pmucru CLK_USBPHY1_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "usb480m_phy1"; + interrupts = ; + rockchip,usbgrf = <&usb2phy1_grf>; + status = "disabled"; + + u2phy1_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@fdd60000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfdd60000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@fe740000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe740000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@fe750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe750000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@fe760000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe760000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@fe770000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe770000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3568-pinctrl.dtsi" Index: sys/contrib/device-tree/src/arm64/rockchip/rockchip-pinconf.dtsi =================================================================== --- sys/contrib/device-tree/src/arm64/rockchip/rockchip-pinconf.dtsi +++ sys/contrib/device-tree/src/arm64/rockchip/rockchip-pinconf.dtsi @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +&pinctrl { + /omit-if-no-ref/ + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { + bias-disable; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { + bias-disable; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { + bias-disable; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { + bias-disable; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { + bias-disable; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { + bias-disable; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { + bias-disable; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { + bias-disable; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { + bias-disable; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { + bias-pull-down; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { + bias-pull-down; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { + bias-pull-down; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { + bias-pull-down; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { + bias-pull-down; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { + bias-pull-down; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { + bias-pull-down; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { + bias-pull-down; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { + bias-pull-down; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_smt: pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_down_smt: pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_output_high: pcfg-output-high { + output-high; + }; + + /omit-if-no-ref/ + pcfg_output_low: pcfg-output-low { + output-low; + }; +}; Index: sys/dev/iicbus/pmic/fan53555.c =================================================================== --- sys/dev/iicbus/pmic/fan53555.c +++ sys/dev/iicbus/pmic/fan53555.c @@ -56,17 +56,19 @@ #define FAN53555_VSEL_MASK 0x3f #define FAN53555_CTRL 0x02 #define FAN53555_ID1 0x03 -#define FAN53555_ID1_DIE_ID(x) (((x) >> 4) & 0x0F) +#define FAN53555_ID1_DIE_ID(x) (x & 0x0F) #define FAN53555_ID2 0x04 -#define FAN53555_ID2_DIE_REV(x) (((x) >> 4) & 0x0F) +#define FAN53555_ID2_DIE_REV(x) (x & 0x0F) #define FAN53555_MON 0x05 +#define TCS4525_VSEL0 0x11 +#define TCS4525_VSEL1 0x10 #if 0 -#define dprintf(sc, format, arg...) \ - device_printf(sc->base_dev, "%s: " format, __func__, arg) +#define dprintf(dev, format, arg...) \ + device_printf(dev, "%s: " format, __func__, arg) #else -#define dprintf(sc, format, arg...) +#define dprintf(dev, format, arg...) #endif enum fan53555_pmic_type { @@ -73,6 +75,7 @@ FAN53555 = 1, SYR827, SYR828, + TCS4525, }; static struct ofw_compat_data compat_data[] = { @@ -79,6 +82,7 @@ {"fcs,fan53555", FAN53555}, {"silergy,syr827", SYR827}, {"silergy,syr828", SYR828}, + {"tcs,tcs4525", TCS4525}, {NULL, 0} }; @@ -88,6 +92,8 @@ device_t base_dev; uint8_t live_reg; uint8_t sleep_reg; + uint8_t mode_reg; + uint8_t mode_mask; struct regulator_range *range; struct regnode_std_param *param; }; @@ -110,6 +116,8 @@ static struct regulator_range fan_4_range = REG_RANGE_INIT( 0, 0x3F, 603000, 12826); +static struct regulator_range tcs_12_range = + REG_RANGE_INIT( 0, 0x3F, 800000, 6250); static int fan53555_read(device_t dev, uint8_t reg, uint8_t *val) @@ -202,7 +210,7 @@ sc = regnode_get_softc(regnode); - dprintf(sc, "%sabling regulator %s\n", enable ? "En" : "Dis", + dprintf(sc->base_dev, "%sabling regulator %s\n", enable ? "En" : "Dis", sc->name); fan53555_read(sc->base_dev, sc->live_reg, &val); if (enable) @@ -226,8 +234,8 @@ sc = regnode_get_softc(regnode); - dprintf(sc, "Setting %s to %d<->%d uvolts\n", sc->name, min_uvolt, - max_uvolt); + dprintf(sc->base_dev, "Setting %s to %d<->%d uvolts\n", sc->name, + min_uvolt, max_uvolt); rv = regulator_range_volt_to_sel8(sc->range, 1, min_uvolt, max_uvolt, &sel); if (rv != 0) @@ -234,12 +242,13 @@ return (rv); *udelay = sc->param->ramp_delay; rv = fan53555_write_sel(sc, sel); - dprintf(sc, "Regulator %s writing sel: 0x%02X\n", sc->name, sel); + dprintf(sc->base_dev, "Regulator %s writing sel: 0x%02X\n", sc->name, + sel); fan53555_read_sel(sc, &sel); regulator_range_sel8_to_volt(sc->range, 1, sel, &uvolt); - dprintf(sc, "Regulator %s set to %d uvolt (sel: 0x%02X)\n", sc->name, - uvolt, sel); + dprintf(sc->base_dev, "Regulator %s set to %d uvolt (sel: 0x%02X)\n", + sc->name, uvolt, sel); return (rv); } @@ -257,8 +266,8 @@ if (rv != 0) return (rv); rv = regulator_range_sel8_to_volt(sc->range, 1, sel, uvolt); - dprintf(sc, "Regulator %s is at %d uvolt ((sel: 0x%02X)\n", sc->name, - *uvolt, sel); + dprintf(sc->base_dev, "Regulator %s is at %d uvolt ((sel: 0x%02X)\n", + sc->name, *uvolt, sel); return (rv); } @@ -308,6 +317,15 @@ } } + if (type == TCS4525) { + switch (id) { + case 12: + return (&tcs_12_range); + default: + return (NULL); + } + } + return (NULL); } @@ -335,7 +353,7 @@ device_printf(sc->dev, "cannot read ID2\n"); return (NULL); } - dprintf(sc, "Device ID1: 0x%02X, ID2: 0x%02X\n", id1, id2); + dprintf(sc->dev, "Device ID1: 0x%02X, ID2: 0x%02X\n", id1, id2); range = fan53555_get_range(sc, type, FAN53555_ID1_DIE_ID(id1), FAN53555_ID2_DIE_REV(id2)); @@ -411,6 +429,9 @@ case SYR828: device_set_desc(dev, "SYR828 PMIC"); break; + case TCS4525: + device_set_desc(dev, "TCS4525 PMIC"); + break; default: return (ENXIO); } @@ -434,12 +455,30 @@ sizeof(susp_sel)); if (rv <= 0) susp_sel = 1; - if (susp_sel == 1) { - sc->live_reg = FAN53555_VSEL0; - sc->sleep_reg = FAN53555_VSEL1; - } else { - sc->live_reg = FAN53555_VSEL1; - sc->sleep_reg = FAN53555_VSEL0; + + switch (type) { + case FAN53555: + case SYR827: + case SYR828: + if (susp_sel == 1) { + sc->live_reg = FAN53555_VSEL0; + sc->sleep_reg = FAN53555_VSEL1; + } else { + sc->live_reg = FAN53555_VSEL1; + sc->sleep_reg = FAN53555_VSEL0; + } + break; + case TCS4525: + if (susp_sel == 1) { + sc->live_reg = TCS4525_VSEL0; + sc->sleep_reg = TCS4525_VSEL1; + } else { + sc->live_reg = TCS4525_VSEL1; + sc->sleep_reg = TCS4525_VSEL0; + } + break; + default: + return (ENXIO); } if (fan53555_reg_attach(sc, node, type) == NULL) device_printf(dev, "cannot attach regulator.\n"); Index: sys/dev/iicbus/pmic/rockchip/rk817.c =================================================================== --- sys/dev/iicbus/pmic/rockchip/rk817.c +++ sys/dev/iicbus/pmic/rockchip/rk817.c @@ -0,0 +1,980 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSS + * + * Copyright (c) 2021, 2022 Soren Schmidt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include + +#include "regdev_if.h" +#include "clock_if.h" + +MALLOC_DEFINE(M_RK817_REG, "RK817 regulator", "RK817 power regulator"); + +#if 0 +#define dprintf(sc, format, arg...) \ + device_printf(sc->base_dev, "%s: " format, __func__, arg) +#else +#define dprintf(sc, format, arg...) +#endif + +enum rk817_type { + RK809 = 1, + RK817, +}; + +static struct ofw_compat_data compat_data[] = { + {"rockchip,rk809", RK809}, + {"rockchip,rk817", RK817}, + {NULL, 0} +}; + +struct rk817_regdef { + intptr_t id; + char *name; + uint8_t enable_reg; + uint8_t enable_mask; + uint8_t voltage_reg; + uint8_t voltage_mask; + int voltage_min1; + int voltage_max1; + int voltage_step1; + int voltage_min2; + int voltage_max2; + int voltage_step2; + int voltage_steps; +}; + +struct rk817_reg_sc { + struct regnode *regnode; + device_t base_dev; + struct rk817_regdef *def; + phandle_t xref; + struct regnode_std_param *param; +}; + +struct reg_list { + TAILQ_ENTRY(reg_list) next; + struct rk817_reg_sc *reg; +}; + +struct rk817_softc { + device_t dev; + struct mtx mtx; + enum rk817_type type; + TAILQ_HEAD(, reg_list) regs; + int nregs; +}; + +static struct rk817_regdef rk809_regdefs[] = { + { + .id = RK809_DCDC1, + .name = "DCDC_REG1", + .enable_reg = RK817_DCDC_EN, + .enable_mask = 0x11, + .voltage_reg = RK817_DCDC1_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 500000, + .voltage_max1 = 1487500, + .voltage_min2 = 1500000, + .voltage_max2 = 2400000, + .voltage_step1 = 12500, + .voltage_step2 = 100000, + .voltage_steps = 177, + }, + { + .id = RK809_DCDC2, + .name = "DCDC_REG2", + .enable_reg = RK817_DCDC_EN, + .enable_mask = 0x22, + .voltage_reg = RK817_DCDC2_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 500000, + .voltage_max1 = 1487500, + .voltage_min2 = 1500000, + .voltage_max2 = 2400000, + .voltage_step1 = 12500, + .voltage_step2 = 100000, + .voltage_steps = 177, + }, + { + .id = RK809_DCDC3, + .name = "DCDC_REG3", + .enable_reg = RK817_DCDC_EN, + .enable_mask = 0x44, + .voltage_reg = RK817_DCDC3_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 500000, + .voltage_max1 = 1487500, + .voltage_min2 = 1500000, + .voltage_max2 = 2400000, + .voltage_step1 = 12500, + .voltage_step2 = 100000, + .voltage_steps = 177, + }, + { + .id = RK809_DCDC4, + .name = "DCDC_REG4", + .enable_reg = RK817_DCDC_EN, + .enable_mask = 0x88, + .voltage_reg = RK817_DCDC4_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 500000, + .voltage_max1 = 1487500, + .voltage_min2 = 1500000, + .voltage_max2 = 3400000, + .voltage_step1 = 12500, + .voltage_step2 = 100000, + .voltage_steps = 195, + }, + { + .id = RK809_DCDC5, + .name = "DCDC_REG5", + .enable_reg = RK817_LDO_EN3, + .enable_mask = 0x22, + .voltage_reg = RK817_BOOST_ON_VSEL, + .voltage_mask = 0x07, + .voltage_min1 = 1600000, /* cheat is 1.5V */ + .voltage_max1 = 3400000, + .voltage_min2 = 3500000, + .voltage_max2 = 3600000, + .voltage_step1 = 200000, + .voltage_step2 = 300000, + .voltage_steps = 8, + }, + { + .id = RK809_LDO1, + .name = "LDO_REG1", + .enable_reg = RK817_LDO_EN1, + .enable_mask = 0x11, + .voltage_reg = RK817_LDO1_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK809_LDO2, + .name = "LDO_REG2", + .enable_reg = RK817_LDO_EN1, + .enable_mask = 0x22, + .voltage_reg = RK817_LDO2_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK809_LDO3, + .name = "LDO_REG3", + .enable_reg = RK817_LDO_EN1, + .enable_mask = 0x44, + .voltage_reg = RK817_LDO3_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK809_LDO4, + .name = "LDO_REG4", + .enable_reg = RK817_LDO_EN1, + .enable_mask = 0x88, + .voltage_reg = RK817_LDO4_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK809_LDO5, + .name = "LDO_REG5", + .enable_reg = RK817_LDO_EN2, + .enable_mask = 0x11, + .voltage_reg = RK817_LDO5_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK809_LDO6, + .name = "LDO_REG6", + .enable_reg = RK817_LDO_EN2, + .enable_mask = 0x22, + .voltage_reg = RK817_LDO6_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK809_LDO7, + .name = "LDO_REG7", + .enable_reg = RK817_LDO_EN2, + .enable_mask = 0x44, + .voltage_reg = RK817_LDO7_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK809_LDO8, + .name = "LDO_REG8", + .enable_reg = RK817_LDO_EN2, + .enable_mask = 0x88, + .voltage_reg = RK817_LDO8_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK809_LDO9, + .name = "LDO_REG9", + .enable_reg = RK817_LDO_EN3, + .enable_mask = 0x11, + .voltage_reg = RK817_LDO9_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK809_SWITCH1, + .name = "SWITCH_REG1", + .enable_reg = RK817_LDO_EN3, + .enable_mask = 0x44, + .voltage_min1 = 3300000, + .voltage_max1 = 3300000, + .voltage_steps = 0, + }, + { + .id = RK809_SWITCH2, + .name = "SWITCH_REG2", + .enable_reg = RK817_LDO_EN3, + .enable_mask = 0x88, + .voltage_min1 = 3300000, + .voltage_max1 = 3300000, + .voltage_steps = 0, + }, +}; + +static struct rk817_regdef rk817_regdefs[] = { + { + .id = RK817_DCDC1, + .name = "DCDC_REG1", + .enable_reg = RK817_DCDC_EN, + .enable_mask = 0x11, + .voltage_reg = RK817_DCDC1_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 500000, + .voltage_max1 = 1487500, + .voltage_min2 = 1500000, + .voltage_max2 = 2400000, + .voltage_step1 = 12500, + .voltage_step2 = 100000, + .voltage_steps = 177, + }, + { + .id = RK817_DCDC2, + .name = "DCDC_REG2", + .enable_reg = RK817_DCDC_EN, + .enable_mask = 0x22, + .voltage_reg = RK817_DCDC2_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 500000, + .voltage_max1 = 1487500, + .voltage_min2 = 1500000, + .voltage_max2 = 2400000, + .voltage_step1 = 12500, + .voltage_step2 = 100000, + .voltage_steps = 177, + }, + { + .id = RK817_DCDC3, + .name = "DCDC_REG3", + .enable_reg = RK817_DCDC_EN, + .enable_mask = 0x44, + .voltage_reg = RK817_DCDC3_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 500000, + .voltage_max1 = 1487500, + .voltage_min2 = 1500000, + .voltage_max2 = 2400000, + .voltage_step1 = 12500, + .voltage_step2 = 100000, + .voltage_steps = 177, + }, + { + .id = RK817_DCDC4, + .name = "DCDC_REG4", + .enable_reg = RK817_DCDC_EN, + .enable_mask = 0x88, + .voltage_reg = RK817_DCDC4_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 500000, + .voltage_max1 = 1487500, + .voltage_min2 = 1500000, + .voltage_max2 = 3400000, + .voltage_step1 = 12500, + .voltage_step2 = 100000, + .voltage_steps = 195, + }, + { + .id = RK817_LDO1, + .name = "LDO_REG1", + .enable_reg = RK817_LDO_EN1, + .enable_mask = 0x11, + .voltage_reg = RK817_LDO1_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK817_LDO2, + .name = "LDO_REG2", + .enable_reg = RK817_LDO_EN1, + .enable_mask = 0x22, + .voltage_reg = RK817_LDO2_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK817_LDO3, + .name = "LDO_REG3", + .enable_reg = RK817_LDO_EN1, + .enable_mask = 0x44, + .voltage_reg = RK817_LDO3_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK817_LDO4, + .name = "LDO_REG4", + .enable_reg = RK817_LDO_EN1, + .enable_mask = 0x88, + .voltage_reg = RK817_LDO4_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK817_LDO5, + .name = "LDO_REG5", + .enable_reg = RK817_LDO_EN2, + .enable_mask = 0x11, + .voltage_reg = RK817_LDO5_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK817_LDO6, + .name = "LDO_REG6", + .enable_reg = RK817_LDO_EN2, + .enable_mask = 0x22, + .voltage_reg = RK817_LDO6_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK817_LDO7, + .name = "LDO_REG7", + .enable_reg = RK817_LDO_EN2, + .enable_mask = 0x44, + .voltage_reg = RK817_LDO7_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK817_LDO8, + .name = "LDO_REG8", + .enable_reg = RK817_LDO_EN2, + .enable_mask = 0x88, + .voltage_reg = RK817_LDO8_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK817_LDO9, + .name = "LDO_REG9", + .enable_reg = RK817_LDO_EN3, + .enable_mask = 0x11, + .voltage_reg = RK817_LDO9_ON_VSEL, + .voltage_mask = 0x7f, + .voltage_min1 = 600000, + .voltage_max1 = 3400000, + .voltage_step1 = 25000, + .voltage_steps = 112, + }, + { + .id = RK817_BOOST, + .name = "BOOST", + .enable_reg = RK817_LDO_EN3, + .enable_mask = 0x22, + .voltage_reg = RK817_BOOST_ON_VSEL, + .voltage_mask = 0x07, + .voltage_min1 = 4700000, + .voltage_max1 = 5400000, + .voltage_step1 = 100000, + .voltage_steps = 8, + }, + { + .id = RK817_OTG_SWITCH, + .name = "OTG_SWITCH", + .enable_reg = RK817_LDO_EN3, + .enable_mask = 0x44, + .voltage_steps = 0, + }, +}; + +static int +rk817_read(device_t dev, uint8_t reg, uint8_t *data, uint8_t size) +{ + + return (iicdev_readfrom(dev, reg, data, size, IIC_INTRWAIT)); +} + +static int +rk817_write(device_t dev, uint8_t reg, uint8_t data) +{ + + return (iicdev_writeto(dev, reg, &data, 1, IIC_INTRWAIT)); +} + +static void +rk817_regnode_reg_to_voltage(struct rk817_reg_sc *sc, uint8_t steps, int *uv) +{ + + if (sc->def->voltage_step2) { + int change; + + change = ((sc->def->voltage_min2 - sc->def->voltage_min1) / + sc->def->voltage_step1); + if (steps > change) { + if (steps < sc->def->voltage_steps) + *uv = sc->def->voltage_min2 + (steps - change) * + sc->def->voltage_step2; + else + *uv = sc->def->voltage_max2; + return; + } + } + if (steps < sc->def->voltage_steps) + *uv = sc->def->voltage_min1 + steps * sc->def->voltage_step1; + else + *uv = sc->def->voltage_max1; +} + +static int +rk817_regnode_voltage_to_reg(struct rk817_reg_sc *sc, int min_uvolt, + int max_uvolt, uint8_t *steps) +{ + uint8_t count; + int uvolt; + + uvolt = sc->def->voltage_min1; + for (count = 0; count < sc->def->voltage_steps && uvolt < min_uvolt; + count++) { + if (sc->def->voltage_step2) { + if (uvolt < sc->def->voltage_min2) + uvolt += sc->def->voltage_step1; + else + uvolt += sc->def->voltage_step2; + } + else + uvolt += sc->def->voltage_step1; + } + if (uvolt > max_uvolt) + return EINVAL; + *steps = count; + return (0); +} + +static int +rk817_regnode_set_voltage(struct regnode *regnode, int min_uvolt, int max_uvolt, + int *udelay) +{ + struct rk817_reg_sc *sc = regnode_get_softc(regnode); + uint8_t old, new; + int uvolt; + + if (!sc->def->voltage_steps) { + dprintf(sc, "Switch %s can not set voltage\n", sc->def->name); + return (ENXIO); + } + + dprintf(sc, "Setting %s to %d<->%d uvolts\n", + sc->def->name, min_uvolt, max_uvolt); + + rk817_read(sc->base_dev, sc->def->voltage_reg, &old, 1); + dprintf(sc, "Current %s %d setting\n", sc->def->name, old); + + if (rk817_regnode_voltage_to_reg(sc, min_uvolt, max_uvolt, &new) != 0) + return (ERANGE); + + rk817_write(sc->base_dev, sc->def->voltage_reg, + new | (old &= ~sc->def->voltage_mask)); + + rk817_read(sc->base_dev, sc->def->voltage_reg, &new, 1); + dprintf(sc, "Changed %s %d setting\n", sc->def->name, new); + + *udelay = 0; + + rk817_regnode_reg_to_voltage(sc, new & sc->def->voltage_mask, &uvolt); + dprintf(sc, "Regulator %s set to %d uvolt\n", sc->def->name, uvolt); + + return (0); +} + +static int +rk817_regnode_get_voltage(struct regnode *regnode, int *uvolt) +{ + struct rk817_reg_sc *sc = regnode_get_softc(regnode); + uint8_t val; + + if (sc->def->voltage_min1 == sc->def->voltage_max1) { + *uvolt = sc->def->voltage_min1; + return (0); + } + + if (!sc->def->voltage_steps) { + dprintf(sc, "Switch %s can not get voltage\n", sc->def->name); + return (ENXIO); + } + + rk817_read(sc->base_dev, sc->def->voltage_reg, &val, 1); + rk817_regnode_reg_to_voltage(sc, val & sc->def->voltage_mask, uvolt); + + dprintf(sc, "Regulator %s is at %d uvolt\n", sc->def->name, *uvolt); + + return (0); +} + +static int +rk817_regnode_status(struct regnode *regnode, int *status) +{ + struct rk817_reg_sc *sc = regnode_get_softc(regnode); + uint8_t val; + + *status = 0; + rk817_read(sc->base_dev, sc->def->enable_reg, &val, 1); + if (val & sc->def->enable_mask) + *status = REGULATOR_STATUS_ENABLED; + + return (0); +} + +static int +rk817_regnode_init(struct regnode *regnode) +{ + struct regnode_std_param *param = regnode_get_stdparam(regnode); + int retval, uvolt, udelay, status; + + if (!param->min_uvolt) + return (0); + + /* Check that the regulator is preset to the correct voltage */ + if ((retval = rk817_regnode_get_voltage(regnode, &uvolt))) + return (retval); + if (uvolt >= param->min_uvolt && uvolt <= param->max_uvolt) + return (0); + + /* if the regulator is enabled dont touch it */ + retval = rk817_regnode_status(regnode, &status); + if (retval || status == REGULATOR_STATUS_ENABLED) + return (retval); + + /* + * Set regulator at the correct voltage if it is not enabled. + * Do not enable it, this is will be done either by a + * consumer or by regnode_set_constraint if boot_on is true + */ + retval = rk817_regnode_set_voltage(regnode, param->min_uvolt, + param->max_uvolt, &udelay); + if (udelay) + DELAY(udelay); + + return (retval); +} + +static int +rk817_regnode_enable(struct regnode *regnode, bool enable, int *udelay) +{ + struct rk817_reg_sc *sc = regnode_get_softc(regnode); + uint8_t val; + + dprintf(sc, "%sabling regulator %s\n", + enable ? "En" : "Dis", sc->def->name); + rk817_read(sc->base_dev, sc->def->enable_reg, &val, 1); + if (enable) + val |= sc->def->enable_mask; + else + val &= ~sc->def->enable_mask; + rk817_write(sc->base_dev, sc->def->enable_reg, val); + + *udelay = 0; + + return (0); +} + +static regnode_method_t rk817_regnode_methods[] = { + /* Regulator interface */ + REGNODEMETHOD(regnode_init, rk817_regnode_init), + REGNODEMETHOD(regnode_enable, rk817_regnode_enable), + REGNODEMETHOD(regnode_status, rk817_regnode_status), + REGNODEMETHOD(regnode_set_voltage, rk817_regnode_set_voltage), + REGNODEMETHOD(regnode_get_voltage, rk817_regnode_get_voltage), + REGNODEMETHOD(regnode_check_voltage, regnode_method_check_voltage), + REGNODEMETHOD_END +}; +DEFINE_CLASS_1(rk817_regnode, rk817_regnode_class, rk817_regnode_methods, + sizeof(struct rk817_reg_sc), regnode_class); + +static struct rk817_reg_sc * +rk817_reg_attach(device_t dev, phandle_t node, struct rk817_regdef *def) +{ + struct rk817_reg_sc *reg_sc; + struct regnode_init_def initdef; + struct regnode *regnode; + + memset(&initdef, 0, sizeof(initdef)); + if (regulator_parse_ofw_stdparam(dev, node, &initdef) != 0) { + device_printf(dev, "cannot create regulator\n"); + return (NULL); + } + if (initdef.std_param.min_uvolt == 0) + initdef.std_param.min_uvolt = def->voltage_min1; + if (initdef.std_param.max_uvolt == 0) + initdef.std_param.max_uvolt = def->voltage_max1; + initdef.id = def->id; + initdef.ofw_node = node; + + regnode = regnode_create(dev, &rk817_regnode_class, &initdef); + if (regnode == NULL) { + device_printf(dev, "cannot create regulator\n"); + return (NULL); + } + + reg_sc = regnode_get_softc(regnode); + reg_sc->regnode = regnode; + reg_sc->base_dev = dev; + reg_sc->def = def; + reg_sc->xref = OF_xref_from_node(node); + reg_sc->param = regnode_get_stdparam(regnode); + regnode_register(regnode); + return (reg_sc); +} + +static void +rk817_shutdown(void *devp, int howto) +{ + device_t dev = (device_t)devp; + + if (howto & RB_POWEROFF) { + if (bootverbose) + device_printf(dev, "Shutdown PMIC\n"); + rk817_write(dev, RK817_SYS_CFG3, 0x01); + return; + } + if (howto & RB_POWERCYCLE) { + if (bootverbose) + device_printf(dev, "Powercycle PMIC\n"); + rk817_write(dev, RK817_SYS_CFG3, 0x04); + return; + } + if (bootverbose) + device_printf(dev, "Shutdown called howto=0x%x unhandled\n", + howto); +} + +static int +rk817_rtc_gettime(device_t dev, struct timespec *ts) +{ + struct bcd_clocktime ct; + uint8_t reg, val; + + /* read ctrl reg, set 24h and read from shadow regs mode */ + reg = RK817_RTC_CTRL_REG; + rk817_read(dev, reg, &val, 1); + val &= ~((1<<3) | (1<<6)); + val |= (1<<7); + rk817_write(dev, reg, val); + + /* latch clock regs to shadow regs */ + rk817_write(dev, reg, val | (1<<6)); + + /* wait one 32khz cycle for clock shadow registers to latch */ + DELAY(1000000 / 32000); + + /* release latch */ + rk817_write(dev, reg, val); + + /* read registers */ + rk817_read(dev, RK817_SECONDS_REG, &ct.sec, 1); + rk817_read(dev, RK817_MINUTES_REG, &ct.min, 1); + rk817_read(dev, RK817_HOURS_REG, &ct.hour, 1); + rk817_read(dev, RK817_DAYS_REG, &ct.day, 1); + rk817_read(dev, RK817_MONTHS_REG, &ct.mon, 1); + rk817_read(dev, RK817_WEEKS_REG, &ct.dow, 1); + rk817_read(dev, RK817_YEARS_REG, &val, 1); + + if (val < 0x19) /* if year "out of range" bail */ + return (EINVAL); + + ct.year = val + 0x2000; /* valid for 2000-2099 only */ + if (ct.dow == 7) /* our sunday is 0 not 7 */ + ct.dow = 0; + ct.nsec = 0; /* RTC resolution is 1 sec */ + + if (bootverbose) + device_printf(dev, "gettime %04x-%02x-%02x %02x:%02x:%02x\n", + ct.year, ct.mon, ct.day, ct.hour, ct.min, ct.sec); + + return (clock_bcd_to_ts(&ct, ts, false)); +} + +static int +rk817_rtc_settime(device_t dev, struct timespec *ts) +{ + struct bcd_clocktime ct; + uint8_t reg, val; + + reg = RK817_RTC_CTRL_REG; + clock_ts_to_bcd(ts, &ct, false); + + if (bootverbose) + device_printf(dev, "settime %04x-%02x-%02x %02x:%02x:%02x\n", + ct.year, ct.mon, ct.day, ct.hour, ct.min, ct.sec); + + /* valid for 2000-2099 only */ + if ((ct.year & 0xff00) != 0x2000) { + device_printf(dev, "year out of range\n"); + return (EINVAL); + } + ct.year &= 0x00ff; + + /* read ctrl reg and set 24h mode as default */ + rk817_read(dev, reg, &val, 1); + val &= ~(1<<3); + + /* stop RTC clock */ + rk817_write(dev, reg, val | (1<<0)); + + /* update registers */ + rk817_write(dev, RK817_SECONDS_REG, ct.sec); + rk817_write(dev, RK817_MINUTES_REG, ct.min); + rk817_write(dev, RK817_HOURS_REG, ct.hour); + rk817_write(dev, RK817_DAYS_REG, ct.day); + rk817_write(dev, RK817_MONTHS_REG, ct.mon); + rk817_write(dev, RK817_WEEKS_REG, (ct.dow == 0) ? 7 : ct.dow); + rk817_write(dev, RK817_YEARS_REG, ct.year); + + /* start RTC clock */ + rk817_write(dev, reg, val & ~(1<<0)); + + return (0); +} + +static int +rk817_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { + case RK809: + device_set_desc(dev, "RockChip RK809 PMIC"); + break; + case RK817: + device_set_desc(dev, "RockChip RK817 PMIC"); + break; + default: + return (ENXIO); + } + + return (BUS_PROBE_DEFAULT); +} + +static int +rk817_attach(device_t dev) +{ + struct rk817_softc *sc = device_get_softc(dev); + struct rk817_reg_sc *reg; + struct rk817_regdef *regdefs; + struct reg_list *regp; + phandle_t rnode, child; + int i; + + sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + switch (sc->type) { + case RK809: + regdefs = rk809_regdefs; + sc->nregs = nitems(rk809_regdefs); + break; + case RK817: + regdefs = rk817_regdefs; + sc->nregs = nitems(rk817_regdefs); + break; + default: + device_printf(dev, "Unknown type %d\n", sc->type); + return (ENXIO); + } + + TAILQ_INIT(&sc->regs); + rnode = ofw_bus_find_child(ofw_bus_get_node(dev), "regulators"); + if (rnode > 0) { + for (i = 0; i < sc->nregs; i++) { + if (!(child=ofw_bus_find_child(rnode, regdefs[i].name))) + continue; + if (OF_hasprop(child, "regulator-name") != 1) + continue; + if (!(reg = rk817_reg_attach(dev, child, ®defs[i]))) + device_printf(dev, + "cannot attach regulator %s\n", + regdefs[i].name); + regp = malloc(sizeof(*regp), M_DEVBUF, M_WAITOK|M_ZERO); + regp->reg = reg; + TAILQ_INSERT_TAIL(&sc->regs, regp, next); + if (bootverbose) + device_printf(dev, "Regulator %s attached\n", + regdefs[i].name); + } + } + + /* Register this as a 1Hz clock */ + clock_register(dev, 1000000); + + /* Register shutdown method */ + EVENTHANDLER_REGISTER(shutdown_final, rk817_shutdown, dev, + SHUTDOWN_PRI_LAST - 100); + + return (0); +} + +static int +rk817_detach(device_t dev) +{ + + /* We cannot detach regulators */ + return (EBUSY); +} + +static int +rk817_map(device_t dev, phandle_t xref, int ncells, pcell_t *cells, intptr_t *id) +{ + struct rk817_softc *sc = device_get_softc(dev);; + struct reg_list *regp; + + TAILQ_FOREACH(regp, &sc->regs, next) { + if (regp->reg->xref == xref) { + *id = regp->reg->def->id; + return (0); + } + } + return (ERANGE); +} + +static device_method_t rk817_methods[] = { + DEVMETHOD(device_probe, rk817_probe), + DEVMETHOD(device_attach, rk817_attach), + DEVMETHOD(device_detach, rk817_detach), + + /* regdev interface */ + DEVMETHOD(regdev_map, rk817_map), + + /* Clock interface */ + DEVMETHOD(clock_gettime, rk817_rtc_gettime), + DEVMETHOD(clock_settime, rk817_rtc_settime), + + DEVMETHOD_END +}; + +static driver_t rk817_driver = { + "rk817_pmic", + rk817_methods, + sizeof(struct rk817_softc), +}; + +static devclass_t rk817_devclass; + +EARLY_DRIVER_MODULE(rk817, iicbus, rk817_driver, rk817_devclass, 0, 0, + BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); +MODULE_DEPEND(rk817, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); +MODULE_VERSION(rk817, 1); Index: sys/dev/iicbus/pmic/rockchip/rk817reg.h =================================================================== --- sys/dev/iicbus/pmic/rockchip/rk817reg.h +++ sys/dev/iicbus/pmic/rockchip/rk817reg.h @@ -0,0 +1,102 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBS + * + * Copyright (c) 2021, 2022 Soren Schmidt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + + +#ifndef _RK8XXREG_H_ +#define _RK8XXREG_H_ + +#define RK817_SECONDS_REG 0x00 +#define RK817_MINUTES_REG 0x01 +#define RK817_HOURS_REG 0x02 +#define RK817_DAYS_REG 0x03 +#define RK817_MONTHS_REG 0x04 +#define RK817_YEARS_REG 0x05 +#define RK817_WEEKS_REG 0x06 +#define RK817_RTC_CTRL_REG 0x0d +#define RK817_RTC_STATUS_REG 0x0e +#define RK817_RTC_INT_REG 0x0f +#define RK817_RTC_COMP_LSB_REG 0x10 +#define RK817_RTC_COMP_MSB_REG 0x11 + +#define RK817_DCDC_EN 0xb1 +#define RK817_LDO_EN1 0xb2 +#define RK817_LDO_EN2 0xb3 +#define RK817_LDO_EN3 0xb4 +#define RK817_DCDC1_ON_VSEL 0xbb +#define RK817_DCDC2_ON_VSEL 0xbe +#define RK817_DCDC3_ON_VSEL 0xc1 +#define RK817_DCDC4_ON_VSEL 0xc4 +#define RK817_LDO1_ON_VSEL 0xcc +#define RK817_LDO2_ON_VSEL 0xce +#define RK817_LDO3_ON_VSEL 0xd0 +#define RK817_LDO4_ON_VSEL 0xd2 +#define RK817_LDO5_ON_VSEL 0xd4 +#define RK817_LDO6_ON_VSEL 0xd6 +#define RK817_LDO7_ON_VSEL 0xd8 +#define RK817_LDO8_ON_VSEL 0xda +#define RK817_LDO9_ON_VSEL 0xdc +#define RK817_BOOST_ON_VSEL 0xde +#define RK817_SYS_CFG3 0xf4 + +enum rk809_regulator { + RK809_DCDC1 = 0, + RK809_DCDC2, + RK809_DCDC3, + RK809_DCDC4, + RK809_DCDC5, + RK809_LDO1, + RK809_LDO2, + RK809_LDO3, + RK809_LDO4, + RK809_LDO5, + RK809_LDO6, + RK809_LDO7, + RK809_LDO8, + RK809_LDO9, + RK809_SWITCH1, + RK809_SWITCH2, +}; + +enum rk817_regulator { + RK817_DCDC1 = 0, + RK817_DCDC2, + RK817_DCDC3, + RK817_DCDC4, + RK817_LDO1, + RK817_LDO2, + RK817_LDO3, + RK817_LDO4, + RK817_LDO5, + RK817_LDO6, + RK817_LDO7, + RK817_LDO8, + RK817_LDO9, + RK817_BOOST, + RK817_OTG_SWITCH, +}; +#endif /* _RK8XXREG_H_ */ Index: sys/dev/usb/controller/dwc3.h =================================================================== --- sys/dev/usb/controller/dwc3.h +++ sys/dev/usb/controller/dwc3.h @@ -49,6 +49,7 @@ #define DWC3_GUCTL1 0xc11c #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS (1 << 28) +#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK (1 << 26) #define DWC3_GSNPSID 0xc120 #define DWC3_GGPIO 0xc124 Index: sys/dev/usb/controller/dwc3.c =================================================================== --- sys/dev/usb/controller/dwc3.c +++ sys/dev/usb/controller/dwc3.c @@ -363,10 +363,6 @@ snps_dwc3_common_attach(device_t dev, bool is_fdt) { struct snps_dwc3_softc *sc; -#ifdef FDT - phandle_t node; - phy_t usb2_phy, usb3_phy; -#endif int error, rid; sc = device_get_softc(dev); @@ -390,22 +386,28 @@ #endif #ifdef FDT - if (!is_fdt) - goto skip_phys; + if (is_fdt) { + phy_t usb2_phy, usb3_phy; + phandle_t node; + uint32_t reg; - /* Get the phys */ - node = ofw_bus_get_node(dev); - - usb2_phy = usb3_phy = NULL; - error = phy_get_by_ofw_name(dev, node, "usb2-phy", &usb2_phy); - if (error == 0 && usb2_phy != NULL) - phy_enable(usb2_phy); - error = phy_get_by_ofw_name(dev, node, "usb3-phy", &usb3_phy); - if (error == 0 && usb3_phy != NULL) - phy_enable(usb3_phy); - - snps_dwc3_configure_phy(sc, node); -skip_phys: + node = ofw_bus_get_node(dev); + usb2_phy = usb3_phy = NULL; + error = phy_get_by_ofw_name(dev, node, "usb2-phy", &usb2_phy); + if (error == 0 && usb2_phy != NULL) + phy_enable(usb2_phy); + error = phy_get_by_ofw_name(dev, node, "usb3-phy", &usb3_phy); + if (error == 0 && usb3_phy != NULL) + phy_enable(usb3_phy); + else { + reg = DWC3_READ(sc, DWC3_GUCTL1); + if (bootverbose) + device_printf(dev, "Forcing USB2 clock only\n"); + reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; + DWC3_WRITE(sc, DWC3_GUCTL1, reg); + } + snps_dwc3_configure_phy(sc, node); + } #endif snps_dwc3_reset(sc);