Index: sys/contrib/device-tree/include/dt-bindings/clock/sun20i-d1-ccu.h =================================================================== --- /dev/null +++ sys/contrib/device-tree/include/dt-bindings/clock/sun20i-d1-ccu.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2020 huangzhenwei@allwinnertech.com + * Copyright (C) 2021 Samuel Holland + */ + +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ +#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ + +#define CLK_PLL_CPUX 0 +#define CLK_PLL_DDR0 1 +#define CLK_PLL_PERIPH0_4X 2 +#define CLK_PLL_PERIPH0_2X 3 +#define CLK_PLL_PERIPH0_800M 4 +#define CLK_PLL_PERIPH0 5 +#define CLK_PLL_PERIPH0_DIV3 6 +#define CLK_PLL_VIDEO0_4X 7 +#define CLK_PLL_VIDEO0_2X 8 +#define CLK_PLL_VIDEO0 9 +#define CLK_PLL_VIDEO1_4X 10 +#define CLK_PLL_VIDEO1_2X 11 +#define CLK_PLL_VIDEO1 12 +#define CLK_PLL_VE 13 +#define CLK_PLL_AUDIO0_4X 14 +#define CLK_PLL_AUDIO0_2X 15 +#define CLK_PLL_AUDIO0 16 +#define CLK_PLL_AUDIO1 17 +#define CLK_PLL_AUDIO1_DIV2 18 +#define CLK_PLL_AUDIO1_DIV5 19 +#define CLK_CPUX 20 +#define CLK_CPUX_AXI 21 +#define CLK_CPUX_APB 22 +#define CLK_PSI_AHB 23 +#define CLK_APB0 24 +#define CLK_APB1 25 +#define CLK_MBUS 26 +#define CLK_DE 27 +#define CLK_BUS_DE 28 +#define CLK_DI 29 +#define CLK_BUS_DI 30 +#define CLK_G2D 31 +#define CLK_BUS_G2D 32 +#define CLK_CE 33 +#define CLK_BUS_CE 34 +#define CLK_VE 35 +#define CLK_BUS_VE 36 +#define CLK_BUS_DMA 37 +#define CLK_BUS_MSGBOX0 38 +#define CLK_BUS_MSGBOX1 39 +#define CLK_BUS_MSGBOX2 40 +#define CLK_BUS_SPINLOCK 41 +#define CLK_BUS_HSTIMER 42 +#define CLK_AVS 43 +#define CLK_BUS_DBG 44 +#define CLK_BUS_PWM 45 +#define CLK_BUS_IOMMU 46 +#define CLK_DRAM 47 +#define CLK_MBUS_DMA 48 +#define CLK_MBUS_VE 49 +#define CLK_MBUS_CE 50 +#define CLK_MBUS_TVIN 51 +#define CLK_MBUS_CSI 52 +#define CLK_MBUS_G2D 53 +#define CLK_MBUS_RISCV 54 +#define CLK_BUS_DRAM 55 +#define CLK_MMC0 56 +#define CLK_MMC1 57 +#define CLK_MMC2 58 +#define CLK_BUS_MMC0 59 +#define CLK_BUS_MMC1 60 +#define CLK_BUS_MMC2 61 +#define CLK_BUS_UART0 62 +#define CLK_BUS_UART1 63 +#define CLK_BUS_UART2 64 +#define CLK_BUS_UART3 65 +#define CLK_BUS_UART4 66 +#define CLK_BUS_UART5 67 +#define CLK_BUS_I2C0 68 +#define CLK_BUS_I2C1 69 +#define CLK_BUS_I2C2 70 +#define CLK_BUS_I2C3 71 +#define CLK_SPI0 72 +#define CLK_SPI1 73 +#define CLK_BUS_SPI0 74 +#define CLK_BUS_SPI1 75 +#define CLK_EMAC_25M 76 +#define CLK_BUS_EMAC 77 +#define CLK_IR_TX 78 +#define CLK_BUS_IR_TX 79 +#define CLK_BUS_GPADC 80 +#define CLK_BUS_THS 81 +#define CLK_I2S0 82 +#define CLK_I2S1 83 +#define CLK_I2S2 84 +#define CLK_I2S2_ASRC 85 +#define CLK_BUS_I2S0 86 +#define CLK_BUS_I2S1 87 +#define CLK_BUS_I2S2 88 +#define CLK_SPDIF_TX 89 +#define CLK_SPDIF_RX 90 +#define CLK_BUS_SPDIF 91 +#define CLK_DMIC 92 +#define CLK_BUS_DMIC 93 +#define CLK_AUDIO_DAC 94 +#define CLK_AUDIO_ADC 95 +#define CLK_BUS_AUDIO 96 +#define CLK_USB_OHCI0 97 +#define CLK_USB_OHCI1 98 +#define CLK_BUS_OHCI0 99 +#define CLK_BUS_OHCI1 100 +#define CLK_BUS_EHCI0 101 +#define CLK_BUS_EHCI1 102 +#define CLK_BUS_OTG 103 +#define CLK_BUS_LRADC 104 +#define CLK_BUS_DPSS_TOP 105 +#define CLK_HDMI_24M 106 +#define CLK_HDMI_CEC_32K 107 +#define CLK_HDMI_CEC 108 +#define CLK_BUS_HDMI 109 +#define CLK_MIPI_DSI 110 +#define CLK_BUS_MIPI_DSI 111 +#define CLK_TCON_LCD0 112 +#define CLK_BUS_TCON_LCD0 113 +#define CLK_TCON_TV 114 +#define CLK_BUS_TCON_TV 115 +#define CLK_TVE 116 +#define CLK_BUS_TVE_TOP 117 +#define CLK_BUS_TVE 118 +#define CLK_TVD 119 +#define CLK_BUS_TVD_TOP 120 +#define CLK_BUS_TVD 121 +#define CLK_LEDC 122 +#define CLK_BUS_LEDC 123 +#define CLK_CSI_TOP 124 +#define CLK_CSI_MCLK 125 +#define CLK_BUS_CSI 126 +#define CLK_TPADC 127 +#define CLK_BUS_TPADC 128 +#define CLK_BUS_TZMA 129 +#define CLK_DSP 130 +#define CLK_BUS_DSP_CFG 131 +#define CLK_RISCV 132 +#define CLK_RISCV_AXI 133 +#define CLK_BUS_RISCV_CFG 134 +#define CLK_FANOUT_24M 135 +#define CLK_FANOUT_12M 136 +#define CLK_FANOUT_16M 137 +#define CLK_FANOUT_25M 138 +#define CLK_FANOUT_32K 139 +#define CLK_FANOUT_27M 140 +#define CLK_FANOUT_PCLK 141 +#define CLK_FANOUT0 142 +#define CLK_FANOUT1 143 +#define CLK_FANOUT2 144 + +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ Index: sys/contrib/device-tree/include/dt-bindings/clock/sun20i-d1-r-ccu.h =================================================================== --- /dev/null +++ sys/contrib/device-tree/include/dt-bindings/clock/sun20i-d1-r-ccu.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2021 Samuel Holland + */ + +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ + +#define CLK_R_AHB 0 + +#define CLK_BUS_R_TIMER 2 +#define CLK_BUS_R_TWD 3 +#define CLK_BUS_R_PPU 4 +#define CLK_R_IR_RX 5 +#define CLK_BUS_R_IR_RX 6 +#define CLK_BUS_R_RTC 7 +#define CLK_BUS_R_CPUCFG 8 + +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */ Index: sys/contrib/device-tree/include/dt-bindings/clock/sun6i-rtc.h =================================================================== --- /dev/null +++ sys/contrib/device-tree/include/dt-bindings/clock/sun6i-rtc.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ + +#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ +#define _DT_BINDINGS_CLK_SUN6I_RTC_H_ + +#define CLK_OSC32K 0 +#define CLK_OSC32K_FANOUT 1 +#define CLK_IOSC 2 + +#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */ Index: sys/contrib/device-tree/include/dt-bindings/mailbox/sun20i-d1-msgbox.h =================================================================== --- /dev/null +++ sys/contrib/device-tree/include/dt-bindings/mailbox/sun20i-d1-msgbox.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for binding nvidia,tegra186-hsp. + */ + +#ifndef _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_ +#define _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_ + +/* First cell: channel (transmitting user) */ +#define MBOX_USER_CPUX 0 +#define MBOX_USER_DSP 1 +#define MBOX_USER_RISCV 2 + +/* Second cell: direction (RX if phandle references local mailbox, else TX) */ +#define MBOX_RX 0 +#define MBOX_TX 1 + +#endif /* _DT_BINDINGS_MAILBOX_SUN20I_D1_MSGBOX_H_ */ Index: sys/contrib/device-tree/include/dt-bindings/reset/sun20i-d1-ccu.h =================================================================== --- /dev/null +++ sys/contrib/device-tree/include/dt-bindings/reset/sun20i-d1-ccu.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2020 huangzhenwei@allwinnertech.com + * Copyright (C) 2021 Samuel Holland + */ + +#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ +#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ + +#define RST_MBUS 0 +#define RST_BUS_DE 1 +#define RST_BUS_DI 2 +#define RST_BUS_G2D 3 +#define RST_BUS_CE 4 +#define RST_BUS_VE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MSGBOX0 7 +#define RST_BUS_MSGBOX1 8 +#define RST_BUS_MSGBOX2 9 +#define RST_BUS_SPINLOCK 10 +#define RST_BUS_HSTIMER 11 +#define RST_BUS_DBG 12 +#define RST_BUS_PWM 13 +#define RST_BUS_DRAM 14 +#define RST_BUS_MMC0 15 +#define RST_BUS_MMC1 16 +#define RST_BUS_MMC2 17 +#define RST_BUS_UART0 18 +#define RST_BUS_UART1 19 +#define RST_BUS_UART2 20 +#define RST_BUS_UART3 21 +#define RST_BUS_UART4 22 +#define RST_BUS_UART5 23 +#define RST_BUS_I2C0 24 +#define RST_BUS_I2C1 25 +#define RST_BUS_I2C2 26 +#define RST_BUS_I2C3 27 +#define RST_BUS_SPI0 28 +#define RST_BUS_SPI1 29 +#define RST_BUS_EMAC 30 +#define RST_BUS_IR_TX 31 +#define RST_BUS_GPADC 32 +#define RST_BUS_THS 33 +#define RST_BUS_I2S0 34 +#define RST_BUS_I2S1 35 +#define RST_BUS_I2S2 36 +#define RST_BUS_SPDIF 37 +#define RST_BUS_DMIC 38 +#define RST_BUS_AUDIO 39 +#define RST_USB_PHY0 40 +#define RST_USB_PHY1 41 +#define RST_BUS_OHCI0 42 +#define RST_BUS_OHCI1 43 +#define RST_BUS_EHCI0 44 +#define RST_BUS_EHCI1 45 +#define RST_BUS_OTG 46 +#define RST_BUS_LRADC 47 +#define RST_BUS_DPSS_TOP 48 +#define RST_BUS_HDMI_SUB 49 +#define RST_BUS_HDMI_MAIN 50 +#define RST_BUS_MIPI_DSI 51 +#define RST_BUS_TCON_LCD0 52 +#define RST_BUS_TCON_TV 53 +#define RST_BUS_LVDS0 54 +#define RST_BUS_TVE 55 +#define RST_BUS_TVE_TOP 56 +#define RST_BUS_TVD 57 +#define RST_BUS_TVD_TOP 58 +#define RST_BUS_LEDC 59 +#define RST_BUS_CSI 60 +#define RST_BUS_TPADC 61 +#define RST_DSP 62 +#define RST_BUS_DSP_CFG 63 +#define RST_BUS_DSP_DBG 64 +#define RST_BUS_RISCV_CFG 65 + +#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */ Index: sys/contrib/device-tree/include/dt-bindings/reset/sun20i-d1-r-ccu.h =================================================================== --- /dev/null +++ sys/contrib/device-tree/include/dt-bindings/reset/sun20i-d1-r-ccu.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2021 Samuel Holland + */ + +#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ + +#define RST_BUS_R_TIMER 0 +#define RST_BUS_R_TWD 1 +#define RST_BUS_R_PPU 2 +#define RST_BUS_R_IR_RX 3 +#define RST_BUS_R_RTC 4 +#define RST_BUS_R_CPUCFG 5 + +#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */ Index: sys/contrib/device-tree/src/riscv/allwinner/sun20i-d1-lichee-rv-dock.dts =================================================================== --- /dev/null +++ sys/contrib/device-tree/src/riscv/allwinner/sun20i-d1-lichee-rv-dock.dts @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Jisheng Zhang +// Copyright (C) 2022 Samuel Holland + +#include "sun20i-d1-lichee-rv.dts" + +#include + +/ { + model = "Sipeed Lichee RV Dock"; + compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv", + "allwinner,sun20i-d1"; + + aliases { + mmc1 = &mmc1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dmic-card { + compatible = "simple-audio-card"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + format = "pdm"; + frame-master = <&link0_cpu>; + bitclock-master = <&link0_cpu>; + + link0_cpu: cpu { + sound-dai = <&dmic>; + }; + + link0_codec: codec { + sound-dai = <&dmic_codec>; + }; + }; + }; + + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <2>; + #sound-dai-cells = <0>; + }; + + hdmi_connector: connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + // FIXME: remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&codec { + allwinner,routing = "Internal Speaker", "HPOUTL", + "Internal Speaker", "HPOUTR", + "LINEINL", "HPOUTL", + "LINEINR", "HPOUTR", + "MICIN3", "Internal Microphone", + "Internal Microphone", "HBIAS"; + allwinner,widgets = "Microphone", "Internal Microphone", + "Speaker", "Internal Speaker"; + status = "okay"; +}; + +&dmic { + pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gpio { + dmic_pb11_d0_pin: dmic-pb11-d0-pin { + pins = "PB11"; + function = "dmic"; + }; + + dmic_pe17_clk_pin: dmic-pe17-clk-pin { + pins = "PE17"; + function = "dmic"; + }; + + ledc_pc0_pin: ledc-pc0-pin { + pins = "PC0"; + function = "ledc"; + }; +}; + +&ledc { + pinctrl-0 = <&ledc_pc0_pin>; + pinctrl-names = "default"; + status = "okay"; + + led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_STATUS; + }; +}; + +&lradc { + wakeup-source; + status = "okay"; + + button-220 { + label = "OK"; + linux,code = ; + channel = <0>; + voltage = <220000>; + }; +}; + +&mmc1 { + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + vmmc-supply = <®_vcc_3v3>; + vqmmc-supply = <®_vcc_3v3>; + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc>; +}; Index: sys/contrib/device-tree/src/riscv/allwinner/sun20i-d1-lichee-rv.dts =================================================================== --- /dev/null +++ sys/contrib/device-tree/src/riscv/allwinner/sun20i-d1-lichee-rv.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Jisheng Zhang +// Copyright (C) 2022 Samuel Holland + +/dts-v1/; + +#include "sun20i-d1.dtsi" + +#include +#include + +/ { + model = "Sipeed Lichee RV"; + compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1"; + + aliases { + mmc0 = &mmc0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */ + }; + }; + + reg_vcc: vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc>; + }; + + reg_vdd_cpu: vdd-cpu { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <®_vcc>; + }; +}; + +&codec { + avcc-supply = <®_aldo>; + hpvcc-supply = <®_hpldo>; + vdd33-supply = <®_vcc_3v3>; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpu>; +}; + +&ehci0 { + status = "okay"; +}; + +&gpio { + vcc-pb-supply = <®_vcc_3v3>; + vcc-pc-supply = <®_vcc_3v3>; + vcc-pd-supply = <®_vcc_3v3>; + vcc-pe-supply = <®_vcc_3v3>; + vcc-pf-supply = <®_vcc_3v3>; + vcc-pg-supply = <®_vcc_3v3>; +}; + +&lradc { + vref-supply = <®_aldo>; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc_3v3>; + vqmmc-supply = <®_vcc_3v3>; + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +®_aldo { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vdd33-supply = <®_vcc_3v3>; +}; + +®_hpldo { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + hpldoin-supply = <®_vcc_3v3>; +}; + +®_ldoa { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + ldo-in-supply = <®_vcc_3v3>; +}; + +&spi0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ths { + vref-supply = <®_aldo>; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb8_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_vcc>; + usb0_vbus_det-gpios = <&gpio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + status = "okay"; +}; Index: sys/contrib/device-tree/src/riscv/allwinner/sun20i-d1-nezha.dts =================================================================== --- /dev/null +++ sys/contrib/device-tree/src/riscv/allwinner/sun20i-d1-nezha.dts @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021 Samuel Holland + +/dts-v1/; + +#include "sun20i-d1.dtsi" + +#include +#include +#include +#include + +/ { + model = "Allwinner D1 NeZha"; + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1"; + + aliases { + ethernet0 = &emac; + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &mmc2; + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi_connector: connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + // FIXME: remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_usbvbus: usbvbus { + compatible = "regulator-fixed"; + regulator-name = "usbvbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ + enable-active-high; + vin-supply = <®_vcc>; + }; + + reg_vcc: vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc>; + }; + + reg_vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm 0 50000 0>; + pwm-supply = <®_vcc>; + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1160000>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&codec { + allwinner,routing = "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "LINEINL", "HPOUTL", + "LINEINR", "HPOUTR", + "MICIN3", "Headset Microphone", + "Headset Microphone", "HBIAS"; + allwinner,widgets = "Microphone", "Headset Microphone", + "Headphone", "Headphone Jack"; + avcc-supply = <®_aldo>; + hpvcc-supply = <®_hpldo>; + vdd33-supply = <®_vcc_3v3>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpu>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-0 = <&rgmii_pe_pins>; + pinctrl-names = "default"; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <®_vcc_3v3>; + status = "okay"; +}; + +&gpio { + vcc-pa-supply = <®_vcc_3v3>; + vcc-pb-supply = <®_vcc_3v3>; + vcc-pc-supply = <®_vcc_3v3>; + vcc-pd-supply = <®_vcc_3v3>; + vcc-pe-supply = <®_vcc_3v3>; + vcc-pf-supply = <®_vcc_3v3>; + vcc-pg-supply = <®_vcc_3v3>; + + i2s2_pb_pins: i2s2-pb-pins { + pins = "PB5", "PB6", "PB7"; + function = "i2s2"; + }; + + i2s2_pb3_din_pin: i2s2-pb3-din-pin { + pins = "PB3"; + function = "i2s2_din"; + }; + + i2s2_pb4_dout_pin: i2s2-pb4-dout-pin { + pins = "PB4"; + function = "i2s2_dout"; + }; + + ledc_pc0_pin: ledc-pc0-pin { + pins = "PC0"; + function = "ledc"; + }; + + pwm0_pd16_pin: pwm0-pd16-pin { + pins = "PD16"; + function = "pwm"; + }; + + pwm2_pd18_pin: pwm2-pd18-pin { + pins = "PD18"; + function = "pwm"; + }; + + pwm7_pd22_pin: pwm7-pd22-pin { + pins = "PD22"; + function = "pwm"; + }; + + spdif_pd22_pin: spdif-pd22-pin { + pins = "PD22"; + function = "spdif"; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pb10_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pb0_pins>; + pinctrl-names = "default"; + status = "okay"; + + pcf8574a: gpio@38 { + compatible = "nxp,pcf8574a"; + #address-cells = <0>; + reg = <0x38>; + gpio-controller; + #gpio-cells = <2>; + interrupts-extended = <&gpio 1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */ + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&i2s2 { + pinctrl-0 = <&i2s2_pb_pins>, <&i2s2_pb3_din_pin>, <&i2s2_pb4_dout_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ledc { + pinctrl-0 = <&ledc_pc0_pin>; + pinctrl-names = "default"; + status = "okay"; + + led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; +}; + +&lradc { + vref-supply = <®_aldo>; + wakeup-source; + status = "okay"; + + button-160 { + label = "OK"; + linux,code = ; + channel = <0>; + voltage = <160000>; + }; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&gpio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + disable-wp; + vmmc-supply = <®_vcc_3v3>; + vqmmc-supply = <®_vcc_3v3>; + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + vmmc-supply = <®_vcc_3v3>; + vqmmc-supply = <®_vcc_3v3>; + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + status = "okay"; + + xr829: wifi@1 { + reg = <1>; + host-wake-gpios = <&gpio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pwm { + pinctrl-0 = <&pwm0_pd16_pin>, <&pwm2_pd18_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +®_aldo { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vdd33-supply = <®_vcc_3v3>; +}; + +®_hpldo { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + hpldoin-supply = <®_vcc_3v3>; +}; + +®_ldoa { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + ldo-in-supply = <®_vcc_3v3>; +}; + +&spdif { + pinctrl-0 = <&spdif_pd22_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot0"; + reg = <0x00000000 0x00100000>; + }; + + partition@100000 { + label = "uboot"; + reg = <0x00100000 0x00300000>; + }; + + partition@400000 { + label = "secure_storage"; + reg = <0x00400000 0x00100000>; + }; + + partition@500000 { + label = "sys"; + reg = <0x00500000 0x0fb00000>; + }; + }; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pd_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ths { + vref-supply = <®_aldo>; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb8_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "xradio,xr829-bt"; + device-wakeup-gpios = <&gpio 6 16 GPIO_ACTIVE_LOW>; /* PG16 */ + interrupts-extended = <&gpio 6 17 IRQ_TYPE_LEVEL_LOW>; /* PG17 */ + interrupt-names = "wakeup"; + reset-gpios = <&gpio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + }; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&gpio 3 21 GPIO_ACTIVE_LOW>; /* PD21 */ + usb0_vbus_det-gpios = <&gpio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + usb0_vbus-supply = <®_usbvbus>; + usb1_vbus-supply = <®_vcc>; + status = "okay"; +}; Index: sys/contrib/device-tree/src/riscv/allwinner/sun20i-d1.dtsi =================================================================== --- /dev/null +++ sys/contrib/device-tree/src/riscv/allwinner/sun20i-d1.dtsi @@ -0,0 +1,1162 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021 Samuel Holland + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + // FIXME: no riscv architecture support for cpufreq + cpu_opp_table: cpu-opp-table { + compatible = "allwinner,sun20i-d1-operating-points", + "allwinner,sun50i-h6-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + + opp-1080000000 { + // FIXME: this is probably wrong now. + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1008000000>; + + // FIXME: derive a real voltage range. + opp-microvolt-speed0 = <1100000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <24000000>; + + cpu0: cpu@0 { + // FIXME: is this the right compatible? + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_RISCV>; + clock-frequency = <24000000>; + #cooling-cells = <2>; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + operating-points-v2 = <&cpu_opp_table>; + riscv,isa = "rv64imafdc"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #address-cells = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + // FIXME: depends on what T-HEAD tries to upstream. + pmu { + compatible = "thead,c900-pmu"; + }; + + thermal-zones { + cpu-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&ths 0>; + + trips { + cpu_target: cpu-target { + hysteresis = <3000>; + temperature = <85000>; + type = "passive"; + }; + + cpu-crit { + hysteresis = <0>; + temperature = <110000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + // TODO: write a binding and driver. + dsp: dsp@1700000 { + compatible = "allwinner,sun20i-d1-dsp"; + reg = <0x1700000 0x400>; + reg-names = "cfg"; + clocks = <&ccu CLK_BUS_DSP_CFG>, + <&ccu CLK_DSP>; + clock-names = "cfg", "dsp"; + resets = <&ccu RST_BUS_DSP_CFG>, + <&ccu RST_BUS_DSP_DBG>, + <&ccu RST_DSP>; + allwinner,sram = <&dsp_sram 1>; + interrupts = <136 IRQ_TYPE_LEVEL_HIGH>, + <137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dee", "pfe"; + // FIXME: this will be different for R528 (CPUX). + mboxes = <&riscv_msgbox MBOX_USER_DSP MBOX_RX>, + <&dsp_msgbox MBOX_USER_RISCV MBOX_TX>; + mbox-names = "rx", "tx"; + }; + + dsp_wdt: watchdog@1700400 { + compatible = "allwinner,sun20i-d1-wdt"; + reg = <0x1700400 0x20>; + clocks = <&osc24M>; + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>; + status = "reserved"; + }; + + // TODO: write a binding and driver. + dsp_msgbox: mailbox@1701000 { + compatible = "allwinner,sun20i-d1-msgbox"; + reg = <0x1701000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX1>; + resets = <&ccu RST_BUS_MSGBOX1>; + interrupts = <139 IRQ_TYPE_LEVEL_HIGH>, + <140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + #mbox-cells = <2>; + }; + + ve: video-codec@1c0e000 { + compatible = "allwinner,sun20i-d1-video-engine"; + reg = <0x1c0e000 0x2000>; + clocks = <&ccu CLK_BUS_VE>, + <&ccu CLK_VE>, + <&ccu CLK_MBUS_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + allwinner,sram = <&ve_sram 1>; + interconnects = <&mbus 4>; + interconnect-names = "dma-mem"; + interrupts = <82 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&iommu 0>; + }; + + gpio: pinctrl@2000000 { + compatible = "allwinner,sun20i-d1-pinctrl"; + #address-cells = <0>; + reg = <0x2000000 0x800>; + clocks = <&ccu CLK_APB0>, + <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>, + <87 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <91 IRQ_TYPE_LEVEL_HIGH>, + <93 IRQ_TYPE_LEVEL_HIGH>, + <95 IRQ_TYPE_LEVEL_HIGH>; + // FIXME: not in binding, should we add these? + interrupt-names = "pb", "pc", "pd", "pe", "pf", "pg"; + interrupt-controller; + #interrupt-cells = <3>; + + /omit-if-no-ref/ + i2c0_pb10_pins: i2c0-pb10-pins { + pins = "PB10", "PB11"; + function = "i2c0"; + }; + + /omit-if-no-ref/ + i2c2_pb0_pins: i2c2-pb0-pins { + pins = "PB0", "PB1"; + function = "i2c2"; + }; + + /omit-if-no-ref/ + i2c3_pb6_pins: i2c3-pb6-pins { + pins = "PB6", "PB7"; + function = "i2c3"; + }; + + /omit-if-no-ref/ + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; + function = "mmc1"; + }; + + /omit-if-no-ref/ + mmc2_pins: mmc2-pins { + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; + function = "mmc2"; + }; + + /omit-if-no-ref/ + rgmii_pe_pins: rgmii-pe-pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9", + "PE11", "PE12", "PE13", "PE14", "PE15"; + function = "emac"; + }; + + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pb_pins: spi1-pb-pins { + pins = "PB0", "PB8", "PB9", "PB10", "PB11", "PB12"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_pd_pins: spi1-pd-pins { + pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15"; + function = "spi1"; + }; + + /omit-if-no-ref/ + uart0_pb8_pins: uart0-pb8-pins { + pins = "PB8", "PB9"; + function = "uart0"; + }; + + /omit-if-no-ref/ + uart1_pg6_pins: uart1-pg6-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + /omit-if-no-ref/ + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; + }; + + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x2000c00 0x400>; + clocks = <&ccu CLK_BUS_PWM>, <&osc24M>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_PWM>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ccu: clock-controller@2001000 { + compatible = "allwinner,sun20i-d1-ccu"; + reg = <0x2001000 0x1000>; + clocks = <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + // TODO: write a binding and driver. + ir_tx: irled@2003000 { + compatible = "allwinner,sun20i-d1-ir-tx"; + reg = <0x2003000 0x400>; + clocks = <&ccu CLK_BUS_IR_TX>, + <&osc24M>, + <&ccu CLK_IR_TX>; + clock-names = "bus", "pclk", "mclk"; + resets = <&ccu RST_BUS_IR_TX>; + dmas = <&dma 13>; + dma-names = "tx"; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ledc: led-controller@2008000 { + compatible = "allwinner,sun20i-d1-ledc", + "allwinner,sun50i-r329-ledc"; + reg = <0x2008000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_LEDC>; + dmas = <&dma 42>; + dma-names = "tx"; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a binding and driver. + gpadc: adc@2009000 { + compatible = "allwinner,sun20i-d1-gpadc"; + reg = <0x2009000 0x400>; + clocks = <&ccu CLK_BUS_GPADC>; + resets = <&ccu RST_BUS_GPADC>; + dmas = <&dma 12>; + dma-names = "rx"; + interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ths: temperature-sensor@2009400 { + compatible = "allwinner,sun20i-d1-ths"; + reg = <0x2009400 0x400>; + clocks = <&ccu CLK_BUS_THS>, <&osc24M>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_THS>; + interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; + nvmem-cells = <&ths_calib>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + + lradc: keys@2009800 { + compatible = "allwinner,sun20i-d1-lradc", + "allwinner,sun50i-r329-lradc"; + reg = <0x2009800 0x400>; + clocks = <&ccu CLK_BUS_LRADC>; + resets = <&ccu RST_BUS_LRADC>; + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a binding and driver. + tpadc: touchscreen@2009c00 { + compatible = "allwinner,sun20i-d1-ts"; + reg = <0x2009c00 0x400>; + clocks = <&ccu CLK_BUS_TPADC>, <&ccu CLK_TPADC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_TPADC>; + dmas = <&dma 13>; + dma-names = "rx"; + interrupts = <78 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // FIXME: this driver probably needs updates. + iommu: iommu@2010000 { + compatible = "allwinner,sun20i-d1-iommu"; + reg = <0x2010000 0x10000>; + clocks = <&ccu CLK_BUS_IOMMU>; + interrupts = <80 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + }; + + codec: audio-codec@2030000 { + compatible = "allwinner,sun20i-d1-audio-codec"; + reg = <0x2030000 0x1000>; + clocks = <&ccu CLK_BUS_AUDIO>, + <&ccu CLK_AUDIO_ADC>, + <&ccu CLK_AUDIO_DAC>, + <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "bus", "adc", "dac", "hosc", "losc"; + resets = <&ccu RST_BUS_AUDIO>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + + regulators { + reg_aldo: aldo { + regulator-name = "aldo"; + }; + + reg_hpldo: hpldo { + regulator-name = "hpldo"; + }; + }; + + }; + + // TODO: try the posted driver. + dmic: dmic@2031000 { + compatible = "allwinner,sun20i-d1-dmic"; + reg = <0x2031000 0x400>; + clocks = <&ccu CLK_BUS_DMIC>, + <&ccu CLK_DMIC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_DMIC>; + dmas = <&dma 8>; + dma-names = "rx"; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s0: i2s@2032000 { + compatible = "allwinner,sun20i-d1-i2s"; + reg = <0x2032000 0x1000>; + clocks = <&ccu CLK_BUS_I2S0>, + <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S0>; + dmas = <&dma 3>, <&dma 3>; + dma-names = "rx", "tx"; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1: i2s@2033000 { + compatible = "allwinner,sun20i-d1-i2s"; + reg = <0x2033000 0x1000>; + clocks = <&ccu CLK_BUS_I2S1>, + <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S1>; + dmas = <&dma 4>, <&dma 4>; + dma-names = "rx", "tx"; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + // TODO: how to integrate ASRC? same or separate node? + i2s2: i2s@2034000 { + compatible = "allwinner,sun20i-d1-i2s"; + reg = <0x2034000 0x1000>; + clocks = <&ccu CLK_BUS_I2S2>, + <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S2>; + dmas = <&dma 5>, <&dma 5>; + dma-names = "rx", "tx"; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + // TODO: add receive functionality + spdif: spdif@2036000 { + compatible = "allwinner,sun20i-d1-spdif"; + reg = <0x2036000 0x400>; + clocks = <&ccu CLK_BUS_SPDIF>, + <&ccu CLK_SPDIF_RX>, + <&ccu CLK_SPDIF_TX>; + clock-names = "apb", "rx", "tx"; + resets = <&ccu RST_BUS_SPDIF>; + dmas = <&dma 2>, <&dma 2>; + dma-names = "rx", "tx"; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + timer: timer@2050000 { + compatible = "allwinner,sun20i-d1-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x2050000 0xa0>; + clocks = <&osc24M>; + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>, + <76 IRQ_TYPE_LEVEL_HIGH>; + }; + + wdt: watchdog@20500a0 { + compatible = "allwinner,sun20i-d1-wdt-reset", + "allwinner,sun20i-d1-wdt"; + reg = <0x20500a0 0x20>; + clocks = <&osc24M>; + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>; + status = "reserved"; + }; + + // TODO: write a driver. + uart0: serial@2500000 { + compatible = "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2500000 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + dmas = <&dma 14>, <&dma 14>; + dma-names = "rx", "tx"; + fifo-size = <64>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a driver, add IDMA? + uart1: serial@2500400 { + compatible = "allwinner,sun20i-d1-uart1", + "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2500400 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + fifo-size = <256>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a driver. + uart2: serial@2500800 { + compatible = "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2500800 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + dmas = <&dma 16>, <&dma 16>; + dma-names = "rx", "tx"; + fifo-size = <256>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a driver. + uart3: serial@2500c00 { + compatible = "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2500c00 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + dmas = <&dma 17>, <&dma 17>; + dma-names = "rx", "tx"; + fifo-size = <256>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a driver. + uart4: serial@2501000 { + compatible = "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2501000 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + dmas = <&dma 18>, <&dma 18>; + dma-names = "rx", "tx"; + fifo-size = <256>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + // TODO: write a driver. + uart5: serial@2501400 { + compatible = "allwinner,sun20i-d1-uart", + "snps,dw-apb-uart"; + reg = <0x2501400 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + dmas = <&dma 19>, <&dma 19>; + dma-names = "rx", "tx"; + fifo-size = <256>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c0: i2c@2502000 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + dmas = <&dma 43>, <&dma 43>; + dma-names = "rx", "tx"; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c1: i2c@2502400 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + dmas = <&dma 44>, <&dma 44>; + dma-names = "rx", "tx"; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c2: i2c@2502800 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + dmas = <&dma 45>, <&dma 45>; + dma-names = "rx", "tx"; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c3: i2c@2502c00 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + dmas = <&dma 46>, <&dma 46>; + dma-names = "rx", "tx"; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + syscon: syscon@3000000 { + compatible = "allwinner,sun20i-d1-system-control"; + reg = <0x3000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + regulators { + reg_ldoa: ldoa { + regulator-name = "ldoa"; + }; + + reg_ldob: ldob { + regulator-name = "ldob"; + }; + }; + + sram@400000 { + compatible = "mmio-sram"; + reg = <0x400000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400000 0x20000>; + + /* + * This can be further divided into DSP IRAM, + * DSP DRAM0, and DSP DRAM1, but the mapping + * of all three is controlled by a single bit. + */ + dsp_sram: sram-section@0 { + compatible = "allwinner,sun20i-d1-dsp-sram"; + reg = <0 0x20000>; + }; + }; + + // FIXME: Address is not verified. It is copied from A64/H6. + sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x1d00000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1d00000 0x40000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun20i-d1-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0 0x40000>; + }; + }; + }; + + dma: dma-controller@3002000 { + compatible = "allwinner,sun20i-d1-dma"; + reg = <0x3002000 0x1000>; + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names = "bus", "mbus"; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + dma-channels = <16>; + dma-requests = <48>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>, + <142 IRQ_TYPE_LEVEL_HIGH>; + }; + + msgbox: mailbox@3003000 { + compatible = "allwinner,sun20i-d1-msgbox"; + reg = <0x3003000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX0>; + resets = <&ccu RST_BUS_MSGBOX0>; + interrupts = <101 IRQ_TYPE_LEVEL_HIGH>, + <102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + #mbox-cells = <2>; + }; + + hwspinlock: hwlock@3005000 { + compatible = "allwinner,sun20i-d1-hwspinlock", + "allwinner,sun6i-a31-hwspinlock"; + reg = <0x3005000 0x1000>; + clocks = <&ccu CLK_BUS_SPINLOCK>; + resets = <&ccu RST_BUS_SPINLOCK>; + interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; + }; + + sid: efuse@3006000 { + compatible = "allwinner,sun20i-d1-sid", + "allwinner,sun50i-a64-sid"; + reg = <0x3006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: cpu-speed-grade@0 { + reg = <0x0 0x2>; + }; + + ths_calib: ths-calib@14 { + reg = <0x14 0x4>; + }; + }; + + // TODO: write a binding and driver. + hstimer: timer@3008000 { + compatible = "allwinner,sun20i-d1-hstimer", + "allwinner,sun50i-h6-hstimer"; + reg = <0x3008000 0x1000>; + clocks = <&ccu CLK_BUS_HSTIMER>; + resets = <&ccu RST_BUS_HSTIMER>; + interrupts = <71 IRQ_TYPE_LEVEL_HIGH>, + <72 IRQ_TYPE_LEVEL_HIGH>; + }; + + crypto: crypto@3040000 { + compatible = "allwinner,sun20i-d1-crypto"; + reg = <0x3040000 0x800>; + clocks = <&ccu CLK_BUS_CE>, + <&ccu CLK_CE>, + <&ccu CLK_MBUS_CE>, + <&rtc CLK_IOSC>; + clock-names = "bus", "mod", "ram", "trng"; + resets = <&ccu RST_BUS_CE>; + interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; + }; + + // TODO: write a binding and driver. + mbus: dram-controller@3102000 { + compatible = "allwinner,sun20i-d1-mbus"; + reg = <0x3102000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&ccu CLK_BUS_DRAM>, + <&ccu CLK_DRAM>, + <&ccu CLK_MBUS>; + clock-names = "bus", "dram", "mbus"; + dma-ranges = <0 0x40000000 0x80000000>; + #interconnect-cells = <1>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; + }; + + mmc0: mmc@4020000 { + compatible = "allwinner,sun20i-d1-mmc"; + reg = <0x4020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + cap-sd-highspeed; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + no-mmc; + status = "disabled"; + }; + + mmc1: mmc@4021000 { + compatible = "allwinner,sun20i-d1-mmc"; + reg = <0x4021000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + cap-sd-highspeed; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + no-mmc; + status = "disabled"; + }; + + mmc2: mmc@4022000 { + compatible = "allwinner,sun20i-d1-emmc"; + reg = <0x4022000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + cap-mmc-highspeed; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + no-sd; + no-sdio; + status = "disabled"; + }; + + spi0: spi@4025000 { + compatible = "allwinner,sun20i-d1-spi", + "allwinner,sun50i-r329-spi"; + reg = <0x4025000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + spi1: spi@4026000 { + compatible = "allwinner,sun20i-d1-spi-dbi", + "allwinner,sun50i-r329-spi-dbi", + "allwinner,sun50i-r329-spi"; + reg = <0x4026000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + status = "disabled"; + }; + + usb_otg: usb@4100000 { + compatible = "allwinner,sun20i-d1-musb", + "allwinner,sun8i-a33-musb"; + reg = <0x4100000 0x400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + dmas = <&dma 30>, <&dma 30>, + <&dma 31>, <&dma 31>, + <&dma 32>, <&dma 32>, + <&dma 33>, <&dma 33>, + <&dma 34>, <&dma 34>; + dma-names = "ep1_rx", "ep1_tx", + "ep2_rx", "ep2_tx", + "ep3_rx", "ep3_tx", + "ep4_rx", "ep4_tx", + "ep5_rx", "ep5_tx"; + extcon = <&usbphy 0>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: phy@4100400 { + compatible = "allwinner,sun20i-d1-usb-phy"; + reg = <0x4100400 0x100>, + <0x4101800 0x100>, + <0x4200800 0x100>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1"; + clocks = <&osc24M>, + <&osc24M>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + #phy-cells = <1>; + status = "disabled"; + }; + + ehci0: usb@4101000 { + compatible = "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg = <0x4101000 0x100>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@4101400 { + compatible = "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg = <0x4101400 0x100>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@4200000 { + compatible = "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg = <0x4200000 0x100>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@4200400 { + compatible = "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg = <0x4200400 0x100>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + emac: ethernet@4500000 { + compatible = "allwinner,sun20i-d1-emac", + "allwinner,sun50i-a64-emac"; + reg = <0x4500000 0x10000>; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + syscon = <&syscon>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + de: display-engine@5000000 { + reg = <0x5000000 0x400000>; + interrupts = <103 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mbus 11>; + interconnect-names = "dma-mem"; + iommus = <&iommu 2>; + }; + + deinterlace: deinterlace@5400000 { + reg = <0x5400000 0x10000>; + interconnects = <&mbus 10>; + interconnect-names = "dma-mem"; + interrupts = <104 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&iommu 4>; + }; + + g2d: g2d@5410000 { + reg = <0x5410000 0x40000>; + interconnects = <&mbus 9>; + interconnect-names = "dma-mem"; + interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&iommu 3>; + }; + + dsi: dsi@5450000 { + reg = <0x5450000 0x2000>; + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; + }; + + tcon_top: tcon-top@5460000 { + reg = <0x5460000 0x1000>; + }; + + tcon_lcd: lcd-controller@5461000 { + reg = <0x5461000 0x1000>; + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; + }; + + tcon_tv: lcd-controller@5470000 { + reg = <0x5470000 0x1000>; + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; + }; + + hdmi: hdmi@5500000 { + reg = <0x5500000 0x100000>; + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; + }; + + tve_top: video-codec@5600000 { + reg = <0x5600000 0x4000>; + }; + + tve0: video-codec@5604000 { + reg = <0x5604000 0x4000>; + interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; + }; + + csi: csi@5800000 { + reg = <0x5800000 0x400000>; + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>, + <112 IRQ_TYPE_LEVEL_HIGH>, + <116 IRQ_TYPE_LEVEL_HIGH>, + <122 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mbus 7>; + interconnect-names = "dma-mem"; + iommus = <&iommu 1>; + }; + + tvd_top: video-codec@5c00000 { + reg = <0x5c00000 0x1000>; + interconnects = <&mbus 6>; + interconnect-names = "dma-mem"; + }; + + tvd0: video-codec@5c01000 { + reg = <0x5c01000 0x1000>; + interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; + }; + + intc: interrupt-controller@6010000 { + compatible = "allwinner,sun20i-d1-intc"; + reg = <0x6010000 0x100>; + #address-cells = <0>; + clocks = <&ccu CLK_BUS_RISCV_CFG>; + resets = <&ccu RST_BUS_RISCV_CFG>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + riscv_wdt: watchdog@6011000 { + compatible = "allwinner,sun20i-d1-wdt"; + reg = <0x6011000 0x20>; + clocks = <&osc24M>; + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>; + }; + + riscv_msgbox: mailbox@601f000 { + compatible = "allwinner,sun20i-d1-msgbox"; + reg = <0x601f000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX2>; + resets = <&ccu RST_BUS_MSGBOX2>; + interrupts = <144 IRQ_TYPE_LEVEL_HIGH>, + <145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + #mbox-cells = <2>; + }; + + r_ccu: clock-controller@7010000 { + compatible = "allwinner,sun20i-d1-r-ccu"; + reg = <0x7010000 0x400>; + clocks = <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0_DIV3>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; + }; + + r_ir_rx: ir@7040000 { + compatible = "allwinner,sun20i-d1-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x7040000 0x400>; + clocks = <&r_ccu CLK_BUS_R_IR_RX>, <&r_ccu CLK_R_IR_RX>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_BUS_R_IR_RX>; + interrupts = <167 IRQ_TYPE_LEVEL_HIGH>; + }; + + // TODO: audit all blocks for hidden use of CLK_DCXO24M + rtc: rtc@7090000 { + compatible = "allwinner,sun20i-d1-rtc", + "allwinner,sun50i-r329-rtc"; + reg = <0x7090000 0x400>; + clocks = <&r_ccu CLK_BUS_R_RTC>, + <&osc24M>, + <&r_ccu CLK_R_AHB>; + clock-names = "bus", "hosc", "ahb"; + #clock-cells = <1>; + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>; + }; + + plic: interrupt-controller@10000000 { + compatible = "allwinner,sun20i-d1-plic", + "thead,c900-plic"; + reg = <0x10000000 0x4000000>; + #address-cells = <0>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu0_intc 9>; + interrupt-controller; + #interrupt-cells = <1>; + riscv,ndev = <176>; + }; + + clint: clint@14000000 { + compatible = "allwinner,sun20i-d1-clint", + "sifive,clint0"; + reg = <0x14000000 0xc000>; + reg-io-width = <4>; + interrupts-extended = <&cpu0_intc 3>, + <&cpu0_intc 7>; + }; + }; +}; Index: sys/modules/dtb/allwinner/Makefile =================================================================== --- sys/modules/dtb/allwinner/Makefile +++ sys/modules/dtb/allwinner/Makefile @@ -66,6 +66,13 @@ sun50i-h5-opp.dtso \ sun50i-h5-nanopi-neo2-opp.dtso +.elif ${MACHINE_ARCH} == "riscv64" + +DTS= \ + allwinner/sun20i-d1-lichee-rv.dts \ + allwinner/sun20i-d1-lichee-rv-dock.dts \ + allwinner/sun20i-d1-nezha.dts \ + .endif .include Index: sys/riscv/conf/GENERIC =================================================================== --- sys/riscv/conf/GENERIC +++ sys/riscv/conf/GENERIC @@ -203,6 +203,7 @@ # Flattened Device Tree options FDT +makeoptions MODULES_EXTRA+="dtb/allwinner" makeoptions MODULES_EXTRA+="dtb/sifive" # I2C support