Index: sys/dev/nvme/nvme_ns.c
===================================================================
--- sys/dev/nvme/nvme_ns.c
+++ sys/dev/nvme/nvme_ns.c
@@ -571,20 +571,14 @@
 	 * that improves performance.  If present use for the stripe size.  NVMe
 	 * 1.3 standardized this as NOIOB, and newer Intel drives use that.
 	 */
-	switch (pci_get_devid(ctrlr->dev)) {
-	case 0x09538086:		/* Intel DC PC3500 */
-	case 0x0a538086:		/* Intel DC PC3520 */
-	case 0x0a548086:		/* Intel DC PC4500 */
-	case 0x0a558086:		/* Dell Intel P4600 */
+	if ((ctrlr->quirks & QUIRK_INTEL_ALIGNMENT) != 0) {
 		if (ctrlr->cdata.vs[3] != 0)
 			ns->boundary =
 			    (1 << ctrlr->cdata.vs[3]) * ctrlr->min_page_size;
 		else
 			ns->boundary = 0;
-		break;
-	default:
+	} else {
 		ns->boundary = ns->data.noiob * nvme_ns_get_sector_size(ns);
-		break;
 	}
 
 	if (nvme_ctrlr_has_dataset_mgmt(&ctrlr->cdata))
Index: sys/dev/nvme/nvme_pci.c
===================================================================
--- sys/dev/nvme/nvme_pci.c
+++ sys/dev/nvme/nvme_pci.c
@@ -85,6 +85,10 @@
 	{ 0x09538086,		1, 0x3705, "DC P3500 SSD [2.5\" SFF]" },
 	{ 0x09538086,		1, 0x3709, "DC P3600 SSD [Add-in Card]" },
 	{ 0x09538086,		1, 0x370a, "DC P3600 SSD [2.5\" SFF]" },
+	{ 0x09538086,		0, 0, "Intel DC PC3500", QUIRK_INTEL_ALIGNMENT },
+	{ 0x0a538086,		0, 0, "Intel DC PC3520", QUIRK_INTEL_ALIGNMENT },
+	{ 0x0a548086,		0, 0, "Intel DC PC4500", QUIRK_INTEL_ALIGNMENT },
+	{ 0x0a558086,		0, 0, "Dell Intel P4600", QUIRK_INTEL_ALIGNMENT },
 	{ 0x00031c58,		0, 0, "HGST SN100",	QUIRK_DELAY_B4_CHK_RDY },
 	{ 0x00231c58,		0, 0, "WDC SN200",	QUIRK_DELAY_B4_CHK_RDY },
 	{ 0x05401c5f,		0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY },
Index: sys/dev/nvme/nvme_private.h
===================================================================
--- sys/dev/nvme/nvme_private.h
+++ sys/dev/nvme/nvme_private.h
@@ -240,6 +240,7 @@
 	uint32_t		quirks;
 #define	QUIRK_DELAY_B4_CHK_RDY	1		/* Can't touch MMIO on disable */
 #define	QUIRK_DISABLE_TIMEOUT	2		/* Disable broken completion timeout feature */
+#define	QUIRK_INTEL_ALIGNMENT	4		/* Pre NVMe 1.3 performance alignment */
 
 	bus_space_tag_t		bus_tag;
 	bus_space_handle_t	bus_handle;