Index: sys/dev/nvme/nvme.h =================================================================== --- sys/dev/nvme/nvme.h +++ sys/dev/nvme/nvme.h @@ -533,6 +533,316 @@ #define NVME_SS_PAGE_SSTAT_GDE_SHIFT (8) #define NVME_SS_PAGE_SSTAT_GDE_MASK (0x1) +/* Features */ +/* Get Features */ +#define NVME_FEAT_GET_SEL_SHIFT (8) +#define NVME_FEAT_GET_SEL_MASK (0x7) +#define NVME_FEAT_GET_FID_SHIFT (0) +#define NVME_FEAT_GET_FID_MASK (0xFF) + +#define NVME_FEAT_GET_SEL(x) \ + (((x) >> NVME_FEAT_GET_SEL_SHIFT) & \ + NVME_FEAT_GET_SEL_MASK) +#define NVME_FEAT_GET_FID(x) \ + (((x) >> NVME_FEAT_GET_FID_SHIFT) & \ + NVME_FEAT_GET_FID_MASK) + +/* Set Features */ +#define NVME_FEAT_SET_SV_SHIFT (31) +#define NVME_FEAT_SET_SV_MASK (0x1) +#define NVME_FEAT_SET_FID_SHIFT (0) +#define NVME_FEAT_SET_FID_MASK (0xFF) + +#define NVME_FEAT_SET_SV(x) \ + (((x) >> NVME_FEAT_SET_SV_SHIFT) & \ + NVME_FEAT_SET_SV_MASK) +#define NVME_FEAT_SET_FID(x) \ + (((x) >> NVME_FEAT_SET_FID_SHIFT) & \ + NVME_FEAT_SET_FID_MASK) + +/* Arbitration */ +#define NVME_FEAT_ARBITRATION_HPW_SHIFT (24) +#define NVME_FEAT_ARBITRATION_HPW_MASK (0xFF) +#define NVME_FEAT_ARBITRATION_MPW_SHIFT (16) +#define NVME_FEAT_ARBITRATION_MPW_MASK (0xFF) +#define NVME_FEAT_ARBITRATION_LPW_SHIFT (8) +#define NVME_FEAT_ARBITRATION_LPW_MASK (0xFF) +#define NVME_FEAT_ARBITRATION_AB_SHIFT (0) +#define NVME_FEAT_ARBITRATION_AB_MASK (0x7) + +#define NVME_FEAT_ARBITRATION_HPW(x) \ + (((x) >> NVME_FEAT_ARBITRATION_HPW_SHIFT) & \ + NVME_FEAT_ARBITRATION_HPW_MASK) +#define NVME_FEAT_ARBITRATION_MPW(x) \ + (((x) >> NVME_FEAT_ARBITRATION_MPW_SHIFT) & \ + NVME_FEAT_ARBITRATION_MPW_MASK) +#define NVME_FEAT_ARBITRATION_LPW(x) \ + (((x) >> NVME_FEAT_ARBITRATION_LPW_SHIFT) & \ + NVME_FEAT_ARBITRATION_LPW_MASK) +#define NVME_FEAT_ARBITRATION_AB(x) \ + (((x) >> NVME_FEAT_ARBITRATION_AB_SHIFT) & \ + NVME_FEAT_ARBITRATION_AB_MASK) + +/* Power Management */ +#define NVME_FEAT_POWER_MANAGEMENT_WH_SHIFT (5) +#define NVME_FEAT_POWER_MANAGEMENT_WH_MASK (0x7) +#define NVME_FEAT_POWER_MANAGEMENT_PS_SHIFT (0) +#define NVME_FEAT_POWER_MANAGEMENT_PS_MASK (0x1F) + +#define NVME_FEAT_POWER_MANAGEMENT_WH(x) \ + (((x) >> NVME_FEAT_POWER_MANAGEMENT_WH_SHIFT) & \ + NVME_FEAT_POWER_MANAGEMENT_WH_MASK) +#define NVME_FEAT_POWER_MANAGEMENT_PS(x) \ + (((x) >> NVME_FEAT_POWER_MANAGEMENT_PS_SHIFT) & \ + NVME_FEAT_POWER_MANAGEMENT_PS_MASK) + +/* LBA Range Type */ +#define NVME_FEAT_LBA_RANGE_TYPE_NUM_SHIFT (0) +#define NVME_FEAT_LBA_RANGE_TYPE_NUM_MASK (0x3F) + +#define NVME_FEAT_LBA_RANGE_TYPE_NUM(x) \ + (((x) >> NVME_FEAT_LBA_RANGE_TYPE_NUM_SHIFT) & \ + NVME_FEAT_LBA_RANGE_TYPE_NUM_MASK) + +/* Temperature Threshold */ +#define NVME_FEAT_TEMPERATURE_THRESHOLD_THSEL_SHIFT (20) +#define NVME_FEAT_TEMPERATURE_THRESHOLD_THSEL_MASK (0x3) +#define NVME_FEAT_TEMPERATURE_THRESHOLD_TMPSEL_SHIFT (16) +#define NVME_FEAT_TEMPERATURE_THRESHOLD_TMPSEL_MASK (0xF) +#define NVME_FEAT_TEMPERATURE_THRESHOLD_TMPTH_SHIFT (0) +#define NVME_FEAT_TEMPERATURE_THRESHOLD_TMPTH_MASK (0xFFFF) + +#define NVME_FEAT_TEMPERATURE_THRESHOLD_THSEL(x) \ + (((x) >> NVME_FEAT_TEMPERATURE_THRESHOLD_THSEL_SHIFT) & \ + NVME_FEAT_TEMPERATURE_THRESHOLD_THSEL_MASK) +#define NVME_FEAT_TEMPERATURE_THRESHOLD_TMPSEL(x) \ + (((x) >> NVME_FEAT_TEMPERATURE_THRESHOLD_TMPSEL_SHIFT) & \ + NVME_FEAT_TEMPERATURE_THRESHOLD_TMPSEL_MASK) +#define NVME_FEAT_TEMPERATURE_THRESHOLD_TMPTH(x) \ + (((x) >> NVME_FEAT_TEMPERATURE_THRESHOLD_TMPTH_SHIFT) & \ + NVME_FEAT_TEMPERATURE_THRESHOLD_TMPTH_MASK) + +/* Error Recovery */ +#define NVME_FEAT_ERROR_RECOVERY_DULBE_SHIFT (16) +#define NVME_FEAT_ERROR_RECOVERY_DULBE_MASK (0x1) +#define NVME_FEAT_ERROR_RECOVERY_TLER_SHIFT (0) +#define NVME_FEAT_ERROR_RECOVERY_TLER_MASK (0xFF) + +#define NVME_FEAT_ERROR_RECOVERY_DULBE(x) \ + (((x) >> NVME_FEAT_ERROR_RECOVERY_DULBE_SHIFT) & \ + NVME_FEAT_ERROR_RECOVERY_DULBE_MASK) +#define NVME_FEAT_ERROR_RECOVERY_TLER(x) \ + (((x) >> NVME_FEAT_ERROR_RECOVERY_TLER_SHIFT) & \ + NVME_FEAT_ERROR_RECOVERY_TLER_MASK) + +/* Volatile Write Cache */ +#define NVME_FEAT_VOLATILE_WRITE_CACHE_WCE_SHIFT (0) +#define NVME_FEAT_VOLATILE_WRITE_CACHE_WCE_MASK (0x1) + +#define NVME_FEAT_VOLATILE_WRITE_CACHE_WCE(x) \ + (((x) >> NVME_FEAT_VOLATILE_WRITE_CACHE_WCE_SHIFT) & \ + NVME_FEAT_VOLATILE_WRITE_CACHE_WCE_MASK) + +/* Number of Queues */ +#define NVME_FEAT_NUMBER_OF_QUEUES_NCQR_SHIFT (16) +#define NVME_FEAT_NUMBER_OF_QUEUES_NCQR_MASK (0xFFFF) +#define NVME_FEAT_NUMBER_OF_QUEUES_NSQR_SHIFT (0) +#define NVME_FEAT_NUMBER_OF_QUEUES_NSQR_MASK (0xFFFF) +#define NVME_FEAT_NUMBER_OF_QUEUES_NCQA_SHIFT (16) +#define NVME_FEAT_NUMBER_OF_QUEUES_NCQA_MASK (0xFFFF) +#define NVME_FEAT_NUMBER_OF_QUEUES_NSQA_SHIFT (0) +#define NVME_FEAT_NUMBER_OF_QUEUES_NSQA_MASK (0xFFFF) + +#define NVME_FEAT_NUMBER_OF_QUEUES_NCQR(x) \ + (((x) >> NVME_FEAT_NUMBER_OF_QUEUES_NCQR_SHIFT) & \ + NVME_FEAT_NUMBER_OF_QUEUES_NCQR_MASK) +#define NVME_FEAT_NUMBER_OF_QUEUES_NSQR(x) \ + (((x) >> NVME_FEAT_NUMBER_OF_QUEUES_NSQR_SHIFT) & \ + NVME_FEAT_NUMBER_OF_QUEUES_NSQR_MASK) +#define NVME_FEAT_NUMBER_OF_QUEUES_NCQA(x) \ + (((x) >> NVME_FEAT_NUMBER_OF_QUEUES_NCQA_SHIFT) & \ + NVME_FEAT_NUMBER_OF_QUEUES_NCQA_MASK) +#define NVME_FEAT_NUMBER_OF_QUEUES_NSQA(x) \ + (((x) >> NVME_FEAT_NUMBER_OF_QUEUES_NSQA_SHIFT) & \ + NVME_FEAT_NUMBER_OF_QUEUES_NSQA_MASK) + +/* Interrupt Coalescing */ +#define NVME_FEAT_INTERRUPT_COALESCING_TIME_SHIFT (8) +#define NVME_FEAT_INTERRUPT_COALESCING_TIME_MASK (0xFF) +#define NVME_FEAT_INTERRUPT_COALESCING_THR_SHIFT (0) +#define NVME_FEAT_INTERRUPT_COALESCING_THR_MASK (0xFF) + +#define NVME_FEAT_INTERRUPT_COALESCING_TIME(x) \ + (((x) >> NVME_FEAT_INTERRUPT_COALESCING_TIME_SHIFT) & \ + NVME_FEAT_INTERRUPT_COALESCING_TIME_MASK) +#define NVME_FEAT_INTERRUPT_COALESCING_THR(x) \ + (((x) >> NVME_FEAT_INTERRUPT_COALESCING_THR_SHIFT) & \ + NVME_FEAT_INTERRUPT_COALESCING_THR_MASK) + +/* Interrupt Vector Configuration */ +#define NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION_CD_SHIFT (16) +#define NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION_CD_MASK (0x1) +#define NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION_IV_SHIFT (0) +#define NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION_IV_MASK (0xFF) + +#define NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION_CD(x) \ + (((x) >> NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION_CD_SHIFT) & \ + NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION_CD_MASK) +#define NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION_IV(x) \ + (((x) >> NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION_IV_SHIFT) & \ + NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION_IV_MASK) + +/* Write Atomicity Normal */ +#define NVME_FEAT_WRITE_ATOMICITY_DN_SHIFT (0) +#define NVME_FEAT_WRITE_ATOMICITY_DN_MASK (0x1) + +#define NVME_FEAT_WRITE_ATOMICITY_DN(x) \ + (((x) >> NVME_FEAT_WRITE_ATOMICITY_DN_SHIFT) & \ + NVME_FEAT_WRITE_ATOMICITY_DN_MASK) + +/* Asynchronous Event Configuration */ +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_TLN_SHIFT (10) +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_TLN_MASK (0x1) +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_FAN_SHIFT (9) +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_FAN_MASK (0x1) +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_NAN_SHIFT (8) +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_NAN_MASK (0x1) +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_HCW_SHIFT (0) +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_HCW_MASK (0xFF) + +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_TLN(x) \ + (((x) >> NVME_FEAT_ASYNC_EVENT_CONFIGURATION_TLN_SHIFT) & \ + NVME_FEAT_ASYNC_EVENT_CONFIGURATION_TLN_MASK) +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_FAN(x) \ + (((x) >> NVME_FEAT_ASYNC_EVENT_CONFIGURATION_FAN_SHIFT) & \ + NVME_FEAT_ASYNC_EVENT_CONFIGURATION_FAN_MASK) +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_NAN(x) \ + (((x) >> NVME_FEAT_ASYNC_EVENT_CONFIGURATION_NAN_SHIFT) & \ + NVME_FEAT_ASYNC_EVENT_CONFIGURATION_NAN_MASK) +#define NVME_FEAT_ASYNC_EVENT_CONFIGURATION_HCW(x) \ + (((x) >> NVME_FEAT_ASYNC_EVENT_CONFIGURATION_HCW_SHIFT) & \ + NVME_FEAT_ASYNC_EVENT_CONFIGURATION_HCW_MASK) + +/* Autonomous Power State Transition */ +#define NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION_APSTE_SHIFT (0) +#define NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION_APSTE_MASK (0x1) + +#define NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION_APSTE(x) \ + (((x) >> NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION_APSTE_SHIFT) & \ + NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION_APSTE_MASK) + +/* Host Memory Buffer */ +#define NVME_FEAT_HOST_MEMORY_BUFFER_MR_SHIFT (1) +#define NVME_FEAT_HOST_MEMORY_BUFFER_MR_MASK (0x1) +#define NVME_FEAT_HOST_MEMORY_BUFFER_EHM_SHIFT (0) +#define NVME_FEAT_HOST_MEMORY_BUFFER_EHM_MASK (0x1) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HSIZE_SHIFT (0) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HSIZE_MASK (0xFFFF) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HMDLLA_SHIFT (4) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HMDLLA_MASK (0xFFF) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HMDLUA_SHIFT (0) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HMDLUA_MASK (0xFFFF) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HMDLEC_SHIFT (0) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HMDLEC_MASK (0xFFFF) + +#define NVME_FEAT_HOST_MEMORY_BUFFER_MR(x) \ + (((x) >> NVME_FEAT_HOST_MEMORY_BUFFER_MR_SHIFT) & \ + NVME_FEAT_HOST_MEMORY_BUFFER_MR_MASK) +#define NVME_FEAT_HOST_MEMORY_BUFFER_EHM(x) \ + (((x) >> NVME_FEAT_HOST_MEMORY_BUFFER_EHM_SHIFT) & \ + NVME_FEAT_HOST_MEMORY_BUFFER_EHM_MASK) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HSIZE(x) \ + (((x) >> NVME_FEAT_HOST_MEMORY_BUFFER_HSIZE_SHIFT) & \ + NVME_FEAT_HOST_MEMORY_BUFFER_HSIZE_MASK) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HMDLLA(x) \ + (((x) >> NVME_FEAT_HOST_MEMORY_BUFFER_HMDLLA_SHIFT) & \ + NVME_FEAT_HOST_MEMORY_BUFFER_HMDLLA_MASK) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HMDLUA(x) \ + (((x) >> NVME_FEAT_HOST_MEMORY_BUFFER_HMDLUA_SHIFT) & \ + NVME_FEAT_HOST_MEMORY_BUFFER_HMDLUA_MASK) +#define NVME_FEAT_HOST_MEMORY_BUFFER_HMDLEC(x) \ + (((x) >> NVME_FEAT_HOST_MEMORY_BUFFER_HMDLEC_SHIFT) & \ + NVME_FEAT_HOST_MEMORY_BUFFER_HMDLEC_MASK) + +/* Timestamp */ +#define NVME_FEAT_TIMESTAMP_TS_SHIFT (0x0) +#define NVME_FEAT_TIMESTAMP_TS_MASK (0x3F) + +#define NVME_FEAT_TIMESTAMP_TS(x) \ + (((x) >> NVME_FEAT_TIMESTAMP_TS_SHIFT) & \ + NVME_FEAT_TIMESTAMP_TS_MASK) + +/* Keep Alive Timer */ +#define NVME_FEAT_KEEP_ALIVE_TIMER_KATO_SHIFT (0x0) +#define NVME_FEAT_KEEP_ALIVE_TIMER_KATO_MASK (0xFFFF) + +#define NVME_FEAT_KEEP_ALIVE_TIMER_KATO(x) \ + (((x) >> NVME_FEAT_KEEP_ALIVE_TIMER_KATO_SHIFT) & \ + NVME_FEAT_KEEP_ALIVE_TIMER_KATO_MASK) + +/* Host Controlled Thermal Management */ +#define NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT_TMT1_SHIFT (16) +#define NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT_TMT1_MASK (0xFF) +#define NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT_TMT2_SHIFT (0) +#define NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT_TMT2_MASK (0xFF) + +#define NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT_TMT1(x) \ + (((x) >> NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT_TMT1_SHIFT) & \ + NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT_TMT1_MASK) +#define NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT_TMT2(x) \ + (((x) >> NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT_TMT2_SHIFT) & \ + NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT_TMT2_MASK) + +/* Non-Operational Power State Config */ +#define NVME_FEAT_NON_OP_POWER_STATE_CONFIG_NOPPME_SHIFT (0) +#define NVME_FEAT_NON_OP_POWER_STATE_CONFIG_NOPPME_MASK (0x1) + +#define NVME_FEAT_NON_OP_POWER_STATE_CONFIG_NOPPME(x) \ + (((x) >> NVME_FEAT_NON_OP_POWER_STATE_CONFIG_NOPPME_SHIFT) & \ + NVME_FEAT_NON_OP_POWER_STATE_CONFIG_NOPPME_MASK) + +/* Software Progress Marker */ +#define NVME_FEAT_SOFTWARE_PROGRESS_MARKER_PBSLC_SHIFT (0) +#define NVME_FEAT_SOFTWARE_PROGRESS_MARKER_PBSLC_MASK (0xFF) + +#define NVME_FEAT_SOFTWARE_PROGRESS_MARKER_PBSLC(x) \ + (((x) >> NVME_FEAT_SOFTWARE_PROGRESS_MARKER_PBSLC_SHIFT) & \ + NVME_FEAT_SOFTWARE_PROGRESS_MARKER_PBSLC_MASK) + +/* Host Identifier */ +#define NVME_FEAT_HOST_IDENTIFIER_EXHID_SHIFT (0) +#define NVME_FEAT_HOST_IDENTIFIER_EXHID_MASK (0x1) + +#define NVME_FEAT_HOST_IDENTIFIER_EXHID(x) \ + (((x) >> NVME_FEAT_HOST_IDENTIFIER_EXHID_SHIFT) & \ + NVME_FEAT_HOST_IDENTIFIER_EXHID_MASK) + +/* Reservation Notification Mask */ +#define NVME_FEAT_RESERVATION_NOTIFICATION_MASK_RESPRE_SHIFT (3) +#define NVME_FEAT_RESERVATION_NOTIFICATION_MASK_RESPRE_MASK (0x1) +#define NVME_FEAT_RESERVATION_NOTIFICATION_MASK_RESREL_SHIFT (2) +#define NVME_FEAT_RESERVATION_NOTIFICATION_MASK_RESREL_MASK (0x1) +#define NVME_FEAT_RESERVATION_NOTIFICATION_MASK_REGPRE_SHIFT (1) +#define NVME_FEAT_RESERVATION_NOTIFICATION_MASK_REGPRE_MASK (0x1) + +#define NVME_FEAT_RESERVATION_NOTIFICATION_MASK_RESPRE(x) \ + (((x) >> NVME_FEAT_RESERVATION_NOTIFICATION_MASK_RESPRE_SHIFT) & \ + NVME_FEAT_RESERVATION_NOTIFICATION_MASK_RESPRE_MASK) +#define NVME_FEAT_RESERVATION_NOTIFICATION_MASK_RESREL(x) \ + (((x) >> NVME_FEAT_RESERVATION_NOTIFICATION_MASK_RESREL_SHIFT) & \ + NVME_FEAT_RESERVATION_NOTIFICATION_MASK_RESREL_MASK) +#define NVME_FEAT_RESERVATION_NOTIFICATION_MASK_REGPRE(x) \ + (((x) >> NVME_FEAT_RESERVATION_NOTIFICATION_MASK_REGPRE_SHIFT) & \ + NVME_FEAT_RESERVATION_NOTIFICATION_MASK_REGPRE_MASK) + +/* Reservation Persistence */ +#define NVME_FEAT_RESERVATION_PERSISTENCE_PTPL_SHIFT (0) +#define NVME_FEAT_RESERVATION_PERSISTENCE_PTPL_MASK (0x1) + +#define NVME_FEAT_RESERVATION_PERSISTENCE_PTPL(x) \ + (((x) >> NVME_FEAT_RESERVATION_PERSISTENCE_PTPL_SHIFT) & \ + NVME_FEAT_RESERVATION_PERSISTENCE_PTPL_MASK) + /* CC register SHN field values */ enum shn_value { NVME_SHN_NORMAL = 0x1,