diff --git a/sys/dev/e1000/e1000_82575.h b/sys/dev/e1000/e1000_82575.h
--- a/sys/dev/e1000/e1000_82575.h
+++ b/sys/dev/e1000/e1000_82575.h
@@ -143,13 +143,12 @@
 #define E1000_TX_HEAD_WB_ENABLE		0x1
 #define E1000_TX_SEQNUM_WB_ENABLE	0x2
 
-#define E1000_MRQC_ENABLE_RSS_4Q		0x00000002
+#define E1000_MRQC_ENABLE_RSS_MQ		0x00000002
 #define E1000_MRQC_ENABLE_VMDQ			0x00000003
 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q		0x00000005
 #define E1000_MRQC_RSS_FIELD_IPV4_UDP		0x00400000
 #define E1000_MRQC_RSS_FIELD_IPV6_UDP		0x00800000
 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX	0x01000000
-#define E1000_MRQC_ENABLE_RSS_8Q		0x00000002
 
 #define E1000_VMRCTL_MIRROR_PORT_SHIFT		8
 #define E1000_VMRCTL_MIRROR_DSTPORT_MASK	(7 << \
diff --git a/sys/dev/e1000/e1000_defines.h b/sys/dev/e1000/e1000_defines.h
--- a/sys/dev/e1000/e1000_defines.h
+++ b/sys/dev/e1000/e1000_defines.h
@@ -428,11 +428,12 @@
 #define E1000_SCTL_ENABLE_SERDES_LOOPBACK	0x0410
 
 /* Receive Checksum Control */
-#define E1000_RXCSUM_IPOFL	0x00000100 /* IPv4 checksum offload */
-#define E1000_RXCSUM_TUOFL	0x00000200 /* TCP / UDP checksum offload */
-#define E1000_RXCSUM_CRCOFL	0x00000800 /* CRC32 offload enable */
-#define E1000_RXCSUM_IPPCSE	0x00001000 /* IP payload checksum enable */
-#define E1000_RXCSUM_PCSD	0x00002000 /* packet checksum disabled */
+#define E1000_RXCSUM_IPOFL		0x00000100 /* IPv4 checksum offload */
+#define E1000_RXCSUM_TUOFL		0x00000200 /* TCP / UDP checksum offload */
+#define E1000_RXCSUM_IPV6OFL	0x00000400  /* lem(4) IPv6 checksum offload */
+#define E1000_RXCSUM_CRCOFL		0x00000800 /* CRC32 offload enable */
+#define E1000_RXCSUM_IPPCSE		0x00001000 /* IP payload checksum enable */
+#define E1000_RXCSUM_PCSD		0x00002000 /* packet checksum disabled */
 
 /* Header split receive */
 #define E1000_RFCTL_NFSW_DIS		0x00000040
diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c
--- a/sys/dev/e1000/if_em.c
+++ b/sys/dev/e1000/if_em.c
@@ -2838,7 +2838,7 @@
 	 * MRQC: Multiple Receive Queues Command
 	 * Set queuing to RSS control, number depends on the device.
 	 */
-	mrqc = E1000_MRQC_ENABLE_RSS_8Q;
+	mrqc = E1000_MRQC_ENABLE_RSS_MQ;
 
 #ifdef RSS
 	/* XXX ew typecasting */
@@ -3245,37 +3245,33 @@
 		E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
 	}
 
+	/* Set up L3 and L4 csum Rx descriptor offloads */
 	rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
-	if (if_getcapenable(ifp) & IFCAP_RXCSUM &&
-	    hw->mac.type >= e1000_82543) {
-		if (adapter->tx_num_queues > 1) {
-			if (hw->mac.type >= igb_mac_min) {
-				rxcsum |= E1000_RXCSUM_PCSD;
-				if (hw->mac.type != e1000_82575)
-					rxcsum |= E1000_RXCSUM_CRCOFL;
-			} else
-				rxcsum |= E1000_RXCSUM_TUOFL |
-					E1000_RXCSUM_IPOFL |
-					E1000_RXCSUM_PCSD;
-		} else {
-			if (hw->mac.type >= igb_mac_min)
-				rxcsum |= E1000_RXCSUM_IPPCSE;
-			else
-				rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
-			if (hw->mac.type > e1000_82575)
-				rxcsum |= E1000_RXCSUM_CRCOFL;
-		}
-	} else
-		rxcsum &= ~E1000_RXCSUM_TUOFL;
-
-	E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
+	if (scctx->isc_capenable & IFCAP_RXCSUM) {
+		rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL;
+		if (hw->mac.type > e1000_82575)
+			rxcsum |= E1000_RXCSUM_CRCOFL;
+		else if (hw->mac.type < em_mac_min &&
+		    scctx->isc_capenable & IFCAP_HWCSUM_IPV6)
+			rxcsum |= E1000_RXCSUM_IPV6OFL;
+	} else {
+		rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
+		if (hw->mac.type > e1000_82575)
+			rxcsum &= ~E1000_RXCSUM_CRCOFL;
+		else if (hw->mac.type < em_mac_min)
+			rxcsum &= ~E1000_RXCSUM_IPV6OFL;
+	}
 
 	if (adapter->rx_num_queues > 1) {
+		/* RSS hash needed in the Rx descriptor */
+		rxcsum |= E1000_RXCSUM_PCSD;
+
 		if (hw->mac.type >= igb_mac_min)
 			igb_initialize_rss_mapping(adapter);
 		else
 			em_initialize_rss_mapping(adapter);
 	}
+	E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
 
 	/*
 	 * XXX TEMPORARY WORKAROUND: on some systems with 82573