Index: sys/arm64/arm64/elf32_machdep.c =================================================================== --- sys/arm64/arm64/elf32_machdep.c +++ sys/arm64/arm64/elf32_machdep.c @@ -77,6 +77,9 @@ extern void freebsd32_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask); +u_long __read_frequently elf32_hwcap; +u_long __read_frequently elf32_hwcap2; + static struct sysentvec elf32_freebsd_sysvec = { .sv_size = SYS_MAXSYSCALL, .sv_table = freebsd32_sysent, @@ -112,6 +115,8 @@ .sv_schedtail = NULL, .sv_thread_detach = NULL, .sv_trap = NULL, + .sv_hwcap = &elf32_hwcap, + .sv_hwcap2 = &elf32_hwcap2, .sv_onexec_old = exec_onexec_old, .sv_onexit = exit_onexit, }; Index: sys/arm64/arm64/identcpu.c =================================================================== --- sys/arm64/arm64/identcpu.c +++ sys/arm64/arm64/identcpu.c @@ -50,6 +50,10 @@ static void print_cpu_features(u_int cpu); static u_long parse_cpu_features_hwcap(void); static u_long parse_cpu_features_hwcap2(void); +#ifdef COMPAT_FREEBSD32 +static u_long parse_cpu_features_hwcap32(void); +static u_long parse_cpu_features_hwcap32_2(void); +#endif char machine[] = "arm64"; @@ -135,6 +139,12 @@ uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; uint64_t ctr; +#ifdef COMPAT_FREEBSD32 + uint64_t id_isar5; + uint64_t id_pfr0; + uint64_t mvfr0; + uint64_t mvfr1; +#endif }; static struct cpu_desc cpu_desc[MAXCPU]; @@ -1272,6 +1282,12 @@ elf_hwcap = parse_cpu_features_hwcap(); elf_hwcap2 = parse_cpu_features_hwcap2(); +#ifdef COMPAT_FREEBSD32 + /* 32-bit ARM versions of AT_HWCAP/HWCAP2 */ + elf32_hwcap = parse_cpu_features_hwcap32(); + elf32_hwcap2 = parse_cpu_features_hwcap32_2(); +#endif + if (dic && idc) { arm64_icache_sync_range = &arm64_dic_idc_icache_sync_range; if (bootverbose) @@ -1482,6 +1498,70 @@ return (hwcap2); } +#ifdef COMPAT_FREEBSD32 +static u_long +parse_cpu_features_hwcap32(void) +{ + u_long hwcap = HWCAP32_DEFAULT; + + if (MVFR0_EL1_FPDP_VAL(cpu_desc[0].mvfr0) >= + MVFR0_EL1_FPDP_VFP_v2) { + hwcap |= HWCAP32_VFP; + + if (MVFR0_EL1_FPDP_VAL(cpu_desc[0].mvfr0) == + MVFR0_EL1_FPDP_VFP_v3_v4) { + hwcap |= HWCAP32_VFPv3; + + if (MVFR1_EL1_SIMDFMAC_VAL(cpu_desc[0].mvfr1) == + MVFR1_EL1_SIMDFMAC_IMPL) + hwcap |= HWCAP32_VFPv4; + } + } + + if (ID_PFR0_EL1_STATE3_VAL(cpu_desc[0].id_pfr0) == + ID_PFR0_EL1_STATE3_T32EE) + hwcap |= HWCAP32_THUMBEE; + + if ((MVFR1_EL1_SIMDLS_VAL(cpu_desc[0].mvfr1) == + MVFR1_EL1_SIMDLS_IMPL) && + (MVFR1_EL1_SIMDInt_VAL(cpu_desc[0].mvfr1) == + MVFR1_EL1_SIMDInt_IMPL) && + (MVFR1_EL1_SIMDSP_VAL(cpu_desc[0].mvfr1) == + MVFR1_EL1_SIMDSP_IMPL)) + hwcap |= HWCAP32_NEON; + + return (hwcap); +} + +static u_long +parse_cpu_features_hwcap32_2(void) +{ + u_long hwcap2 = 0; + + if (ID_ISAR5_EL1_AES_VAL(cpu_desc[0].id_isar5) >= + ID_ISAR5_EL1_AES_BASE) + hwcap2 |= HWCAP32_2_AES; + + if (ID_ISAR5_EL1_AES_VAL(cpu_desc[0].id_isar5) == + ID_ISAR5_EL1_AES_VMULL) + hwcap2 |= HWCAP32_2_PMULL; + + if (ID_ISAR5_EL1_SHA1_VAL(cpu_desc[0].id_isar5) == + ID_ISAR5_EL1_SHA1_IMPL) + hwcap2 |= HWCAP32_2_SHA1; + + if (ID_ISAR5_EL1_SHA2_VAL(cpu_desc[0].id_isar5) == + ID_ISAR5_EL1_SHA2_IMPL) + hwcap2 |= HWCAP32_2_SHA2; + + if (ID_ISAR5_EL1_CRC32_VAL(cpu_desc[0].id_isar5) == + ID_ISAR5_EL1_CRC32_IMPL) + hwcap2 |= HWCAP32_2_CRC32; + + return (hwcap2); +} +#endif /* COMPAT_FREEBSD32 */ + static void print_ctr_fields(struct sbuf *sb, uint64_t reg, void *arg) { @@ -1794,6 +1874,12 @@ cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1); cpu_desc[cpu].id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1); cpu_desc[cpu].id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1); +#ifdef COMPAT_FREEBSD32 + cpu_desc[cpu].id_isar5 = READ_SPECIALREG(id_isar5_el1); + cpu_desc[cpu].id_pfr0 = READ_SPECIALREG(id_pfr0_el1); + cpu_desc[cpu].mvfr0 = READ_SPECIALREG(mvfr0_el1); + cpu_desc[cpu].mvfr1 = READ_SPECIALREG(mvfr1_el1); +#endif } static void Index: sys/arm64/include/armreg.h =================================================================== --- sys/arm64/include/armreg.h +++ sys/arm64/include/armreg.h @@ -772,6 +772,92 @@ #define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) #define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) +/* ID_ISAR5_EL1 */ +#define ID_ISAR5_EL1 MRS_REG(3, 0, 0, 2, 5) +#define ID_ISAR5_EL1_SEVL_SHIFT 0 +#define ID_ISAR5_EL1_SEVL_MASK (UL(0xf) << ID_ISAR5_EL1_SEVL_SHIFT) +#define ID_ISAR5_EL1_SEVL_VAL(x) ((x) & ID_ISAR5_EL1_SEVL_MASK) +#define ID_ISAR5_EL1_SEVL_NOP (UL(0x0) << ID_ISAR5_EL1_SEVL_SHIFT) +#define ID_ISAR5_EL1_SEVL_IMPL (UL(0x1) << ID_ISAR5_EL1_SEVL_SHIFT) +#define ID_ISAR5_EL1_AES_SHIFT 4 +#define ID_ISAR5_EL1_AES_MASK (UL(0xf) << ID_ISAR5_EL1_AES_SHIFT) +#define ID_ISAR5_EL1_AES_VAL(x) ((x) & ID_ISAR5_EL1_AES_MASK) +#define ID_ISAR5_EL1_AES_NONE (UL(0x0) << ID_ISAR5_EL1_AES_SHIFT) +#define ID_ISAR5_EL1_AES_BASE (UL(0x1) << ID_ISAR5_EL1_AES_SHIFT) +#define ID_ISAR5_EL1_AES_VMULL (UL(0x2) << ID_ISAR5_EL1_AES_SHIFT) +#define ID_ISAR5_EL1_SHA1_SHIFT 8 +#define ID_ISAR5_EL1_SHA1_MASK (UL(0xf) << ID_ISAR5_EL1_SHA1_SHIFT) +#define ID_ISAR5_EL1_SHA1_VAL(x) ((x) & ID_ISAR5_EL1_SHA1_MASK) +#define ID_ISAR5_EL1_SHA1_NONE (UL(0x0) << ID_ISAR5_EL1_SHA1_SHIFT) +#define ID_ISAR5_EL1_SHA1_IMPL (UL(0x1) << ID_ISAR5_EL1_SHA1_SHIFT) +#define ID_ISAR5_EL1_SHA2_SHIFT 12 +#define ID_ISAR5_EL1_SHA2_MASK (UL(0xf) << ID_ISAR5_EL1_SHA2_SHIFT) +#define ID_ISAR5_EL1_SHA2_VAL(x) ((x) & ID_ISAR5_EL1_SHA2_MASK) +#define ID_ISAR5_EL1_SHA2_NONE (UL(0x0) << ID_ISAR5_EL1_SHA2_SHIFT) +#define ID_ISAR5_EL1_SHA2_IMPL (UL(0x1) << ID_ISAR5_EL1_SHA2_SHIFT) +#define ID_ISAR5_EL1_CRC32_SHIFT 16 +#define ID_ISAR5_EL1_CRC32_MASK (UL(0xf) << ID_ISAR5_EL1_CRC32_SHIFT) +#define ID_ISAR5_EL1_CRC32_VAL(x) ((x) & ID_ISAR5_EL1_CRC32_MASK) +#define ID_ISAR5_EL1_CRC32_NONE (UL(0x0) << ID_ISAR5_EL1_CRC32_SHIFT) +#define ID_ISAR5_EL1_CRC32_IMPL (UL(0x1) << ID_ISAR5_EL1_CRC32_SHIFT) +#define ID_ISAR5_EL1_RDM_SHIFT 24 +#define ID_ISAR5_EL1_RDM_MASK (UL(0xf) << ID_ISAR5_EL1_RDM_SHIFT) +#define ID_ISAR5_EL1_RDM_VAL(x) ((x) & ID_ISAR5_EL1_RDM_MASK) +#define ID_ISAR5_EL1_RDM_NONE (UL(0x0) << ID_ISAR5_EL1_RDM_SHIFT) +#define ID_ISAR5_EL1_RDM_IMPL (UL(0x1) << ID_ISAR5_EL1_RDM_SHIFT) +#define ID_ISAR5_EL1_VCMA_SHIFT 28 +#define ID_ISAR5_EL1_VCMA_MASK (UL(0xf) << ID_ISAR5_EL1_VCMA_SHIFT) +#define ID_ISAR5_EL1_VCMA_VAL(x) ((x) & ID_ISAR5_EL1_VCMA_MASK) +#define ID_ISAR5_EL1_VCMA_NONE (UL(0x0) << ID_ISAR5_EL1_VCMA_SHIFT) +#define ID_ISAR5_EL1_VCMA_IMPL (UL(0x0) << ID_ISAR5_EL1_VCMA_SHIFT) + +/* ID_PFR0_EL1 */ +#define ID_PFR0_EL1 MRS_REG(3, 0, 0, 1, 0) +#define ID_PFR0_EL1_STATE0_SHIFT 0 +#define ID_PFR0_EL1_STATE0_MASK (UL(0xf) << ID_PFR0_EL1_STATE0_SHIFT) +#define ID_PFR0_EL1_STATE0_VAL(x) ((x) & ID_PFR0_EL1_STATE0_MASK) +#define ID_PFR0_EL1_STATE0_NONE (UL(0x0) << ID_PFR0_EL1_STATE0_SHIFT) +#define ID_PFR0_EL1_STATE0_A32IMPL (UL(0x1) << ID_PFR0_EL1_STATE0_SHIFT) +#define ID_PFR0_EL1_STATE1_SHIFT 4 +#define ID_PFR0_EL1_STATE1_MASK (UL(0xf) << ID_PFR0_EL1_STATE1_SHIFT) +#define ID_PFR0_EL1_STATE1_VAL(x) ((x) & ID_PFR0_EL1_STATE1_MASK) +#define ID_PFR0_EL1_STATE1_NONE (UL(0x0) << ID_PFR0_EL1_STATE1_SHIFT) +#define ID_PFR0_EL1_STATE1_THUMB (UL(0x1) << ID_PFR0_EL1_STATE1_SHIFT) +#define ID_PFR0_EL1_STATE1_T32 (UL(0x3) << ID_PFR0_EL1_STATE1_SHIFT) +#define ID_PFR0_EL1_STATE2_SHIFT 8 +#define ID_PFR0_EL1_STATE2_MASK (UL(0xf) << ID_PFR0_EL1_STATE2_SHIFT) +#define ID_PFR0_EL1_STATE2_VAL(x) ((x) & ID_PFR0_EL1_STATE2_MASK) +#define ID_PFR0_EL1_STATE2_NONE (UL(0x0) << ID_PFR0_EL1_STATE2_SHIFT) +#define ID_PFR0_EL1_STATE2_JZLBASE (UL(0x1) << ID_PFR0_EL1_STATE2_SHIFT) +#define ID_PFR0_EL1_STATE2_JZLEXT (UL(0x2) << ID_PFR0_EL1_STATE2_SHIFT) +#define ID_PFR0_EL1_STATE3_SHIFT 12 +#define ID_PFR0_EL1_STATE3_MASK (UL(0xf) << ID_PFR0_EL1_STATE3_SHIFT) +#define ID_PFR0_EL1_STATE3_VAL(x) ((x) & ID_PFR0_EL1_STATE3_MASK) +#define ID_PFR0_EL1_STATE3_NONE (UL(0x0) << ID_PFR0_EL1_STATE3_SHIFT) +#define ID_PFR0_EL1_STATE3_T32EE (UL(0x1) << ID_PFR0_EL1_STATE3_SHIFT) +#define ID_PFR0_EL1_CSV2_SHIFT 16 +#define ID_PFR0_EL1_CSV2_MASK (UL(0xf) << ID_PFR0_EL1_CSV2_SHIFT) +#define ID_PFR0_EL1_CSV2_VAL(x) ((x) & ID_PFR0_EL1_CSV2_MASK) +#define ID_PFR0_EL1_CSV2_NONE (UL(0x0) << ID_PFR0_EL1_CSV2_SHIFT) +#define ID_PFR0_EL1_CSV2_IMPL (UL(0x1) << ID_PFR0_EL1_CSV2_SHIFT) +#define ID_PFR0_EL1_AMU_SHIFT 20 +#define ID_PFR0_EL1_AMU_MASK (UL(0xf) << ID_PFR0_EL1_AMU_SHIFT) +#define ID_PFR0_EL1_AMU_VAL(x) ((x) & ID_PFR0_EL1_AMU_MASK) +#define ID_PFR0_EL1_AMU_NONE (UL(0x0) << ID_PFR0_EL1_AMU_SHIFT) +#define ID_PFR0_EL1_AMU_v1 (UL(0x1) << ID_PFR0_EL1_AMU_SHIFT) +#define ID_PFR0_EL1_AMU_v1p1 (UL(0x2) << ID_PFR0_EL1_AMU_SHIFT) +#define ID_PFR0_EL1_DIT_SHIFT 24 +#define ID_PFR0_EL1_DIT_MASK (UL(0xf) << ID_PFR0_EL1_DIT_SHIFT) +#define ID_PFR0_EL1_DIT_VAL(x) ((x) & ID_PFR0_EL1_DIT_MASK) +#define ID_PFR0_EL1_DIT_NONE (UL(0x0) << ID_PFR0_EL1_DIT_SHIFT) +#define ID_PFR0_EL1_DIT_CPSR (UL(0x1) << ID_PFR0_EL1_DIT_SHIFT) +#define ID_PFR0_EL1_RAS_SHIFT 28 +#define ID_PFR0_EL1_RAS_MASK (UL(0xf) << ID_PFR0_EL1_RAS_SHIFT) +#define ID_PFR0_EL1_RAS_VAL(x) ((x) & ID_PFR0_EL1_RAS_MASK) +#define ID_PFR0_EL1_RAS_NONE (UL(0x0) << ID_PFR0_EL1_RAS_SHIFT) +#define ID_PFR0_EL1_RAS_IMPL (UL(0x1) << ID_PFR0_EL1_RAS_SHIFT) +#define ID_PFR0_EL1_RAS_8_4 (UL(0x1) << ID_PFR0_EL1_RAS_SHIFT) + /* MAIR_EL1 - Memory Attribute Indirection Register */ #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) @@ -781,6 +867,97 @@ #define MAIR_NORMAL_WT 0xbb #define MAIR_NORMAL_WB 0xff +/* MVFR0_EL1 */ +#define MVFR0_EL1 MRS_REG(3, 0, 0, 3, 0) +#define MVFR0_EL1_SIMDReg_SHIFT 0 +#define MVFR0_EL1_SIMDReg_MASK (UL(0xf) << MVFR0_EL1_SIMDReg_SHIFT) +#define MVFR0_EL1_SIMDReg_VAL(x) ((x) & MVFR0_EL1_SIMDReg_MASK) +#define MVFR0_EL1_SIMDReg_NONE (UL(0x0) << MVFR0_EL1_SIMDReg_SHIFT) +#define MVFR0_EL1_SIMDReg_FP (UL(0x1) << MVFR0_EL1_SIMDReg_SHIFT) +#define MVFR0_EL1_SIMDReg_AdvSIMD (UL(0x2) << MVFR0_EL1_SIMDReg_SHIFT) +#define MVFR0_EL1_FPSP_SHIFT 4 +#define MVFR0_EL1_FPSP_MASK (UL(0xf) << MVFR0_EL1_FPSP_SHIFT) +#define MVFR0_EL1_FPSP_VAL(x) ((x) & MVFR0_EL1_FPSP_MASK) +#define MVFR0_EL1_FPSP_NONE (UL(0x0) << MVFR0_EL1_FPSP_SHIFT) +#define MVFR0_EL1_FPSP_VFP_v2 (UL(0x1) << MVFR0_EL1_FPSP_SHIFT) +#define MVFR0_EL1_FPSP_VFP_v3_v4 (UL(0x2) << MVFR0_EL1_FPSP_SHIFT) +#define MVFR0_EL1_FPDP_SHIFT 8 +#define MVFR0_EL1_FPDP_MASK (UL(0xf) << MVFR0_EL1_FPDP_SHIFT) +#define MVFR0_EL1_FPDP_VAL(x) ((x) & MVFR0_EL1_FPDP_MASK) +#define MVFR0_EL1_FPDP_NONE (UL(0x0) << MVFR0_EL1_FPDP_SHIFT) +#define MVFR0_EL1_FPDP_VFP_v2 (UL(0x1) << MVFR0_EL1_FPDP_SHIFT) +#define MVFR0_EL1_FPDP_VFP_v3_v4 (UL(0x2) << MVFR0_EL1_FPDP_SHIFT) +#define MVFR0_EL1_FPTrap_SHIFT 12 +#define MVFR0_EL1_FPTrap_MASK (UL(0xf) << MVFR0_EL1_FPTrap_SHIFT) +#define MVFR0_EL1_FPTrap_VAL(x) ((x) & MVFR0_EL1_FPTrap_MASK) +#define MVFR0_EL1_FPTrap_NONE (UL(0x0) << MVFR0_EL1_FPTrap_SHIFT) +#define MVFR0_EL1_FPTrap_IMPL (UL(0x1) << MVFR0_EL1_FPTrap_SHIFT) +#define MVFR0_EL1_FPDivide_SHIFT 16 +#define MVFR0_EL1_FPDivide_MASK (UL(0xf) << MVFR0_EL1_FPDivide_SHIFT) +#define MVFR0_EL1_FPDivide_VAL(x) ((x) & MVFR0_EL1_FPDivide_MASK) +#define MVFR0_EL1_FPDivide_NONE (UL(0x0) << MVFR0_EL1_FPDivide_SHIFT) +#define MVFR0_EL1_FPDivide_IMPL (UL(0x1) << MVFR0_EL1_FPDivide_SHIFT) +#define MVFR0_EL1_FPSqrt_SHIFT 20 +#define MVFR0_EL1_FPSqrt_MASK (UL(0xf) << MVFR0_EL1_FPSqrt_SHIFT) +#define MVFR0_EL1_FPSqrt_VAL(x) ((x) & MVFR0_EL1_FPSqrt_MASK) +#define MVFR0_EL1_FPSqrt_NONE (UL(0x0) << MVFR0_EL1_FPSqrt_SHIFT) +#define MVFR0_EL1_FPSqrt_IMPL (UL(0x1) << MVFR0_EL1_FPSqrt_SHIFT) +#define MVFR0_EL1_FPshVec_SHIFT 24 +#define MVFR0_EL1_FPshVec_MASK (UL(0xf) << MVFR0_EL1_FPshVec_SHIFT) +#define MVFR0_EL1_FPshVec_VAL(x) ((x) & MVFR0_EL1_FPshVec_MASK) +#define MVFR0_EL1_FPshVec_NONE (UL(0x0) << MVFR0_EL1_FPshVec_SHIFT) +#define MVFR0_EL1_FPshVec_IMPL (UL(0x1) << MVFR0_EL1_FPshVec_SHIFT) +#define MVFR0_EL1_FPRound_SHIFT 28 +#define MVFR0_EL1_FPRound_MASK (UL(0xf) << MVFR0_EL1_FPRound_SHIFT) +#define MVFR0_EL1_FPRound_VAL(x) ((x) & MVFR0_EL1_FPRound_MASK) +#define MVFR0_EL1_FPRound_NONE (UL(0x0) << MVFR0_EL1_FPRound_SHIFT) +#define MVFR0_EL1_FPRound_IMPL (UL(0x1) << MVFR0_EL1_FPRound_SHIFT) + +/* MVFR1_EL1 */ +#define MVFR1_EL1 MRS_REG(3, 0, 0, 3, 1) +#define MVFR1_EL1_FPFtZ_SHIFT 0 +#define MVFR1_EL1_FPFtZ_MASK (UL(0xf) << MVFR1_EL1_FPFtZ_SHIFT) +#define MVFR1_EL1_FPFtZ_VAL(x) ((x) & MVFR1_EL1_FPFtZ_MASK) +#define MVFR1_EL1_FPFtZ_NONE (UL(0x0) << MVFR1_EL1_FPFtZ_SHIFT) +#define MVFR1_EL1_FPFtZ_IMPL (UL(0x1) << MVFR1_EL1_FPFtZ_SHIFT) +#define MVFR1_EL1_FPDNaN_SHIFT 4 +#define MVFR1_EL1_FPDNaN_MASK (UL(0xf) << MVFR1_EL1_FPDNaN_SHIFT) +#define MVFR1_EL1_FPDNaN_VAL(x) ((x) & MVFR1_EL1_FPDNaN_MASK) +#define MVFR1_EL1_FPDNaN_NONE (UL(0x0) << MVFR1_EL1_FPDNaN_SHIFT) +#define MVFR1_EL1_FPDNaN_IMPL (UL(0x1) << MVFR1_EL1_FPDNaN_SHIFT) +#define MVFR1_EL1_SIMDLS_SHIFT 8 +#define MVFR1_EL1_SIMDLS_MASK (UL(0xf) << MVFR1_EL1_SIMDLS_SHIFT) +#define MVFR1_EL1_SIMDLS_VAL(x) ((x) & MVFR1_EL1_SIMDLS_MASK) +#define MVFR1_EL1_SIMDLS_NONE (UL(0x0) << MVFR1_EL1_SIMDLS_SHIFT) +#define MVFR1_EL1_SIMDLS_IMPL (UL(0x1) << MVFR1_EL1_SIMDLS_SHIFT) +#define MVFR1_EL1_SIMDInt_SHIFT 12 +#define MVFR1_EL1_SIMDInt_MASK (UL(0xf) << MVFR1_EL1_SIMDInt_SHIFT) +#define MVFR1_EL1_SIMDInt_VAL(x) ((x) & MVFR1_EL1_SIMDInt_MASK) +#define MVFR1_EL1_SIMDInt_NONE (UL(0x0) << MVFR1_EL1_SIMDInt_SHIFT) +#define MVFR1_EL1_SIMDInt_IMPL (UL(0x1) << MVFR1_EL1_SIMDInt_SHIFT) +#define MVFR1_EL1_SIMDSP_SHIFT 16 +#define MVFR1_EL1_SIMDSP_MASK (UL(0xf) << MVFR1_EL1_SIMDSP_SHIFT) +#define MVFR1_EL1_SIMDSP_VAL(x) ((x) & MVFR1_EL1_SIMDSP_MASK) +#define MVFR1_EL1_SIMDSP_NONE (UL(0x0) << MVFR1_EL1_SIMDSP_SHIFT) +#define MVFR1_EL1_SIMDSP_IMPL (UL(0x1) << MVFR1_EL1_SIMDSP_SHIFT) +#define MVFR1_EL1_SIMDHP_SHIFT 20 +#define MVFR1_EL1_SIMDHP_MASK (UL(0xf) << MVFR1_EL1_SIMDHP_SHIFT) +#define MVFR1_EL1_SIMDHP_VAL(x) ((x) & MVFR1_EL1_SIMDHP_MASK) +#define MVFR1_EL1_SIMDHP_NONE (UL(0x0) << MVFR1_EL1_SIMDHP_SHIFT) +#define MVFR1_EL1_SIMDHP_CONV (UL(0x1) << MVFR1_EL1_SIMDHP_SHIFT) +#define MVFR1_EL1_SIMDHP_FULL (UL(0x2) << MVFR1_EL1_SIMDHP_SHIFT) +#define MVFR1_EL1_FPHP_SHIFT 24 +#define MVFR1_EL1_FPHP_MASK (UL(0xf) << MVFR1_EL1_FPHP_SHIFT) +#define MVFR1_EL1_FPHP_VAL(x) ((x) & MVFR1_EL1_FPHP_MASK) +#define MVFR1_EL1_FPHP_NONE (UL(0x0) << MVFR1_EL1_FPHP_SHIFT) +#define MVFR1_EL1_FPHP_CONV (UL(0x1) << MVFR1_EL1_FPHP_SHIFT) +#define MVFR1_EL1_FPHP_FULL (UL(0x2) << MVFR1_EL1_FPHP_SHIFT) +#define MVFR1_EL1_SIMDFMAC_SHIFT 28 +#define MVFR1_EL1_SIMDFMAC_MASK (UL(0xf) << MVFR1_EL1_SIMDFMAC_SHIFT) +#define MVFR1_EL1_SIMDFMAC_VAL(x) ((x) & MVFR1_EL1_SIMDFMAC_MASK) +#define MVFR1_EL1_SIMDFMAC_NONE (UL(0x0) << MVFR1_EL1_SIMDFMAC_SHIFT) +#define MVFR1_EL1_SIMDFMAC_IMPL (UL(0x1) << MVFR1_EL1_SIMDFMAC_SHIFT) + /* PAR_EL1 - Physical Address Register */ #define PAR_F_SHIFT 0 #define PAR_F (0x1 << PAR_F_SHIFT) Index: sys/arm64/include/elf.h =================================================================== --- sys/arm64/include/elf.h +++ sys/arm64/include/elf.h @@ -150,4 +150,34 @@ #define HWCAP2_RNG 0x00010000 #define HWCAP2_BTI 0x00020000 +#ifdef COMPAT_FREEBSD32 +/* ARM HWCAP */ +#define HWCAP32_HALF 0x00000002 /* Always set. */ +#define HWCAP32_THUMB 0x00000004 +#define HWCAP32_FAST_MULT 0x00000010 /* Always set. */ +#define HWCAP32_VFP 0x00000040 +#define HWCAP32_EDSP 0x00000080 /* Always set for ARMv6+. */ +#define HWCAP32_THUMBEE 0x00000800 +#define HWCAP32_NEON 0x00001000 +#define HWCAP32_VFPv3 0x00002000 +#define HWCAP32_TLS 0x00008000 /* Always set for ARMv6+. */ +#define HWCAP32_VFPv4 0x00010000 +#define HWCAP32_IDIVA 0x00020000 +#define HWCAP32_IDIVT 0x00040000 +#define HWCAP32_VFPD32 0x00080000 +#define HWCAP32_LPAE 0x00100000 + +#define HWCAP32_DEFAULT \ + (HWCAP32_HALF | HWCAP32_THUMB | HWCAP32_FAST_MULT | HWCAP32_EDSP |\ + HWCAP32_TLS | HWCAP32_IDIVA | HWCAP32_IDIVT | HWCAP32_VFPD32 | \ + HWCAP32_LPAE) + +/* ARM HWCAP2 */ +#define HWCAP32_2_AES 0x00000001 +#define HWCAP32_2_PMULL 0x00000002 +#define HWCAP32_2_SHA1 0x00000004 +#define HWCAP32_2_SHA2 0x00000008 +#define HWCAP32_2_CRC32 0x00000010 +#endif + #endif /* !_MACHINE_ELF_H_ */ Index: sys/arm64/include/md_var.h =================================================================== --- sys/arm64/include/md_var.h +++ sys/arm64/include/md_var.h @@ -38,6 +38,10 @@ extern int szsigcode; extern u_long elf_hwcap; extern u_long elf_hwcap2; +#ifdef COMPAT_FREEBSD32 +extern u_long elf32_hwcap; +extern u_long elf32_hwcap2; +#endif struct dumperinfo;