diff --git a/lib/libpmc/pmc.haswell.3 b/lib/libpmc/pmc.haswell.3 --- a/lib/libpmc/pmc.haswell.3 +++ b/lib/libpmc/pmc.haswell.3 @@ -93,12 +93,12 @@ .It Li DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry -cacheline reads. Does not count L2 data read prefetches or -instruction fetches. +cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. @@ -146,8 +146,9 @@ -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) @@ -157,14 +158,15 @@ This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured @@ -242,7 +244,8 @@ Load misses that missed DTLB but hit STLB (2M). .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H , Umask 60H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS .Pq Event 08H , Umask 80H DTLB demand load misses with low part of linear-to- @@ -250,7 +253,8 @@ .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH , Umask 03H Cycles waiting to recover after Machine Clears -except JEClear. Set Cmask= 1. +except JEClear. +Set Cmask= 1. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H ncrements each cycle the # of Uops issued by the @@ -259,12 +263,12 @@ of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H -Number of flags-merge uops allocated. Such uops -adds delay. +Number of flags-merge uops allocated. +Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H -Number of slow LEA or similar uops allocated. Such -uop has 3 sources (e.g. 2 sources + immediate) +Number of slow LEA or similar uops allocated. +Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SiNGLE_MUL .Pq Event 0EH , Umask 40H @@ -337,20 +341,17 @@ references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H -Counts the number of thread cycles while the thread -is not in a halt state. The thread enters the halt state -when it is running the HLT instruction. The core -frequency may change from time to time due to -power or thermal throttling. +Counts the number of thread cycles while the thread is not in a halt state. +The thread enters the halt state when it is running the HLT instruction. +The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H -Increments the number of outstanding L1D misses -every cycle. Set Cmaks = 1 and Edge =1 to count -occurrences. +Increments the number of outstanding L1D misses every cycle. +Set Cmaks = 1 and Edge =1 to count occurrences. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any @@ -422,25 +423,23 @@ Cycles the RS is empty for the thread. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H -Offcore outstanding Demand Data Read transactions -in SQ to uncore. Set Cmask=1 to count cycles. +Offcore outstanding Demand Data Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD .Pq Event 60H , Umask 02H -Offcore outstanding Demand code Read transactions -in SQ to uncore. Set Cmask=1 to count cycles. +Offcore outstanding Demand code Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H -Offcore outstanding RFO store transactions in SQ to -uncore. Set Cmask=1 to count cycles. +Offcore outstanding RFO store transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H -Offcore outstanding cacheable data read -transactions in SQ to uncore. Set Cmask=1 to count -cycles. +Offcore outstanding cacheable data read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H -Cycles in which the L1D and L2 are locked, due to a -UC lock or split lock. +Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. @@ -449,8 +448,7 @@ Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H -Increment each cycle # of uops delivered to IDQ from -MITE path. +Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H @@ -459,42 +457,40 @@ Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H -Increment each cycle # of uops delivered to IDQ -when MS_busy by DSB. Set Cmask = 1 to count -cycles. Add Edge=1 to count # of delivery. +Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. +Set Cmask = 1 to count cycles. +Add Edge=1 to count # of delivery. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H -ncrement each cycle # of uops delivered to IDQ -when MS_busy by MITE. Set Cmask = 1 to count -cycles. +ncrement each cycle # of uops delivered to IDQ when MS_busy by MITE. +Set Cmask = 1 to count cycles. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H -Increment each cycle # of uops delivered to IDQ from -MS by either DSB or MITE. Set Cmask = 1 to count -cycles. +Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. +Set Cmask = 1 to count cycles. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered at least one uops. Set -Cmask = 1. +Counts cycles DSB is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered four uops. Set Cmask -=4. +Counts cycles DSB is delivered four uops. +Set Cmask=4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered at least one uops. Set -Cmask = 1. +Counts cycles MITE is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered four uops. Set Cmask -=4. +Counts cycles MITE is delivered four uops. +Set Cmask =4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H -Number of Instruction Cache, Streaming Buffer and -Victim Cache Misses. Includes UC accesses. +Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. +Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in ITLB that causes a page walk of any page @@ -521,7 +517,8 @@ ITLB misses that hit STLB (2K). .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 60H -TLB misses that hit STLB. No page walk. +TLB misses that hit STLB. +No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the @@ -635,19 +632,19 @@ Cycles stalled due to re-order buffer full. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H -Cycles with pending L2 miss loads. Set Cmask=2 to -count cycle. +Cycles with pending L2 miss loads. +Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING .Pq Event A3H , Umask 02H -Cycles with pending memory loads. Set Cmask=2 to -count cycle. +Cycles with pending memory loads. +Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.STALLS_L2_PENDING .Pq Event A3H , Umask 05H Number of loads missed L2. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 08H -Cycles with pending L1 cache miss loads. Set -Cmask=8 to count cycle. +Cycles with pending L1 cache miss loads. +Set Cmask=8 to count cycle. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes @@ -805,9 +802,8 @@ Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H -Randomly sampled loads whose latency is above a -user defined threshold. A small fraction of the overall -loads are sampled due to randomization. +Randomly sampled loads whose latency is above a user defined threshold. +A small fraction of the overall loads are sampled due to randomization. .It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS .Pq Event D0H , Umask 11H Count retired load uops that missed the STLB. @@ -838,8 +834,8 @@ sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_MISS .Pq Event D1H , Umask 10H -Retired load uops missed L2. Unknown data source -excluded. +Retired load uops missed L2. +Unknown data source excluded. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops diff --git a/lib/libpmc/pmc.haswelluc.3 b/lib/libpmc/pmc.haswelluc.3 --- a/lib/libpmc/pmc.haswelluc.3 +++ b/lib/libpmc/pmc.haswelluc.3 @@ -154,22 +154,21 @@ .It Li UNC_CBO_CACHE_LOOKUP.READ_FILTER .Pq Event 34H , Umask 10H Filter on processor core initiated cacheable read -requests. Must combine with at least one of 01H, 02H, -04H, 08H. +requests. +Must combine with at least one of 01H, 02H, 04H, 08H. .It Li UNC_CBO_CACHE_LOOKUP.WRITE_FILTER .Pq Event 34H , Umask 20H -Filter on processor core initiated cacheable write -requests. Must combine with at least one of 01H, 02H, -04H, 08H. +Filter on processor core initiated cacheable write requests. +Must combine with at least one of 01H, 02H, 04H, 08H. .It Li UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER .Pq Event 34H , Umask 40H -Filter on external snoop requests. Must combine with -at least one of 01H, 02H, 04H, 08H. +Filter on external snoop requests. +Must combine with at least one of 01H, 02H, 04H, 08H. .It Li UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER .Pq Event 34H , Umask 80H Filter on any IRQ or IPQ initiated requests including -uncacheable, non-coherent requests. Must combine -with at least one of 01H, 02H, 04H, 08H. +uncacheable, non-coherent requests. +Must combine with at least one of 01H, 02H, 04H, 08H. .It Li UNC_ARB_TRK_OCCUPANCY.ALL .Pq Event 80H , Umask 01H Counts cycles weighted by the number of requests diff --git a/lib/libpmc/pmc.haswellxeon.3 b/lib/libpmc/pmc.haswellxeon.3 --- a/lib/libpmc/pmc.haswellxeon.3 +++ b/lib/libpmc/pmc.haswellxeon.3 @@ -94,12 +94,12 @@ .It Li DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry -cacheline reads. Does not count L2 data read prefetches or -instruction fetches. +cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. @@ -147,8 +147,9 @@ -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) @@ -158,14 +159,15 @@ This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured @@ -243,7 +245,8 @@ Load misses that missed DTLB but hit STLB (2M). .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H , Umask 60H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS .Pq Event 08H , Umask 80H DTLB demand load misses with low part of linear-to- @@ -251,7 +254,8 @@ .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH , Umask 03H Cycles waiting to recover after Machine Clears -except JEClear. Set Cmask= 1. +except JEClear. +Set Cmask= 1. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H ncrements each cycle the # of Uops issued by the @@ -260,12 +264,12 @@ of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H -Number of flags-merge uops allocated. Such uops -adds delay. +Number of flags-merge uops allocated. +Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H -Number of slow LEA or similar uops allocated. Such -uop has 3 sources (e.g. 2 sources + immediate) +Number of slow LEA or similar uops allocated. +Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SiNGLE_MUL .Pq Event 0EH , Umask 40H @@ -279,7 +283,7 @@ .Pq Event 24H , Umask 41H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD -.Pq Event 24H , Umask E1H +.Pq Event 24H , Umask E1H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HIT @@ -339,9 +343,9 @@ .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread -is not in a halt state. The thread enters the halt state -when it is running the HLT instruction. The core -frequency may change from time to time due to +is not in a halt state. +The thread enters the halt state when it is running the HLT instruction. +The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H @@ -350,8 +354,8 @@ .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H Increments the number of outstanding L1D misses -every cycle. Set Cmaks = 1 and Edge =1 to count -occurrences. +every cycle. +Set Cmaks = 1 and Edge =1 to count occurrences. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any @@ -424,20 +428,22 @@ .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H Offcore outstanding Demand Data Read transactions -in SQ to uncore. Set Cmask=1 to count cycles. +in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD .Pq Event 60H , Umask 02H Offcore outstanding Demand code Read transactions -in SQ to uncore. Set Cmask=1 to count cycles. +in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H -Offcore outstanding RFO store transactions in SQ to -uncore. Set Cmask=1 to count cycles. +Offcore outstanding RFO store transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H Offcore outstanding cacheable data read -transactions in SQ to uncore. Set Cmask=1 to count -cycles. +transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a @@ -461,41 +467,43 @@ .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H Increment each cycle # of uops delivered to IDQ -when MS_busy by DSB. Set Cmask = 1 to count -cycles. Add Edge=1 to count # of delivery. +when MS_busy by DSB. +Set Cmask = 1 to count cycles. +Add Edge=1 to count # of delivery. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H ncrement each cycle # of uops delivered to IDQ -when MS_busy by MITE. Set Cmask = 1 to count -cycles. +when MS_busy by MITE. +Set Cmask = 1 to count cycles. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from -MS by either DSB or MITE. Set Cmask = 1 to count -cycles. +MS by either DSB or MITE. +Set Cmask = 1 to count cycles. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered at least one uops. Set -Cmask = 1. +Counts cycles DSB is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered four uops. Set Cmask -=4. +Counts cycles DSB is delivered four uops. +Set Cmask =4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered at least one uops. Set -Cmask = 1. +Counts cycles MITE is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered four uops. Set Cmask -=4. +Counts cycles MITE is delivered four uops. +Set Cmask =4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and -Victim Cache Misses. Includes UC accesses. +Victim Cache Misses. +Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in ITLB that causes a page walk of any page @@ -522,7 +530,8 @@ ITLB misses that hit STLB (2K). .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 60H -TLB misses that hit STLB. No page walk. +TLB misses that hit STLB. +No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the @@ -636,19 +645,19 @@ Cycles stalled due to re-order buffer full. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H -Cycles with pending L2 miss loads. Set Cmask=2 to -count cycle. +Cycles with pending L2 miss loads. +Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING .Pq Event A3H , Umask 02H -Cycles with pending memory loads. Set Cmask=2 to -count cycle. +Cycles with pending memory loads. +Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.STALLS_L2_PENDING .Pq Event A3H , Umask 05H Number of loads missed L2. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 08H -Cycles with pending L1 cache miss loads. Set -Cmask=8 to count cycle. +Cycles with pending L1 cache miss loads. +Set Cmask=8 to count cycle. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes @@ -665,8 +674,7 @@ regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H -Data read requests sent to uncore (demand and -prefetch). +Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core @@ -807,8 +815,8 @@ .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H Randomly sampled loads whose latency is above a -user defined threshold. A small fraction of the overall -loads are sampled due to randomization. +user defined threshold. +A small fraction of the overall loads are sampled due to randomization. .It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS .Pq Event D0H , Umask 11H Count retired load uops that missed the STLB. @@ -839,8 +847,8 @@ sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_MISS .Pq Event D1H , Umask 10H -Retired load uops missed L2. Unknown data source -excluded. +Retired load uops missed L2. +Unknown data source excluded. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops @@ -918,26 +926,26 @@ .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , -.Xr pmc.iaf 3 , -.Xr pmc.ucf 3 , -.Xr pmc.k7 3 , -.Xr pmc.k8 3 , -.Xr pmc.p4 3 , -.Xr pmc.p5 3 , -.Xr pmc.p6 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.haswell 3 , .Xr pmc.haswelluc 3 , +.Xr pmc.iaf 3 , .Xr pmc.ivybridge 3 , .Xr pmc.ivybridgexeon 3 , +.Xr pmc.k7 3 , +.Xr pmc.k8 3 , +.Xr pmc.p4 3 , +.Xr pmc.p5 3 , +.Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , -.Xr pmc.westmere 3 , -.Xr pmc.westmereuc 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , +.Xr pmc.ucf 3 , +.Xr pmc.westmere 3 , +.Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 diff --git a/lib/libpmc/pmc.corei7.3 b/lib/libpmc/pmc.corei7.3 --- a/lib/libpmc/pmc.corei7.3 +++ b/lib/libpmc/pmc.corei7.3 @@ -93,17 +93,17 @@ .It Li DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry -cacheline reads. Does not count L2 data read prefetches or -instruction fetches. +cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li DMND_RFO Counts the number of demand and DCU prefetch reads for ownership -(RFO) requests generated by a write to data cacheline. Does not -count L2 RFO. +(RFO) requests generated by a write to data cacheline. +Does not count L2 RFO. .It Li DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline -reads. Does not count L2 code read prefetches. -WB -Counts the number of writeback (modified to exclusive) transactions. +reads. +Does not count L2 code read prefetches. +WB Counts the number of writeback (modified to exclusive) transactions. .It Li PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li PF_RFO @@ -176,11 +176,11 @@ Counts the number of store buffer drains. .It Li STORE_BLOCKS.AT_RET .Pq Event 06H , Umask 04H -Counts number of loads delayed with at-Retirement block code. The following -loads need to be executed at retirement and wait for all senior stores on -the same thread to be drained: load splitting across 4K boundary (page -split), load accessing uncacheable (UC or USWC) memory, load lock, and load -with page table in UC or USWC memory region. +Counts number of loads delayed with at-Retirement block code. +The following loads need to be executed at retirement and wait for all +senior stores on the same thread to be drained: load splitting across +4K boundary (page split), load accessing uncacheable +(UC or USWC) memory, load lock, and load with page table in UC or USWC memory region. .It Li STORE_BLOCKS.L1D_BLOCK .Pq Event 06H , Umask 08H Cacheable loads delayed with L1D block code @@ -220,9 +220,10 @@ In conjunction with ld_lat facility .It Li MEM_STORE_RETIRED.DTLB_MISS .Pq Event 0CH , Umask 01H -The event counts the number of retired stores that missed the DTLB. The DTLB -miss is not counted if the store operation causes a fault. Does not counter -prefetches. Counts both primary and secondary misses to the TLB +The event counts the number of retired stores that missed the DTLB. +The DTLB miss is not counted if the store operation causes a fault. +Does not counter prefetches. +Counts both primary and secondary misses to the TLB .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H Counts the number of Uops issued by the Register Allocation Table to the @@ -250,18 +251,20 @@ .It Li MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT .Pq Event 0FH , Umask 08H Counts number of memory load instructions retired where the memory reference -missed the L1, L2 and L3 caches and HIT in a remote socket's cache. Only -counts locally homed lines. +missed the L1, L2 and L3 caches and HIT in a remote socket's cache. +Only counts locally homed lines. .It Li MEM_UNCORE_RETIRED.REMOTE_DRAM .Pq Event 0FH , Umask 10H Counts number of memory load instructions retired where the memory reference -missed the L1, L2 and L3 caches and was remotely homed. This includes both -DRAM access and HITM in a remote socket's cache for remotely homed lines. +missed the L1, L2 and L3 caches and was remotely homed. +This includes both DRAM access and HITM in a remote socket's cache +for remotely homed lines. .It Li MEM_UNCORE_RETIRED.LOCAL_DRAM .Pq Event 0FH , Umask 20H Counts number of memory load instructions retired where the memory reference missed the L1, L2 and L3 caches and required a local socket memory -reference. This includes locally homed cachelines that were in a modified +reference. +This includes locally homed cachelines that were in a modified state in another socket. .It Li MEM_UNCORE_RETIRED.UNCACHEABLE .Pq Event 0FH , Umask 80H @@ -270,10 +273,10 @@ Available only for CPUID signature 06_2EH .It Li FP_COMP_OPS_EXE.X87 .Pq Event 10H , Umask 01H -Counts the number of FP Computational Uops Executed. The number of FADD, -FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer -DIVs, and IDIVs. This event does not distinguish an FADD used in the middle -of a transcendental flow from a separate FADD instruction. +Counts the number of FP Computational Uops Executed. +The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer +DIVs, and IDIVs. +This event does not distinguish an FADD used in the middle of a transcendental flow from a separate FADD instruction. .It Li FP_COMP_OPS_EXE.MMX .Pq Event 10H , Umask 02H Counts number of MMX Uops executed. @@ -322,8 +325,8 @@ the Memory Order Buffer. .It Li LOAD_DISPATCH.RS_DELAYED .Pq Event 13H , Umask 02H -Counts the number of delayed RS dispatches at the stage latch. If an RS -dispatch can not bypass to LB, it has another chance to dispatch from the +Counts the number of delayed RS dispatches at the stage latch. +If an RS dispatch can not bypass to LB, it has another chance to dispatch from the one-cycle delayed staging latch before it is written into the LB. .It Li LOAD_DISPATCH.MOB .Pq Event 13H , Umask 04H @@ -335,14 +338,15 @@ .It Li ARITH.CYCLES_DIV_BUSY .Pq Event 14H , Umask 01H Counts the number of cycles the divider is busy executing divide or square -root operations. The divide can be integer, X87 or Streaming SIMD Extensions -(SSE). The square root operation can be either X87 or SSE. +root operations. +The divide can be integer, X87 or Streaming SIMD Extensions (SSE). +The square root operation can be either X87 or SSE. Set 'edge =1, invert=1, cmask=1' to count the number of divides. Count may be incorrect When SMT is on. .It Li ARITH.MUL .Pq Event 14H , Umask 02H -Counts the number of multiply operations executed. This includes integer as -well as floating point multiply operations but excludes DPPS mul and MPSAD. +Counts the number of multiply operations executed. +This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. Count may be incorrect When SMT is on .It Li INST_QUEUE_WRITES .Pq Event 17H , Umask 01H @@ -350,65 +354,68 @@ cycle. .It Li INST_DECODED.DEC0 .Pq Event 18H , Umask 01H -Counts number of instructions that require decoder 0 to be decoded. Usually, -this means that the instruction maps to more than 1 uop +Counts number of instructions that require decoder 0 to be decoded. +Usually, this means that the instruction maps to more than 1 uop .It Li TWO_UOP_INSTS_DECODED .Pq Event 19H , Umask 01H An instruction that generates two uops was decoded .It Li INST_QUEUE_WRITE_CYCLES .Pq Event 1EH , Umask 01H This event counts the number of cycles during which instructions are written -to the instruction queue. Dividing this counter by the number of -instructions written to the instruction queue (INST_QUEUE_WRITES) yields the -average number of instructions decoded each cycle. If this number is less -than four and the pipe stalls, this indicates that the decoder is failing to +to the instruction queue. +Dividing this counter by the number of instructions written to the +instruction queue (INST_QUEUE_WRITES) yields the average number of +instructions decoded each cycle. +If this number is less than four and the pipe stalls, this indicates that the decoder is failing to decode enough instructions per cycle to sustain the 4-wide pipeline. If SSE* instructions that are 6 bytes or longer arrive one after another, -then front end throughput may limit execution speed. In such case, +then front end throughput may limit execution speed. +In such case, .It Li LSD_OVERFLOW .Pq Event 20H , Umask 01H Counts number of loops that cant stream from the instruction queue. .It Li L2_RQSTS.LD_HIT .Pq Event 24H , Umask 01H -Counts number of loads that hit the L2 cache. L2 loads include both L1D -demand misses as well as L1D prefetches. L2 loads can be rejected for -various reasons. Only non rejected loads are counted. +Counts number of loads that hit the L2 cache. +L2 loads include both L1D demand misses as well as L1D prefetches. +L2 loads can be rejected for various reasons. +Only non rejected loads are counted. .It Li L2_RQSTS.LD_MISS .Pq Event 24H , Umask 02H -Counts the number of loads that miss the L2 cache. L2 loads include both L1D -demand misses as well as L1D prefetches. +Counts the number of loads that miss the L2 cache. +L2 loads include both L1D demand misses as well as L1D prefetches. .It Li L2_RQSTS.LOADS .Pq Event 24H , Umask 03H -Counts all L2 load requests. L2 loads include both L1D demand misses as well -as L1D prefetches. +Counts all L2 load requests. +L2 loads include both L1D demand misses as well as L1D prefetches. .It Li L2_RQSTS.RFO_HIT .Pq Event 24H , Umask 04H -Counts the number of store RFO requests that hit the L2 cache. L2 RFO -requests include both L1D demand RFO misses as well as L1D RFO prefetches. +Counts the number of store RFO requests that hit the L2 cache. +L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. Count includes WC memory requests, where the data is not fetched but the permission to write the line is required. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 08H -Counts the number of store RFO requests that miss the L2 cache. L2 RFO -requests include both L1D demand RFO misses as well as L1D RFO prefetches. +Counts the number of store RFO requests that miss the L2 cache. +L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. .It Li L2_RQSTS.RFOS .Pq Event 24H , Umask 0CH -Counts all L2 store RFO requests. L2 RFO requests include both L1D demand -RFO misses as well as L1D RFO prefetches. +Counts all L2 store RFO requests. +L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. .It Li L2_RQSTS.IFETCH_HIT .Pq Event 24H , Umask 10H -Counts number of instruction fetches that hit the L2 cache. L2 instruction -fetches include both L1I demand misses as well as L1I instruction +Counts number of instruction fetches that hit the L2 cache. +L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.IFETCH_MISS .Pq Event 24H , Umask 20H -Counts number of instruction fetches that miss the L2 cache. L2 instruction -fetches include both L1I demand misses as well as L1I instruction +Counts number of instruction fetches that miss the L2 cache. +L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.IFETCHES .Pq Event 24H , Umask 30H -Counts all instruction fetches. L2 instruction fetches include both L1I -demand misses as well as L1I instruction prefetches. +Counts all instruction fetches. +L2 instruction fetches include both L1I demand misses as well as L1I instruction prefetches. .It Li L2_RQSTS.PREFETCH_HIT .Pq Event 24H , Umask 40H Counts L2 prefetch hits for both code and data. @@ -427,27 +434,27 @@ .It Li L2_DATA_RQSTS.DEMAND.I_STATE .Pq Event 26H , Umask 01H Counts number of L2 data demand loads where the cache line to be loaded is -in the I (invalid) state, i.e. a cache miss. L2 demand loads are both L1D -demand misses and L1D prefetches. +in the I (invalid) state, i.e. a cache miss. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.S_STATE .Pq Event 26H , Umask 02H Counts number of L2 data demand loads where the cache line to be loaded is -in the S (shared) state. L2 demand loads are both L1D demand misses and L1D -prefetches. +in the S (shared) state. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.E_STATE .Pq Event 26H , Umask 04H Counts number of L2 data demand loads where the cache line to be loaded is -in the E (exclusive) state. L2 demand loads are both L1D demand misses and -L1D prefetches. +in the E (exclusive) state. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.M_STATE .Pq Event 26H , Umask 08H Counts number of L2 data demand loads where the cache line to be loaded is -in the M (modified) state. L2 demand loads are both L1D demand misses and -L1D prefetches. +in the M (modified) state. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.DEMAND.MESI .Pq Event 26H , Umask 0FH -Counts all L2 data demand requests. L2 demand loads are both L1D demand -misses and L1D prefetches. +Counts all L2 data demand requests. +L2 demand loads are both L1D demand misses and L1D prefetches. .It Li L2_DATA_RQSTS.PREFETCH.I_STATE .Pq Event 26H , Umask 10H Counts number of L2 prefetch data loads where the cache line to be loaded is @@ -455,8 +462,9 @@ .It Li L2_DATA_RQSTS.PREFETCH.S_STATE .Pq Event 26H , Umask 20H Counts number of L2 prefetch data loads where the cache line to be loaded is -in the S (shared) state. A prefetch RFO will miss on an S state line, while -a prefetch read will hit on an S state line. +in the S (shared) state. +A prefetch RFO will miss on an S state line, while a prefetch read will +hit on an S state line. .It Li L2_DATA_RQSTS.PREFETCH.E_STATE .Pq Event 26H , Umask 40H Counts number of L2 prefetch data loads where the cache line to be loaded is @@ -474,29 +482,31 @@ .It Li L2_WRITE.RFO.I_STATE .Pq Event 27H , Umask 01H Counts number of L2 demand store RFO requests where the cache line to be -loaded is in the I (invalid) state, i.e, a cache miss. The L1D prefetcher -does not issue a RFO prefetch. +loaded is in the I (invalid) state, i.e, a cache miss. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.S_STATE .Pq Event 27H , Umask 02H Counts number of L2 store RFO requests where the cache line to be loaded is -in the S (shared) state. The L1D prefetcher does not issue a RFO prefetch,. +in the S (shared) state. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.M_STATE .Pq Event 27H , Umask 08H Counts number of L2 store RFO requests where the cache line to be loaded is -in the M (modified) state. The L1D prefetcher does not issue a RFO prefetch. +in the M (modified) state. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.HIT .Pq Event 27H , Umask 0EH Counts number of L2 store RFO requests where the cache line to be loaded is -in either the S, E or M states. The L1D prefetcher does not issue a RFO -prefetch. +in either the S, E or M states. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.RFO.MESI .Pq Event 27H , Umask 0FH -Counts all L2 store RFO requests.The L1D prefetcher does not issue a RFO -prefetch. +Counts all L2 store RFO requests. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li L2_WRITE.LOCK.I_STATE .Pq Event 27H , Umask 10H @@ -543,25 +553,26 @@ .It Li L3_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache -line in the last level cache. The event count includes speculative traffic -but excludes cache line fills due to a L2 hardware-prefetch. Because cache -hierarchy, cache sizes and other implementation-specific characteristics; -value comparison to estimate performance differences is not recommended. +line in the last level cache. +The event count includes speculative traffic but excludes cache line fills +due to a L2 hardware-prefetch. +Because cache hierarchy, cache sizes and other implementation-specific +characteristics; value comparison to estimate performance differences is not recommended. see Table A-1 .It Li L3_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level -cache. The event count may include speculative traffic but excludes cache -line fills due to L2 hardware-prefetches. Because cache hierarchy, cache -sizes and other implementation-specific characteristics; value comparison to -estimate performance differences is not recommended. +cache. +The event count may include speculative traffic but excludes cache +line fills due to L2 hardware-prefetches. +Because cache hierarchy, cache sizes and other implementation-specific +characteristics; value comparison to estimate performance differences is not recommended. see Table A-1 .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. -The thread enters the halt state when it is running the HLT instruction. The -core frequency may change from time to time due to power or thermal -throttling. +The thread enters the halt state when it is running the HLT instruction. +The core frequency may change from time to time due to power or thermal throttling. see Table A-1 .It Li CPU_CLK_UNHALTED.REF_P .Pq Event 3CH , Umask 01H @@ -609,10 +620,10 @@ .It Li L1D_CACHE_LOCK.HIT .Pq Event 42H , Umask 01H Counts retired load locks that hit in the L1 data cache or hit in an already -allocated fill buffer. The lock portion of the load lock transaction must -hit in the L1D. -The initial load will pull the lock into the L1 data cache. Counter 0, 1 -only +allocated fill buffer. +The lock portion of the load lock transaction must hit in the L1D. +The initial load will pull the lock into the L1 data cache. +Counter 0, 1 only .It Li L1D_CACHE_LOCK.S_STATE .Pq Event 42H , Umask 02H Counts L1 data cache retired load locks that hit the target cache line in @@ -631,10 +642,10 @@ .It Li L1D_ALL_REF.ANY .Pq Event 43H , Umask 01H Counts all references (uncached, speculated and retired) to the L1 data -cache, including all loads and stores with any memory types. The event -counts memory accesses only when they are actually performed. For example, a -load blocked by unknown store address and later performed is only counted -once. +cache, including all loads and stores with any memory types. +The event counts memory accesses only when they are actually performed. +For example, a load blocked by unknown store address and later performed +is only counted once. The event does not include non- memory accesses, such as I/O accesses. Counter 0, 1 only .It Li L1D_ALL_REF.CACHEABLE @@ -650,8 +661,8 @@ Counts number of misses in the STLB which resulted in a completed page walk. .It Li DTLB_MISSES.STLB_HIT .Pq Event 49H , Umask 10H -Counts the number of DTLB first level misses that hit in the second level -TLB. This event is only relevant if the core contains multiple DTLB levels. +Counts the number of DTLB first level misses that hit in the second level TLB. +This event is only relevant if the core contains multiple DTLB levels. .It Li DTLB_MISSES.PDE_MISS .Pq Event 49H , Umask 20H Number of DTLB misses caused by low part of address, includes references to 2M pages because 2M pages do not use the PDE. @@ -669,17 +680,18 @@ FIFO. .It Li L1D_PREFETCH.MISS .Pq Event 4EH , Umask 02H -Counts number of hardware prefetch requests that miss the L1D. There are two -prefetchers in the L1D. A streamer, which predicts lines sequentially after -this one should be fetched, and the IP prefetcher that remembers access -patterns for the current instruction. The streamer prefetcher stops on an -L1D hit, while the IP prefetcher does not. +Counts number of hardware prefetch requests that miss the L1D. +There are two prefetchers in the L1D. +A streamer, which predicts lines sequentially after this one should be fetched, +and the IP prefetcher that remembers access patterns for the current instruction. +The streamer prefetcher stops on an L1D hit, while the IP prefetcher does not. .It Li L1D_PREFETCH.TRIGGERS .Pq Event 4EH , Umask 04H Counts number of prefetch requests triggered by the Finite State Machine and -pushed into the prefetch FIFO. Some of the prefetch requests are dropped due -to overwrites or competition between the IP index prefetcher and streamer -prefetcher. The prefetch FIFO contains 4 entries. +pushed into the prefetch FIFO. +Some of the prefetch requests are dropped due to overwrites or competition between +the IP index prefetcher and streamer prefetcher. +The prefetch FIFO contains 4 entries. .It Li L1D.REPL .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. @@ -708,12 +720,13 @@ accepted into the fill buffer. .It Li CACHE_LOCK_CYCLES.L1D_L2 .Pq Event 63H , Umask 01H -Cycle count during which the L1D and L2 are locked. A lock is asserted when -there is a locked memory access, due to uncacheable memory, a locked +Cycle count during which the L1D and L2 are locked. +A lock is asserted when there is a locked memory access, due to uncacheable memory, a locked operation that spans two cache lines, or a page walk from an uncacheable page table. -Counter 0, 1 only. L1D and L2 locks have a very high performance penalty and -it is highly recommended to avoid such accesses. +Counter 0, 1 only. +L1D and L2 locks have a very high performance penalty and it is highly recommended to +avoid such accesses. .It Li CACHE_LOCK_CYCLES.L1D .Pq Event 63H , Umask 02H Counts the number of cycles that cacheline in the L1 data cache unit is @@ -727,10 +740,11 @@ Counts all instruction fetches that hit the L1 instruction cache. .It Li L1I.MISSES .Pq Event 80H , Umask 02H -Counts all instruction fetches that miss the L1I cache. This includes -instruction cache misses, streaming buffer misses, victim cache misses and -uncacheable fetches. An instruction fetch miss is counted only once and not -once for every cycle it is outstanding. +Counts all instruction fetches that miss the L1I cache. +This includes instruction cache misses, streaming buffer misses, victim cache misses and +uncacheable fetches. +An instruction fetch miss is counted only once and not once for every cycle +it is outstanding. .It Li L1I.READS .Pq Event 80H , Umask 03H Counts all instruction fetches, including uncacheable fetches that bypass @@ -803,10 +817,10 @@ Counts taken near branches executed, but not necessarily retired. .It Li BR_INST_EXEC.ANY .Pq Event 88H , Umask 7FH -Counts all near executed branches (not necessarily retired). This includes -only instructions and not micro-op branches. Frequent branching is not -necessarily a major performance issue. However frequent branch -mispredictions may be a problem. +Counts all near executed branches (not necessarily retired). +This includes only instructions and not micro-op branches. +Frequent branching is not necessarily a major performance issue. +However frequent branch mispredictions may be a problem. .It Li BR_MISP_EXEC.COND .Pq Event 89H , Umask 01H Counts the number of mispredicted conditional near branch instructions @@ -847,10 +861,10 @@ executed, but not necessarily retired. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H -Counts the number of Allocator resource related stalls. Includes register -renaming buffer entries, memory buffer entries. In addition to resource -related stalls, this event counts some other events. Includes stalls arising -during branch misprediction recovery, such as if retirement of the +Counts the number of Allocator resource related stalls. +Includes register renaming buffer entries, memory buffer entries. +In addition to resource related stalls, this event counts some other events. +Includes stalls arising during branch misprediction recovery, such as if retirement of the mispredicted branch is delayed and stalls arising while store buffer is draining from synchronizing operations. Does not include stalls due to SuperQ (off core) queue full, too many cache @@ -861,8 +875,8 @@ .It Li RESOURCE_STALLS.RS_FULL .Pq Event A2H , Umask 04H This event counts the number of cycles when the number of instructions in -the pipeline waiting for execution reaches the limit the processor can -handle. A high count of this event indicates that there are long latency +the pipeline waiting for execution reaches the limit the processor can handle. +A high count of this event indicates that there are long latency operations in the pipe (possibly load and store operations that miss the L2 cache, or instructions dependent upon instructions further down the pipeline that have yet to retire. @@ -872,8 +886,8 @@ .Pq Event A2H , Umask 08H This event counts the number of cycles that a resource related stall will occur due to the number of store instructions reaching the limit of the -pipeline, (i.e. all store buffers are used). The stall ends when a store -instruction commits its data to the cache or memory. +pipeline, (i.e. all store buffers are used). +The stall ends when a store instruction commits its data to the cache or memory. .It Li RESOURCE_STALLS.ROB_FULL .Pq Event A2H , Umask 10H Counts the cycles of stall due to re- order buffer full. @@ -884,7 +898,8 @@ .It Li RESOURCE_STALLS.MXCSR .Pq Event A2H , Umask 40H Stalls due to the MXCSR register rename occurring to close to a previous -MXCSR rename. The MXCSR provides control and status for the MMX registers. +MXCSR rename. +The MXCSR provides control and status for the MMX registers. .It Li RESOURCE_STALLS.OTHER .Pq Event A2H , Umask 80H Counts the number of cycles while execution was stalled due to other @@ -895,14 +910,15 @@ necessarily executed or retired. .It Li BACLEAR_FORCE_IQ .Pq Event A7H , Umask 01H -Counts number of times a BACLEAR was forced by the Instruction Queue. The IQ -is also responsible for providing conditional branch prediction direction +Counts number of times a BACLEAR was forced by the Instruction Queue. +The IQ is also responsible for providing conditional branch prediction direction based on a static scheme and dynamic data provided by the L2 Branch -Prediction Unit. If the conditional branch target is not found in the Target -Array and the IQ predicts that the branch is taken, then the IQ will force -the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by -the BAC generates approximately an 8 cycle bubble in the instruction fetch -pipeline. +Prediction Unit. +If the conditional branch target is not found in the Target Array and the IQ +predicts that the branch is taken, then the IQ will force +the Branch Address Calculator to issue a BACLEAR. +Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble +in the instruction fetch pipeline. .It Li LSD.UOPS .Pq Event A8H , Umask 01H Counts the number of micro-ops delivered by loop stream detector @@ -915,30 +931,32 @@ Counts number of L1D writebacks to the uncore. .It Li UOPS_EXECUTED.PORT0 .Pq Event B1H , Umask 01H -Counts number of Uops executed that were issued on port 0. Port 0 handles -integer arithmetic, SIMD and FP add Uops. +Counts number of Uops executed that were issued on port 0. +Port 0 handles integer arithmetic, SIMD and FP add Uops. .It Li UOPS_EXECUTED.PORT1 .Pq Event B1H , Umask 02H -Counts number of Uops executed that were issued on port 1. Port 1 handles -integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops. +Counts number of Uops executed that were issued on port 1. +Port 1 handles integer arithmetic, SIMD, integer shift, FP multiply and FP divide Uops. .It Li UOPS_EXECUTED.PORT2_CORE .Pq Event B1H , Umask 04H -Counts number of Uops executed that were issued on port 2. Port 2 handles -the load Uops. This is a core count only and can not be collected per -thread. +Counts number of Uops executed that were issued on port 2. +Port 2 handles the load Uops. +This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.PORT3_CORE .Pq Event B1H , Umask 08H -Counts number of Uops executed that were issued on port 3. Port 3 handles -store Uops. This is a core count only and can not be collected per thread. +Counts number of Uops executed that were issued on port 3. +Port 3 handles store Uops. +This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.PORT4_CORE .Pq Event B1H , Umask 10H -Counts number of Uops executed that where issued on port 4. Port 4 handles -the value to be stored for the store Uops issued on port 3. This is a core -count only and can not be collected per thread. +Counts number of Uops executed that where issued on port 4. +Port 4 handles the value to be stored for the store Uops issued on port 3. +This is a core count only and can not be collected per thread. .It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 .Pq Event B1H , Umask 1FH Counts cycles when the Uops executed were issued from any ports except port -5. Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, +5. +Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls. .It Li UOPS_EXECUTED.PORT5 @@ -946,8 +964,8 @@ Counts number of Uops executed that where issued on port 5. .It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES .Pq Event B1H , Umask 3FH -Counts cycles when the Uops are executing. Use Cmask=1 for active cycles; -Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled +Counts cycles when the Uops are executing. +Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls. .It Li UOPS_EXECUTED.PORT015 .Pq Event B1H , Umask 40H @@ -986,7 +1004,8 @@ See Table A-1 Notes: INST_RETIRED.ANY is counted by a designated fixed counter. INST_RETIRED.ANY_P is counted by a programmable counter and is an -architectural performance event. Event is supported if CPUID.A.EBX[1] = 0. +architectural performance event. +Event is supported if CPUID.A.EBX[1] = 0. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions. .It Li INST_RETIRED.X87 @@ -1001,10 +1020,10 @@ .It Li UOPS_RETIRED.ANY .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2, -others=1; maximum count of 8 per cycle). Most instructions are composed of -one or two micro-ops. Some instructions are decoded into longer sequences -such as repeat instructions, floating point transcendental instructions, and -assists. +others=1; maximum count of 8 per cycle). +Most instructions are composed of one or two micro-ops. +Some instructions are decoded into longer sequences such as repeat instructions, +floating point transcendental instructions, and assists. Use cmask=1 and invert to count active cycles or stalled cycles .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H @@ -1022,7 +1041,8 @@ .Pq Event C3H , Umask 04H Counts the number of times that a program writes to a code section. Self-modifying code causes a sever penalty in all Intel 64 and IA-32 -processors. The modified cache line is written back to the L2 and L3caches. +processors. +The modified cache line is written back to the L2 and L3caches. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H See Table A-1 @@ -1072,24 +1092,25 @@ cache. .It Li MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM .Pq Event CBH , Umask 08H -Counts number of retired loads that hit in a sibling core's L2 (on die -core). Since the L3 is inclusive of all cores on the package, this is an L3 -hit. This counts both clean or modified hits. +Counts number of retired loads that hit in a sibling core's L2 (on die core). +Since the L3 is inclusive of all cores on the package, this is an L3 hit. +This counts both clean or modified hits. .It Li MEM_LOAD_RETIRED.L3_MISS .Pq Event CBH , Umask 10H -Counts number of retired loads that miss the L3 cache. The load was -satisfied by a remote socket, local memory or an IOH. +Counts number of retired loads that miss the L3 cache. +The load was satisfied by a remote socket, local memory or an IOH. .It Li MEM_LOAD_RETIRED.HIT_LFB .Pq Event CBH , Umask 40H Counts number of retired loads that miss the L1D and the address is located -in an allocated line fill buffer and will soon be committed to cache. This -is counting secondary L1D misses. +in an allocated line fill buffer and will soon be committed to cache. +This is counting secondary L1D misses. .It Li MEM_LOAD_RETIRED.DTLB_MISS .Pq Event CBH , Umask 80H -Counts the number of retired loads that missed the DTLB. The DTLB miss is -not counted if the load operation causes a fault. This event counts loads -from cacheable memory only. The event does not count loads by software -prefetches. Counts both primary and secondary misses to the TLB. +Counts the number of retired loads that missed the DTLB. +The DTLB miss is not counted if the load operation causes a fault. +This event counts loads from cacheable memory only. +The event does not count loads by software prefetches. +Counts both primary and secondary misses to the TLB. .It Li FP_MMX_TRANS.TO_FP .Pq Event CCH , Umask 01H Counts the first floating-point instruction following any MMX instruction. @@ -1097,29 +1118,30 @@ floating-point and MMX technology states. .It Li FP_MMX_TRANS.TO_MMX .Pq Event CCH , Umask 02H -Counts the first MMX instruction following a floating-point instruction. You -can use this event to estimate the penalties for the transitions between +Counts the first MMX instruction following a floating-point instruction. +You can use this event to estimate the penalties for the transitions between floating-point and MMX technology states. .It Li FP_MMX_TRANS.ANY .Pq Event CCH , Umask 03H Counts all transitions from floating point to MMX instructions and from MMX -instructions to floating point instructions. You can use this event to -estimate the penalties for the transitions between floating-point and MMX -technology states. +instructions to floating point instructions. +You can use this event to estimate the penalties for the transitions between +floating-point and MMX technology states. .It Li MACRO_INSTS.DECODED .Pq Event D0H , Umask 01H Counts the number of instructions decoded, (but not necessarily executed or retired). .It Li UOPS_DECODED.MS .Pq Event D1H , Umask 02H -Counts the number of Uops decoded by the Microcode Sequencer, MS. The MS -delivers uops when the instruction is more than 4 uops long or a microcode +Counts the number of Uops decoded by the Microcode Sequencer, MS. +The MS delivers uops when the instruction is more than 4 uops long or a microcode assist is occurring. .It Li UOPS_DECODED.ESP_FOLDING .Pq Event D1H , Umask 04H Counts number of stack pointer (ESP) instructions decoded: push , pop , call -, ret, etc. ESP instructions do not generate a Uop to increment or decrement -ESP. Instead, they update an ESP_Offset register that keeps track of the +, ret, etc. +ESP instructions do not generate a Uop to increment or decrement ESP. +Instead, they update an ESP_Offset register that keeps track of the delta to the current value of the ESP register. .It Li UOPS_DECODED.ESP_SYNC .Pq Event D1H , Umask 08H @@ -1129,8 +1151,8 @@ .It Li RAT_STALLS.FLAGS .Pq Event D2H , Umask 01H Counts the number of cycles during which execution stalled due to several -reasons, one of which is a partial flag register stall. A partial register -stall may occur when two conditions are met: 1) an instruction modifies +reasons, one of which is a partial flag register stall. +A partial register stall may occur when two conditions are met: 1) an instruction modifies some, but not all, of the flags in the flag register and 2) the next instruction, which depends on flags, depends on flags that were not modified by this instruction. @@ -1142,30 +1164,33 @@ .It Li RAT_STALLS.ROB_READ_PORT .Pq Event D2H , Umask 04H Counts the number of cycles when ROB read port stalls occurred, which did -not allow new micro-ops to enter the out-of-order pipeline. Note that, at -this stage in the pipeline, additional stalls may occur at the same cycle -and prevent the stalled micro-ops from entering the pipe. In such a case, -micro-ops retry entering the execution pipe in the next cycle and the -ROB-read port stall is counted again. +not allow new micro-ops to enter the out-of-order pipeline. +Note that, at this stage in the pipeline, additional stalls may occur at +the same cycle and prevent the stalled micro-ops from entering the pipe. +In such a case, micro-ops retry entering the execution pipe in the next +cycle and the ROB-read port stall is counted again. .It Li RAT_STALLS.SCOREBOARD .Pq Event D2H , Umask 08H Counts the cycles where we stall due to microarchitecturally required -serialization. Microcode scoreboarding stalls. +serialization. +Microcode scoreboarding stalls. .It Li RAT_STALLS.ANY .Pq Event D2H , Umask 0FH Counts all Register Allocation Table stall cycles due to: Cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the -execution pipe. Cycles when partial register stalls occurred Cycles when -flag stalls occurred Cycles floating-point unit (FPU) status word stalls -occurred. To count each of these conditions separately use the events: +execution pipe. +Cycles when partial register stalls occurred Cycles when flag stalls occurred +Cycles floating-point unit (FPU) status word stalls occurred. +To count each of these conditions separately use the events: RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and RAT_STALLS.FPSW. .It Li SEG_RENAME_STALLS .Pq Event D4H , Umask 01H Counts the number of stall cycles due to the lack of renaming resources for -the ES, DS, FS, and GS segment registers. If a segment is renamed but not -retired and a second update to the same segment occurs, a stall occurs in -the front-end of the pipeline until the renamed segment retires. +the ES, DS, FS, and GS segment registers. +If a segment is renamed but not retired and a second update to the same +segment occurs, a stall occurs in the front-end of the pipeline until the +renamed segment retires. .It Li ES_REG_RENAMES .Pq Event D5H , Umask 01H Counts the number of times the ES segment register is renamed. @@ -1183,17 +1208,19 @@ .Pq Event E6H , Umask 01H Counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is -corrected by the Branch Address Calculator at the front end. This can occur -if the code has many branches such that they cannot be consumed by the BPU. +corrected by the Branch Address Calculator at the front end. +This can occur if the code has many branches such that they cannot be +consumed by the BPU. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble -in the instruction fetch pipeline. The effect on total execution time -depends on the surrounding code. +in the instruction fetch pipeline. +The effect on total execution time depends on the surrounding code. .It Li BACLEAR.BAD_TARGET .Pq Event E6H , Umask 02H Counts number of Branch Address Calculator clears (BACLEAR) asserted due to conditional branch instructions in which there was a target hit but the -direction was wrong. Each BACLEAR asserted by the BAC generates -approximately an 8 cycle bubble in the instruction fetch pipeline. +direction was wrong. +Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in +the instruction fetch pipeline. .It Li BPU_CLEARS.EARLY .Pq Event E8H , Umask 01H Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken @@ -1201,8 +1228,8 @@ The BPU clear leads to 2 cycle bubble in the Front End. .It Li BPU_CLEARS.LATE .Pq Event E8H , Umask 02H -Counts late Branch Prediction Unit clears due to Most Recently Used -conflicts. The PBU clear leads to a 3 cycle bubble in the Front End. +Counts late Branch Prediction Unit clears due to Most Recently Used conflicts. +The PBU clear leads to a 3 cycle bubble in the Front End. .It Li L2_TRANSACTIONS.LOAD .Pq Event F0H , Umask 01H Counts L2 load operations due to HW prefetch or demand loads. @@ -1259,12 +1286,13 @@ Counts the number of SQ lock splits across a cache line. .It Li SQ_FULL_STALL_CYCLES .Pq Event F6H , Umask 01H -Counts cycles the Super Queue is full. Neither of the threads on this core -will be able to access the uncore. +Counts cycles the Super Queue is full. +Neither of the threads on this core will be able to access the uncore. .It Li FP_ASSIST.ALL .Pq Event F7H , Umask 01H Counts the number of floating point operations executed that required -micro-code assist intervention. Assists are required in the following cases: +micro-code assist intervention. +Assists are required in the following cases: SSE instructions, (Denormal input when the DAZ flag is off or Underflow result when the FTZ flag is off): x87 instructions, (NaN or denormal are loaded to a register or used as input from memory, Division by 0 or @@ -1361,8 +1389,8 @@ .It Li HW_INT.CYCLES_PENDING_AND_MASKED .Pq Event 04H , Umask 04H Counts number of L2 store RFO requests where the cache line to be loaded is -in the E (exclusive) state. The L1D prefetcher does not issue a RFO -prefetch. +in the E (exclusive) state. +The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request .It Li HW_INT.CYCLES_PENDING_AND_MASKED .Pq Event 27H , Umask 04H @@ -1403,34 +1431,34 @@ Counts store fence cycles .It Li EPT.EPDE_MISS .Pq Event 4FH , Umask 02H -Counts Extended Page Directory Entry misses. The Extended Page Directory -cache is used by Virtual Machine operating systems while the guest operating -systems use the standard TLB caches. +Counts Extended Page Directory Entry misses. +The Extended Page Directory cache is used by Virtual Machine operating +systems while the guest operating systems use the standard TLB caches. .It Li EPT.EPDPE_HIT .Pq Event 4FH , Umask 04H Counts Extended Page Directory Pointer Entry hits. .It Li EPT.EPDPE_MISS .Pq Event 4FH , Umask 08H -Counts Extended Page Directory Pointer Entry misses. T +Counts Extended Page Directory Pointer Entry misses. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA .Pq Event 60H , Umask 01H -Counts weighted cycles of offcore demand data read requests. Does not -include L2 prefetch requests. +Counts weighted cycles of offcore demand data read requests. +Does not include L2 prefetch requests. counter 0 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE .Pq Event 60H , Umask 02H -Counts weighted cycles of offcore demand code read requests. Does not -include L2 prefetch requests. +Counts weighted cycles of offcore demand code read requests. +Does not include L2 prefetch requests. counter 0 .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO .Pq Event 60H , Umask 04H -Counts weighted cycles of offcore demand RFO requests. Does not include L2 -prefetch requests. +Counts weighted cycles of offcore demand RFO requests. +Does not include L2 prefetch requests. counter 0 .It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ .Pq Event 60H , Umask 08H -Counts weighted cycles of offcore read requests of any kind. Include L2 -prefetch requests. +Counts weighted cycles of offcore read requests of any kind. +Include L2 prefetch requests. counter 0 .It Li IFU_IVC.FULL .Pq Event 81H , Umask 01H @@ -1463,22 +1491,24 @@ Counts number of completed large page walks due to misses in the STLB. .It Li ITLB_MISSES.LARGE_WALK_COMPLETED .Pq Event 01H , Umask 80H -Counts number of offcore demand data read requests. Does not count L2 -prefetch requests. +Counts number of offcore demand data read requests. +Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.DEMAND.READ_CODE .Pq Event B0H , Umask 02H -Counts number of offcore demand code read requests. Does not count L2 -prefetch requests. +Counts number of offcore demand code read requests. +Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.DEMAND.RFO .Pq Event B0H , Umask 04H -Counts number of offcore demand RFO requests. Does not count L2 prefetch -requests. +Counts number of offcore demand RFO requests. +Does not count L2 prefetch requests. .It Li OFFCORE_REQUESTS.ANY.READ .Pq Event B0H , Umask 08H -Counts number of offcore read requests. Includes L2 prefetch requests. +Counts number of offcore read requests. +Includes L2 prefetch requests. .It Li OFFCORE_REQUESTS.ANY.RFO .Pq Event B0H , Umask 10H -Counts number of offcore RFO requests. Includes L2 prefetch requests. +Counts number of offcore RFO requests. +Includes L2 prefetch requests. .It Li OFFCORE_REQUESTS.UNCACHED_MEM .Pq Event B0H , Umask 20H Counts number of offcore uncached memory requests. @@ -1487,23 +1517,23 @@ Counts all offcore requests. .It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA .Pq Event B3H , Umask 01H -Counts weighted cycles of snoopq requests for data. Counter 0 only -Use cmask=1 to count cycles not empty. +Counts weighted cycles of snoopq requests for data. +Counter 0 only Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE .Pq Event B3H , Umask 02H -Counts weighted cycles of snoopq invalidate requests. Counter 0 only -Use cmask=1 to count cycles not empty. +Counts weighted cycles of snoopq invalidate requests. +Counter 0 only Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE .Pq Event B3H , Umask 04H -Counts weighted cycles of snoopq requests for code. Counter 0 only -Use cmask=1 to count cycles not empty. +Counts weighted cycles of snoopq requests for code. +Counter 0 only Use cmask=1 to count cycles not empty. .It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE .Pq Event BAH , Umask 04H Counts number of TPR reads .It Li PIC_ACCESSES.TPR_WRITES .Pq Event BAH , Umask 02H -Counts number of TPR writes -one or two micro-ops. Some instructions are decoded into longer sequences +Counts number of TPR writes one or two micro-ops. +Some instructions are decoded into longer sequences .It Li MACHINE_CLEARS.FUSION_ASSIST .Pq Event C3H , Umask 10H Counts the number of macro-fusion assists diff --git a/lib/libpmc/pmc.corei7uc.3 b/lib/libpmc/pmc.corei7uc.3 --- a/lib/libpmc/pmc.corei7uc.3 +++ b/lib/libpmc/pmc.corei7uc.3 @@ -115,8 +115,8 @@ Uncore cycles Global Queue write tracker is full. .It Li GQ_CYCLES_FULL.PEER_PROBE_TRACKER .Pq Event 00H , Umask 04H -Uncore cycles Global Queue peer probe tracker is full. The peer probe -tracker queue tracks snoops from the IOH and remote sockets. +Uncore cycles Global Queue peer probe tracker is full. +The peer probe tracker queue tracks snoops from the IOH and remote sockets. .It Li GQ_CYCLES_NOT_EMPTY.READ_TRACKER .Pq Event 01H , Umask 01H Uncore cycles were Global Queue read tracker has at least one valid entry. @@ -125,88 +125,93 @@ Uncore cycles were Global Queue write tracker has at least one valid entry. .It Li GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER .Pq Event 01H , Umask 04H -Uncore cycles were Global Queue peer probe tracker has at least one valid -entry. The peer probe tracker queue tracks IOH and remote socket snoops. +Uncore cycles were Global Queue peer probe tracker has at least one valid entry. +The peer probe tracker queue tracks IOH and remote socket snoops. .It Li GQ_ALLOC.READ_TRACKER .Pq Event 03H , Umask 01H -Counts the number of tread tracker allocate to deallocate entries. The GQ -read tracker allocate to deallocate occupancy count is divided by the count -to obtain the average read tracker latency. +Counts the number of tread tracker allocate to deallocate entries. +The GQ read tracker allocate to deallocate occupancy count is divided +by the count to obtain the average read tracker latency. .It Li GQ_ALLOC.RT_L3_MISS .Pq Event 03H , Umask 02H Counts the number GQ read tracker entries for which a full cache line read -has missed the L3. The GQ read tracker L3 miss to fill occupancy count is -divided by this count to obtain the average cache line read L3 miss latency. +has missed the L3. +The GQ read tracker L3 miss to fill occupancy count is divided by this count +to obtain the average cache line read L3 miss latency. The latency represents the time after which the L3 has determined that the -cache line has missed. The time between a GQ read tracker allocation and the -L3 determining that the cache line has missed is the average L3 hit latency. +cache line has missed. +The time between a GQ read tracker allocation and the L3 determining that the +cache line has missed is the average L3 hit latency. The total L3 cache line read miss latency is the hit latency + L3 miss latency. .It Li GQ_ALLOC.RT_TO_L3_RESP .Pq Event 03H , Umask 04H Counts the number of GQ read tracker entries that are allocated in the read -tracker queue that hit or miss the L3. The GQ read tracker L3 hit occupancy -count is divided by this count to obtain the average L3 hit latency. +tracker queue that hit or miss the L3. +The GQ read tracker L3 hit occupancy count is divided by this count to obtain +the average L3 hit latency. .It Li GQ_ALLOC.RT_TO_RTID_ACQUIRED .Pq Event 03H , Umask 08H Counts the number of GQ read tracker entries that are allocated in the read -tracker, have missed in the L3 and have not acquired a Request Transaction -ID. The GQ read tracker L3 miss to RTID acquired occupancy count is +tracker, have missed in the L3 and have not acquired a Request Transaction ID. +The GQ read tracker L3 miss to RTID acquired occupancy count is divided by this count to obtain the average latency for a read L3 miss to acquire an RTID. .It Li GQ_ALLOC.WT_TO_RTID_ACQUIRED .Pq Event 03H , Umask 10H Counts the number of GQ write tracker entries that are allocated in the write tracker, have missed in the L3 and have not acquired a Request -Transaction ID. The GQ write tracker L3 miss to RTID occupancy count is -divided by this count to obtain the average latency for a write L3 miss to -acquire an RTID. +Transaction ID. +The GQ write tracker L3 miss to RTID occupancy count is divided by this count +to obtain the average latency for a write L3 miss to acquire an RTID. .It Li GQ_ALLOC.WRITE_TRACKER .Pq Event 03H , Umask 20H Counts the number of GQ write tracker entries that are allocated in the -write tracker queue that miss the L3. The GQ write tracker occupancy count -is divided by the this count to obtain the average L3 write miss latency. +write tracker queue that miss the L3. +The GQ write tracker occupancy count is divided by the this count to obtain the average L3 write miss latency. .It Li GQ_ALLOC.PEER_PROBE_TRACKER .Pq Event 03H , Umask 40H Counts the number of GQ peer probe tracker (snoop) entries that are -allocated in the peer probe tracker queue that miss the L3. The GQ peer -probe occupancy count is divided by this count to obtain the average L3 peer +allocated in the peer probe tracker queue that miss the L3. +The GQ peer probe occupancy count is divided by this count to obtain the average L3 peer probe miss latency. .It Li GQ_DATA.FROM_QPI .Pq Event 04H , Umask 01H Cycles Global Queue Quickpath Interface input data port is busy importing -data from the Quickpath Interface. Each cycle the input port can transfer 8 -or 16 bytes of data. +data from the Quickpath Interface. +Each cycle the input port can transfer 8 or 16 bytes of data. .It Li GQ_DATA.FROM_QMC .Pq Event 04H , Umask 02H Cycles Global Queue Quickpath Memory Interface input data port is busy -importing data from the Quickpath Memory Interface. Each cycle the input -port can transfer 8 or 16 bytes of data. +importing data from the Quickpath Memory Interface. +Each cycle the input port can transfer 8 or 16 bytes of data. .It Li GQ_DATA.FROM_L3 .Pq Event 04H , Umask 04H -Cycles GQ L3 input data port is busy importing data from the Last Level -Cache. Each cycle the input port can transfer 32 bytes of data. +Cycles GQ L3 input data port is busy importing data from the Last Level Cache. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.FROM_CORES_02 .Pq Event 04H , Umask 08H Cycles GQ Core 0 and 2 input data port is busy importing data from processor -cores 0 and 2. Each cycle the input port can transfer 32 bytes of data. +cores 0 and 2. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.FROM_CORES_13 .Pq Event 04H , Umask 10H Cycles GQ Core 1 and 3 input data port is busy importing data from processor -cores 1 and 3. Each cycle the input port can transfer 32 bytes of data. +cores 1 and 3. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.TO_QPI_QMC .Pq Event 05H , Umask 01H Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath -Interface or Quickpath Memory Interface. Each cycle the output port can -transfer 32 bytes of data. +Interface or Quickpath Memory Interface. +Each cycle the output port can transfer 32 bytes of data. .It Li GQ_DATA.TO_L3 .Pq Event 05H , Umask 02H Cycles GQ L3 output data port is busy sending data to the Last Level Cache. Each cycle the output port can transfer 32 bytes of data. .It Li GQ_DATA.TO_CORES .Pq Event 05H , Umask 04H -Cycles GQ Core output data port is busy sending data to the Cores. Each -cycle the output port can transfer 32 bytes of data. +Cycles GQ Core output data port is busy sending data to the Cores. +Each cycle the output port can transfer 32 bytes of data. .It Li SNP_RESP_TO_LOCAL_HOME.I_STATE .Pq Event 06H , Umask 01H Number of snoop responses to the local home that L3 does not have the @@ -218,14 +223,15 @@ .It Li SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE .Pq Event 06H , Umask 04H Number of responses to code or data read snoops to the local home that the -L3 has the referenced cache line in the E state. The L3 cache line state is -changed to the S state and the line is forwarded to the local home in the S -state. +L3 has the referenced cache line in the E state. +The L3 cache line state is changed to the S state and the line is +forwarded to the local home in the S state. .It Li SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE .Pq Event 06H , Umask 08H Number of responses to read invalidate snoops to the local home that the L3 -has the referenced cache line in the M state. The L3 cache line state is -invalidated and the line is forwarded to the local home in the M state. +has the referenced cache line in the M state. +The L3 cache line state is invalidated and the line is forwarded to the +local home in the M state. .It Li SNP_RESP_TO_LOCAL_HOME.CONFLICT .Pq Event 06H , Umask 10H Number of conflict snoop responses sent to the local home. @@ -244,14 +250,15 @@ .It Li SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE .Pq Event 07H , Umask 04H Number of responses to code or data read snoops to a remote home that the L3 -has the referenced cache line in the E state. The L3 cache line state is -changed to the S state and the line is forwarded to the remote home in the S -state. +has the referenced cache line in the E state. +The L3 cache line state is changed to the S state and the line is forwarded to +the remote home in the S state. .It Li SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE .Pq Event 07H , Umask 08H Number of responses to read invalidate snoops to a remote home that the L3 -has the referenced cache line in the M state. The L3 cache line state is -invalidated and the line is forwarded to the remote home in the M state. +has the referenced cache line in the M state. +The L3 cache line state is invalidated and the line is forwarded to the +remote home in the M state. .It Li SNP_RESP_TO_REMOTE_HOME.CONFLICT .Pq Event 07H , Umask 10H Number of conflict snoop responses sent to the local home. @@ -267,8 +274,8 @@ Number of code read, data read and RFO requests that hit in the L3 .It Li L3_HITS.WRITE .Pq Event 08H , Umask 02H -Number of writeback requests that hit in the L3. Writebacks from the cores -will always result in L3 hits due to the inclusive property of the L3. +Number of writeback requests that hit in the L3. +Writebacks from the cores will always result in L3 hits due to the inclusive property of the L3. .It Li L3_HITS.PROBE .Pq Event 08H , Umask 04H Number of snoops from IOH or remote sockets that hit in the L3. @@ -280,9 +287,9 @@ Number of code read, data read and RFO requests that miss the L3. .It Li L3_MISS.WRITE .Pq Event 09H , Umask 02H -Number of writeback requests that miss the L3. Should always be zero as -writebacks from the cores will always result in L3 hits due to the inclusive -property of the L3. +Number of writeback requests that miss the L3. +Should always be zero as writebacks from the cores will always result in +L3 hits due to the inclusive property of the L3. .It Li L3_MISS.PROBE .Pq Event 09H , Umask 04H Number of snoops from IOH or remote sockets that miss the L3. @@ -291,9 +298,9 @@ Number of reads and writes that miss the L3. .It Li L3_LINES_IN.M_STATE .Pq Event 0AH , Umask 01H -Counts the number of L3 lines allocated in M state. The only time a cache -line is allocated in the M state is when the line was forwarded in M state -is forwarded due to a Snoop Read Invalidate Own request. +Counts the number of L3 lines allocated in M state. +The only time a cache line is allocated in the M state is when the line +was forwarded in M state is forwarded due to a Snoop Read Invalidate Own request. .It Li L3_LINES_IN.E_STATE .Pq Event 0AH , Umask 02H Counts the number of L3 lines allocated in E state. @@ -308,8 +315,8 @@ Counts the number of L3 lines allocated in any state. .It Li L3_LINES_OUT.M_STATE .Pq Event 0BH , Umask 01H -Counts the number of L3 lines victimized that were in the M state. When the -victim cache line is in M state, the line is written to its home cache agent +Counts the number of L3 lines victimized that were in the M state. +When the victim cache line is in M state, the line is written to its home cache agent which can be either local or remote. .It Li L3_LINES_OUT.E_STATE .Pq Event 0BH , Umask 02H @@ -378,32 +385,38 @@ .It Li QHL_ADDRESS_CONFLICTS.2WAY .Pq Event 24H , Umask 02H Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 -conflicts. The AAT is a structure that tracks requests that are in conflict. -The requests themselves are in the home tracker entries. The count is -reported when an AAT entry deallocates. +conflicts. +The AAT is a structure that tracks requests that are in conflict. +The requests themselves are in the home tracker entries. +The count is reported when an AAT entry deallocates. .It Li QHL_ADDRESS_CONFLICTS.3WAY .Pq Event 24H , Umask 04H Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 -conflicts. The AAT is a structure that tracks requests that are in conflict. -The requests themselves are in the home tracker entries. The count is -reported when an AAT entry deallocates. +conflicts. +The AAT is a structure that tracks requests that are in conflict. +The requests themselves are in the home tracker entries. +The count is reported when an AAT entry deallocates. .It Li QHL_CONFLICT_CYCLES.IOH .Pq Event 25H , Umask 01H Counts cycles the Quickpath Home Logic IOH Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_CONFLICT_CYCLES.REMOTE .Pq Event 25H , Umask 02H Counts cycles the Quickpath Home Logic Remote Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_CONFLICT_CYCLES.LOCAL .Pq Event 25H , Umask 04H Counts cycles the Quickpath Home Logic Local Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_TO_QMC_BYPASS .Pq Event 26H , Umask 01H Counts number or requests to the Quickpath Memory Controller that bypass the -Quickpath Home Logic. All local accesses can be bypassed. For remote -requests, only read requests can be bypassed. +Quickpath Home Logic. +All local accesses can be bypassed. +For remote requests, only read requests can be bypassed. .It Li QMC_NORMAL_FULL.READ.CH0 .Pq Event 27H , Umask 01H Uncore cycles all the entries in the DRAM channel 0 medium or low priority @@ -500,23 +513,27 @@ .It Li QMC_NORMAL_READS.CH0 .Pq Event 2CH , Umask 01H Counts the number of Quickpath Memory Controller channel 0 medium and low -priority read requests. The QMC channel 0 normal read occupancy divided by -this count provides the average QMC channel 0 read latency. +priority read requests. +The QMC channel 0 normal read occupancy divided by this count provides the +average QMC channel 0 read latency. .It Li QMC_NORMAL_READS.CH1 .Pq Event 2CH , Umask 02H Counts the number of Quickpath Memory Controller channel 1 medium and low -priority read requests. The QMC channel 1 normal read occupancy divided by -this count provides the average QMC channel 1 read latency. +priority read requests. +The QMC channel 1 normal read occupancy divided by this count provides the +average QMC channel 1 read latency. .It Li QMC_NORMAL_READS.CH2 .Pq Event 2CH , Umask 04H Counts the number of Quickpath Memory Controller channel 2 medium and low -priority read requests. The QMC channel 2 normal read occupancy divided by -this count provides the average QMC channel 2 read latency. +priority read requests. +The QMC channel 2 normal read occupancy divided by this count provides the +average QMC channel 2 read latency. .It Li QMC_NORMAL_READS.ANY .Pq Event 2CH , Umask 07H Counts the number of Quickpath Memory Controller medium and low priority -read requests. The QMC normal read occupancy divided by this count provides -the average QMC read latency. +read requests. +The QMC normal read occupancy divided by this count provides the average +QMC read latency. .It Li QMC_HIGH_PRIORITY_READS.CH0 .Pq Event 2DH , Umask 01H Counts the number of Quickpath Memory Controller channel 0 high priority @@ -587,32 +604,32 @@ Counts number of DRAM cancel requests. .It Li QMC_PRIORITY_UPDATES.CH0 .Pq Event 31H , Umask 01H -Counts number of DRAM channel 0 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to -expedite the request. +Counts number of DRAM channel 0 priority updates. +A priority update occurs when an ISOC high or critical request +is received by the QHL and there is a matching request with normal priority +that has already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.CH1 .Pq Event 31H , Umask 02H -Counts number of DRAM channel 1 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to -expedite the request. +Counts number of DRAM channel 1 priority updates. +A priority update occurs when an ISOC high or critical request is received by +the QHL and there is a matching request with normal priority that has +already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.CH2 .Pq Event 31H , Umask 04H -Counts number of DRAM channel 2 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to -expedite the request. +Counts number of DRAM channel 2 priority updates. +A priority update occurs when an ISOC high or critical request is received by +the QHL and there is a matching request with normal priority that has +already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.ANY .Pq Event 31H , Umask 07H -Counts number of DRAM priority updates. A priority update occurs when an -ISOC high or critical request is received by the QHL and there is a matching -request with normal priority that has already been issued to the QMC. In -this instance, the QHL will send a priority update to QMC to expedite the -request. +Counts number of DRAM priority updates. +A priority update occurs when an ISOC high or critical request is received by +the QHL and there is a matching request with normal priority that has +already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QHL_FRC_ACK_CNFLTS.LOCAL .Pq Event 33H , Umask 04H Counts number of Force Acknowledge Conflict messages sent by the Quickpath @@ -620,99 +637,99 @@ .It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0 .Pq Event 40H , Umask 01H Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0 .Pq Event 40H , Umask 02H Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0 .Pq Event 40H , Umask 04H Counts cycles the Quickpath outbound link 0 non-data response virtual -channel is stalled due to lack of a VNA and VN0 credit. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1 .Pq Event 40H , Umask 08H Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1 .Pq Event 40H , Umask 10H Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1 .Pq Event 40H , Umask 20H Counts cycles the Quickpath outbound link 1 non-data response virtual -channel is stalled due to lack of a VNA and VN0 credit. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_0 .Pq Event 40H , Umask 07H Counts cycles the Quickpath outbound link 0 virtual channels are stalled due -to lack of a VNA and VN0 credit. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_1 .Pq Event 40H , Umask 38H Counts cycles the Quickpath outbound link 1 virtual channels are stalled due -to lack of a VNA and VN0 credit. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0 .Pq Event 41H , Umask 01H Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is -stalled due to lack of VNA and VN0 credits. Note that this event does not -filter out when a flit would not have been selected for arbitration because -another virtual channel is getting arbitrated. +stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0 .Pq Event 41H , Umask 02H Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0 .Pq Event 41H , Umask 04H Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1 .Pq Event 41H , Umask 08H Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is -stalled due to lack of VNA and VN0 credits. Note that this event does not -filter out when a flit would not have been selected for arbitration because -another virtual channel is getting arbitrated. +stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1 .Pq Event 41H , Umask 10H Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1 .Pq Event 41H , Umask 20H Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.LINK_0 .Pq Event 41H , Umask 07H Counts cycles the Quickpath outbound link 0 virtual channels are stalled due -to lack of VNA and VN0 credits. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.LINK_1 .Pq Event 41H , Umask 38H Counts cycles the Quickpath outbound link 1 virtual channels are stalled due -to lack of VNA and VN0 credits. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been +selected for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_HEADER.BUSY.LINK_0 .Pq Event 42H , Umask 02H Number of cycles that the header buffer in the Quickpath Interface outbound @@ -733,49 +750,55 @@ does not have any available entries. .It Li DRAM_OPEN.CH0 .Pq Event 60H , Umask 01H -Counts number of DRAM Channel 0 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 0 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_OPEN.CH1 .Pq Event 60H , Umask 02H -Counts number of DRAM Channel 1 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 1 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_OPEN.CH2 .Pq Event 60H , Umask 04H -Counts number of DRAM Channel 2 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 2 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_PAGE_CLOSE.CH0 .Pq Event 61H , Umask 01H DRAM channel 0 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_CLOSE.CH1 .Pq Event 61H , Umask 02H DRAM channel 1 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_CLOSE.CH2 .Pq Event 61H , Umask 04H DRAM channel 2 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH0 .Pq Event 62H , Umask 01H Counts the number of precharges (PRE) that were issued to DRAM channel 0 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and +another page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH1 .Pq Event 62H , Umask 02H Counts the number of precharges (PRE) that were issued to DRAM channel 1 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and +another page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH2 .Pq Event 62H , Umask 04H Counts the number of precharges (PRE) that were issued to DRAM channel 2 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and +another page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_READ_CAS.CH0 .Pq Event 63H , Umask 01H Counts the number of times a read CAS command was issued on DRAM channel 0. @@ -820,34 +843,40 @@ where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_REFRESH.CH0 .Pq Event 65H , Umask 01H -Counts number of DRAM channel 0 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be +Counts number of DRAM channel 0 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_REFRESH.CH1 .Pq Event 65H , Umask 02H -Counts number of DRAM channel 1 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be +Counts number of DRAM channel 1 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_REFRESH.CH2 .Pq Event 65H , Umask 04H -Counts number of DRAM channel 2 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be +Counts number of DRAM channel 2 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_PRE_ALL.CH0 .Pq Event 66H , Umask 01H Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go +into a power down mode. .It Li DRAM_PRE_ALL.CH1 .Pq Event 66H , Umask 02H Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go +into a power down mode. .It Li DRAM_PRE_ALL.CH2 .Pq Event 66H , Umask 04H Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go +into a power down mode. .El .Sh SEE ALSO .Xr pmc 3 , diff --git a/lib/libpmc/pmc.iaf.3 b/lib/libpmc/pmc.iaf.3 --- a/lib/libpmc/pmc.iaf.3 +++ b/lib/libpmc/pmc.iaf.3 @@ -55,7 +55,6 @@ .%D July 2008 .%Q "Intel Corporation" .Re -.Pp .Ss PMC Capabilities Fixed-function PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" diff --git a/lib/libpmc/pmc.ivybridge.3 b/lib/libpmc/pmc.ivybridge.3 --- a/lib/libpmc/pmc.ivybridge.3 +++ b/lib/libpmc/pmc.ivybridge.3 @@ -91,12 +91,12 @@ .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial -cachelines as well as demand data page table entry cacheline reads. Does not -count L2 data read prefetches or instruction fetches. +cachelines as well as demand data page table entry cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. @@ -144,8 +144,9 @@ -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) @@ -155,14 +156,15 @@ This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured @@ -225,18 +227,19 @@ Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H -Number of flags-merge uops allocated. Such uops adds delay. +Number of flags-merge uops allocated. +Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H -Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 -sources + immediate) regardless if as a result of LEA instruction or not. +Number of slow LEA or similar uops allocated. +Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SINGLE_MUL .Pq Event 0EH , Umask 40H Number of multiply packed/scalar single precision uops allocated. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H , Umask 01H -Cycles that the divider is active, includes INT and FP. Set 'edge =1, -cmask=1' to count the number of divides. +Cycles that the divider is active, includes INT and FP. +Set 'edge =1, cmask=1' to count the number of divides. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 01H Demand Data Read requests that hit L2 cache. @@ -302,16 +305,16 @@ .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. -The thread enters the halt state when it is running the HLT instruction. The -core frequency may change from time to time due to power or thermal +The thread enters the halt state when it is running the HLT instruction. +The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H -Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 -and Edge =1 to count occurrences. +Increments the number of outstanding L1D misses every cycle. +Set Cmaks = 1 and Edge =1 to count occurrences. Counter 2 only. Set Cmask = 1 to count cycles. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK @@ -364,20 +367,20 @@ Counts load operations that missed 1st level DTLB but hit the 2nd level. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H -Offcore outstanding Demand Data Read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding Demand Data Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD .Pq Event 60H , Umask 02H -Offcore outstanding Demand Code Read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding Demand Code Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H -Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to -count cycles. +Offcore outstanding RFO store transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H -Offcore outstanding cacheable data read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding cacheable data read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. @@ -399,31 +402,37 @@ Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H -Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set -Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. +Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. +Set Cmask = 1 to count cycles. +Add Edge=1 to count # of delivery. Can combine Umask 04H, 08H. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H -Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set -Cmask = 1 to count cycles. +Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. +Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or -MITE. Set Cmask = 1 to count cycles. +MITE. +Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered at least one uops. Set Cmask = 1. +Counts cycles DSB is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered four uops. Set Cmask = 4. +Counts cycles DSB is delivered four uops. +Set Cmask = 4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered at least one uops. Set Cmask = 1. +Counts cycles MITE is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered four uops. Set Cmask = 4. +Counts cycles MITE is delivered four uops. +Set Cmask = 4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. @@ -442,7 +451,8 @@ Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. @@ -577,8 +587,8 @@ Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.THREAD .Pq Event B1H , Umask 01H -Counts total number of uops to be executed per-thread each cycle. Set Cmask -= 1, INV =1 to count stall cycles. +Counts total number of uops to be executed per-thread each cycle. +Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core each cycle. diff --git a/lib/libpmc/pmc.ivybridgexeon.3 b/lib/libpmc/pmc.ivybridgexeon.3 --- a/lib/libpmc/pmc.ivybridgexeon.3 +++ b/lib/libpmc/pmc.ivybridgexeon.3 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd Jan 25, 2013 +.Dd January 25, 2013 .Dt PMC.IVYBRIDGEXEON 3 .Os .Sh NAME @@ -91,12 +91,12 @@ .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial -cachelines as well as demand data page table entry cacheline reads. Does not -count L2 data read prefetches or instruction fetches. +cachelines as well as demand data page table entry cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. @@ -144,8 +144,9 @@ -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) @@ -155,14 +156,15 @@ This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured @@ -225,18 +227,19 @@ Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H -Number of flags-merge uops allocated. Such uops adds delay. +Number of flags-merge uops allocated. +Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H -Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 -sources + immediate) regardless if as a result of LEA instruction or not. +Number of slow LEA or similar uops allocated. +Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SINGLE_MUL .Pq Event 0EH , Umask 40H Number of multiply packed/scalar single precision uops allocated. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H , Umask 01H -Cycles that the divider is active, includes INT and FP. Set 'edge =1, -cmask=1' to count the number of divides. +Cycles that the divider is active, includes INT and FP. +Set 'edge =1, cmask=1' to count the number of divides. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 01H Demand Data Read requests that hit L2 cache. @@ -302,16 +305,15 @@ .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. -The thread enters the halt state when it is running the HLT instruction. The -core frequency may change from time to time due to power or thermal -throttling. +The thread enters the halt state when it is running the HLT instruction. +The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H -Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 -and Edge =1 to count occurrences. +Increments the number of outstanding L1D misses every cycle. +Set Cmaks = 1 and Edge =1 to count occurrences. Counter 2 only. Set Cmask = 1 to count cycles. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK @@ -364,20 +366,20 @@ Counts load operations that missed 1st level DTLB but hit the 2nd level. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H -Offcore outstanding Demand Data Read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding Demand Data Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD .Pq Event 60H , Umask 02H -Offcore outstanding Demand Code Read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding Demand Code Read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H -Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to -count cycles. +Offcore outstanding RFO store transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H -Offcore outstanding cacheable data read transactions in SQ to uncore. Set -Cmask=1 to count cycles. +Offcore outstanding cacheable data read transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. @@ -399,31 +401,37 @@ Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H -Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set -Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. +Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. +Set Cmask = 1 to count cycles. +Add Edge=1 to count # of delivery. Can combine Umask 04H, 08H. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H -Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set -Cmask = 1 to count cycles. +Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. +Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or -MITE. Set Cmask = 1 to count cycles. +MITE. +Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered at least one uops. Set Cmask = 1. +Counts cycles DSB is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H -Counts cycles DSB is delivered four uops. Set Cmask = 4. +Counts cycles DSB is delivered four uops. +Set Cmask = 4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered at least one uops. Set Cmask = 1. +Counts cycles MITE is delivered at least one uops. +Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H -Counts cycles MITE is delivered four uops. Set Cmask = 4. +Counts cycles MITE is delivered four uops. +Set Cmask = 4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. @@ -442,7 +450,8 @@ Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. @@ -552,16 +561,20 @@ Cycles stalled due to re-order buffer full. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H -Cycles with pending L2 miss loads. Set AnyThread to count per core. +Cycles with pending L2 miss loads. +Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING .Pq Event A3H , Umask 02H -Cycles with pending memory loads. Set AnyThread to count per core. +Cycles with pending memory loads. +Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_NO_EXECUTE .Pq Event A3H , Umask 04H -Cycles of dispatch stalls. Set AnyThread to count per core. +Cycles of dispatch stalls. +Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 08H -Cycles with pending L1 cache miss loads. Set AnyThread to count per core. +Cycles with pending L1 cache miss loads. +Set AnyThread to count per core. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH , Umask 01H Number of DSB to MITE switches. @@ -589,8 +602,8 @@ Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.THREAD .Pq Event B1H , Umask 01H -Counts total number of uops to be executed per-thread each cycle. Set Cmask -= 1, INV =1 to count stall cycles. +Counts total number of uops to be executed per-thread each cycle. +Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core each cycle. diff --git a/lib/libpmc/pmc.sandybridge.3 b/lib/libpmc/pmc.sandybridge.3 --- a/lib/libpmc/pmc.sandybridge.3 +++ b/lib/libpmc/pmc.sandybridge.3 @@ -95,12 +95,12 @@ .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial -cachelines as well as demand data page table entry cacheline reads. Does not -count L2 data read prefetches or instruction fetches. +cachelines as well as demand data page table entry cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. @@ -148,8 +148,9 @@ -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) @@ -159,14 +160,15 @@ This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured @@ -662,7 +664,8 @@ Requires programming MSR 01A6H .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH, Umask 01H -Off-core Response Performance Monitoring. PMC3 only. +Off-core Response Performance Monitoring. +PMC3 only. Requires programming MSR 01A7H .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH, Umask 01H diff --git a/lib/libpmc/pmc.sandybridgexeon.3 b/lib/libpmc/pmc.sandybridgexeon.3 --- a/lib/libpmc/pmc.sandybridgexeon.3 +++ b/lib/libpmc/pmc.sandybridgexeon.3 @@ -92,12 +92,12 @@ .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial -cachelines as well as demand data page table entry cacheline reads. Does not -count L2 data read prefetches or instruction fetches. +cachelines as well as demand data page table entry cacheline reads. +Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) -requests generated by a write to data cacheline. Does not count L2 RFO -prefetches. +requests generated by a write to data cacheline. +Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. @@ -145,8 +145,9 @@ -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD -A snoop was needed and it hits in at least one snooped cache. Hit denotes a -cache-line was valid before snoop effect. This includes: +A snoop was needed and it hits in at least one snooped cache. +Hit denotes a cache-line was valid before snoop effect. +This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) @@ -156,14 +157,15 @@ This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM -A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a -cache-line was in modified state before effect as a results of snoop. This -includes: +A snoop was needed and it HitM-ed in local or remote cache. +HitM denotes a cache-line was in modified state before effect as a results of snoop. +This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM -Target was non-DRAM system address. This includes MMIO transactions. +Target was non-DRAM system address. +This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured @@ -228,8 +230,8 @@ .Pq Event 07H , Umask 08H The number of times that load operations are temporarily blocked because of older stores, with addresses that are -not yet known. A load operation may incur more than one -block of this type. +not yet known. +A load operation may incur more than one block of this type. .It Li TLB_LOAD_MISSES.MISS_CAUSES_A_WALK .Pq Event 08H , Umask 01H Misses in all TLB levels that cause a page walk of any @@ -243,7 +245,8 @@ Cycle PMH is busy with a walk. .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H , Umask 10H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH , Umask 03H Cycles waiting to recover after Machine Clears or EClear. @@ -375,10 +378,10 @@ .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the -thread is not in a halt state. The thread enters -the halt state when it is running the HLT -instruction. The core frequency may change from -time to time due to power or thermal throttling. +thread is not in a halt state. +The thread enters the halt state when it is running the HLT +instruction. +The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) @@ -413,10 +416,9 @@ buffer allocated for H/W prefetch. .It Li HW_PRE_REQ.DL1_MISS .Pq Event 4EH , Umask 02H -Hardware Prefetch requests that miss the L1D -cache. A request is being counted each time -it access the cache & miss it, including if -a block is applicable or if hit the Fill +Hardware Prefetch requests that miss the L1D cache. +A request is being counted each time it access the cache +& miss it, including if a block is applicable or if hit the Fill Buffer for example. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H @@ -472,17 +474,18 @@ .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H Offcore outstanding Demand Data Read -transactions in SQ to uncore. Set Cmask=1 to count -cycles. +transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H Offcore outstanding RFO store transactions in SQ to -uncore. Set Cmask=1 to count cycles. +uncore. +Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H Offcore outstanding cacheable data read -transactions in SQ to uncore. Set Cmask=1 to count -cycles. +transactions in SQ to uncore. +Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a @@ -506,23 +509,24 @@ .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H Increment each cycle # of uops delivered to IDQ -when MS busy by DSB. Set Cmask = 1 to count -cycles MS is busy. Set Cmask=1 and Edge =1 to -count MS activations. +when MS busy by DSB. +Set Cmask = 1 to count cycles MS is busy. +Set Cmask=1 and Edge =1 to count MS activations. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H Increment each cycle # of uops delivered to IDQ -when MS is busy by MITE. Set Cmask = 1 to count -cycles. +when MS is busy by MITE. +Set Cmask = 1 to count cycles. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ -from MS by either DSB or MITE. Set Cmask = 1 to -count cycles. +from MS by either DSB or MITE. +Set Cmask = 1 to count cycles. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and -Victim Cache Misses. Includes UC accesses. +Victim Cache Misses. +Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in all ITLB levels that cause page walks. @@ -535,7 +539,8 @@ Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H -Number of cache load STLB hits. No page walk. +Number of cache load STLB hits. +No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the @@ -645,8 +650,8 @@ Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H -Cycles stalled due to no store buffers available. (not -including draining form sync). +Cycles stalled due to no store buffers available. +(not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. @@ -663,16 +668,16 @@ other resource issues. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H -Cycles with pending L2 miss loads. Set AnyThread -to count per core. +Cycles with pending L2 miss loads. +Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 02H -Cycles with pending L1 cache miss loads.Set -AnyThread to count per core. +Cycles with pending L1 cache miss loads. +Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH .Pq Event A3H , Umask 04H -Cycles of dispatch stalls. Set AnyThread to count per -core. +Cycles of dispatch stalls. +Set AnyThread to count per core. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH , Umask 01H Number of DSB to MITE switches. @@ -708,8 +713,8 @@ .It Li UOPS_DISPATCHED.THREAD .Pq Event B1H , Umask 01H Counts total number of uops to be dispatched per- -thread each cycle. Set Cmask = 1, INV =1 to count -stall cycles. +thread each cycle. +Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_DISPATCHED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be dispatched per- @@ -728,11 +733,13 @@ .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H (Event B7H, Umask 01H) Off-core Response Performance -Monitoring; PMC0 only. Requires programming MSR 01A6H +Monitoring; PMC0 only. +Requires programming MSR 01A6H .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H (Event BBH, Umask 01H) Off-core Response Performance -Monitoring; PMC3 only. Requires programming MSR 01A7H +Monitoring; PMC3 only. +Requires programming MSR 01A7H .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread-specific entries. @@ -859,7 +866,8 @@ .It Li MEM_TRANS_RETIRED.PRECISE_STORE .Pq Event CDH , Umask 02H Sample stores and collect precise store operation -via PEBS record. PMC3 only. +via PEBS record. +PMC3 only. .It Li MEM_UOP_RETIRED.LOADS .Pq Event D0H , Umask 10H Qualify retired memory uops that are loads. @@ -870,20 +878,20 @@ Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STLB_MISS .Pq Event D0H , Umask -Qualify retired memory uops with STLB miss. Must -combine with umask 01H, 02H, to produce counts. +Qualify retired memory uops with STLB miss. +Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.LOCK .Pq Event D0H , Umask -Qualify retired memory uops with lock. Must -combine with umask 01H, 02H, to produce counts. +Qualify retired memory uops with lock. +Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.SPLIT .Pq Event D0H , Umask -Qualify retired memory uops with line split. Must -combine with umask 01H, 02H, to produce counts. +Qualify retired memory uops with line split. +Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED_ALL .Pq Event D0H , Umask -Qualify any retired memory uops. Must combine -with umask 01H, 02H, to produce counts. +Qualify any retired memory uops. +Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data diff --git a/lib/libpmc/pmc.westmere.3 b/lib/libpmc/pmc.westmere.3 --- a/lib/libpmc/pmc.westmere.3 +++ b/lib/libpmc/pmc.westmere.3 @@ -1168,8 +1168,8 @@ .It Li UOPS_DECODED.ESP_FOLDING .Pq Event D1H , Umask 04H Counts number of stack pointer (ESP) instructions decoded: push , pop , call -, ret, etc. ESP instructions do not generate a Uop to increment or decrement -ESP. +, ret, etc. +ESP instructions do not generate a Uop to increment or decrement ESP. Instead, they update an ESP_Offset register that keeps track of the delta to the current value of the ESP register. .It Li UOPS_DECODED.ESP_SYNC diff --git a/lib/libpmc/pmc.westmereuc.3 b/lib/libpmc/pmc.westmereuc.3 --- a/lib/libpmc/pmc.westmereuc.3 +++ b/lib/libpmc/pmc.westmereuc.3 @@ -116,8 +116,8 @@ Uncore cycles Global Queue write tracker is full. .It Li GQ_CYCLES_FULL.PEER_PROBE_TRACKER .Pq Event 00H , Umask 04H -Uncore cycles Global Queue peer probe tracker is full. The peer probe -tracker queue tracks snoops from the IOH and remote sockets. +Uncore cycles Global Queue peer probe tracker is full. +The peer probe tracker queue tracks snoops from the IOH and remote sockets. .It Li GQ_CYCLES_NOT_EMPTY.READ_TRACKER .Pq Event 01H , Umask 01H Uncore cycles were Global Queue read tracker has at least one valid entry. @@ -126,93 +126,99 @@ Uncore cycles were Global Queue write tracker has at least one valid entry. .It Li GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER .Pq Event 01H , Umask 04H -Uncore cycles were Global Queue peer probe tracker has at least one valid -entry. The peer probe tracker queue tracks IOH and remote socket snoops. +Uncore cycles were Global Queue peer probe tracker has at least one valid entry. +The peer probe tracker queue tracks IOH and remote socket snoops. .It Li GQ_OCCUPANCY.READ_TRACKER .Pq Event 02H , Umask 01H Increments the number of queue entries (code read, data read, and RFOs) in -the tread tracker. The GQ read tracker allocate to deallocate occupancy -count is divided by the count to obtain the average read tracker latency. +the tread tracker. +The GQ read tracker allocate to deallocate occupancy count is divided by the +count to obtain the average read tracker latency. .It Li GQ_ALLOC.READ_TRACKER .Pq Event 03H , Umask 01H -Counts the number of tread tracker allocate to deallocate entries. The GQ -read tracker allocate to deallocate occupancy count is divided by the count -to obtain the average read tracker latency. +Counts the number of tread tracker allocate to deallocate entries. +The GQ read tracker allocate to deallocate occupancy count is divided by +the count to obtain the average read tracker latency. .It Li GQ_ALLOC.RT_L3_MISS .Pq Event 03H , Umask 02H Counts the number GQ read tracker entries for which a full cache line read -has missed the L3. The GQ read tracker L3 miss to fill occupancy count is -divided by this count to obtain the average cache line read L3 miss latency. +has missed the L3. +The GQ read tracker L3 miss to fill occupancy count is divided by this count +to obtain the average cache line read L3 miss latency. The latency represents the time after which the L3 has determined that the -cache line has missed. The time between a GQ read tracker allocation and the -L3 determining that the cache line has missed is the average L3 hit latency. +cache line has missed. +The time between a GQ read tracker allocation and the L3 determining that +the cache line has missed is the average L3 hit latency. The total L3 cache line read miss latency is the hit latency + L3 miss latency. .It Li GQ_ALLOC.RT_TO_L3_RESP .Pq Event 03H , Umask 04H Counts the number of GQ read tracker entries that are allocated in the read -tracker queue that hit or miss the L3. The GQ read tracker L3 hit occupancy -count is divided by this count to obtain the average L3 hit latency. +tracker queue that hit or miss the L3. +The GQ read tracker L3 hit occupancy count is divided by this count to obtain the average L3 hit latency. .It Li GQ_ALLOC.RT_TO_RTID_ACQUIRED .Pq Event 03H , Umask 08H Counts the number of GQ read tracker entries that are allocated in the read -tracker, have missed in the L3 and have not acquired a Request Transaction -ID. The GQ read tracker L3 miss to RTID acquired occupancy count is +tracker, have missed in the L3 and have not acquired a Request Transaction ID. +The GQ read tracker L3 miss to RTID acquired occupancy count is divided by this count to obtain the average latency for a read L3 miss to acquire an RTID. .It Li GQ_ALLOC.WT_TO_RTID_ACQUIRED .Pq Event 03H , Umask 10H Counts the number of GQ write tracker entries that are allocated in the write tracker, have missed in the L3 and have not acquired a Request -Transaction ID. The GQ write tracker L3 miss to RTID occupancy count is -divided by this count to obtain the average latency for a write L3 miss to -acquire an RTID. +Transaction ID. +The GQ write tracker L3 miss to RTID occupancy count is divided by this count +to obtain the average latency for a write L3 miss to acquire an RTID. .It Li GQ_ALLOC.WRITE_TRACKER .Pq Event 03H , Umask 20H -Counts the number of GQ write tracker entries that are allocated in the -write tracker queue that miss the L3. The GQ write tracker occupancy count +Counts the number of GQ write tracker entries that are allocated in the write +tracker queue that miss the L3. +The GQ write tracker occupancy count is divided by the this count to obtain the average L3 write miss latency. .It Li GQ_ALLOC.PEER_PROBE_TRACKER .Pq Event 03H , Umask 40H Counts the number of GQ peer probe tracker (snoop) entries that are -allocated in the peer probe tracker queue that miss the L3. The GQ peer -probe occupancy count is divided by this count to obtain the average L3 peer -probe miss latency. +allocated in the peer probe tracker queue that miss the L3. +The GQ peer probe occupancy count is divided by this count to obtain the average +L3 peer probe miss latency. .It Li GQ_DATA.FROM_QPI .Pq Event 04H , Umask 01H Cycles Global Queue Quickpath Interface input data port is busy importing -data from the Quickpath Interface. Each cycle the input port can transfer 8 -or 16 bytes of data. +data from the Quickpath Interface. +Each cycle the input port can transfer 8 or 16 bytes of data. .It Li GQ_DATA.FROM_QMC .Pq Event 04H , Umask 02H Cycles Global Queue Quickpath Memory Interface input data port is busy -importing data from the Quickpath Memory Interface. Each cycle the input -port can transfer 8 or 16 bytes of data. +importing data from the Quickpath Memory Interface. +Each cycle the input port can transfer 8 or 16 bytes of data. .It Li GQ_DATA.FROM_L3 .Pq Event 04H , Umask 04H -Cycles GQ L3 input data port is busy importing data from the Last Level -Cache. Each cycle the input port can transfer 32 bytes of data. +Cycles GQ L3 input data port is busy importing data from the Last Level Cache. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.FROM_CORES_02 .Pq Event 04H , Umask 08H Cycles GQ Core 0 and 2 input data port is busy importing data from processor -cores 0 and 2. Each cycle the input port can transfer 32 bytes of data. +cores 0 and 2. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.FROM_CORES_13 .Pq Event 04H , Umask 10H Cycles GQ Core 1 and 3 input data port is busy importing data from processor -cores 1 and 3. Each cycle the input port can transfer 32 bytes of data. +cores 1 and 3. +Each cycle the input port can transfer 32 bytes of data. .It Li GQ_DATA.TO_QPI_QMC .Pq Event 05H , Umask 01H Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath -Interface or Quickpath Memory Interface. Each cycle the output port can -transfer 32 bytes of data. +Interface or Quickpath Memory Interface. +Each cycle the output port can transfer 32 bytes of data. .It Li GQ_DATA.TO_L3 .Pq Event 05H , Umask 02H Cycles GQ L3 output data port is busy sending data to the Last Level Cache. Each cycle the output port can transfer 32 bytes of data. .It Li GQ_DATA.TO_CORES .Pq Event 05H , Umask 04H -Cycles GQ Core output data port is busy sending data to the Cores. Each -cycle the output port can transfer 32 bytes of data. +Cycles GQ Core output data port is busy sending data to the Cores. +Each cycle the output port can transfer 32 bytes of data. .It Li SNP_RESP_TO_LOCAL_HOME.I_STATE .Pq Event 06H , Umask 01H Number of snoop responses to the local home that L3 does not have the @@ -224,14 +230,15 @@ .It Li SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE .Pq Event 06H , Umask 04H Number of responses to code or data read snoops to the local home that the -L3 has the referenced cache line in the E state. The L3 cache line state is -changed to the S state and the line is forwarded to the local home in the S -state. +L3 has the referenced cache line in the E state. +The L3 cache line state is changed to the S state and the line is forwarded +to the local home in the S state. .It Li SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE .Pq Event 06H , Umask 08H Number of responses to read invalidate snoops to the local home that the L3 -has the referenced cache line in the M state. The L3 cache line state is -invalidated and the line is forwarded to the local home in the M state. +has the referenced cache line in the M state. +The L3 cache line state is invalidated and the line is forwarded to the +local home in the M state. .It Li SNP_RESP_TO_LOCAL_HOME.CONFLICT .Pq Event 06H , Umask 10H Number of conflict snoop responses sent to the local home. @@ -250,14 +257,15 @@ .It Li SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE .Pq Event 07H , Umask 04H Number of responses to code or data read snoops to a remote home that the L3 -has the referenced cache line in the E state. The L3 cache line state is -changed to the S state and the line is forwarded to the remote home in the S -state. +has the referenced cache line in the E state. +The L3 cache line state is changed to the S state and the line is forwarded +to the remote home in the S state. .It Li SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE .Pq Event 07H , Umask 08H Number of responses to read invalidate snoops to a remote home that the L3 -has the referenced cache line in the M state. The L3 cache line state is -invalidated and the line is forwarded to the remote home in the M state. +has the referenced cache line in the M state. +The L3 cache line state is invalidated and the line is forwarded to the +remote home in the M state. .It Li SNP_RESP_TO_REMOTE_HOME.CONFLICT .Pq Event 07H , Umask 10H Number of conflict snoop responses sent to the local home. @@ -273,8 +281,9 @@ Number of code read, data read and RFO requests that hit in the L3. .It Li L3_HITS.WRITE .Pq Event 08H , Umask 02H -Number of writeback requests that hit in the L3. Writebacks from the cores -will always result in L3 hits due to the inclusive property of the L3. +Number of writeback requests that hit in the L3. +Writebacks from the cores will always result in L3 hits due to the +inclusive property of the L3. .It Li L3_HITS.PROBE .Pq Event 08H , Umask 04H Number of snoops from IOH or remote sockets that hit in the L3. @@ -286,8 +295,8 @@ Number of code read, data read and RFO requests that miss the L3. .It Li L3_MISS.WRITE .Pq Event 09H , Umask 02H -Number of writeback requests that miss the L3. Should always be zero as -writebacks from the cores will always result in L3 hits due to the inclusive +Number of writeback requests that miss the L3. +Should always be zero as writebacks from the cores will always result in L3 hits due to the inclusive property of the L3. .It Li L3_MISS.PROBE .Pq Event 09H , Umask 04H @@ -297,9 +306,9 @@ Number of reads and writes that miss the L3. .It Li L3_LINES_IN.M_STATE .Pq Event 0AH , Umask 01H -Counts the number of L3 lines allocated in M state. The only time a cache -line is allocated in the M state is when the line was forwarded in M state -is forwarded due to a Snoop Read Invalidate Own request. +Counts the number of L3 lines allocated in M state. +The only time a cache line is allocated in the M state is when the +line was forwarded in M state is forwarded due to a Snoop Read Invalidate Own request. .It Li L3_LINES_IN.E_STATE .Pq Event 0AH , Umask 02H Counts the number of L3 lines allocated in E state. @@ -314,8 +323,8 @@ Counts the number of L3 lines allocated in any state. .It Li L3_LINES_OUT.M_STATE .Pq Event 0BH , Umask 01H -Counts the number of L3 lines victimized that were in the M state. When the -victim cache line is in M state, the line is written to its home cache agent +Counts the number of L3 lines victimized that were in the M state. +When the victim cache line is in M state, the line is written to its home cache agent which can be either local or remote. .It Li L3_LINES_OUT.E_STATE .Pq Event 0BH , Umask 02H @@ -431,33 +440,37 @@ QHL local tracker allocate to deallocate read occupancy. .It Li QHL_ADDRESS_CONFLICTS.2WAY .Pq Event 24H , Umask 02H -Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 -conflicts. The AAT is a structure that tracks requests that are in conflict. -The requests themselves are in the home tracker entries. The count is -reported when an AAT entry deallocates. +Counts number of QHL Active Address Table (AAT) entries that saw a max of 2 conflicts. +The AAT is a structure that tracks requests that are in conflict. +The requests themselves are in the home tracker entries. +The count is reported when an AAT entry deallocates. .It Li QHL_ADDRESS_CONFLICTS.3WAY .Pq Event 24H , Umask 04H -Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 -conflicts. The AAT is a structure that tracks requests that are in conflict. -The requests themselves are in the home tracker entries. The count is -reported when an AAT entry deallocates. +Counts number of QHL Active Address Table (AAT) entries that saw a max of 3 conflicts. +The AAT is a structure that tracks requests that are in conflict. +The requests themselves are in the home tracker entries. +The count is reported when an AAT entry deallocates. .It Li QHL_CONFLICT_CYCLES.IOH .Pq Event 25H , Umask 01H Counts cycles the Quickpath Home Logic IOH Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_CONFLICT_CYCLES.REMOTE .Pq Event 25H , Umask 02H Counts cycles the Quickpath Home Logic Remote Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_CONFLICT_CYCLES.LOCAL .Pq Event 25H , Umask 04H Counts cycles the Quickpath Home Logic Local Tracker contains two or more -requests with an address conflict. A max of 3 requests can be in conflict. +requests with an address conflict. +A max of 3 requests can be in conflict. .It Li QHL_TO_QMC_BYPASS .Pq Event 26H , Umask 01H Counts number or requests to the Quickpath Memory Controller that bypass the -Quickpath Home Logic. All local accesses can be bypassed. For remote -requests, only read requests can be bypassed. +Quickpath Home Logic. +All local accesses can be bypassed. +For remote requests, only read requests can be bypassed. .It Li QMC_ISOC_FULL.READ.CH0 .Pq Event 28H , Umask 01H Counts cycles all the entries in the DRAM channel 0 high priority queue are @@ -533,23 +546,26 @@ .It Li QMC_NORMAL_READS.CH0 .Pq Event 2CH , Umask 01H Counts the number of Quickpath Memory Controller channel 0 medium and low -priority read requests. The QMC channel 0 normal read occupancy divided by -this count provides the average QMC channel 0 read latency. +priority read requests. +The QMC channel 0 normal read occupancy divided by this count provides the +average QMC channel 0 read latency. .It Li QMC_NORMAL_READS.CH1 .Pq Event 2CH , Umask 02H Counts the number of Quickpath Memory Controller channel 1 medium and low -priority read requests. The QMC channel 1 normal read occupancy divided by -this count provides the average QMC channel 1 read latency. +priority read requests. +The QMC channel 1 normal read occupancy divided by this count provides the +average QMC channel 1 read latency. .It Li QMC_NORMAL_READS.CH2 .Pq Event 2CH , Umask 04H Counts the number of Quickpath Memory Controller channel 2 medium and low -priority read requests. The QMC channel 2 normal read occupancy divided by -this count provides the average QMC channel 2 read latency. +priority read requests. +The QMC channel 2 normal read occupancy divided by this count provides the +average QMC channel 2 read latency. .It Li QMC_NORMAL_READS.ANY .Pq Event 2CH , Umask 07H -Counts the number of Quickpath Memory Controller medium and low priority -read requests. The QMC normal read occupancy divided by this count provides -the average QMC read latency. +Counts the number of Quickpath Memory Controller medium and low priority read requests. +The QMC normal read occupancy divided by this count provides the average +QMC read latency. .It Li QMC_HIGH_PRIORITY_READS.CH0 .Pq Event 2DH , Umask 01H Counts the number of Quickpath Memory Controller channel 0 high priority @@ -620,48 +636,49 @@ Counts number of DRAM cancel requests. .It Li QMC_PRIORITY_UPDATES.CH0 .Pq Event 31H , Umask 01H -Counts number of DRAM channel 0 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to +Counts number of DRAM channel 0 priority updates. +A priority update occurs when an ISOC high or critical request is +received by the QHL and there is a matching request with normal priority +that has already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.CH1 .Pq Event 31H , Umask 02H -Counts number of DRAM channel 1 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to -expedite the request. +Counts number of DRAM channel 1 priority updates. +A priority update occurs when an ISOC high or critical request is received +by the QHL and there is a matching request with normal priority that has +already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.CH2 .Pq Event 31H , Umask 04H -Counts number of DRAM channel 2 priority updates. A priority update occurs -when an ISOC high or critical request is received by the QHL and there is a -matching request with normal priority that has already been issued to the -QMC. In this instance, the QHL will send a priority update to QMC to -expedite the request. +Counts number of DRAM channel 2 priority updates. +A priority update occurs when an ISOC high or critical request is received +by the QHL and there is a matching request with normal priority that has +already been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li QMC_PRIORITY_UPDATES.ANY .Pq Event 31H , Umask 07H -Counts number of DRAM priority updates. A priority update occurs when an -ISOC high or critical request is received by the QHL and there is a matching -request with normal priority that has already been issued to the QMC. In -this instance, the QHL will send a priority update to QMC to expedite the -request. +Counts number of DRAM priority updates. +A priority update occurs when an ISOC high or critical request is received +by the QHL and there is a matching request with normal priority that has already +been issued to the QMC. +In this instance, the QHL will send a priority update to QMC to expedite the request. .It Li IMC_RETRY.CH0 .Pq Event 32H , Umask 01H -Counts number of IMC DRAM channel 0 retries. DRAM retry only occurs when -configured in RAS mode. +Counts number of IMC DRAM channel 0 retries. +DRAM retry only occurs when configured in RAS mode. .It Li IMC_RETRY.CH1 .Pq Event 32H , Umask 02H -Counts number of IMC DRAM channel 1 retries. DRAM retry only occurs when -configured in RAS mode. +Counts number of IMC DRAM channel 1 retries. +DRAM retry only occurs when configured in RAS mode. .It Li IMC_RETRY.CH2 .Pq Event 32H , Umask 04H -Counts number of IMC DRAM channel 2 retries. DRAM retry only occurs when -configured in RAS mode. +Counts number of IMC DRAM channel 2 retries. +DRAM retry only occurs when configured in RAS mode. .It Li IMC_RETRY.ANY .Pq Event 32H , Umask 07H -Counts number of IMC DRAM retries from any channel. DRAM retry only occurs -when configured in RAS mode. +Counts number of IMC DRAM retries from any channel. +DRAM retry only occurs when configured in RAS mode. .It Li QHL_FRC_ACK_CNFLTS.IOH .Pq Event 33H , Umask 01H Counts number of Force Acknowledge Conflict messages sent by the Quickpath @@ -681,153 +698,151 @@ .It Li QHL_SLEEPS.IOH_ORDER .Pq Event 34H , Umask 01H Counts number of occurrences a request was put to sleep due to IOH ordering -(write after read) conflicts. While in the sleep state, the request is not -eligible to be scheduled to the QMC. +(write after read) conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li QHL_SLEEPS.REMOTE_ORDER .Pq Event 34H , Umask 02H Counts number of occurrences a request was put to sleep due to remote socket -ordering (write after read) conflicts. While in the sleep state, the request -is not eligible to be scheduled to the QMC. +ordering (write after read) conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li QHL_SLEEPS.LOCAL_ORDER .Pq Event 34H , Umask 04H Counts number of occurrences a request was put to sleep due to local socket -ordering (write after read) conflicts. While in the sleep state, the request -is not eligible to be scheduled to the QMC. +ordering (write after read) conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li QHL_SLEEPS.IOH_CONFLICT .Pq Event 34H , Umask 08H -Counts number of occurrences a request was put to sleep due to IOH address -conflicts. While in the sleep state, the request is not eligible to be -scheduled to the QMC. +Counts number of occurrences a request was put to sleep due to IOH address conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li QHL_SLEEPS.REMOTE_CONFLICT .Pq Event 34H , Umask 10H Counts number of occurrences a request was put to sleep due to remote socket -address conflicts. While in the sleep state, the request is not eligible to -be scheduled to the QMC. +address conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li QHL_SLEEPS.LOCAL_CONFLICT .Pq Event 34H , Umask 20H -Counts number of occurrences a request was put to sleep due to local socket -address conflicts. While in the sleep state, the request is not eligible to -be scheduled to the QMC. +Counts number of occurrences a request was put to sleep due to local socket address conflicts. +While in the sleep state, the request is not eligible to be scheduled to the QMC. .It Li ADDR_OPCODE_MATCH.IOH .Pq Event 35H , Umask 01H Counts number of requests from the IOH, address/opcode of request is -qualified by mask value written to MSR 396H. The following mask values are -supported: +qualified by mask value written to MSR 396H. +The following mask values are supported: 0: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 40001D00_00000000H:RSPIWB Match opcode/address by writing MSR 396H with mask supported mask value. .It Li ADDR_OPCODE_MATCH.REMOTE .Pq Event 35H , Umask 02H Counts number of requests from the remote socket, address/opcode of request -is qualified by mask value written to MSR 396H. The following mask values -are supported: +is qualified by mask value written to MSR 396H. +The following mask values are supported: 0: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 40001D00_00000000H:RSPIWB Match opcode/address by writing MSR 396H with mask supported mask value. .It Li ADDR_OPCODE_MATCH.LOCAL .Pq Event 35H , Umask 04H Counts number of requests from the local socket, address/opcode of request -is qualified by mask value written to MSR 396H. The following mask values -are supported: +is qualified by mask value written to MSR 396H. +The following mask values are supported: 0: NONE 40000000_00000000H:RSPFWDI 40001A00_00000000H:RSPFWDS 40001D00_00000000H:RSPIWB Match opcode/address by writing MSR 396H with mask supported mask value. .It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0 .Pq Event 40H , Umask 01H Counts cycles the Quickpath outbound link 0 HOME virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0 .Pq Event 40H , Umask 02H Counts cycles the Quickpath outbound link 0 SNOOP virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0 .Pq Event 40H , Umask 04H Counts cycles the Quickpath outbound link 0 non-data response virtual -channel is stalled due to lack of a VNA and VN0 credit. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1 .Pq Event 40H , Umask 08H Counts cycles the Quickpath outbound link 1 HOME virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1 .Pq Event 40H , Umask 10H Counts cycles the Quickpath outbound link 1 SNOOP virtual channel is stalled -due to lack of a VNA and VN0 credit. Note that this event does not filter -out when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1 .Pq Event 40H , Umask 20H Counts cycles the Quickpath outbound link 1 non-data response virtual -channel is stalled due to lack of a VNA and VN0 credit. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_0 .Pq Event 40H , Umask 07H Counts cycles the Quickpath outbound link 0 virtual channels are stalled due -to lack of a VNA and VN0 credit. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_SINGLE_FLIT.LINK_1 .Pq Event 40H , Umask 38H Counts cycles the Quickpath outbound link 1 virtual channels are stalled due -to lack of a VNA and VN0 credit. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of a VNA and VN0 credit. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0 .Pq Event 41H , Umask 01H Counts cycles the Quickpath outbound link 0 Data ResponSe virtual channel is -stalled due to lack of VNA and VN0 credits. Note that this event does not -filter out when a flit would not have been selected for arbitration because -another virtual channel is getting arbitrated. +stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0 .Pq Event 41H , Umask 02H Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0 .Pq Event 41H , Umask 04H Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1 .Pq Event 41H , Umask 08H Counts cycles the Quickpath outbound link 1 Data ResponSe virtual channel is -stalled due to lack of VNA and VN0 credits. Note that this event does not -filter out when a flit would not have been selected for arbitration because -another virtual channel is getting arbitrated. +stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1 .Pq Event 41H , Umask 10H Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1 .Pq Event 41H , Umask 20H Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual -channel is stalled due to lack of VNA and VN0 credits. Note that this event -does not filter out when a flit would not have been selected for arbitration -because another virtual channel is getting arbitrated. +channel is stalled due to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.LINK_0 .Pq Event 41H , Umask 07H Counts cycles the Quickpath outbound link 0 virtual channels are stalled due -to lack of VNA and VN0 credits. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_STALLED_MULTI_FLIT.LINK_1 .Pq Event 41H , Umask 38H Counts cycles the Quickpath outbound link 1 virtual channels are stalled due -to lack of VNA and VN0 credits. Note that this event does not filter out -when a flit would not have been selected for arbitration because another -virtual channel is getting arbitrated. +to lack of VNA and VN0 credits. +Note that this event does not filter out when a flit would not have been selected +for arbitration because another virtual channel is getting arbitrated. .It Li QPI_TX_HEADER.FULL.LINK_0 .Pq Event 42H , Umask 01H Number of cycles that the header buffer in the Quickpath Interface outbound @@ -856,49 +871,52 @@ does not have any available entries. .It Li DRAM_OPEN.CH0 .Pq Event 60H , Umask 01H -Counts number of DRAM Channel 0 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 0 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_OPEN.CH1 .Pq Event 60H , Umask 02H -Counts number of DRAM Channel 1 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 1 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_OPEN.CH2 .Pq Event 60H , Umask 04H -Counts number of DRAM Channel 2 open commands issued either for read or -write. To read or write data, the referenced DRAM page must first be opened. +Counts number of DRAM Channel 2 open commands issued either for read or write. +To read or write data, the referenced DRAM page must first be opened. .It Li DRAM_PAGE_CLOSE.CH0 .Pq Event 61H , Umask 01H -DRAM channel 0 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +DRAM channel 0 command issued to CLOSE a page due to page idle timer expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_CLOSE.CH1 .Pq Event 61H , Umask 02H -DRAM channel 1 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +DRAM channel 1 command issued to CLOSE a page due to page idle timer expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_CLOSE.CH2 .Pq Event 61H , Umask 04H -DRAM channel 2 command issued to CLOSE a page due to page idle timer -expiration. Closing a page is done by issuing a precharge. +DRAM channel 2 command issued to CLOSE a page due to page idle timer expiration. +Closing a page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH0 .Pq Event 62H , Umask 01H Counts the number of precharges (PRE) that were issued to DRAM channel 0 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and another +page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH1 .Pq Event 62H , Umask 02H Counts the number of precharges (PRE) that were issued to DRAM channel 1 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and another +page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_PAGE_MISS.CH2 .Pq Event 62H , Umask 04H Counts the number of precharges (PRE) that were issued to DRAM channel 2 -because there was a page miss. A page miss refers to a situation in which a -page is currently open and another page from the same bank needs to be -opened. The new page experiences a page miss. Closing of the old page is -done by issuing a precharge. +because there was a page miss. +A page miss refers to a situation in which a page is currently open and another +page from the same bank needs to be opened. +The new page experiences a page miss. +Closing of the old page is done by issuing a precharge. .It Li DRAM_READ_CAS.CH0 .Pq Event 63H , Umask 01H Counts the number of times a read CAS command was issued on DRAM channel 0. @@ -943,34 +961,35 @@ where the command issued used the auto-precharge (auto page close) mode. .It Li DRAM_REFRESH.CH0 .Pq Event 65H , Umask 01H -Counts number of DRAM channel 0 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be +Counts number of DRAM channel 0 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_REFRESH.CH1 .Pq Event 65H , Umask 02H -Counts number of DRAM channel 1 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be -refreshed periodically. +Counts number of DRAM channel 1 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_REFRESH.CH2 .Pq Event 65H , Umask 04H -Counts number of DRAM channel 2 refresh commands. DRAM loses data content -over time. In order to keep correct data content, the data values have to be -refreshed periodically. +Counts number of DRAM channel 2 refresh commands. +DRAM loses data content over time. +In order to keep correct data content, the data values have to be refreshed periodically. .It Li DRAM_PRE_ALL.CH0 .Pq Event 66H , Umask 01H Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode. .It Li DRAM_PRE_ALL.CH1 .Pq Event 66H , Umask 02H Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode. .It Li DRAM_PRE_ALL.CH2 .Pq Event 66H , Umask 04H Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close -all open pages in a rank. PREALL is issued when the DRAM needs to be -refreshed or needs to go into a power down mode. +all open pages in a rank. +PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode. .It Li DRAM_THERMAL_THROTTLED .Pq Event 67H , Umask 01H Uncore cycles DRAM was throttled due to its temperature being above the