Index: sys/riscv/sifive/sifive_uart.c
===================================================================
--- sys/riscv/sifive/sifive_uart.c
+++ sys/riscv/sifive/sifive_uart.c
@@ -137,9 +137,15 @@
 static int
 sfuart_rxready(struct uart_bas *bas)
 {
-
-	return ((uart_getreg(bas, SFUART_RXDATA) &
-	    SFUART_RXDATA_EMPTY) == 0);
+	/*
+	 * Unfortunately the FIFO empty flag is in the FIFO data register so
+	 * reading it would dequeue the character. Instead, rely on the fact
+	 * we've configured the watermark to be 0 and that interrupts are off
+	 * when using the low-level console function, and read the interrupt
+	 * pending state instead.
+	 */
+	return ((uart_getreg(bas, SFUART_IRQ_PENDING) &
+	    SFUART_IRQ_PENDING_RXQM) != 0);
 }
 
 static int