Index: sys/amd64/include/xen/arch-intr.h =================================================================== --- /dev/null +++ sys/amd64/include/xen/arch-intr.h @@ -0,0 +1 @@ +../../../x86/include/xen/arch-intr.h \ No newline at end of file Index: sys/i386/include/xen/arch-intr.h =================================================================== --- /dev/null +++ sys/i386/include/xen/arch-intr.h @@ -0,0 +1 @@ +../../../x86/include/xen/arch-intr.h \ No newline at end of file Index: sys/x86/include/xen/arch-intr.h =================================================================== --- /dev/null +++ sys/x86/include/xen/arch-intr.h @@ -0,0 +1,43 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2021 Elliott Mitchell + * Copyright (c) 2015 Julien Grall + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_X86_XEN_ARCH_INTR_H_ +#define _MACHINE_X86_XEN_ARCH_INTR_H_ + +#include + +struct xen_arch_isrc { + struct intsrc xai_intsrc; /* @TOP -> *xen_arch_isrc */ + u_int xai_vector; /* Global isrc vector number */ +}; + +typedef struct xen_arch_isrc xen_arch_isrc_t; + +#endif /* _MACHINE_X86_XEN_ARCH_INTR_H_ */ Index: sys/x86/xen/xen_intr.c =================================================================== --- sys/x86/xen/xen_intr.c +++ sys/x86/xen/xen_intr.c @@ -59,6 +59,7 @@ #include #include +#include #include #include #include @@ -114,10 +115,9 @@ DPCPU_DECLARE(struct vcpu_info *, vcpu_info); struct xenisrc { - struct intsrc xi_intsrc; + xen_arch_isrc_t xi_arch; /* @TOP -> *xi_arch=*xenisrc */ enum evtchn_type xi_type; int xi_cpu; /* VCPU for delivery. */ - int xi_vector; /* Global isrc vector number. */ evtchn_port_t xi_port; int xi_virq; void *xi_cookie; @@ -282,7 +282,7 @@ isrc = (struct xenisrc *)intr_lookup_source(vector); if (isrc != NULL && isrc->xi_type == EVTCHN_TYPE_UNBOUND) { - KASSERT(isrc->xi_intsrc.is_handlers == 0, + KASSERT(isrc->xi_arch.xai_intsrc.is_handlers == 0, ("Free evtchn still has handlers")); isrc->xi_type = type; return (isrc); @@ -324,10 +324,10 @@ mtx_unlock(&xen_intr_isrc_lock); isrc = malloc(sizeof(*isrc), M_XENINTR, M_WAITOK | M_ZERO); - isrc->xi_intsrc.is_pic = &xen_intr_pic; - isrc->xi_vector = vector; + isrc->xi_arch.xai_intsrc.is_pic = &xen_intr_pic; + isrc->xi_arch.xai_vector = vector; isrc->xi_type = type; - intr_register_source(&isrc->xi_intsrc); + intr_register_source(&isrc->xi_arch.xai_intsrc); mtx_lock(&xen_intr_isrc_lock); return (isrc); @@ -345,7 +345,7 @@ { mtx_lock(&xen_intr_isrc_lock); - KASSERT(isrc->xi_intsrc.is_handlers == 0, + KASSERT(isrc->xi_arch.xai_intsrc.is_handlers == 0, ("Release called, but xenisrc still in use")); evtchn_mask_port(isrc->xi_port); evtchn_clear_port(isrc->xi_port); @@ -432,7 +432,7 @@ * unless specified otherwise, so shuffle them to balance * the interrupt load. */ - xen_intr_assign_cpu(&isrc->xi_intsrc, intr_next_cpu(0)); + xen_intr_assign_cpu(&isrc->xi_arch.xai_intsrc, intr_next_cpu(0)); } #endif @@ -569,7 +569,7 @@ ("Received unexpected event on vCPU#%d, event bound to vCPU#%d", PCPU_GET(cpuid), isrc->xi_cpu)); - intr_execute_handlers(&isrc->xi_intsrc, trap_frame); + intr_execute_handlers(&isrc->xi_arch.xai_intsrc, trap_frame); /* * If this is the final port processed, @@ -735,7 +735,7 @@ #ifdef SMP isrc->xi_cpu = 0; - error = xen_intr_assign_cpu(&isrc->xi_intsrc, + error = xen_intr_assign_cpu(&isrc->xi_arch.xai_intsrc, cpu_apic_ids[cpu]); if (error) panic(errfmt, __func__, cpu, error, isrc->xi_virq); @@ -806,6 +806,7 @@ xen_intr_disable_intr(struct intsrc *base_isrc) { struct xenisrc *isrc = (struct xenisrc *)base_isrc; + CTASSERT(offsetof(struct xenisrc, xi_arch.xai_intsrc) == 0); evtchn_mask_port(isrc->xi_port); } @@ -822,8 +823,9 @@ xen_intr_vector(struct intsrc *base_isrc) { struct xenisrc *isrc = (struct xenisrc *)base_isrc; + CTASSERT(offsetof(struct xenisrc, xi_arch.xai_intsrc) == 0); - return (isrc->xi_vector); + return (isrc->xi_arch.xai_vector); } /** @@ -877,6 +879,7 @@ struct xenisrc *isrc; u_int to_cpu, vcpu_id; int error, masked; + CTASSERT(offsetof(struct xenisrc, xi_arch.xai_intsrc) == 0); if (!xen_has_percpu_evtchn()) return (EOPNOTSUPP); @@ -944,6 +947,7 @@ xen_intr_disable_source(struct intsrc *base_isrc, int eoi) { struct xenisrc *isrc; + CTASSERT(offsetof(struct xenisrc, xi_arch.xai_intsrc) == 0); isrc = (struct xenisrc *)base_isrc; @@ -967,6 +971,7 @@ xen_intr_enable_source(struct intsrc *base_isrc) { struct xenisrc *isrc; + CTASSERT(offsetof(struct xenisrc, xi_arch.xai_intsrc) == 0); isrc = (struct xenisrc *)base_isrc; @@ -982,6 +987,7 @@ static void xen_intr_eoi_source(struct intsrc *base_isrc) { + CTASSERT(offsetof(struct xenisrc, xi_arch.xai_intsrc) == 0); } /* @@ -993,6 +999,7 @@ xen_intr_enable_intr(struct intsrc *base_isrc) { struct xenisrc *isrc = (struct xenisrc *)base_isrc; + CTASSERT(offsetof(struct xenisrc, xi_arch.xai_intsrc) == 0); evtchn_unmask_port(isrc->xi_port); } @@ -1121,7 +1128,7 @@ #ifdef SMP if (error == 0) - error = intr_event_bind(isrc->xi_intsrc.is_event, cpu); + error = intr_event_bind(isrc->xi_arch.xai_intsrc.is_event, cpu); #endif if (error != 0) { @@ -1141,7 +1148,7 @@ * masks manually so events can't fire on the wrong cpu * during AP startup. */ - xen_intr_assign_cpu(&isrc->xi_intsrc, cpu_apic_ids[cpu]); + xen_intr_assign_cpu(&isrc->xi_arch.xai_intsrc, cpu_apic_ids[cpu]); } #endif @@ -1197,7 +1204,7 @@ * masks manually so events can't fire on the wrong cpu * during AP startup. */ - xen_intr_assign_cpu(&isrc->xi_intsrc, cpu_apic_ids[cpu]); + xen_intr_assign_cpu(&isrc->xi_arch.xai_intsrc, cpu_apic_ids[cpu]); } /* @@ -1225,7 +1232,7 @@ va_start(ap, fmt); vsnprintf(descr, sizeof(descr), fmt, ap); va_end(ap); - return (intr_describe(isrc->xi_vector, isrc->xi_cookie, descr)); + return (intr_describe(isrc->xi_arch.xai_vector, isrc->xi_cookie, descr)); } void @@ -1292,7 +1299,7 @@ if (isrc == NULL || isrc->xi_cookie != NULL) return (EINVAL); - error = intr_add_handler(name, isrc->xi_vector,filter, handler, arg, + error = intr_add_handler(name, isrc->xi_arch.xai_vector,filter, handler, arg, flags|INTR_EXCL, &isrc->xi_cookie, 0); if (error != 0) printf("%s: %s: add handler failed: %d\n", name, __func__,