Index: emulators/riscv-fesvr/Makefile =================================================================== --- emulators/riscv-fesvr/Makefile +++ emulators/riscv-fesvr/Makefile @@ -21,6 +21,8 @@ USE_GITHUB= yes USE_LDCONFIG= yes +DEPRECATED= No longer required, as libfesvr is bundled with emulators/riscv-isa-sim + STRIP_FILES= bin/elf2hex \ lib/libfesvr.so Index: emulators/riscv-isa-sim/Makefile =================================================================== --- emulators/riscv-isa-sim/Makefile +++ emulators/riscv-isa-sim/Makefile @@ -2,7 +2,7 @@ PORTNAME= riscv-isa-sim DISTVERSION= git -PORTREVISION= 20181007 +PORTREVISION= 20201102 CATEGORIES= emulators MAINTAINER= lwhsu@FreeBSD.org @@ -12,33 +12,28 @@ ONLY_FOR_ARCHS= amd64 -LIB_DEPENDS= libfesvr.so:emulators/riscv-fesvr - USES= compiler:c++11-lang gmake shebangfix -GH_ACCOUNT= freebsd-riscv -GH_TAGNAME= aae60e0 +GH_ACCOUNT= riscv +GH_TAGNAME= 641d7d0 HAS_CONFIGURE= yes SHEBANG_FILES= scripts/vcs-version.sh +CONFLICTS_INSTALL= riscv-fesvr + USE_GITHUB= yes USE_LDCONFIG= yes -LDFLAGS+= -L${LOCALBASE}/lib -CFLAGS+= -I${LOCALBASE}/include \ - -DRISCV_ENABLE_DIRTY=1 +CFLAGS+= -DRISCV_ENABLE_DIRTY=1 -STRIP_FILES= bin/spike \ +STRIP_FILES= bin/elf2hex \ + bin/spike \ bin/spike-dasm \ + bin/spike-log-parser \ bin/termios-xspike \ bin/xspike \ - lib/libdummy_rocc.so \ - lib/libriscv.so \ - lib/libsoftfloat.so \ - lib/libspike_main.so - -post-extract: - @${MV} ${WRKSRC}/riscv/insn_template.h ${WRKSRC}/riscv/insn_template.hpp + lib/libcustomext.so \ + lib/libsoftfloat.so post-patch: ${REINPLACE_CMD} -e \ Index: emulators/riscv-isa-sim/distinfo =================================================================== --- emulators/riscv-isa-sim/distinfo +++ emulators/riscv-isa-sim/distinfo @@ -1,3 +1,3 @@ -TIMESTAMP = 1538736497 -SHA256 (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 423005144e71b272fad7f13b57af7de561a178af096a71d304e0a3c590520195 -SIZE (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 232817 +TIMESTAMP = 1604881926 +SHA256 (riscv-riscv-isa-sim-git-641d7d0_GH0.tar.gz) = 810c0567ba31459a37bd84498071c68b1a85b8dc7f891df800b02201544e5149 +SIZE (riscv-riscv-isa-sim-git-641d7d0_GH0.tar.gz) = 385330 Index: emulators/riscv-isa-sim/files/patch-Makefile.in =================================================================== --- emulators/riscv-isa-sim/files/patch-Makefile.in +++ /dev/null @@ -1,19 +0,0 @@ ---- Makefile.in.orig 2018-10-05 10:52:51 UTC -+++ Makefile.in -@@ -187,13 +187,13 @@ _$(1).cc : - - # Build the object files for this subproject - --$(2)_pch := $$(patsubst %.h, %.h.gch, $$($(2)_precompiled_hdrs)) -+$(2)_pch := $$(patsubst %.hpp, %.h.gch, $$($(2)_precompiled_hdrs)) - $(2)_objs := $$(patsubst %.cc, %.o, $$($(2)_srcs)) - $(2)_c_objs := $$(patsubst %.c, %.o, $$($(2)_c_srcs)) - $(2)_deps := $$(patsubst %.o, %.d, $$($(2)_objs)) - $(2)_deps += $$(patsubst %.o, %.d, $$($(2)_c_objs)) --$(2)_deps += $$(patsubst %.h, %.h.d, $$($(2)_precompiled_hdrs)) --$$($(2)_pch) : %.h.gch : %.h -+$(2)_deps += $$(patsubst %.hpp, %.h.d, $$($(2)_precompiled_hdrs)) -+$$($(2)_pch) : %.h.gch : %.hpp - $(COMPILE) -x c++-header $$< -o $$@ - # If using clang, don't depend (and thus don't build) precompiled headers - $$($(2)_objs) : %.o : %.cc $$($(2)_gen_hdrs) $(if $(filter-out clang,$(CC)),$$($(2)_pch)) Index: emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc =================================================================== --- emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc +++ /dev/null @@ -1,10 +0,0 @@ ---- riscv/insn_template.cc.orig 2018-10-05 10:52:33 UTC -+++ riscv/insn_template.cc -@@ -1,6 +1,6 @@ - // See LICENSE for license details. - --#include "insn_template.h" -+#include "insn_template.hpp" - - reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc) - { Index: emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in =================================================================== --- emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in +++ /dev/null @@ -1,20 +0,0 @@ ---- riscv/riscv.mk.in.orig 2018-10-05 10:52:11 UTC -+++ riscv/riscv.mk.in -@@ -23,7 +23,7 @@ riscv_hdrs = \ - tracer.h \ - extension.h \ - rocc.h \ -- insn_template.h \ -+ insn_template.hpp \ - mulhi.h \ - debug_module.h \ - debug_rom_defines.h \ -@@ -31,7 +31,7 @@ riscv_hdrs = \ - jtag_dtm.h \ - - riscv_precompiled_hdrs = \ -- insn_template.h \ -+ insn_template.hpp \ - - riscv_srcs = \ - processor.cc \ Index: emulators/riscv-isa-sim/pkg-descr =================================================================== --- emulators/riscv-isa-sim/pkg-descr +++ emulators/riscv-isa-sim/pkg-descr @@ -3,4 +3,4 @@ The RISC-V ISA Simulator implements a functional model of one or more RISC-V processors. -WWW: https://github.com/freebsd-riscv/riscv-isa-sim +WWW: https://github.com/riscv/riscv-isa-sim Index: emulators/riscv-isa-sim/pkg-plist =================================================================== --- emulators/riscv-isa-sim/pkg-plist +++ emulators/riscv-isa-sim/pkg-plist @@ -1,44 +1,27 @@ +bin/elf2hex bin/spike bin/spike-dasm +bin/spike-log-parser bin/termios-xspike bin/xspike -include/spike/cachesim.h -include/spike/common.h -include/spike/config.h -include/spike/debug_module.h -include/spike/debug_rom_defines.h -include/spike/decode.h -include/spike/devices.h -include/spike/disasm.h -include/spike/dts.h -include/spike/encoding.h -include/spike/extension.h -include/spike/icache.h -include/spike/insn_list.h -include/spike/insn_template.hpp -include/spike/internals.h -include/spike/jtag_dtm.h -include/spike/memtracer.h -include/spike/mmu.h -include/spike/mulhi.h -include/spike/platform.h -include/spike/primitiveTypes.h -include/spike/primitives.h -include/spike/processor.h -include/spike/remote_bitbang.h -include/spike/rocc.h -include/spike/sim.h -include/spike/simif.h -include/spike/softfloat.h -include/spike/softfloat_types.h -include/spike/specialize.h -include/spike/tracer.h -include/spike/trap.h -lib/libdummy_rocc.so -lib/libriscv.so +include/fesvr/context.h +include/fesvr/device.h +include/fesvr/dtm.h +include/fesvr/elf.h +include/fesvr/elfloader.h +include/fesvr/htif.h +include/fesvr/htif_hexwriter.h +include/fesvr/htif_pthread.h +include/fesvr/memif.h +include/fesvr/option_parser.h +include/fesvr/rfb.h +include/fesvr/syscall.h +include/fesvr/term.h +include/fesvr/tsi.h +include/riscv/mmio_plugin.h +lib/libcustomext.so +lib/libdisasm.a +lib/libfesvr.a lib/libsoftfloat.so -lib/libspike_main.so -libdata/pkgconfig/riscv-dummy_rocc.pc -libdata/pkgconfig/riscv-riscv.pc -libdata/pkgconfig/riscv-softfloat.pc -libdata/pkgconfig/riscv-spike_main.pc +libdata/pkgconfig/riscv-disasm.pc +libdata/pkgconfig/riscv-fesvr.pc