Index: head/sys/riscv/riscv/mp_machdep.c
===================================================================
--- head/sys/riscv/riscv/mp_machdep.c
+++ head/sys/riscv/riscv/mp_machdep.c
@@ -46,6 +46,7 @@
 #include <sys/systm.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
+#include <sys/cpuset.h>
 #include <sys/kernel.h>
 #include <sys/ktr.h>
 #include <sys/malloc.h>
@@ -265,6 +266,9 @@
 
 	/* Enable external (PLIC) interrupts */
 	csr_set(sie, SIE_SEIE);
+
+	/* Activate this hart in the kernel pmap. */
+	CPU_SET_ATOMIC(hart, &kernel_pmap->pm_active);
 
 	/* Activate process 0's pmap. */
 	pmap_activate_boot(vmspace_pmap(proc0.p_vmspace));
Index: head/sys/riscv/riscv/pmap.c
===================================================================
--- head/sys/riscv/riscv/pmap.c
+++ head/sys/riscv/riscv/pmap.c
@@ -573,7 +573,12 @@
 
 	rw_init(&pvh_global_lock, "pmap pv global");
 
-	CPU_FILL(&kernel_pmap->pm_active);
+	/*
+	 * Set the current CPU as active in the kernel pmap. Secondary cores
+	 * will add themselves later in init_secondary(). The SBI firmware
+	 * may rely on this mask being precise, so CPU_FILL() is not used.
+	 */
+	CPU_SET(PCPU_GET(hart), &kernel_pmap->pm_active);
 
 	/* Assume the address we were loaded to is a valid physical address. */
 	min_pa = max_pa = kernstart;