Index: head/sys/arm64/arm64/identcpu.c
===================================================================
--- head/sys/arm64/arm64/identcpu.c
+++ head/sys/arm64/arm64/identcpu.c
@@ -690,6 +690,50 @@
 
 
 /* ID_AA64MMFR2_EL1 */
+static struct mrs_field_value id_aa64mmfr2_e0pd[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, E0PD, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64mmfr2_evt[] = {
+	MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_NONE, ""),
+	MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_2, "EVT-8.2"),
+	MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_5, "EVT-8.5"),
+	MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64mmfr2_bbm[] = {
+	MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL0, ""),
+	MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL1, "BBM level 1"),
+	MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL2, "BBM level 2"),
+	MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64mmfr2_ttl[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, TTL, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64mmfr2_fwb[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, FWB, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64mmfr2_ids[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IDS, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64mmfr2_at[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, AT, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static struct mrs_field_value id_aa64mmfr2_st[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, ST, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
 static struct mrs_field_value id_aa64mmfr2_nv[] = {
 	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, NV, NONE, IMPL),
 	MRS_FIELD_VALUE_END,
@@ -728,6 +772,14 @@
 };
 
 static struct mrs_field id_aa64mmfr2_fields[] = {
+	MRS_FIELD(ID_AA64MMFR2, E0PD, false, MRS_EXACT, id_aa64mmfr2_e0pd),
+	MRS_FIELD(ID_AA64MMFR2, EVT, false, MRS_EXACT, id_aa64mmfr2_evt),
+	MRS_FIELD(ID_AA64MMFR2, BBM, false, MRS_EXACT, id_aa64mmfr2_bbm),
+	MRS_FIELD(ID_AA64MMFR2, TTL, false, MRS_EXACT, id_aa64mmfr2_ttl),
+	MRS_FIELD(ID_AA64MMFR2, FWB, false, MRS_EXACT, id_aa64mmfr2_fwb),
+	MRS_FIELD(ID_AA64MMFR2, IDS, false, MRS_EXACT, id_aa64mmfr2_ids),
+	MRS_FIELD(ID_AA64MMFR2, AT, false, MRS_LOWER, id_aa64mmfr2_at),
+	MRS_FIELD(ID_AA64MMFR2, ST, false, MRS_EXACT, id_aa64mmfr2_st),
 	MRS_FIELD(ID_AA64MMFR2, NV, false, MRS_EXACT, id_aa64mmfr2_nv),
 	MRS_FIELD(ID_AA64MMFR2, CCIDX, false, MRS_EXACT, id_aa64mmfr2_ccidx),
 	MRS_FIELD(ID_AA64MMFR2, VARange, false, MRS_EXACT,
Index: head/sys/arm64/include/armreg.h
===================================================================
--- head/sys/arm64/include/armreg.h
+++ head/sys/arm64/include/armreg.h
@@ -578,6 +578,48 @@
 #define	ID_AA64MMFR2_NV_VAL(x)		((x) & ID_AA64MMFR2_NV_MASK)
 #define	 ID_AA64MMFR2_NV_NONE		(UL(0x0) << ID_AA64MMFR2_NV_SHIFT)
 #define	 ID_AA64MMFR2_NV_IMPL		(UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
+#define	ID_AA64MMFR2_ST_SHIFT		28
+#define	ID_AA64MMFR2_ST_MASK		(UL(0xf) << ID_AA64MMFR2_ST_SHIFT)
+#define	ID_AA64MMFR2_ST_VAL(x)		((x) & ID_AA64MMFR2_ST_MASK)
+#define	 ID_AA64MMFR2_ST_NONE		(UL(0x0) << ID_AA64MMFR2_ST_SHIFT)
+#define	 ID_AA64MMFR2_ST_IMPL		(UL(0x1) << ID_AA64MMFR2_ST_SHIFT)
+#define	ID_AA64MMFR2_AT_SHIFT		32
+#define	ID_AA64MMFR2_AT_MASK		(UL(0xf) << ID_AA64MMFR2_AT_SHIFT)
+#define	ID_AA64MMFR2_AT_VAL(x)		((x) & ID_AA64MMFR2_AT_MASK)
+#define	 ID_AA64MMFR2_AT_NONE		(UL(0x0) << ID_AA64MMFR2_AT_SHIFT)
+#define	 ID_AA64MMFR2_AT_IMPL		(UL(0x1) << ID_AA64MMFR2_AT_SHIFT)
+#define	ID_AA64MMFR2_IDS_SHIFT		36
+#define	ID_AA64MMFR2_IDS_MASK		(UL(0xf) << ID_AA64MMFR2_IDS_SHIFT)
+#define	ID_AA64MMFR2_IDS_VAL(x)		((x) & ID_AA64MMFR2_IDS_MASK)
+#define	 ID_AA64MMFR2_IDS_NONE		(UL(0x0) << ID_AA64MMFR2_IDS_SHIFT)
+#define	 ID_AA64MMFR2_IDS_IMPL		(UL(0x1) << ID_AA64MMFR2_IDS_SHIFT)
+#define	ID_AA64MMFR2_FWB_SHIFT		40
+#define	ID_AA64MMFR2_FWB_MASK		(UL(0xf) << ID_AA64MMFR2_FWB_SHIFT)
+#define	ID_AA64MMFR2_FWB_VAL(x)		((x) & ID_AA64MMFR2_FWB_MASK)
+#define	 ID_AA64MMFR2_FWB_NONE		(UL(0x0) << ID_AA64MMFR2_FWB_SHIFT)
+#define	 ID_AA64MMFR2_FWB_IMPL		(UL(0x1) << ID_AA64MMFR2_FWB_SHIFT)
+#define	ID_AA64MMFR2_TTL_SHIFT		48
+#define	ID_AA64MMFR2_TTL_MASK		(UL(0xf) << ID_AA64MMFR2_TTL_SHIFT)
+#define	ID_AA64MMFR2_TTL_VAL(x)		((x) & ID_AA64MMFR2_TTL_MASK)
+#define	 ID_AA64MMFR2_TTL_NONE		(UL(0x0) << ID_AA64MMFR2_TTL_SHIFT)
+#define	 ID_AA64MMFR2_TTL_IMPL		(UL(0x1) << ID_AA64MMFR2_TTL_SHIFT)
+#define	ID_AA64MMFR2_BBM_SHIFT		52
+#define	ID_AA64MMFR2_BBM_MASK		(UL(0xf) << ID_AA64MMFR2_BBM_SHIFT)
+#define	ID_AA64MMFR2_BBM_VAL(x)		((x) & ID_AA64MMFR2_BBM_MASK)
+#define	 ID_AA64MMFR2_BBM_LEVEL0	(UL(0x0) << ID_AA64MMFR2_BBM_SHIFT)
+#define	 ID_AA64MMFR2_BBM_LEVEL1	(UL(0x1) << ID_AA64MMFR2_BBM_SHIFT)
+#define	 ID_AA64MMFR2_BBM_LEVEL2	(UL(0x2) << ID_AA64MMFR2_BBM_SHIFT)
+#define	ID_AA64MMFR2_EVT_SHIFT		56
+#define	ID_AA64MMFR2_EVT_MASK		(UL(0xf) << ID_AA64MMFR2_EVT_SHIFT)
+#define	ID_AA64MMFR2_EVT_VAL(x)		((x) & ID_AA64MMFR2_EVT_MASK)
+#define	 ID_AA64MMFR2_EVT_NONE		(UL(0x0) << ID_AA64MMFR2_EVT_SHIFT)
+#define	 ID_AA64MMFR2_EVT_8_2		(UL(0x1) << ID_AA64MMFR2_EVT_SHIFT)
+#define	 ID_AA64MMFR2_EVT_8_5		(UL(0x2) << ID_AA64MMFR2_EVT_SHIFT)
+#define	ID_AA64MMFR2_E0PD_SHIFT		60
+#define	ID_AA64MMFR2_E0PD_MASK		(UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT)
+#define	ID_AA64MMFR2_E0PD_VAL(x)	((x) & ID_AA64MMFR2_E0PD_MASK)
+#define	 ID_AA64MMFR2_E0PD_NONE		(UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT)
+#define	 ID_AA64MMFR2_E0PD_IMPL		(UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT)
 
 /* ID_AA64PFR0_EL1 */
 #define	ID_AA64PFR0_EL1			MRS_REG(3, 0, 0, 4, 0)