Index: lib/libpmc/pmu-events/arch/x86/amdfam17h/zen2.json
===================================================================
--- /dev/null
+++ lib/libpmc/pmu-events/arch/x86/amdfam17h/zen2.json
@@ -0,0 +1,160 @@
+[
+ {
+  "EventName": "ls_ret_clflush",
+  "EventCode": "0x26",
+  "BriefDescription": "Retired CLFLUSH Instructions.",
+  "PublicDescription": "The number of CLFLUSH instructions retired."
+ },
+ {
+  "EventName": "ls_ret_cpuid",
+  "EventCode": "0x27",
+  "BriefDescription": "Retired CPUID Instructions.",
+  "PublicDescription": "The number of CPUID instructions retired."
+ },
+ {
+  "EventName": "ls_smi_rx",
+  "EventCode": "0x2b",
+  "BriefDescription": "SMIs Received.",
+  "PublicDescription": "Counts the number of SMIs received."
+ },
+ {
+  "EventName": "ls_int_taken",
+  "EventCode": "0x2c",
+  "BriefDescription": "Interrupts Taken.",
+  "PublicDescription": "Counts the number of interrupts taken."
+ },
+ {
+  "EventName": "ls_rdtsc",
+  "EventCode": "0x2d",
+  "BriefDescription": "RDTSC Instructions (speculative).",
+  "PublicDescription": "The number of RDTSC instructions (speculative)."
+ },
+ {
+  "EventName": "l2_pf_hit_l2",
+  "EventCode": "0x70",
+  "BriefDescription": "L2 Prefetch Hit in L2",
+  "PublicDescription": "L2 prefetch hit in L2"
+ },
+ {
+  "EventName": "l2_pf_miss_l2_hit_l3",
+  "EventCode": "0x71",
+  "BriefDescription": "L2 Prefetcher Hits in L3",
+  "PublicDescription": "Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3."
+ },
+ {
+  "EventName": "l2_pf_miss_l2_l3",
+  "EventCode": "0x72",
+  "BriefDescription": "L2 Prefetcher Misses in L3",
+  "PublicDescription": "Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and the L3 caches."
+ },
+ {
+  "EventName": "xi_sys_fill_latency",
+  "EventCode": "0x90",
+  "BriefDescription": "L3 Cache Miss Latency",
+  "PublicDescription": "Total cycles for all transactions divided by 16."
+ },
+ {
+  "EventName": "de_dis_uop_queue_empty_di0",
+  "EventCode": "0xa9",
+  "BriefDescription": "Micro-Op Queue Empty",
+  "PublicDescription": "cycles where the Micro-Op Queue is empty."
+ },
+ {
+  "EventName": "de_dis_uops_from_decoder",
+  "EventCode": "0xaa",
+  "BriefDescription": "UOps Dispatched From Decoder and OpCache",
+  "PublicDescription": "Ops dispatched from the decoders, OpCache or both.",
+  "UMask": "0xff"
+ },
+ {
+  "EventName": "de_dis_uops_from_decoder.op_cache_dispatched",
+  "EventCode": "0xaa",
+  "BriefDescription": "UOps Dispatched From OpCache",
+  "PublicDescription": "Ops dispatched from the OpCache.",
+  "UMask": "0x02"
+ },
+ {
+  "EventName": "de_dis_uops_from_decoder.decoder_dispatched",
+  "EventCode": "0xaa",
+  "BriefDescription": "UOps Dispatched From Decoder",
+  "PublicDescription": "Ops dispatched from the decoder.",
+  "UMask": "0x01"
+ },
+ {
+  "EventName": "de_dis_dispatch_token_stalls1",
+  "EventCode": "0xae",
+  "BriefDescription": "Dispatch Resource Stall Cycles 1",
+  "PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall.",
+  "UMask": "0xff"
+ },
+ {
+  "EventName": "de_dis_dispatch_token_stalls1",
+  "EventCode": "0xae",
+  "BriefDescription": "Dispatch Resource Stall Cycles 1",
+  "PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall.",
+  "UMask": "0xff"
+ },
+ {
+  "EventName": "de_dis_dispatch_token_stalls1.fp_misc_rsrc_stall",
+  "EventCode": "0xae",
+  "BriefDescription": "Dispatch Resource Stall Cycles 1. FP Miscellaneous resource unavailable.",
+  "PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Applies to the recovery of mispredicts with FP ops.",
+  "UMask": "0x80"
+ },
+ {
+  "EventName": "de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall",
+  "EventCode": "0xae",
+  "BriefDescription": "Dispatch Resource Stall Cycles 1. FP scheduler resource stall.",
+  "PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Applies to ops that use the FP scheduler.",
+  "UMask": "0x40"
+ },
+ {
+  "EventName": "de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall",
+  "EventCode": "0xae",
+  "BriefDescription": "Dispatch Resource Stall Cycles 1. Floating point register file resource stall.",
+  "PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Applies to all FP ops that have a destination register.",
+  "UMask": "0x20"
+ },
+ {
+  "EventName": "de_dis_dispatch_token_stalls1.taken_branch_buffer_rsrc_stall",
+  "EventCode": "0xae",
+  "BriefDescription": "Dispatch Resource Stall Cycles 1. Taken branch buffer resource stall.",
+  "PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall.",
+  "UMask": "0x10"
+ },
+ {
+  "EventName": "de_dis_dispatch_token_stalls1.int_sched_misc_token_stall",
+  "EventCode": "0xae",
+  "BriefDescription": "Dispatch Resource Stall Cycles 1. Integer Scheduler miscellaneous resource stall.",
+  "PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall.",
+  "UMask": "0x08"
+ },
+ {
+  "EventName": "de_dis_dispatch_token_stalls1.store_queue_token_stall",
+  "EventCode": "0xae",
+  "BriefDescription": "Dispatch Resource Stall Cycles 1. Store Queue resource stall.",
+  "PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Applies to all ops with store semantics.",
+  "UMask": "0x04"
+ },
+ {
+  "EventName": "de_dis_dispatch_token_stalls1.load_queue_token_stall",
+  "EventCode": "0xae",
+  "BriefDescription": "Dispatch Resource Stall Cycles 1. Load Queue resource stall.",
+  "PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Applies to all ops with load semantics.",
+  "UMask": "0x02"
+ },
+ {
+  "EventName": "de_dis_dispatch_token_stalls1.int_phys_reg_file_token_stall",
+  "EventCode": "0xae",
+  "BriefDescription": "Dispatch Resource Stall Cycles 1. Integer Physical Register File resource stall.",
+  "PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Integer Physical Register File, applies to all ops that have an integer destination register.",
+  "UMask": "0x01"
+ },
+ {
+  "EventName": "de_dis_dispatch_token_stalls0.alu_token_stall",
+  "EventCode": "0xaf",
+  "BriefDescription": "Dispatch Resource Stall Cycles 0. ALU tokens total unavailable.",
+  "PublicDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable.",
+  "UMask": "0x04"
+ }
+]
Index: lib/libpmc/pmu-events/arch/x86/mapfile.csv
===================================================================
--- lib/libpmc/pmu-events/arch/x86/mapfile.csv
+++ lib/libpmc/pmu-events/arch/x86/mapfile.csv
@@ -46,4 +46,7 @@
 AuthenticAMD-23-03,v1,amdfam17h,core
 AuthenticAMD-23-04,v1,amdfam17h,core
 AuthenticAMD-23-05,v1,amdfam17h,core
+AuthenticAMD-23-08,v1,amdfam17h,core
+AuthenticAMD-23-31,v1,amdfam17h,core
+AuthenticAMD-23-71,v1,amdfam17h,core
 HygonGenuine-24-00,v1,amdfam17h,core
Index: usr.sbin/pmc/cmd_pmc_stat.c
===================================================================
--- usr.sbin/pmc/cmd_pmc_stat.c
+++ usr.sbin/pmc/cmd_pmc_stat.c
@@ -165,7 +165,7 @@
 	CPU_COPY(&rootmask, &cpumask);
 
 	if (pmc_pmu_stat_mode(&pmc_stat_mode_cntrs) != 0)
-		errx(EX_USAGE, "ERROR: hwmpc.ko not loaded or stat not supported on host.");
+		errx(EX_USAGE, "ERROR: hwpmc.ko not loaded or stat not supported on host.");
 	if (system_mode && geteuid() != 0)
 		errx(EX_USAGE, "ERROR: system mode counters can only be used as root");
 	counters = NULL;