Index: sys/dev/ic/z8530.h
===================================================================
--- sys/dev/ic/z8530.h
+++ sys/dev/ic/z8530.h
@@ -32,15 +32,24 @@
 #define	_DEV_IC_Z8530_H_
 
 /*
- * Channel B control:	0
- * Channel B data:	1
- * Channel A control:	2
- * Channel A data:	3
+ * escc-legacy:	SUN compatible
+ * escc: 	Macintosh
+ *			escc-legacy	escc
+ * Channel B control:	0		0
+ * Channel B data:	1		1
+ * Channel A control:	2		16
+ * Channel A data:	3		17
  */
 
 /* The following apply when using a device-scoped bus handle */
+/* XXX These are platform specific and do not belong here. */
+#ifdef __powerpc__
+#define	CHAN_A		16
+#define	CHAN_B		0
+#else
 #define	CHAN_A		2
 #define	CHAN_B		0
+#endif
 
 #define	REG_CTRL	0
 #define	REG_DATA	1
Index: sys/dev/scc/scc_bfe_macio.c
===================================================================
--- sys/dev/scc/scc_bfe_macio.c
+++ sys/dev/scc/scc_bfe_macio.c
@@ -55,6 +55,7 @@
 
 	sc = device_get_softc(dev);
 	nm = ofw_bus_get_name(dev);
+	/* Attach to modern escc (channel shift 4 bits) */
 	if (!strcmp(nm, "escc")) {
 		device_set_desc(dev, "Zilog Z8530 dual channel SCC");
 		sc->sc_class = &scc_z8530_class;
Index: sys/dev/scc/scc_dev_z8530.c
===================================================================
--- sys/dev/scc/scc_dev_z8530.c
+++ sys/dev/scc/scc_dev_z8530.c
@@ -66,6 +66,7 @@
 	.cl_channels = 2,
 	.cl_class = SCC_CLASS_Z8530,
 	.cl_modes = SCC_MODE_ASYNC | SCC_MODE_BISYNC | SCC_MODE_HDLC,
+	/* Negative .cl_range signifies this is channel spacing. */
 	.cl_range = CHAN_B - CHAN_A,
 };