Index: sys/arm/arm/machdep.c
===================================================================
--- sys/arm/arm/machdep.c
+++ sys/arm/arm/machdep.c
@@ -114,7 +114,57 @@
 
 #ifdef DDB
 #include <ddb/ddb.h>
-#endif
+
+#if __ARM_ARCH >= 6
+#include <machine/cpu-v6.h>
+
+DB_SHOW_COMMAND(cp15, db_show_cp15)
+{
+	u_int reg;
+
+	reg = cp15_midr_get();
+	db_printf("Cpu ID: 0x%08x\n", reg);
+	reg = cp15_ctr_get();
+	db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
+
+	reg = cp15_sctlr_get();
+	db_printf("Ctrl: 0x%08x\n",reg);
+	reg = cp15_actlr_get();
+	db_printf("Aux Ctrl: 0x%08x\n",reg);
+
+	reg = cp15_id_pfr0_get();
+	db_printf("Processor Feat 0: 0x%08x\n", reg);
+	reg = cp15_id_pfr1_get();
+	db_printf("Processor Feat 1: 0x%08x\n", reg);
+	reg = cp15_id_dfr0_get();
+	db_printf("Debug Feat 0: 0x%08x\n", reg);
+	reg = cp15_id_afr0_get();
+	db_printf("Auxiliary Feat 0: 0x%08x\n", reg);
+	reg = cp15_id_mmfr0_get();
+	db_printf("Memory Model Feat 0: 0x%08x\n", reg);
+	reg = cp15_id_mmfr1_get();
+	db_printf("Memory Model Feat 1: 0x%08x\n", reg);
+	reg = cp15_id_mmfr2_get();
+	db_printf("Memory Model Feat 2: 0x%08x\n", reg);
+	reg = cp15_id_mmfr3_get();
+	db_printf("Memory Model Feat 3: 0x%08x\n", reg);
+	reg = cp15_ttbr_get();
+	db_printf("TTB0: 0x%08x\n", reg);
+}
+
+DB_SHOW_COMMAND(vtop, db_show_vtop)
+{
+	u_int reg;
+
+	if (have_addr) {
+		cp15_ats1cpr_set(addr);
+		reg = cp15_par_get();
+		db_printf("Physical address reg: 0x%08x\n",reg);
+	} else
+		db_printf("show vtop <virt_addr>\n");
+}
+#endif /* __ARM_ARCH >= 7 */
+#endif /* DDB */
 
 #ifdef DEBUG
 #define	debugf(fmt, args...) printf(fmt, ##args)
Index: sys/arm/include/armreg.h
===================================================================
--- sys/arm/include/armreg.h
+++ sys/arm/include/armreg.h
@@ -346,6 +346,9 @@
 #define	CPUV7_CT_xSIZE_ASSOC(x)	(((x) >> 3) & 0x3ff)	/* associativity */
 #define	CPUV7_CT_xSIZE_SET(x)	(((x) >> 13) & 0x7fff)	/* num sets */
 
+#define	CPUV7_L2CTLR_NPROC_SHIFT	24
+#define	CPUV7_L2CTLR_NPROC(r)	((((r) >> CPUV7_L2CTLR_NPROC_SHIFT) & 3) + 1)
+
 #define	CPU_CLIDR_CTYPE(reg,x)	(((reg) >> ((x) * 3)) & 0x7)
 #define	CPU_CLIDR_LOUIS(reg)	(((reg) >> 21) & 0x7)
 #define	CPU_CLIDR_LOC(reg)	(((reg) >> 24) & 0x7)
Index: sys/arm/include/cpu-v6.h
===================================================================
--- sys/arm/include/cpu-v6.h
+++ sys/arm/include/cpu-v6.h
@@ -143,6 +143,13 @@
 _RF0(cp15_dfar_get, CP15_DFAR(%0))
 #if __ARM_ARCH >= 7
 _RF0(cp15_ifar_get, CP15_IFAR(%0))
+_RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0))
+#endif
+#if __ARM_ARCH >= 6
+_RF0(cp15_actlr_get, CP15_ACTLR(%0))
+_WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0));
+_RF0(cp15_par_get, CP15_PAR);
+_RF0(cp15_sctlr_get, CP15_SCTLR(%0))
 #endif
 
 /*CPU id registers */
Index: sys/arm/include/sysreg.h
===================================================================
--- sys/arm/include/sysreg.h
+++ sys/arm/include/sysreg.h
@@ -212,6 +212,7 @@
 #if __ARM_ARCH == 6 && defined(CPU_ARM1176)
 #define	CP15_PMCCNTR(rr)	p15, 0, rr, c15, c12, 1 /* PM Cycle Count Register */
 #elif __ARM_ARCH > 6
+#define	CP15_L2CTLR(rr)		p15, 1, rr,  c9, c0,  2 /* L2 Control Register */
 #define	CP15_PMCR(rr)		p15, 0, rr,  c9, c12, 0 /* Performance Monitor Control Register */
 #define	CP15_PMCNTENSET(rr)	p15, 0, rr,  c9, c12, 1 /* PM Count Enable Set Register */
 #define	CP15_PMCNTENCLR(rr)	p15, 0, rr,  c9, c12, 2 /* PM Count Enable Clear Register */