There are actually three changes:
- Widen the stored io_apic_id to 8 bits. It seems that the newer Intel chipset did that, and Linux reads 8 bits. The only detail is that all seen datasheets, even under NDA, claim that io apic id is 4 bits. (Submitted by jeff).
- When matching PCIe IOAPIC device against MADT-enumerated IOAPICs, compare io_apic_id from BAR against io_apic_id read from MADT register page before renumbering. It seems that PCIe vs. MADT pointed registers are not coherent.
- If EOI suppression is supported but reported ioapic version is so old that it does not has EOI register, fix Intel trick of eoi-ing by flipping pin type (edge/level) to account for the disabled pin. (Reported by: Juniper)
Items 1 and 2 tested by flo.