Index: sys/conf/options.powerpc =================================================================== --- sys/conf/options.powerpc +++ sys/conf/options.powerpc @@ -4,7 +4,6 @@ AIM opt_global.h BOOKE opt_global.h BOOKE_E500 opt_global.h -BOOKE_PPC4XX opt_global.h CELL POWERPC Index: sys/powerpc/booke/machdep_e500.c =================================================================== --- sys/powerpc/booke/machdep_e500.c +++ sys/powerpc/booke/machdep_e500.c @@ -52,12 +52,6 @@ extern void l2cache_inval(void); extern void bpred_enable(void); -void -booke_init_tlb(vm_paddr_t fdt_immr_pa) -{ - -} - void booke_enable_l1_cache(void) { Index: sys/powerpc/booke/machdep_ppc4xx.c =================================================================== --- sys/powerpc/booke/machdep_ppc4xx.c +++ /dev/null @@ -1,216 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2011-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include - -#include - -#include -#include - -#include - -#define OCP_ADDR_WORDLO(addr) ((uint32_t)((uint64_t)(addr) & 0xFFFFFFFF)) -#define OCP_ADDR_WORDHI(addr) ((uint32_t)((uint64_t)(addr) >> 32)) - -extern void tlb_write(u_int, uint32_t, uint32_t, uint32_t, tlbtid_t, uint32_t, - uint32_t); -extern void tlb_read(u_int, uint32_t *, uint32_t *, uint32_t *, uint32_t *, - uint32_t *, uint32_t *); - -unsigned int tlb_static_entries; -unsigned int tlb_current_entry = TLB_SIZE; -unsigned int tlb_misses = 0; -unsigned int tlb_invals = 0; - -void tlb_map(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); -void tlb_map_mem(uint32_t, uint32_t, uint32_t); -void tlb_dump(void); - -void -booke_init_tlb(vm_paddr_t fdt_immr_pa) -{ - - /* Map register space */ - tlb_map(APM86XXX_DEEP_SLEEP_VA, - OCP_ADDR_WORDLO(APM86XXX_DEEP_SLEEP_PA), - OCP_ADDR_WORDHI(APM86XXX_DEEP_SLEEP_PA), TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - tlb_map(APM86XXX_CSR_VA, OCP_ADDR_WORDLO(APM86XXX_CSR_PA), - OCP_ADDR_WORDHI(APM86XXX_CSR_PA), TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - tlb_map(APM86XXX_PRIMARY_FABRIC_VA, - OCP_ADDR_WORDLO(APM86XXX_PRIMARY_FABRIC_PA), - OCP_ADDR_WORDHI(APM86XXX_PRIMARY_FABRIC_PA), - TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - tlb_map(APM86XXX_AHB_VA, OCP_ADDR_WORDLO(APM86XXX_AHB_PA), - OCP_ADDR_WORDHI(APM86XXX_AHB_PA), - TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - /* Map MailBox space */ - tlb_map(APM86XXX_MBOX_VA, OCP_ADDR_WORDLO(APM86XXX_MBOX_PA), - OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), - TLB_VALID | TLB_SIZE_4K, - TLB_UX | TLB_UW | TLB_UR | - TLB_SX | TLB_SW | TLB_SR | - TLB_I | TLB_G); - - tlb_map(APM86XXX_MBOX_VA + 0x1000, - OCP_ADDR_WORDLO(APM86XXX_MBOX_PA) + 0x1000, - OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), - TLB_VALID | TLB_SIZE_4K, - TLB_UX | TLB_UW | TLB_UR | - TLB_SX | TLB_SW | TLB_SR | - TLB_I | TLB_G); - - tlb_map(APM86XXX_MBOX_VA + 0x2000, - OCP_ADDR_WORDLO(APM86XXX_MBOX_PA)+ 0x2000, - OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), - TLB_VALID | TLB_SIZE_4K, - TLB_UX | TLB_UW | TLB_UR | - TLB_SX | TLB_SW | TLB_SR | - TLB_I | TLB_G); -} - -void -booke_enable_l1_cache(void) -{ -} - -void -booke_enable_l2_cache(void) -{ -} - -void -booke_disable_l2_cache(void) -{ - uint32_t ccr1,l2cr0; - - /* Disable L2 cache op broadcast */ - ccr1 = mfspr(SPR_CCR1); - ccr1 &= ~CCR1_L2COBE; - mtspr(SPR_CCR1, ccr1); - - /* Set L2 array size to 0 i.e. disable L2 cache */ - mtdcr(DCR_L2DCDCRAI, DCR_L2CR0); - l2cr0 = mfdcr(DCR_L2DCDCRDI); - l2cr0 &= ~L2CR0_AS; - mtdcr(DCR_L2DCDCRDI, l2cr0); -} - -void tlb_map(uint32_t epn, uint32_t rpn, uint32_t erpn, uint32_t flags, - uint32_t perms) -{ - - tlb_write(++tlb_static_entries, epn, rpn, erpn, 0, flags, perms); -} - -static void tlb_dump_entry(u_int entry) -{ - uint32_t epn, rpn, erpn, tid, flags, perms; - const char *size; - - tlb_read(entry, &epn, &rpn, &erpn, &tid, &flags, &perms); - - switch (flags & TLB_SIZE_MASK) { - case TLB_SIZE_1K: - size = " 1k"; - break; - case TLB_SIZE_4K: - size = " 4k"; - break; - case TLB_SIZE_16K: - size = " 16k"; - break; - case TLB_SIZE_256K: - size = "256k"; - break; - case TLB_SIZE_1M: - size = " 1M"; - break; - case TLB_SIZE_16M: - size = " 16M"; - break; - case TLB_SIZE_256M: - size = "256M"; - break; - case TLB_SIZE_1G: - size = " 1G"; - break; - default: - size = "????"; - break; - } - - - printf("TLB[%02u]: 0x%08X => " - "0x%01X_%08X %s %c %c %s %s %s %s %s " - "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c (%u)\n", - entry, epn, erpn, rpn, size, - (flags & TLB_TS) ? '1' : '0', - (flags & TLB_VALID) ? 'V' : '.', - (perms & TLB_WL1) ? "WL1" : "___", - (perms & TLB_IL1I) ? "IL1I" : "____", - (perms & TLB_IL1D) ? "IL1D" : "____", - (perms & TLB_IL2I) ? "IL2I" : "____", - (perms & TLB_IL2D) ? "IL2D" : "____", - (perms & TLB_U0) ? '1' : '.', - (perms & TLB_U1) ? '2' : '.', - (perms & TLB_U2) ? '3' : '.', - (perms & TLB_U3) ? '4' : '.', - (perms & TLB_W) ? 'W' : '.', - (perms & TLB_I) ? 'I' : '.', - (perms & TLB_M) ? 'M' : '.', - (perms & TLB_G) ? 'G' : '.', - (perms & TLB_E) ? 'E' : '.', - (perms & TLB_UX) ? 'x' : '.', - (perms & TLB_UW) ? 'w' : '.', - (perms & TLB_UR) ? 'r' : '.', - (perms & TLB_SX) ? 'X' : '.', - (perms & TLB_SW) ? 'W' : '.', - (perms & TLB_SR) ? 'R' : '.', - tid); -} - -void tlb_dump(void) -{ - int i; - - for (i = 0; i < TLB_SIZE; i++) - tlb_dump_entry(i); -} Index: sys/powerpc/conf/NOTES =================================================================== --- sys/powerpc/conf/NOTES +++ sys/powerpc/conf/NOTES @@ -36,7 +36,6 @@ # You must specify at least one CPU (the one you intend to run on). cpu AIM #cpu BOOKE_E500 -#cpu BOOKE_PPC440 options FPU_EMU Index: sys/powerpc/include/machdep.h =================================================================== --- sys/powerpc/include/machdep.h +++ sys/powerpc/include/machdep.h @@ -35,6 +35,5 @@ void booke_enable_l1_cache(void); void booke_enable_l2_cache(void); void booke_enable_bpred(void); -void booke_init_tlb(vm_paddr_t); #endif /* _POWERPC_MACHDEP_H_ */ Index: sys/powerpc/include/profile.h =================================================================== --- sys/powerpc/include/profile.h +++ sys/powerpc/include/profile.h @@ -190,7 +190,7 @@ extern char interrupt_vector_top[]; #define __PROFILE_VECTOR_BASE (uintfptr_t)interrupt_vector_base #define __PROFILE_VECTOR_TOP (uintfptr_t)interrupt_vector_top -#endif /* BOOKE_E500 || BOOKE_PPC4XX */ +#endif /* BOOKE_E500 */ #endif /* !COMPILING_LINT */ Index: sys/powerpc/include/pte.h =================================================================== --- sys/powerpc/include/pte.h +++ sys/powerpc/include/pte.h @@ -241,24 +241,6 @@ #define PTE_PS_SHIFT 8 #define PTE_PS_4KB (2 << PTE_PS_SHIFT) -#elif defined(BOOKE_PPC4XX) - -#define PTE_WL1 TLB_WL1 -#define PTE_IL2I TLB_IL2I -#define PTE_IL2D TLB_IL2D - -#define PTE_W TLB_W -#define PTE_I TLB_I -#define PTE_M TLB_M -#define PTE_G TLB_G - -#define PTE_UX TLB_UX -#define PTE_SX TLB_SX -#define PTE_UW TLB_UW -#define PTE_SW TLB_SW -#define PTE_UR TLB_UR -#define PTE_SR TLB_SR - #endif /* Other PTE flags */ Index: sys/powerpc/include/spr.h =================================================================== --- sys/powerpc/include/spr.h +++ sys/powerpc/include/spr.h @@ -504,11 +504,7 @@ #define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */ #define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */ #define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */ -#if defined(BOOKE_PPC4XX) -#define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */ -#else #define SPR_DEAR 0x03d /* ..8 Data Exception Address Register */ -#endif #define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */ #define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */ #define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */ Index: sys/powerpc/include/tlb.h =================================================================== --- sys/powerpc/include/tlb.h +++ sys/powerpc/include/tlb.h @@ -156,56 +156,6 @@ void tlb1_init(void); #endif /* !LOCORE */ -#elif defined(BOOKE_PPC4XX) - -/* TLB Words */ -#define TLB_PAGEID 0 -#define TLB_XLAT 1 -#define TLB_ATTRIB 2 - -/* Page identification fields */ -#define TLB_EPN_MASK (0xFFFFFC00 >> 0) -#define TLB_VALID (0x80000000 >> 22) -#define TLB_TS (0x80000000 >> 23) -#define TLB_SIZE_1K (0x00000000 >> 24) -#define TLB_SIZE_MASK (0xF0000000 >> 24) - -/* Translation fields */ -#define TLB_RPN_MASK (0xFFFFFC00 >> 0) -#define TLB_ERPN_MASK (0xF0000000 >> 28) - -/* Storage attribute and access control fields */ -#define TLB_WL1 (0x80000000 >> 11) -#define TLB_IL1I (0x80000000 >> 12) -#define TLB_IL1D (0x80000000 >> 13) -#define TLB_IL2I (0x80000000 >> 14) -#define TLB_IL2D (0x80000000 >> 15) -#define TLB_U0 (0x80000000 >> 16) -#define TLB_U1 (0x80000000 >> 17) -#define TLB_U2 (0x80000000 >> 18) -#define TLB_U3 (0x80000000 >> 19) -#define TLB_W (0x80000000 >> 20) -#define TLB_I (0x80000000 >> 21) -#define TLB_M (0x80000000 >> 22) -#define TLB_G (0x80000000 >> 23) -#define TLB_E (0x80000000 >> 24) -#define TLB_UX (0x80000000 >> 26) -#define TLB_UW (0x80000000 >> 27) -#define TLB_UR (0x80000000 >> 28) -#define TLB_SX (0x80000000 >> 29) -#define TLB_SW (0x80000000 >> 30) -#define TLB_SR (0x80000000 >> 31) -#define TLB_SIZE 64 - -#define TLB_SIZE_4K (0x10000000 >> 24) -#define TLB_SIZE_16K (0x20000000 >> 24) -#define TLB_SIZE_64K (0x30000000 >> 24) -#define TLB_SIZE_256K (0x40000000 >> 24) -#define TLB_SIZE_1M (0x50000000 >> 24) -#define TLB_SIZE_16M (0x70000000 >> 24) -#define TLB_SIZE_256M (0x90000000 >> 24) -#define TLB_SIZE_1G (0xA0000000 >> 24) - #endif /* BOOKE_E500 */ #define TID_KERNEL 0 /* TLB TID to use for kernel (shared) translations */ Index: sys/powerpc/powerpc/db_disasm.c =================================================================== --- sys/powerpc/powerpc/db_disasm.c +++ sys/powerpc/powerpc/db_disasm.c @@ -425,11 +425,7 @@ { 0x019, "sdr1" }, { 0x01a, "srr0" }, { 0x01b, "srr1" }, -#ifdef BOOKE_PPC4XX - { 0x100, "usprg0" }, -#else { 0x100, "vrsave" }, -#endif { 0x110, "sprg0" }, { 0x111, "sprg1" }, { 0x112, "sprg2" }, @@ -496,14 +492,6 @@ { 0x3db, "pit" }, { 0x3de, "srr2" }, { 0x3df, "srr3" }, -#ifdef BOOKE_PPC4XX - { 0x3f0, "dbsr" }, - { 0x3f2, "dbcr0" }, - { 0x3f4, "iac1" }, - { 0x3f5, "iac2" }, - { 0x3f6, "dac1" }, - { 0x3f7, "dac2" }, -#else { 0x3f0, "hid0" }, { 0x3f1, "hid1" }, { 0x3f2, "iabr" }, @@ -511,7 +499,6 @@ { 0x3f5, "dabr" }, { 0x3f6, "msscr0" }, { 0x3f7, "msscr1" }, -#endif { 0x3f9, "l2cr" }, { 0x3fa, "dccr" }, { 0x3fb, "iccr" },