Index: sys/powerpc/include/psl.h
===================================================================
--- sys/powerpc/include/psl.h
+++ sys/powerpc/include/psl.h
@@ -88,7 +88,7 @@
 #define	PSL_FE_NONREC	PSL_FE1		/* imprecise non-recoverable */
 #define	PSL_FE_REC	PSL_FE0		/* imprecise recoverable */
 #define	PSL_FE_PREC	(PSL_FE0 | PSL_FE1) /* precise */
-#define	PSL_FE_DFLT	PSL_FE_DIS	/* default == none */
+#define	PSL_FE_DFLT	PSL_FE_PREC	/* default == precise */
 
 #ifndef LOCORE
 extern register_t psl_kernset;		/* Default MSR values for kernel */
Index: sys/powerpc/powerpc/exec_machdep.c
===================================================================
--- sys/powerpc/powerpc/exec_machdep.c
+++ sys/powerpc/powerpc/exec_machdep.c
@@ -1158,6 +1158,11 @@
 	sig = fpu_emulate(frame, &pcb->pcb_fpu);
 	if ((sig == 0 || sig == SIGFPE) && pcb->pcb_flags & PCB_FPU)
 		enable_fpu(td);
+#else
+	if (frame->srr1 & EXC_PGM_FPENABLED) {
+		/* Floating-Point Enabled Exception type Program interrupt */
+		sig = SIGFPE;
+	}
 #endif
 	if (sig == SIGILL) {
 		if (pcb->pcb_lastill != frame->srr0) {
Index: sys/powerpc/powerpc/trap.c
===================================================================
--- sys/powerpc/powerpc/trap.c
+++ sys/powerpc/powerpc/trap.c
@@ -397,8 +397,43 @@
 						ucode = ILL_PRVOPC;
 					else if (frame->srr1 & EXC_PGM_ILLEGAL)
 						ucode = ILL_ILLOPC;
-				} else if (sig == SIGFPE)
-					ucode = FPE_FLTINV;	/* Punt for now, invalid operation. */
+				} else if (sig == SIGFPE) {
+					int msr;
+					union {
+						double d;
+						struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
+							uint32_t reg;
+							uint32_t junk;
+#else
+							uint32_t junk;
+							uint32_t reg;
+#endif
+						} bits;
+					} u;
+
+					msr = mfmsr();
+
+					mtmsr(msr | PSL_FP);
+					__asm __volatile ("mffs 0; stfd 0,0(%0)"
+							:: "b"(&u.d));
+
+					mtmsr(msr);
+
+					ucode = 0;
+					if (u.bits.reg & FPSCR_ZX)
+						ucode |= FPE_FLTDIV;
+					if (u.bits.reg & FPSCR_OX)
+						ucode |= FPE_FLTOVF;
+					if (u.bits.reg & FPSCR_UX)
+						ucode |= FPE_FLTUND;
+					if (u.bits.reg & FPSCR_XX)
+						ucode |= FPE_FLTRES;
+					if (u.bits.reg & FPSCR_VX)
+						ucode |= FPE_FLTINV;
+
+					enable_fpu(td);
+				}
 			}
 			break;