Index: head/sys/arm64/arm64/identcpu.c =================================================================== --- head/sys/arm64/arm64/identcpu.c +++ head/sys/arm64/arm64/identcpu.c @@ -643,6 +643,41 @@ /* ID_AA64PFR0_EL1 */ +static struct mrs_field_value id_aa64pfr0_csv3[] = { + MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""), + MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_ISOLATED, "CSV3"), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_value id_aa64pfr0_csv2[] = { + MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_NONE, ""), + MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_ISOLATED, "CSV2"), + MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "SCXTNUM"), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_value id_aa64pfr0_dit[] = { + MRS_FIELD_VALUE(ID_AA64PFR0_DIT_NONE, ""), + MRS_FIELD_VALUE(ID_AA64PFR0_DIT_PSTATE, "PSTATE.DIT"), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_value id_aa64pfr0_amu[] = { + MRS_FIELD_VALUE(ID_AA64PFR0_AMU_NONE, ""), + MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1, "AMUv1"), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_value id_aa64pfr0_mpam[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, MPAM, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_value id_aa64pfr0_sel2[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SEL2, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static struct mrs_field_value id_aa64pfr0_sve[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SVE, NONE, IMPL), MRS_FIELD_VALUE_END, @@ -696,6 +731,12 @@ }; static struct mrs_field id_aa64pfr0_fields[] = { + MRS_FIELD(ID_AA64PFR0, CSV3, false, MRS_EXACT, id_aa64pfr0_csv3), + MRS_FIELD(ID_AA64PFR0, CSV2, false, MRS_EXACT, id_aa64pfr0_csv2), + MRS_FIELD(ID_AA64PFR0, DIT, false, MRS_EXACT, id_aa64pfr0_dit), + MRS_FIELD(ID_AA64PFR0, AMU, false, MRS_EXACT, id_aa64pfr0_amu), + MRS_FIELD(ID_AA64PFR0, MPAM, false, MRS_EXACT, id_aa64pfr0_mpam), + MRS_FIELD(ID_AA64PFR0, SEL2, false, MRS_EXACT, id_aa64pfr0_sel2), MRS_FIELD(ID_AA64PFR0, SVE, false, MRS_EXACT, id_aa64pfr0_sve), MRS_FIELD(ID_AA64PFR0, RAS, false, MRS_EXACT, id_aa64pfr0_ras), MRS_FIELD(ID_AA64PFR0, GIC, false, MRS_EXACT, id_aa64pfr0_gic), @@ -710,7 +751,30 @@ /* ID_AA64PFR1_EL1 */ +static struct mrs_field_value id_aa64pfr1_bt[] = { + MRS_FIELD_VALUE(ID_AA64PFR1_BT_NONE, ""), + MRS_FIELD_VALUE(ID_AA64PFR1_BT_IMPL, "BTI"), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_value id_aa64pfr1_ssbs[] = { + MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_NONE, ""), + MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE, "PSTATE.SSBS"), + MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE_MSR, "PSTATE.SSBS MSR"), + MRS_FIELD_VALUE_END, +}; + +static struct mrs_field_value id_aa64pfr1_mte[] = { + MRS_FIELD_VALUE(ID_AA64PFR1_MTE_NONE, ""), + MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL_EL0, "MTE EL0"), + MRS_FIELD_VALUE(ID_AA64PFR1_MTE_IMPL, "MTE"), + MRS_FIELD_VALUE_END, +}; + static struct mrs_field id_aa64pfr1_fields[] = { + MRS_FIELD(ID_AA64PFR1, BT, false, MRS_EXACT, id_aa64pfr1_bt), + MRS_FIELD(ID_AA64PFR1, SSBS, false, MRS_EXACT, id_aa64pfr1_ssbs), + MRS_FIELD(ID_AA64PFR1, MTE, false, MRS_EXACT, id_aa64pfr1_mte), MRS_FIELD_END, }; @@ -743,6 +807,13 @@ .Op2 = 0, .offset = __offsetof(struct cpu_desc, id_aa64pfr0), .fields = id_aa64pfr0_fields, + }, + { /* id_aa64pfr0_el1 */ + .reg = ID_AA64PFR1_EL1, + .CRm = 4, + .Op2 = 1, + .offset = __offsetof(struct cpu_desc, id_aa64pfr1), + .fields = id_aa64pfr1_fields, }, { /* id_aa64dfr0_el1 */ .reg = ID_AA64DFR0_EL1, Index: head/sys/arm64/include/armreg.h =================================================================== --- head/sys/arm64/include/armreg.h +++ head/sys/arm64/include/armreg.h @@ -517,6 +517,62 @@ #define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK) #define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT) #define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT) +#define ID_AA64PFR0_SEL2_SHIFT 36 +#define ID_AA64PFR0_SEL2_MASK (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT) +#define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK) +#define ID_AA64PFR0_SEL2_NONE (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT) +#define ID_AA64PFR0_SEL2_IMPL (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT) +#define ID_AA64PFR0_MPAM_SHIFT 40 +#define ID_AA64PFR0_MPAM_MASK (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT) +#define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK) +#define ID_AA64PFR0_MPAM_NONE (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT) +#define ID_AA64PFR0_MPAM_IMPL (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT) +#define ID_AA64PFR0_AMU_SHIFT 44 +#define ID_AA64PFR0_AMU_MASK (UL(0xf) << ID_AA64PFR0_AMU_SHIFT) +#define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK) +#define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT) +#define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT) +#define ID_AA64PFR0_DIT_SHIFT 48 +#define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT) +#define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK) +#define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT) +#define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT) +#define ID_AA64PFR0_CSV2_SHIFT 56 +#define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT) +#define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK) +#define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT) +#define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT) +#define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT) +#define ID_AA64PFR0_CSV3_SHIFT 60 +#define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT) +#define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK) +#define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT) +#define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT) + +/* ID_AA64PFR1_EL1 */ +#define ID_AA64PFR1_EL1 MRS_REG(3, 0, 0, 4, 1) +#define ID_AA64PFR1_BT_SHIFT 0 +#define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT) +#define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK) +#define ID_AA64PFR1_BT_NONE (UL(0x0) << ID_AA64PFR1_BT_SHIFT) +#define ID_AA64PFR1_BT_IMPL (UL(0x1) << ID_AA64PFR1_BT_SHIFT) +#define ID_AA64PFR1_SSBS_SHIFT 4 +#define ID_AA64PFR1_SSBS_MASK (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT) +#define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK) +#define ID_AA64PFR1_SSBS_NONE (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT) +#define ID_AA64PFR1_SSBS_PSTATE (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT) +#define ID_AA64PFR1_SSBS_PSTATE_MSR (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT) +#define ID_AA64PFR1_MTE_SHIFT 8 +#define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT) +#define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK) +#define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT) +#define ID_AA64PFR1_MTE_IMPL_EL0 (UL(0x1) << ID_AA64PFR1_MTE_SHIFT) +#define ID_AA64PFR1_MTE_IMPL (UL(0x2) << ID_AA64PFR1_MTE_SHIFT) +#define ID_AA64PFR1_RAS_frac_SHIFT 12 +#define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT) +#define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) +#define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) +#define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) /* MAIR_EL1 - Memory Attribute Indirection Register */ #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))