Index: sys/dev/hwpmc/hwpmc_amd.h
===================================================================
--- sys/dev/hwpmc/hwpmc_amd.h
+++ sys/dev/hwpmc/hwpmc_amd.h
@@ -76,6 +76,7 @@
 #define	AMD_PMC_PERFCTR_EP_DF_3	0xC0010247
 
 #define	AMD_NPMCS		16
+#define	AMD_CORE_NPMCS		6
 
 
 #define	AMD_PMC_COUNTERMASK	0xFF000000
Index: sys/dev/hwpmc/hwpmc_amd.c
===================================================================
--- sys/dev/hwpmc/hwpmc_amd.c
+++ sys/dev/hwpmc/hwpmc_amd.c
@@ -53,6 +53,8 @@
 enum pmc_class	amd_pmc_class;
 #endif
 
+#define	OVERFLOW_WAIT_COUNT	50
+
 /* AMD K7 & K8 PMCs */
 struct amd_descr {
 	struct pmc_descr pm_descr;  /* "base class" */
@@ -739,6 +741,7 @@
 	struct pmc_hw *phw;
 	const struct amd_descr *pd;
 	uint64_t config;
+	int i;
 
 	KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 	    ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
@@ -761,6 +764,22 @@
 	/* turn off the PMC ENABLE bit */
 	config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE;
 	wrmsr(pd->pm_evsel, config);
+
+	/*
+	 * Due to NMI latency on newer AMD processors
+	 * NMI interrupts are ignored, which leads to
+	 * panic or messages based on kernel configuraiton
+	 */
+
+	/* Wait for the count to be reset */
+	for (i = 0; i < OVERFLOW_WAIT_COUNT; i++)
+	{
+		if (rdmsr(pd->pm_perfctr) & (1 << (pd->pm_descr.pd_width - 1)))
+			break;
+
+		DELAY(1);
+	}
+
 	return 0;
 }
 
@@ -798,13 +817,12 @@
 	 *
 	 * If found, we call a helper to process the interrupt.
 	 *
-	 * If multiple PMCs interrupt at the same time, the AMD64
-	 * processor appears to deliver as many NMIs as there are
-	 * outstanding PMC interrupts.  So we process only one NMI
-	 * interrupt at a time.
+	 * PMCs interrupting at the same time are collapsed into
+	 * a single interrupt. Check all the valid pmcs for 
+	 * overflow.
 	 */
 
-	for (i = 0; retval == 0 && i < AMD_NPMCS; i++) {
+	for (i = 0; i < AMD_CORE_NPMCS; i++) {
 
 		if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL ||
 		    !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
@@ -820,8 +838,8 @@
 			continue;
 
 		/* Stop the PMC, reload count. */
-		evsel   = AMD_PMC_EVSEL_0 + i;
-		perfctr = AMD_PMC_PERFCTR_0 + i;
+		evsel	= amd_pmcdesc[i].pm_evsel;
+		perfctr	= amd_pmcdesc[i].pm_perfctr;
 		v       = pm->pm_sc.pm_reloadcount;
 		config  = rdmsr(evsel);