Index: head/sys/arm64/arm64/pmap.c
===================================================================
--- head/sys/arm64/arm64/pmap.c
+++ head/sys/arm64/arm64/pmap.c
@@ -221,8 +221,11 @@
  * The presence of this flag indicates that the mapping is writeable.
  * If the ATTR_AP_RO bit is also set, then the mapping is clean, otherwise it is
  * dirty.  This flag may only be set on managed mappings.
+ *
+ * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it
+ * as a software managed bit.
  */
-static pt_entry_t ATTR_SW_DBM;
+#define	ATTR_SW_DBM	ATTR_DBM
 
 struct pmap kernel_pmap_store;
 
@@ -783,15 +786,6 @@
 	vm_paddr_t start_pa, pa, min_pa;
 	uint64_t kern_delta;
 	int i;
-
-#ifdef notyet
-	/* Determine whether the hardware implements DBM management. */
-	uint64_t reg = READ_SPECIALREG(ID_AA64MMFR1_EL1);
-	ATTR_SW_DBM = ID_AA64MMFR1_HAFDBS(reg) == ID_AA64MMFR1_HAFDBS_AF_DBS ?
-	    ATTR_DBM : _ATTR_SW_DBM;
-#else
-	ATTR_SW_DBM = _ATTR_SW_DBM;
-#endif
 
 	kern_delta = KERNBASE - kernstart;
 
Index: head/sys/arm64/include/pte.h
===================================================================
--- head/sys/arm64/include/pte.h
+++ head/sys/arm64/include/pte.h
@@ -43,8 +43,8 @@
 #define	ATTR_MASK_L	UINT64_C(0x0000000000000fff)
 #define	ATTR_MASK	(ATTR_MASK_H | ATTR_MASK_L)
 /* Bits 58:55 are reserved for software */
-#define	ATTR_SW_UNUSED	(1UL << 58)
-#define	_ATTR_SW_DBM	(1UL << 57)
+#define	ATTR_SW_UNUSED2	(1UL << 58)
+#define	ATTR_SW_UNUSED1	(1UL << 57)
 #define	ATTR_SW_MANAGED	(1UL << 56)
 #define	ATTR_SW_WIRED	(1UL << 55)
 #define	ATTR_UXN	(1UL << 54)