Index: sys/dev/ntb/ntb_hw/ntb_hw_amd.h
===================================================================
--- sys/dev/ntb/ntb_hw/ntb_hw_amd.h
+++ sys/dev/ntb/ntb_hw/ntb_hw_amd.h
@@ -48,7 +48,8 @@
 #define	NTB_HW_AMD_H
 
 #define	NTB_HW_AMD_VENDOR_ID	0x1022
-#define	NTB_HW_AMD_DEVICE_ID	0x145B
+#define	NTB_HW_AMD_DEVICE_ID1	0x145B
+#define	NTB_HW_AMD_DEVICE_ID2	0x148B
 
 #define	NTB_DEF_PEER_CNT	1
 #define	NTB_DEF_PEER_IDX	0
@@ -136,7 +137,10 @@
 
 enum {
 	/* AMD NTB Capability */
-	AMD_MW_CNT		= 3,
+	AMD_MW_CNT1		= 3,
+	AMD_MW_CNT2		= 2,
+	AMD_BAR_START_IDX1	= 1,
+	AMD_BAR_START_IDX2	= 2,
 	AMD_DB_CNT		= 16,
 	AMD_MSIX_VECTOR_CNT	= 24,
 	AMD_SPADS_CNT		= 16,
@@ -233,6 +237,7 @@
 	struct callout		hb_timer;
 
 	uint8_t			mw_count;
+	uint8_t                 bar_start_idx;
 	uint8_t			spad_count;
 	uint8_t			db_count;
 	uint8_t			msix_vec_count;
Index: sys/dev/ntb/ntb_hw/ntb_hw_amd.c
===================================================================
--- sys/dev/ntb/ntb_hw/ntb_hw_amd.c
+++ sys/dev/ntb/ntb_hw/ntb_hw_amd.c
@@ -80,8 +80,12 @@
 MALLOC_DEFINE(M_AMD_NTB, "amd_ntb_hw", "amd_ntb_hw driver memory allocations");
 
 struct pci_device_table amd_ntb_devs[] = {
-	{ PCI_DEV(NTB_HW_AMD_VENDOR_ID, NTB_HW_AMD_DEVICE_ID),
-	  PCI_DESCR("AMD Non-Transparent Bridge") }
+	{ PCI_DEV(NTB_HW_AMD_VENDOR_ID, NTB_HW_AMD_DEVICE_ID1),
+	  PCI_DESCR("AMD Non-Transparent Bridge")
+	},
+	{ PCI_DEV(NTB_HW_AMD_VENDOR_ID, NTB_HW_AMD_DEVICE_ID2),
+	  PCI_DESCR("AMD Non-Transparent Bridge")
+	}
 };
 
 static unsigned g_amd_ntb_hw_debug_level;
@@ -312,7 +316,7 @@
 	if (mw_idx < 0 || mw_idx >= ntb->mw_count)
 		return (EINVAL);
 
-	bar_info = &ntb->bar_info[mw_idx+1];
+	bar_info = &ntb->bar_info[ntb->bar_start_idx + mw_idx];
 
 	if (base != NULL)
 		*base = bar_info->pbase;
@@ -330,10 +334,15 @@
 		*align_size = 1;
 
 	if (plimit != NULL) {
-		if (mw_idx != 0)
-			*plimit = BUS_SPACE_MAXADDR;
-		else
+		/*
+		 * For Device ID 0x145B (which has 3 memory windows),
+		 * memory window 0 uses a 32-bit bar. Rest all cases
+		 * uses 64-bit bar
+		 */
+		if ((ntb->mw_count == 3) && (mw_idx == 0))
 			*plimit = BUS_SPACE_MAXADDR_32BIT;
+		else
+			*plimit = BUS_SPACE_MAXADDR;
 	}
 
 	return (0);
@@ -348,7 +357,7 @@
 	if (mw_idx < 0 || mw_idx >= ntb->mw_count)
 		return (EINVAL);
 
-	bar_info = &ntb->bar_info[mw_idx+1];
+	bar_info = &ntb->bar_info[ntb->bar_start_idx + mw_idx];
 
 	/* make sure the range fits in the usable mw size */
 	if (size > bar_info->size) {
@@ -372,17 +381,24 @@
 	    __func__, mw_idx, bar_info->xlat_off,
 	    amd_ntb_peer_reg_read(8, bar_info->xlat_off), (void *)addr);
 
-	/* set and verify setting the limit */
-	if (mw_idx != 0) {
-		amd_ntb_reg_write(8, bar_info->limit_off, (uint64_t)size);
-		amd_ntb_printf(1, "%s: limit_off 0x%x cur_val 0x%jx limit 0x%x\n",
-		    __func__, bar_info->limit_off,
-		    amd_ntb_peer_reg_read(8, bar_info->limit_off), (uint32_t)size);
-	} else {
+	/* set and verify setting the limit
+	 *
+	 * For Device ID 0x145B (which has 3 memory windows),
+	 * memory window 0 uses a 32-bit bar. Rest all cases
+	 * uses 64-bit bar
+	 */
+	if ((ntb->mw_count == 3) && (mw_idx == 0)) {
 		amd_ntb_reg_write(4, bar_info->limit_off, (uint64_t)size);
 		amd_ntb_printf(1, "%s: limit_off 0x%x cur_val 0x%x limit 0x%x\n",
 		    __func__, bar_info->limit_off,
-		    amd_ntb_peer_reg_read(4, bar_info->limit_off), (uint32_t)size);
+		    amd_ntb_peer_reg_read(4, bar_info->limit_off),
+		    (uint32_t)size);
+	} else {
+		amd_ntb_reg_write(8, bar_info->limit_off, (uint64_t)size);
+		amd_ntb_printf(1, "%s: limit_off 0x%x cur_val 0x%lx limit 0x%x\n",
+		    __func__, bar_info->limit_off,
+		    amd_ntb_peer_reg_read(8, bar_info->limit_off),
+		    (uint32_t)size);
 	}
 
 	return (0);
@@ -411,7 +427,7 @@
 	if (mw_idx < 0 || mw_idx >= ntb->mw_count)
 		return (EINVAL);
 
-	bar_info = &ntb->bar_info[mw_idx+1];
+	bar_info = &ntb->bar_info[ntb->bar_start_idx + mw_idx];
 	if (mode == bar_info->map_mode)
 		return (0);
 
@@ -433,7 +449,7 @@
 	if (mw_idx < 0 || mw_idx >= ntb->mw_count)
 		return (EINVAL);
 
-	bar_info = &ntb->bar_info[mw_idx+1];
+	bar_info = &ntb->bar_info[ntb->bar_start_idx + mw_idx];
 	*mode = bar_info->map_mode;
 
 	return (0);
@@ -1001,7 +1017,6 @@
 static int
 amd_ntb_init_dev(struct amd_ntb_softc *ntb)
 {
-	ntb->mw_count		 = AMD_MW_CNT;
 	ntb->spad_count		 = AMD_SPADS_CNT;
 	ntb->db_count		 = AMD_DB_CNT;
 	ntb->db_valid_mask	 = (1ull << ntb->db_count) - 1;
@@ -1152,12 +1167,26 @@
 static int
 amd_ntb_probe(device_t device)
 {
+	struct amd_ntb_softc *ntb = device_get_softc(device);
 	const struct pci_device_table *tbl;
 
 	tbl = PCI_MATCH(device, amd_ntb_devs);
 	if (tbl == NULL)
 		return (ENXIO);
 
+	switch (tbl->device) {
+	case NTB_HW_AMD_DEVICE_ID1:
+		ntb->mw_count = AMD_MW_CNT1;
+		ntb->bar_start_idx = AMD_BAR_START_IDX1;
+		break;
+	case NTB_HW_AMD_DEVICE_ID2:
+		ntb->mw_count = AMD_MW_CNT2;
+		ntb->bar_start_idx = AMD_BAR_START_IDX2;
+		break;
+	default:
+		return (ENXIO);
+	}
+
 	device_set_desc(device, tbl->descr);
 
 	return (BUS_PROBE_GENERIC);