Index: sys/arm64/arm64/locore.S
===================================================================
--- sys/arm64/arm64/locore.S
+++ sys/arm64/arm64/locore.S
@@ -622,7 +622,7 @@
 		MAIR_ATTR(MAIR_NORMAL_WB, 2) |		\
 		MAIR_ATTR(MAIR_NORMAL_WT, 3)
 tcr:
-	.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K | \
+	.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TBI0 | TCR_TBI1 | TCR_TG1_4K | \
 	    TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
 sctlr_set:
 	/* Bits to set */
Index: sys/arm64/arm64/trap.c
===================================================================
--- sys/arm64/arm64/trap.c
+++ sys/arm64/arm64/trap.c
@@ -396,7 +396,7 @@
 	exception = ESR_ELx_EXCEPTION(esr);
 	switch (exception) {
 	case EXCP_INSN_ABORT_L:
-		far = READ_SPECIALREG(far_el1);
+		far = READ_SPECIALREG(far_el1) & 0xffffffffffff;
 
 		/*
 		 * Userspace may be trying to train the branch predictor to
@@ -412,7 +412,7 @@
 	case EXCP_UNKNOWN:
 	case EXCP_DATA_ABORT_L:
 	case EXCP_DATA_ABORT:
-		far = READ_SPECIALREG(far_el1);
+		far = READ_SPECIALREG(far_el1) & 0xffffffffffff;
 		break;
 	}
 	intr_enable();
Index: sys/arm64/include/armreg.h
===================================================================
--- sys/arm64/include/armreg.h
+++ sys/arm64/include/armreg.h
@@ -596,6 +596,8 @@
 
 /* TCR_EL1 - Translation Control Register */
 #define	TCR_ASID_16	(1 << 36)
+#define	TCR_TBI0	(1 << 37)
+#define	TCR_TBI1	(1 << 38)
 
 #define	TCR_IPS_SHIFT	32
 #define	TCR_IPS_32BIT	(0 << TCR_IPS_SHIFT)