Index: sys/amd64/amd64/pmap.c
===================================================================
--- sys/amd64/amd64/pmap.c
+++ sys/amd64/amd64/pmap.c
@@ -390,7 +390,7 @@
 	vm_size_t	sz;
 	int		mode;
 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
-static int pmap_initialized;
+int pmap_initialized;
 
 /*
  * Data for the pv entry allocation mechanism.
Index: sys/amd64/include/pmap.h
===================================================================
--- sys/amd64/include/pmap.h
+++ sys/amd64/include/pmap.h
@@ -414,6 +414,7 @@
 extern vm_paddr_t dmaplimit;
 extern int pmap_pcid_enabled;
 extern int invpcid_works;
+extern int pmap_initialized;
 
 #define	pmap_page_get_memattr(m)	((vm_memattr_t)(m)->md.pat_mode)
 #define	pmap_page_is_write_mapped(m)	(((m)->aflags & PGA_WRITEABLE) != 0)
Index: sys/amd64/pci/pci_cfgreg.c
===================================================================
--- sys/amd64/pci/pci_cfgreg.c
+++ sys/amd64/pci/pci_cfgreg.c
@@ -84,6 +84,9 @@
 		return (1);
 	cfgmech = CFGMECH_1;
 
+	if (!pmap_initialized)
+		return (1);
+
 	/*
 	 * Grope around in the PCI config space to see if this is a
 	 * chipset that is capable of doing memory-mapped config cycles.