Index: sys/amd64/pci/pci_cfgreg.c =================================================================== --- sys/amd64/pci/pci_cfgreg.c +++ sys/amd64/pci/pci_cfgreg.c @@ -44,12 +44,6 @@ #include #include -enum { - CFGMECH_NONE = 0, - CFGMECH_1, - CFGMECH_PCIE, -}; - static uint32_t pci_docfgregread(int bus, int slot, int func, int reg, int bytes); static int pciereg_cfgread(int bus, unsigned slot, unsigned func, @@ -61,7 +55,13 @@ SYSCTL_DECL(_hw_pci); -static int cfgmech; +/* + * For amd64 we assume that type 1 I/O port-based access always works. + * If an ACPI MCFG table exists, pcie_cfgregopen() will be called to + * switch to memory-mapped access. + */ +int cfgmech = CFGMECH_1; + static vm_offset_t pcie_base; static int pcie_minbus, pcie_maxbus; static uint32_t pcie_badslots; @@ -72,45 +72,13 @@ "Enable support for PCI-e memory mapped config access"); /* - * Initialise access to PCI configuration space + * Initialize access to PCI configuration space. The initialization + * is temporal and only used for early pci config accesses. Later, + * acpi subsystem calls pcie_cfgregopen() when MCFG table is found. */ int pci_cfgregopen(void) { - uint64_t pciebar; - uint16_t did, vid; - - if (cfgmech != CFGMECH_NONE) - return (1); - cfgmech = CFGMECH_1; - - /* - * Grope around in the PCI config space to see if this is a - * chipset that is capable of doing memory-mapped config cycles. - * This also implies that it can do PCIe extended config cycles. - */ - - /* Check for supported chipsets */ - vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2); - did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2); - switch (vid) { - case 0x8086: - switch (did) { - case 0x3590: - case 0x3592: - /* Intel 7520 or 7320 */ - pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16; - pcie_cfgregopen(pciebar, 0, 255); - break; - case 0x2580: - case 0x2584: - case 0x2590: - /* Intel 915, 925, or 915GM */ - pciebar = pci_cfgregread(0, 0, 0, 0x48, 4); - pcie_cfgregopen(pciebar, 0, 255); - break; - } - } return (1); } @@ -135,9 +103,6 @@ { uint32_t line; - if (cfgmech == CFGMECH_NONE) - return (0xffffffff); - /* * Some BIOS writers seem to want to ignore the spec and put * 0 in the intline rather than 255 to indicate none. Some use @@ -162,9 +127,6 @@ pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) { - if (cfgmech == CFGMECH_NONE) - return; - if (cfgmech == CFGMECH_PCIE && (bus >= pcie_minbus && bus <= pcie_maxbus) && (bus != 0 || !(1 << slot & pcie_badslots))) Index: sys/i386/pci/pci_cfgreg.c =================================================================== --- sys/i386/pci/pci_cfgreg.c +++ sys/i386/pci/pci_cfgreg.c @@ -64,20 +64,13 @@ vm_paddr_t papage; }; -enum { - CFGMECH_NONE = 0, - CFGMECH_1, - CFGMECH_2, - CFGMECH_PCIE, -}; - SYSCTL_DECL(_hw_pci); static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU]; static uint64_t pcie_base; static int pcie_minbus, pcie_maxbus; static uint32_t pcie_badslots; -static int cfgmech; +int cfgmech; static int devmax; static struct mtx pcicfg_mtx; static int mcfg_enable = 1; @@ -136,10 +129,8 @@ int pci_cfgregopen(void) { - static int opened = 0; - uint64_t pciebar; - u_int16_t vid, did; - u_int16_t v; + uint16_t v; + static int opened = 0; if (opened) return (1); @@ -158,38 +149,7 @@ if (v >= 0x0210) pci_pir_open(); - if (cfgmech == CFGMECH_PCIE) - return (1); - - /* - * Grope around in the PCI config space to see if this is a - * chipset that is capable of doing memory-mapped config cycles. - * This also implies that it can do PCIe extended config cycles. - */ - - /* Check for supported chipsets */ - vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2); - did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2); - switch (vid) { - case 0x8086: - switch (did) { - case 0x3590: - case 0x3592: - /* Intel 7520 or 7320 */ - pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16; - pcie_cfgregopen(pciebar, 0, 255); - break; - case 0x2580: - case 0x2584: - case 0x2590: - /* Intel 915, 925, or 915GM */ - pciebar = pci_cfgregread(0, 0, 0, 0x48, 4); - pcie_cfgregopen(pciebar, 0, 255); - break; - } - } - - return(1); + return (1); } static uint32_t Index: sys/x86/include/pci_cfgreg.h =================================================================== --- sys/x86/include/pci_cfgreg.h +++ sys/x86/include/pci_cfgreg.h @@ -48,6 +48,17 @@ #define CONF2_ENABLE_CHK 0x0e #define CONF2_ENABLE_RES 0x0e +enum { + CFGMECH_NONE = 0, + CFGMECH_1, + CFGMECH_2, + CFGMECH_PCIE, +}; + +#ifdef _KERNEL +extern int cfgmech; +#endif + rman_res_t hostb_alloc_start(int type, rman_res_t start, rman_res_t end, rman_res_t count); int pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus); int pci_cfgregopen(void); Index: sys/x86/x86/legacy.c =================================================================== --- sys/x86/x86/legacy.c +++ sys/x86/x86/legacy.c @@ -46,8 +46,10 @@ #include #include #include +#include #include +#include #include #include @@ -111,11 +113,53 @@ return (0); } +/* + * Grope around in the PCI config space to see if this is a chipset + * that is capable of doing memory-mapped config cycles. This also + * implies that it can do PCIe extended config cycles. + */ +static void +legacy_pci_cfgregopen(device_t dev) +{ + uint64_t pciebar; + u_int16_t did, vid; + + if (cfgmech == CFGMECH_NONE || cfgmech == CFGMECH_PCIE) + return; + + /* Check for supported chipsets */ + vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2); + did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2); + switch (vid) { + case 0x8086: + switch (did) { + case 0x3590: + case 0x3592: + /* Intel 7520 or 7320 */ + pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16; + pcie_cfgregopen(pciebar, 0, 255); + break; + case 0x2580: + case 0x2584: + case 0x2590: + /* Intel 915, 925, or 915GM */ + pciebar = pci_cfgregread(0, 0, 0, 0x48, 4); + pcie_cfgregopen(pciebar, 0, 255); + break; + } + } + + if (bootverbose && cfgmech == CFGMECH_PCIE) + device_printf(dev, "Enabled ECAM PCIe accesses\n"); +} + static int legacy_attach(device_t dev) { device_t child; + legacy_pci_cfgregopen(dev); + /* * Let our child drivers identify any child devices that they * can find. Once that is done attach any devices that we