Index: sys/conf/files.amd64 =================================================================== --- sys/conf/files.amd64 +++ sys/conf/files.amd64 @@ -363,6 +363,17 @@ dev/nvram/nvram.c optional nvram isa dev/random/ivy.c optional rdrand_rng dev/random/nehemiah.c optional padlock_rng +dev/tn40xx/AQR105_phy.c optional tn40xx pci +dev/tn40xx/AQR105_phy_FreeBSD.c optional tn40xx pci +dev/tn40xx/CX4.c optional tn40xx pci +dev/tn40xx/CX4_FreeBSD.c optional tn40xx pci +dev/tn40xx/QT2025_phy.c optional tn40xx pci +dev/tn40xx/QT2025_phy_FreeBSD.c optional tn40xx pci +dev/tn40xx/TLK10232_phy.c optional tn40xx pci +dev/tn40xx/TLK10232_phy_FreeBSD.c optional tn40xx pci +dev/tn40xx/tn40.c optional tn40xx pci +dev/tn40xx/tn40_hw.c optional tn40xx pci +dev/tn40xx/tn40_mbuf.c optional tn40xx pci dev/qlxge/qls_dbg.c optional qlxge pci dev/qlxge/qls_dump.c optional qlxge pci dev/qlxge/qls_hw.c optional qlxge pci Index: sys/dev/tn40xx/AQR105_phy.h =================================================================== --- /dev/null +++ sys/dev/tn40xx/AQR105_phy.h @@ -0,0 +1,36106 @@ + +#ifndef _AQR105_PHY_H +#define _AQR105_PHY_H + +unsigned int AQR105_phy_firmware_len = 288770; +static u8 AQR105_phy_firmware[] __initdata = { +/* AQ28nm_v2.C.7-AQR_Tehuti_TN9510_AQR205_ID12385_VER880.cld */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x69, 0x33 +}; +#endif Index: sys/dev/tn40xx/AQR105_phy.c =================================================================== --- /dev/null +++ sys/dev/tn40xx/AQR105_phy.c @@ -0,0 +1,577 @@ +#include "tn40.h" +#include "AQR105_phy.h" + +#define mailboxWrite (0xC000) +#define phyImageHeaderContentOffset (0x300) +#define r1 (0x1E) +#define LINK_LOOP_MAX (25) + +//#define AQ_VERBOSE + +void AQR105_register_settings(struct bdx_priv *priv); +int AQR105_mdio_reset(struct bdx_priv *priv, int port, unsigned short phy); +u32 AQR105_link_changed(struct bdx_priv *priv); +void AQR105_leds(struct bdx_priv *priv, enum PHY_LEDS_OP op); + +//------------------------------------------------------------------------------------------------- + +int AQR105_set_speed(struct bdx_priv *priv, signed int speed) +{ + u16 val, port = priv->phy_mdio_port; + int rVal = 0; + + if (priv->autoneg == AUTONEG_ENABLE) + { + DBG("AQR105 speed %d Autoneg\n", speed); + BDX_MDIO_WRITE(priv, 0x07, 0x10, 0x9101); + BDX_MDIO_WRITE(priv, 0x07, 0xC400, 0x9C5A); + BDX_MDIO_WRITE(priv, 0x07, 0x20, 0x1001); + } + else + { + switch (speed) + { + case 10000: //10G + DBG("AQR105 speed 10G\n"); + BDX_MDIO_WRITE(priv, 0x07, 0x10, 0x9001); + BDX_MDIO_WRITE(priv, 0x07, 0xC400, 0x40); + BDX_MDIO_WRITE(priv, 0x07, 0x20, 0x1001); + break; + + case 5000: //5G + DBG("AQR105 speed 5G\n"); + BDX_MDIO_WRITE(priv, 0x07, 0x10, 0x9001); + BDX_MDIO_WRITE(priv, 0x07, 0xC400, 0x840); + BDX_MDIO_WRITE(priv, 0x07, 0x20, 0x1); + break; + + case 2500: //2.5G + DBG("AQR105 speed 10G\n"); + BDX_MDIO_WRITE(priv, 0x07, 0x10, 0x9001); + BDX_MDIO_WRITE(priv, 0x07, 0xC400, 0x440); + BDX_MDIO_WRITE(priv, 0x07, 0x20, 0x1); + break; + + case 1000: //1G + DBG("AQR105 speed 1G\n"); + BDX_MDIO_WRITE(priv, 0x07, 0x10, 0x8001); + BDX_MDIO_WRITE(priv, 0x07, 0xC400, 0x8040); + BDX_MDIO_WRITE(priv, 0x07, 0x20, 0x1); + break; + + case 100: //100m + DBG("AQR105 speed 100m\n"); + BDX_MDIO_WRITE(priv, 0x07, 0x10, 0x101); + BDX_MDIO_WRITE(priv, 0x07, 0xC400, 0x40); + BDX_MDIO_WRITE(priv, 0x07, 0x20, 0x1); + break; + + default: + ERR("does not support speed %u\n", speed); + rVal = -1; + break; + } + } + if (rVal == 0) + { + // restart autoneg + val = (1 << 12) | (1 << 9) | (1 << 13); + BDX_MDIO_WRITE(priv, 0x07, 0x0, val); + } + + return rVal; + +} // AQR105_set_settings() +//------------------------------------------------------------------------------------------------- + +__init int AQR105_mdio_reset(struct bdx_priv *priv, int port, unsigned short phy) +{ + u16 val, val1,val2; + int rVal = 0; + u32 i; + u8 *image=AQR105_phy_firmware; + u32 primaryHeaderPtr; + u32 primaryIramPtr,primaryIramSize,primaryDramPtr,primaryDramSize; + u32 byteSize, dWordSize,bytePointer; + u16 msw=0,lsw=0, sd, sv; + + ENTER; + + BDX_MDIO_WRITE(priv, 0x1E, 0, 1<<0xF); // Soft Reset + msleep(10); + BDX_MDIO_WRITE(priv, 0x1E, 0, 0); // + + BDX_MDIO_WRITE(priv, 0x1E, 0xC001, 1<<0xF); // uP Reset + msleep(10); + BDX_MDIO_WRITE(priv, 0x1E, 0xC001, 0); // + msleep(1); + + val1 = bdx_mdio_read(priv, r1, port, 0xC441); + +//Reset start + BDX_MDIO_WRITE(priv, 4,0xC440,1); //Reset XAUI SerDes + for(i=3;i--;){ //Wait until XAUI Serdes reset done and clear + val = bdx_mdio_read(priv, 4, port, 0xC440); + //ERR("AQPHYXS RST 4.C440=%x loop =%u\n",val,i); + if(!val) break; + msleep(1); + } + BDX_MDIO_WRITE(priv, 4,0xC440,0); //clear Reset XAUI SerDes (probably needed) + + val = bdx_mdio_read(priv, 4, port, 0x0); + BDX_MDIO_WRITE(priv, 4,0x0,0xA040); //Reset PHY XS core + bdx_mdio_get(priv);//Wait until MDIO transaction finished + + msleep(2); + BDX_MDIO_WRITE(priv, 4,0x0,0x2040); //Reset PHY XS core + for(i=10;i--;){ //Wait until PHy XS register read correctly + val = bdx_mdio_read(priv, 4, port, 0x0); + if(!(val==0xFFFF)) break; + msleep(1); + } +//Reset End + + BDX_MDIO_WRITE(priv, r1,0xC452,1); //NVR Daisy Chain Disable + BDX_MDIO_WRITE(priv, r1,0xC441,0); + + val=0;//bdx_mdio_read(priv, r1, port,0xC001); + val |= 1; //upRunStall + val |= 1<<6; //upRunStallOverride + BDX_MDIO_WRITE(priv, r1,0xC001,val); + + /*--- Read the segment addresses and sizes -----------------*/ + primaryHeaderPtr = (((image[0x9] & 0x0F) << 8) | image[0x8]) << 12; + + primaryIramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4]; + primaryIramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7]; + primaryDramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA]; + primaryDramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 2] << 16) | + (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 1] << 8) | + image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD]; + + if ( 1 /*AQ_DEVICE_HHD == port->device*/ ) { + primaryIramPtr += primaryHeaderPtr; + primaryDramPtr += primaryHeaderPtr; + } + +#ifdef AQ_VERBOSE + MSG ("Segment Addresses and Sizes as read from the PHY ROM image header:\n\n"); + MSG ("Primary Iram Address: 0x%x\n", primaryIramPtr); + MSG ("Primary Iram Size: 0x%x\n", primaryIramSize); + MSG ("Primary Dram Address: 0x%x\n", primaryDramPtr); + MSG ("Primary Dram Size: 0x%x\n\n", primaryDramSize); +#endif + + /*-- Load IRAM and DRAM ----------------------*/ + + /* clear the mailbox CRC */ + BDX_MDIO_WRITE(priv, r1,0x200,0x1000); /*resetUpMailboxCrc*/ + BDX_MDIO_WRITE(priv, r1,0x200,0x0000); /*resetUpMailboxCrc*/ + + /* load the IRAM */ +#ifdef AQ_VERBOSE + MSG ("Loading IRAM:\n"); +#endif + +//#define AQ_IRAM_BASE_ADDRESS 0x40000000 + + BDX_MDIO_WRITE(priv, r1,0x202,0x4000); //msw + BDX_MDIO_WRITE(priv, r1,0x203,0x0000); //lsw + + /* set block size so that there are from 0-3 bytes remaining */ + byteSize = primaryIramSize; + dWordSize = byteSize >> 2; + + bytePointer = primaryIramPtr; + for (i = 0; i < dWordSize; i++) + { + /* write 4 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + + BDX_MDIO_WRITE(priv, r1,0x204,msw); + BDX_MDIO_WRITE(priv, r1,0x205,lsw); + val = bdx_mdio_read(priv, r1, port, 0x200); + if (val & (1<<8)) + { + ERR("Mailbox Busy !!!\n"); + return -1; + } + BDX_MDIO_WRITE(priv, r1,0x200,mailboxWrite); + } + /* Note: this final write right-justifies non-dWord data in the final dWord */ + if(byteSize & 0x3){ + switch (byteSize & 0x3) + { + case 0x1: + /* write 1 byte of data */ + lsw = image[bytePointer++]; + msw = 0x0000; + break; + + case 0x2: + /* write 2 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = 0x0000; + break; + + case 0x3: + /* write 3 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = image[bytePointer++]; + break; + } + BDX_MDIO_WRITE(priv, r1,0x204,msw); + BDX_MDIO_WRITE(priv, r1,0x205,lsw); + BDX_MDIO_WRITE(priv, r1,0x200,mailboxWrite); + } + + /* load the DRAM */ +#ifdef AQ_VERBOSE + MSG ("Last IRAM data lsw=0x%x msw=0x%x \n",lsw, msw); + msw = bdx_mdio_read(priv, r1, port, 0x202); + lsw = bdx_mdio_read(priv, r1, port, 0x203); + MSG ("Last+1 IRAM address lsw=0x%x msw=0x%x \n",lsw, msw); + MSG ("Loading DRAM:\n"); +#endif + +//#define AQ_DRAM_BASE_ADDRESS 0x3FFE0000 + BDX_MDIO_WRITE(priv, r1,0x202,0x3FFE); //msw + BDX_MDIO_WRITE(priv, r1,0x203,0x0000); //lsw + + /* set block size so that there are from 0-3 bytes remaining */ + byteSize = primaryDramSize; + dWordSize = byteSize >> 2; + + bytePointer = primaryDramPtr; + for (i = 0; i < dWordSize; i++) + { + /* write 4 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + BDX_MDIO_WRITE(priv, r1,0x204,msw); + BDX_MDIO_WRITE(priv, r1,0x205,lsw); + BDX_MDIO_WRITE(priv, r1,0x200,mailboxWrite); + } + + /* Note: this final write right-justifies non-dWord data in the final dWord */ + if(byteSize & 0x3){ + switch (byteSize & 0x3) + { + case 0x1: + /* write 1 byte of data */ + lsw = image[bytePointer++]; + msw = 0x0000; + break; + + case 0x2: + /* write 2 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = 0x0000; + break; + + case 0x3: + /* write 3 bytes of data */ + lsw = (image[bytePointer+1] << 8) | image[bytePointer]; + bytePointer += 2; + msw = image[bytePointer++]; + break; + } + BDX_MDIO_WRITE(priv, r1,0x204,msw); + BDX_MDIO_WRITE(priv, r1,0x205,lsw); + BDX_MDIO_WRITE(priv, r1,0x200,mailboxWrite); + } + +#ifdef AQ_VERBOSE + MSG ("Last DRAM data lsw=0x%x msw=0x%x \n",lsw, msw); + msw = bdx_mdio_read(priv, r1, port, 0x202); + lsw = bdx_mdio_read(priv, r1, port, 0x203); + MSG ("Last+1 DRAM address lsw=0x%x msw=0x%x \n",lsw, msw); +#endif + + /*-- Clear any resets -----------------------------------*/ + BDX_MDIO_WRITE(priv, r1,0,0); + + /*-- Release the uP --------------------------------------*/ + + val = 1; //upRunStall + val |= 1<<6; //upRunStallOverride + BDX_MDIO_WRITE(priv, r1,0xC001,val); + val |= 1<<15; //upReset + BDX_MDIO_WRITE(priv, r1,0xC001,val); + + /* Need to wait at least 100us. */ + msleep(200); + BDX_MDIO_WRITE(priv, r1,0xC001, 0x40); + for(i=100;i--;){ + msleep(20); + val = bdx_mdio_read(priv, r1, port, 0xCC00); + if(val&(1<<6)) break; +// ERR("1E.CC00.6 loop =%u\n",i); + }; + /*if(!(val&(1<<6))){ // Reset timeout + ERR("AQR105 FW reset timeout 1E.CC00=%x\n",val); + };*/ + + val = bdx_mdio_read(priv, r1, port, 0x20); + val2 = bdx_mdio_read(priv, r1, port, 0xC885); + val1 = val >> 8; + val &= 0xFF; + val2 &= 0xFF; + MSG("AQR105 FW ver: %x.%x.%x\n",val1,val,val2); +//Enable AQRate speeds + msleep(20); + BDX_MDIO_WRITE(priv, 0x07,0x10,0x9101); + BDX_MDIO_WRITE(priv, 0x07,0xC400,0x9C5A); + BDX_MDIO_WRITE(priv, 0x07,0x20,0x1001); + // restart autoneg + val=(1<<12)|(1<<9)|(1<<13); + BDX_MDIO_WRITE(priv, 0x07,0x0,val); + +#if 1 // led setup +/* +0xC430=f // Act led (right) black-no link or no act; green-link blink on act +0xC431=80 // Speed led Amber -on on 10G +Tehuti settings +0xC432=C040 // Speed led Green -on on 5G/2.5G/1G (black on 100M) +D-link settings +0xC432=C060 // Speed led Green -on on 5G/2.5/1G/100M +*/ +{ +//ACT Led - off on no link + sv=priv->subsystem_vendor; + sd=priv->subsystem_device; + + if ((sv == 0x105A) && (sd == 0x7203)) + { // Promise + BDX_MDIO_WRITE(priv, r1, 0xC430, 0xc0ef); + BDX_MDIO_WRITE(priv, r1, 0xC431, 0xC080); + BDX_MDIO_WRITE(priv, r1, 0xC432, 0xC040); + } + else + { + BDX_MDIO_WRITE(priv, r1, 0xC430, 0x00); + BDX_MDIO_WRITE(priv, r1, 0xC431, 0x80); + if ((sv == 0x1186) && (sd == 0x2900)) + { //isDlink + BDX_MDIO_WRITE(priv, r1, 0xC432, 0xC060); + } + else + { + BDX_MDIO_WRITE(priv, r1, 0xC432, 0xC040); + } + } +} +#endif + +return rVal; + +} // AQR105_mdio_reset + +//------------------------------------------------------------------------------------------------- + +static int AQR105_get_link_speed(struct bdx_priv *priv) +{ + unsigned short val; //, leds; + int link = 0; + u16 ActLnk_MSK = 0; + u16 sd, sv; + + ENTER; + val = bdx_mdio_read(priv, 7, priv->phy_mdio_port, 0xC810); + val = bdx_mdio_read(priv, 7, priv->phy_mdio_port, 0xC810); +//DBG("AQR105 7.C810 = 0x%x\n", val); + val = val>>9; + val &=0x1f; + if (val == 4) // Link up + { + val = bdx_mdio_read(priv, 7, priv->phy_mdio_port, 0xC800); + val = bdx_mdio_read(priv, 7, priv->phy_mdio_port, 0xC800); +//DBG("AQR105 7.c800 val=%x\n",val); + val &= 0xF; + if((val >> 1)>0){ + sv=priv->subsystem_vendor; + sd=priv->subsystem_device; + if(!((sv==0x1186)&&(sd==0x2900))){ //isNotDlink + ActLnk_MSK = 0xC0E0 ; + } + bdx_mdio_write(priv, 0x1E, priv->phy_mdio_port, 0xC430,0x0f | ActLnk_MSK); + } + switch(val >> 1) + { + case 5: //SPEED_RES_5GIG + link = SPEED_5000; + DBG("AQR105 5G link detected\n"); + break; + + case 4: //SPEED_RES_2.5GIG + link = SPEED_2500; + DBG("AQR105 2.5G link detected\n"); + break; + + case 3: //SPEED_RES_10GIG + link = SPEED_10000; + DBG("AQR105 10G link detected\n"); + break; + + case 2: // SPEED_RES_1GIG + link = SPEED_1000; + DBG("AQR105 1G link detected\n"); + break; + + case 1: // SPEED_RES_100M + link = SPEED_100; + DBG("AQR105 100M %s link detected\n", (val & 1 ) ? "" :"Half Duplex" ); + break; + + case 0: // SPEED_RES_10M + link = 0; + bdx_mdio_write(priv, 0x1E, priv->phy_mdio_port, 0xC430,0x0); + DBG("AQR105 10M %s link detected. Not Supported\n", (val & 1 ) ? "" :"Half Duplex" ); + break; + + } + priv->errmsg_count = 0; + } + else + { + bdx_mdio_write(priv, 0x1E, priv->phy_mdio_port, 0xC430,0x0); + if (++priv->errmsg_count < MAX_ERRMSGS) + { + DBG("AQR105 link down.\n"); + } + } + + RET(link); + +} // AQR105_get_link_speed() + +//------------------------------------------------------------------------------------------------- + +u32 AQR105_link_changed(struct bdx_priv *priv) +{ + u32 link, speed; + + ENTER; + speed = AQR105_get_link_speed(priv); + DBG("AQR105_link_changed speed=%u priv->link_speed=%u\n",speed,priv->link_speed); + if(speed != (u32)priv->link_speed) + { + switch (speed) + { + case SPEED_10000: + DBG("AQR105 10G link detected\n"); + break; + case SPEED_5000: + DBG("AQR105 5G link detected\n"); + break; + case SPEED_2500: + DBG("AQR105 2.5G link detected\n"); + break; + case SPEED_1000: + DBG("AQR105 1G link detected\n"); + break; + case SPEED_100: + DBG("AQR105 100M link detected\n"); + break; + case SPEED_10: + DBG("AQR105 10M link detected\n"); + break; + default: + DBG("AQR105 link down.\n"); + break; + } + bdx_speed_changed(priv,speed); + } + link = 0; + if((!speed) || (!(link = (READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT)))) // // XAUI link + { + u32 timeout; + if (speed) + { + timeout = 1000000; // 1/5 sec + if(priv->link_loop_cnt++ > LINK_LOOP_MAX) + { + bdx_speed_changed(priv,0); + priv->link_loop_cnt = 0; + DBG("AQR105 trying to recover link after %d tries\n", LINK_LOOP_MAX); + } + } + else + { + timeout = 5000000; // 1 sec + } + DBG("AQR105 link = 0x%x speed = 0x%x setting %d timer\n", link, speed, timeout); + WRITE_REG(priv, 0x5150,timeout); + } + + RET(link); + +} // AQR105_link_changed() + +//------------------------------------------------------------------------------------------------- + +void AQR105_leds(struct bdx_priv *priv, enum PHY_LEDS_OP op) +{ + u16 dev=0x1e, led=0xC430, led_off=0, led_on=(1<<8); + + switch (op) + { + case PHY_LEDS_SAVE: + priv->phy_ops.leds[0] = bdx_mdio_read(priv, dev, priv->phy_mdio_port, led); + bdx_mdio_write(priv, dev, priv->phy_mdio_port, led, led_off); + break; + + case PHY_LEDS_RESTORE: + bdx_mdio_write(priv, dev, priv->phy_mdio_port, led, priv->phy_ops.leds[0]); + + break; + + case PHY_LEDS_ON: + bdx_mdio_write(priv, dev, priv->phy_mdio_port, led, led_on); + + break; + + case PHY_LEDS_OFF: + bdx_mdio_write(priv, dev, priv->phy_mdio_port, led, led_off); + + break; + + default: + DBG("AQR105_leds() unknown op 0x%x\n", op); + break; + + } + +} // AQR105_leds() + +//------------------------------------------------------------------------------------------------- + +__init enum PHY_TYPE AQR105_register(struct bdx_priv *priv) +{ + priv->isr_mask= IR_RX_FREE_0 | IR_LNKCHG0 |IR_LNKCHG1 | IR_PSE | IR_TMR0 | IR_RX_DESC_0 | IR_TX_FREE_0; + priv->phy_ops.mdio_reset = AQR105_mdio_reset; + priv->phy_ops.link_changed = AQR105_link_changed; + priv->phy_ops.ledset = AQR105_leds; + priv->phy_ops.mdio_speed = MDIO_SPEED_6MHZ; + AQR105_register_settings(priv); + + return PHY_TYPE_AQR105; + +} // AQR105_register() + +//------------------------------------------------------------------------------------------------- + Index: sys/dev/tn40xx/AQR105_phy_FreeBSD.c =================================================================== --- /dev/null +++ sys/dev/tn40xx/AQR105_phy_FreeBSD.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include "tn40.h" + +void AQR105_register_settings(struct bdx_priv *priv); +int AQR105_setMedia (struct bdx_priv *priv, int ifm_media); +//------------------------------------------------------------------------------------------------- + +int AQR105_setMedia(struct bdx_priv *priv, int ifm_media) +{ + int rVal, speed = -1; + + if (ifm_media == 0) + { + speed = 0; + priv->autoneg = AUTONEG_ENABLE; + } + else + { + priv->autoneg = AUTONEG_DISABLE; + switch (ifm_media) + { + case IFM_10G_T: + speed = 10000; + break; + + case IFM_5000_T: + speed = 5000; + break; + + case IFM_2500_T: + speed = 2500; + break; + + case IFM_1000_T: + speed = 1000; + break; + + case IFM_100_T: + speed = 100; + break; + + default: + ERR("Unsupported mediad 0x%x\n", ifm_media); + break; + } + } + if (speed >= 0) + { + rVal = AQR105_set_speed(priv, speed); + } + else + { + rVal = -1; + } + return rVal; + +} // AQR105_setMedia() + +//------------------------------------------------------------------------------------------------- + +__init void AQR105_register_settings(struct bdx_priv *priv) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + struct ifmedia *ifm = &tn40_priv->media; + + priv->autoneg = AUTONEG_ENABLE; + ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); + ifmedia_add(ifm, IFM_ETHER | IFM_10G_T | IFM_FDX, 0, NULL); + ifmedia_add(ifm, IFM_ETHER | IFM_5000_T | IFM_FDX, 0, NULL); + ifmedia_add(ifm, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL); + ifmedia_add(ifm, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); + ifmedia_add(ifm, IFM_ETHER | IFM_100_T | IFM_FDX, 0, NULL); + ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); + + priv->phy_ops.set_settings = AQR105_setMedia; + +} // AQR105_register_settings() + +//------------------------------------------------------------------------------------------------- + Index: sys/dev/tn40xx/CX4.c =================================================================== --- /dev/null +++ sys/dev/tn40xx/CX4.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include "tn40.h" + +#define LINK_LOOP_MAX (10) + +void CX4_register_settings (struct bdx_priv *priv); +int CX4_mdio_reset (struct bdx_priv *priv, int port, unsigned short phy); +u32 CX4_link_changed (struct bdx_priv *priv); +void CX4_leds (struct bdx_priv *priv, enum PHY_LEDS_OP op); +//------------------------------------------------------------------------------------------------- + +int CX4_mdio_reset(struct bdx_priv *priv, int port, unsigned short phy) +{ + + return 0; + +} // CX4_mdio_reset + +//------------------------------------------------------------------------------------------------- + +u32 CX4_link_changed(struct bdx_priv *priv) +{ + u32 link=0; + + if (priv->link_speed != SPEED_10000) + { + bdx_speed_changed(priv, SPEED_10000); + } + link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT; + if (link) + { + link = SPEED_10000; + DBG("CX4 link speed is 10G\n"); + } + else + { + if(priv->link_loop_cnt++ > LINK_LOOP_MAX) + { + DBG("CX4 MAC reset\n"); + priv->link_speed = 0; + priv->link_loop_cnt = 0; + } + DBG("CX4 no link, setting 1/5 sec timer\n"); + WRITE_REG(priv, 0x5150,1000000); // 1/5 sec timeout + } + + return link; + +} // CX4_link_changed() + +//------------------------------------------------------------------------------------------------- + +void CX4_leds(struct bdx_priv *priv, enum PHY_LEDS_OP op) +{ + switch (op) + { + case PHY_LEDS_SAVE: + break; + + case PHY_LEDS_RESTORE: + break; + + case PHY_LEDS_ON: + break; + + case PHY_LEDS_OFF: + break; + + default: + DBG("CX4_leds() unknown op 0x%x\n", op); + break; + + } + +} // CX4_leds() + + +//------------------------------------------------------------------------------------------------- + +__init enum PHY_TYPE CX4_register(struct bdx_priv *priv) +{ + priv->isr_mask= IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | IR_TMR0 | IR_RX_DESC_0 | IR_TX_FREE_0; + priv->phy_ops.mdio_reset = CX4_mdio_reset; + priv->phy_ops.link_changed = CX4_link_changed; + priv->phy_ops.ledset = CX4_leds; + CX4_register_settings(priv); + + return PHY_TYPE_CX4; + +} // CX4_init() + +//------------------------------------------------------------------------------------------------- + Index: sys/dev/tn40xx/CX4_FreeBSD.c =================================================================== --- /dev/null +++ sys/dev/tn40xx/CX4_FreeBSD.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include "tn40.h" + +void CX4_register_settings(struct bdx_priv *priv); +//------------------------------------------------------------------------------------------------- + +__init void CX4_register_settings(struct bdx_priv *priv) +{ + + priv->autoneg = AUTONEG_DISABLE; +} // CX4_register_settings() + +//------------------------------------------------------------------------------------------------- + Index: sys/dev/tn40xx/QT2025_phy.h =================================================================== --- /dev/null +++ sys/dev/tn40xx/QT2025_phy.h @@ -0,0 +1,3076 @@ + +#ifndef _QT2025x_PHY_H +#define _QT2025x_PHY_H + +//QT2x25D_module_firmware_v2_0_3_3_ff_MDIO.bin +static u16 QT2025_phy_firmware[] __initdata = { +0x02,0x07,0x0c,0x90,0x11,0x60,0xef,0xf0, +0x00,0x00,0x22,0x02,0x05,0x9c,0x89,0x82, +0x8a,0x83,0x8b,0x93,0x15,0x93,0x53,0x93, +0x7f,0xbb,0x80,0x00,0x50,0x05,0xe0,0x75, +0x93,0x00,0x22,0xe4,0x93,0x75,0x93,0x00, +0x22,0x89,0x82,0x8a,0x83,0x8b,0x93,0x15, +0x93,0x53,0x93,0x7f,0xbb,0x80,0x00,0x50, +0x01,0xf0,0x75,0x93,0x00,0x22,0x89,0x82, +0x8a,0x83,0x8b,0x93,0x15,0x93,0x53,0x93, +0x7f,0xbb,0x80,0x00,0x50,0x09,0xe0,0xf5, +0xf0,0xa3,0xe0,0x75,0x93,0x00,0x22,0xe4, +0x93,0xf5,0xf0,0x74,0x01,0x93,0x75,0x93, +0x00,0x22,0x89,0x82,0x8a,0x83,0x8b,0x93, +0x15,0x93,0x53,0x93,0x7f,0xbb,0x80,0x00, +0x50,0x05,0xf0,0xa3,0xe5,0xf0,0xf0,0x75, +0x93,0x00,0x22,0x89,0x82,0x8a,0x83,0x8b, +0x93,0x15,0x93,0x53,0x93,0x7f,0xbb,0x80, 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short phy); +u32 QT2025_link_changed(struct bdx_priv *priv); +void QT2025_leds(struct bdx_priv *priv, enum PHY_LEDS_OP op); + +//------------------------------------------------------------------------------------------------- + +static int QT2025_get_link_speed(struct bdx_priv *priv) +{ + int speed; + u16 module = (bdx_mdio_read(priv, 3, priv->phy_mdio_port, 0xD70C)) & 0xFF; + + switch (module) + { + case 5: + case 6: + case 8: + case 9: + speed = SPEED_1000; + break; + + default: + speed = SPEED_10000; + break; + + } + + return speed; + +} // QT2025_get_link_speed() + +//------------------------------------------------------------------------------------------------- + +__init int QT2025_mdio_reset(struct bdx_priv *priv, int port, unsigned short phy) +{ + u16 *phy_fw= QT2025_phy_firmware,j, fwVer01, fwVer2, fwVer3, module; + int s_fw, i, a; + int phy_id= 0, rev= 0; + + phy_id= bdx_mdio_read(priv, 1, port, 0xD001); + // ERR("PHY_ID %x, port=%x\n", phy_id, port); + + switch(0xFF&(phy_id>> 8)) + { + case 0xb3: + rev= 0xd; + s_fw= sizeof(QT2025_phy_firmware) / sizeof(u16); + break; + + default: + ERR("PHY ID =0x%x, returning\n", (0xFF & (phy_id >> 8))); + return 1; + break; + } + switch(rev) + { + default: + ERR("bdx: failed unknown PHY ID %x\n", phy_id); + return 1; + break; + + case 0xD: + BDX_MDIO_WRITE(priv, 1,0xC300,0x0000); + BDX_MDIO_WRITE(priv, 1,0xC302,0x4); + BDX_MDIO_WRITE(priv, 1,0xC319,0x0038); + // BDX_MDIO_WRITE(priv, 1,0xC319,0x0088); //1G + BDX_MDIO_WRITE(priv, 1,0xC31A,0x0098); + BDX_MDIO_WRITE(priv, 3,0x0026,0x0E00); + // BDX_MDIO_WRITE(priv, 3,0x0027,0x08983); //10G + BDX_MDIO_WRITE(priv, 3,0x0027,0x0893); //10G + // BDX_MDIO_WRITE(priv, 3,0x0027,0x01092); //1G //3092 + BDX_MDIO_WRITE(priv, 3,0x0028,0xA528); + BDX_MDIO_WRITE(priv, 3,0x0029,0x03); + BDX_MDIO_WRITE(priv, 1,0xC30A,0x06E1); + BDX_MDIO_WRITE(priv, 1,0xC300,0x0002); + BDX_MDIO_WRITE(priv, 3,0xE854,0x00C0); + + /* Dump firmware starting at address 3.8000 */ + for (i = 0, j = 0x8000, a = 3; i < s_fw; i++, j++) + { + if(i == 0x4000) + { + a = 4; + j = 0x8000; + } + if (phy_fw[i] < 0x100) + { + BDX_MDIO_WRITE(priv, a, j, phy_fw[i]); + } + } + BDX_MDIO_WRITE(priv, 3, 0xE854, 0x0040); + for(i = 60; i; i--) + { + msleep(50); + j = bdx_mdio_read(priv, 3, port, 0xD7FD); + if(!(j== 0x10 || j== 0)) + { + break; + } + } + if(!i) + { + ERR("PHY init error\n"); + } + break; + } + fwVer01 = bdx_mdio_read(priv, 3, port, 0xD7F3); + fwVer2 = bdx_mdio_read(priv, 3, port, 0xD7F4); + fwVer3 = bdx_mdio_read(priv, 3, port, 0xD7F5); + module = bdx_mdio_read(priv, 3, port, 0xD70C); + + MSG("QT2025 FW version %d.%d.%d.%d module type 0x%x\n", + ((fwVer01 >> 4) & 0xf), + (fwVer01 & 0xf), + (fwVer2 & 0xff), + (fwVer3 & 0xff), + (u32)(module & 0xff)); + + priv->link_speed = QT2025_get_link_speed(priv); + bdx_speed_set(priv, priv->link_speed); + + return 0; + +} // QT2025_mdio_reset + +//------------------------------------------------------------------------------------------------- + +/* + * Module types: + * + 1 = 10GBASE-LRM + 2 = 10GBASE-SR + 3 = 10GBASE-LR + 4 = SFP+ passive copper direct attach cable + 5 = 1000BASE-SX + 6 = 1000BASE-LX + 7 = Invalid Module Type + 8 = 1000BASE-CX (1GE copper cable) + 9 = 1000BASE-T + 10 (0xA) = 10GBASE-ER + 11 (0xB) = SFP+ active copper direct attach cable + >11 reserved for future use +*/ +//------------------------------------------------------------------------------------------------- + +u32 QT2025_link_changed(struct bdx_priv *priv) +{ + u32 link = 0; + + priv->link_speed = QT2025_get_link_speed(priv); + link = READ_REG(priv,regMAC_LNK_STAT) & MAC_LINK_STAT; + if (link) + { + DBG("QT2025 link speed is %s\n", (priv->link_speed == SPEED_10000) ? "10G" : "1G"); + link = priv->link_speed; + } + else + { + if(priv->link_loop_cnt++ > LINK_LOOP_MAX) + { + DBG("QT2025 trying to recover link after %d tries\n", LINK_LOOP_MAX); + // MAC reset + bdx_speed_set(priv,0); + bdx_speed_set(priv,priv->link_speed); + priv->link_loop_cnt = 0; + } + DBG("QT2025 no link, setting 1/5 sec timer\n"); + WRITE_REG(priv, 0x5150,1000000); // 1/5 sec timeout + } + + return link; + +} // QT2025_link_changed() + +//------------------------------------------------------------------------------------------------- + +void QT2025_leds(struct bdx_priv *priv, enum PHY_LEDS_OP op) +{ + switch (op) + { + case PHY_LEDS_SAVE: + break; + + case PHY_LEDS_RESTORE: + break; + + case PHY_LEDS_ON: + WRITE_REG(priv, regBLNK_LED, 4); + break; + + case PHY_LEDS_OFF: + WRITE_REG(priv, regBLNK_LED, 0); + break; + + default: + DBG("QT2025_leds() unknown op 0x%x\n", op); + break; + + } + +} // QT2025_leds() + +//------------------------------------------------------------------------------------------------- + +__init enum PHY_TYPE QT2025_register(struct bdx_priv *priv) +{ + priv->isr_mask= IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | IR_TMR0 | IR_RX_DESC_0 | IR_TX_FREE_0; + priv->phy_ops.mdio_reset = QT2025_mdio_reset; + priv->phy_ops.link_changed = QT2025_link_changed; + priv->phy_ops.ledset = QT2025_leds; + priv->phy_ops.mdio_speed = MDIO_SPEED_6MHZ; + QT2025_register_settings(priv); + + return PHY_TYPE_QT2025; + +} // QT2025_init() + +//------------------------------------------------------------------------------------------------- + Index: sys/dev/tn40xx/QT2025_phy_FreeBSD.c =================================================================== --- /dev/null +++ sys/dev/tn40xx/QT2025_phy_FreeBSD.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include "tn40.h" + +void QT2025_register_settings(struct bdx_priv *priv); +int QT2025_setMedia (struct bdx_priv *priv, int ifm_media); +//------------------------------------------------------------------------------------------------- + +int QT2025_setMedia(struct bdx_priv *priv, int ifm_media) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + struct ifnet *ifp = tn40_priv->ifp; + + ERR("%s Does not support ifconfig media option\n", ifp->if_xname); + + return EPERM; + +} // QT2025_setMedia() + +//------------------------------------------------------------------------------------------------- + +__init void QT2025_register_settings(struct bdx_priv *priv) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + struct ifmedia *ifm = &tn40_priv->media; + + priv->autoneg = AUTONEG_ENABLE; + ifmedia_add(ifm, IFM_ETHER | IFM_10G_LR | IFM_FDX, 0, NULL); + ifmedia_add(ifm, IFM_ETHER | IFM_10G_SR | IFM_FDX, 0, NULL); + ifmedia_set(ifm, IFM_ETHER | IFM_10G_LR | IFM_FDX); + + priv->phy_ops.set_settings = QT2025_setMedia; + +} // QT2025_register_settings() + +//------------------------------------------------------------------------------------------------- + Index: sys/dev/tn40xx/README =================================================================== --- /dev/null +++ sys/dev/tn40xx/README @@ -0,0 +1,91 @@ +Tehuti Networks TN40XX Network Adapter driver for FreeBSD +========================================================= + +Release Notes +============= +Version 1.0, svn 3714, 2019/01/22 + - Initial release for FreeBSD 11.2 and 12.0 + +Version 1.1, svn 3737, 2019/02/26 + - Fix for TCP Retries + - Fix for short packet handling (SMB RX fail) + - Fix wrong NIC name reporting + - Latest PHY firmware and code files as of Linux 0.3.6.17.1 + - Remove some redundant error messages + +Supported FreeBSD versions: +--------------------------- + tn40xx_freebsd11_amd64-1.1.txz - FreeBSD/FreeNAS 11.2, 64b version + tn40xx_freebsd12_amd64-1.1.txz - FreeBSD 12.0, 64b version + +Supported TN40XX based products: +-------------------------------- + +VID /DID /SVID/SDID Interface Print Name +------------------------------------------------------------------ +1fc9/4020/1fc9/3015 CX4 "TN9030 10GbE CX4 Ethernet Adapter" +1fc9/4020/180c/2040 CX4 "IEI Mustang-200 10GbE Ethernet Adapter" +1fc9/4022/1fc9/3015 SFP+ APM QT2025 "TN9310 10GbE SFP+ Ethernet Adapter" +1fc9/4022/1186/4d00 SFP+ APM QT2025 "D-Link DXE-810S 10GbE SFP+ Ethernet Adapter" +1fc9/4022/1043/8709 SFP+ APM QT2025 "ASUS XG-C100F 10GbE SFP+ Ethernet Adapter" +1fc9/4022/1432/8103 SFP+ APM QT2025 "Edimax 10 Gigabit Ethernet SFP+ PCI Express Adapter" +1fc9/4024/1fc9/3015 10GBASE-T Pele MV88X3110 "TN9210 10GBase-T Ethernet Adapter" +1fc9/4025/1fc9/3015 NBASE-T Aquantia AQR105 "TN9510 10GBase-T/NBASE-T Ethernet Adapter" +1fc9/4025/1186/2900 10GBASE-T Aquantia AQ2104 "D-Link DXE-810T 10GBase-T Ethernet Adapter" +1fc9/4025/1432/8102 NBASE-T Aquantia AQR105 "Edimax 10 Gigabit Ethernet PCI Express Adapter" +1fc9/4026/1fc9/3015 SFP+ TI TLK10232 "TN9610 10GbE SFP+ Ethernet Adapter" +1fc9/4026/4c52/1000 SFP+ TI TLK10232 "LR-Link LREC6860AF 10 Gigabit Ethernet Adapter" +1fc9/4027/1fc9/3015 NBASE-T Pele MV88X3310 "TN9710P 10GBase-T/NBASE-T Ethernet Adapter" +1fc9/4027/1432/8104 NBASE-T Pele MV88X3310 "Edimax 10 Gigabit Ethernet PCI Express Adapter" +1fc9/4027/1154/0368 NBASE-T Pele MV88X3310 "Buffalo LGY-PCIE-MG Ethernet Adapter" +1fc9/4027/1546/4027 NBASE-T Pele MV88X3310 "IOI GE10-PCIE4XG202P 10Gbase-T/NBASE-T Ethernet Adapter" +1fc9/4027/4c52/1001 NBASE-T Pele MV88X3310 "LR-Link LREC6860BT 10 Gigabit Ethernet Adapter" +1fc9/4027/1baa/3310 NBASE-T Pele MV88X3310 "QNAP LAN-10G1T-THT 10Gbase-T/NBASE-T Ethernet Adapter" +1fc9/4527/1fc9/3015 5GBASE-T Pele MV88E2010 "TN9710Q 5GBase-T/NBASE-T Ethernet Adapter" + + +Installing the package +---------------------- + % sudo pkg add tn40xx_freebsd12_amd64-1.1.txz + % sudo reboot + + + If pkg add command fails with the following message: + % sudo pkg add tn40xx_freebsd12_amd64-1.1.txz + Signature for pkg not available + + It could mean pkg tool is not correctly setup on your system. In this case, run pkg with no arguments and while host have internet access: + % sudo pkg + The package management tool is not yet installed on your system. + Do you want to fetch and install it now [y/N]: + + Enter or answer "y" to complete pkg tool installation + +Verifying installed package +--------------------------- + % pkg info | grep tn40 + +Uninstalling the package +------------------------ + % sudo pkg delete tn40xx_freebsd12_amd64-1.1 + % sudo reboot + +Configuring adapter +------------------- + % sudo vi /etc/rc.conf + For DHCP: + ifconfig_tn400="DHCP" + For Static IP, ipv4: + ifconfig_tn400="inet 17.0.0.201 netmask 255.255.255.0" + For Static IP, ipv4 and MTU: + ifconfig_tn400="inet 17.0.0.201 netmask 255.255.255.0 mtu 9000" + For Static IP, ipv6: + ifconfig_tn400_ipv6="inet6 2017::201 prefixlen 64" + For Bonding, failover mode, tn400+tn401, DHCP: + ifconfig_tn400="up" + ifconfig_tn401="up" + cloned_interfaces="lagg0" + ifconfig_lagg0="laggproto failover laggport tn400 laggport tn401 DHCP" + % sudo reboot + + * If there is more than one adapter present, they will be named tn400, tn401, etc. Index: sys/dev/tn40xx/TLK10232_phy.h =================================================================== --- /dev/null +++ sys/dev/tn40xx/TLK10232_phy.h @@ -0,0 +1,266 @@ + +#ifndef _TLK10232_H +#define _TLK10232_H + +#define GLOBAL_CONTROL_1 0 // 0x1e +#define GLOBAL_RESET 0x8000 + +#define CHANNEL_CONTROL_1 0x1 // 0x1e +#define HS_SERDES_CONTROL_1 0x2 // 0x1e +#define HS_SERDES_CONTROL_2 0x3 // 0x1e +#define HS_SERDES_CONTROL_3 0x4 // 0x1e +#define HS_SERDES_CONTROL_4 0x5 // 0x1e +#define LS_SERDES_CONTROL_1 0x6 // 0x1e +#define LS_LANE_0 0x1 +#define LS_LANE_1 0x2 +#define LS_LANE_2 0x4 +#define LS_LANE_3 0x8 +#define LS_SERDES_CONTROL_2 0x7 // 0x1e +#define LS_SERDES_CONTROL_3 0x8 // 0x1e +#define HS_OVERLAY_CONTROL 0x9 // 0x1e +#define LS_OVERLAY_CONTROL 0xa // 0x1e +#define LOOPBACK_TP_CONTROL 0xb // 0x1e +#define LS_CONFIG_CONTROL 0xc // 0x1e +#define TI_RESERVED_STATUS_7 +#define CLK_CONTROL 0xd // 0x1e +#define RESET_CONTROL 0xe // 0x1e +#define CHANNEL_STATUS_1 0xf // 0x1e +#define HS_ERROR_COUNTER 0x10 // 0x1e +#define LS_LN0_ERROR_COUNTER 0x11 // 0x1e +#define LS_LN1_ERROR_COUNTER 0x12 // 0x1e +#define LS_LN2_ERROR_COUNTER 0x13 // 0x1e +#define LS_LN3_ERROR_COUNTER 0x14 // 0x1e +#define LN3_LS_STATUS_1 +#define LN2_LS_STATUS_1 +#define LN1_LS_STATUS_1 +#define LN0_LS_STATUS_1 +#define HS_STATUS_1 0x16 // 0x1e +#define DST_CONTROL_1 0x17 // 0x1e +#define DST_CONTROL_2 0x18 // 0x1e +#define DSR_CONTROL_1 0x19 // 0x1e +#define DSR_CONTROL_2 0x1a // 0x1e +#define DATA_SWITCH_STATUS 0x1b // 0x1e +#define LS_CH_CONTROL_1 0x1C // 0x1e +#define HS_CH_CONTROL_1 0x1d // 0x1e +#define EXT_ADDRESS_CONTROL 0x1e // 0x1e +#define EXT_ADDRESS_DATA 0x1f // 0x1e +#define TI_RESERVED_CONTROL_1 +#define TI_RESERVED_CONTROL_2 +#define TI_RESERVED_CONTROL_3 +#define VS_10G_LN_ALIGN_ACODE_P 0x8003 // 0x1e +#define VS_10G_LN_ALIGN_ACODE_N 0x8004 // 0x1e +#define TI_RESERVED_CONTROL_4 +#define TI_RESERVED_CONTROL_5 +#define TI_RESERVED_CONTROL_6 +#define TI_RESERVED_CONTROL_7 +#define TI_RESERVED_CONTROL_8 +#define TI_RESERVED_CONTROL_9 +#define TI_RESERVED_CONTROL_10 +#define TI_RESERVED_CONTROL_11 +#define TI_RESERVED_CONTROL_12 +#define TI_RESERVED_CONTROL_13 +#define TI_RESERVED_CONTROL_14 +#define TI_RESERVED_CONTROL_15 +#define TI_RESERVED_STATUS_1 +#define TI_RESERVED_STATUS_2 +#define TI_RESERVED_STATUS_3 +#define TI_RESERVED_STATUS_4 +#define TI_RESERVED_CONTROL_16 +#define TI_RESERVED_CONTROL_17 +#define TI_RESERVED_CONTROL_18 +#define TI_RESERVED_CONTROL_19 +#define TI_RESERVED_CONTROL_20 +#define TI_RESERVED_CONTROL_21 +#define TI_RESERVED_CONTROL_22 +#define AUTO_CLKOUT_CONTROL +#define TI_RESERVED_CONTROL_23 +#define TI_RESERVED_CONTROL_24 +#define TI_RESERVED_CONTROL_25 +#define TI_RESERVED_CONTROL_26 +#define MC_AUTO_CONTROL 0x8021 // 0x1e +#define DST_ON_CHAR_CONTROL 0x802a // 0x1e +#define DST_OFF_CHAR_CONTROL 0x802b // 0x1e +#define DST_STUFF_CHAR_CONTROL 0x802c // 0x1e +#define DSR_ON_CHAR_CONTROL 0x802d // 0x1e +#define DSR_OFF_CHAR_CONTROL 0x802e // 0x1e +#define DSR_STUFF_CHAR_CONTROL 0x802f // 0x1e +#define TI_RESERVED_STATUS_5 +#define TI_RESERVED_STATUS_6 +#define TI_RESERVED_STATUS_8 +#define TI_RESERVED_STATUS_9 +#define TI_RESERVED_STATUS_10 +#define LATENCY_MEASURE_CONTROL 0x8040 // 0x1e +#define LATENCY_COUNTER_2 0x8041 // 0x1e +#define LATENCY_COUNTER_1 0x8042 // 0x1e +#define TI_RESERVED_CONTROL_27 +#define TRIGGER_LOAD_CONTROL 0x8100 // 0x1e +#define TRIGGER_EN_CONTROL 0x8101 // 0x1e +#define TI_RESERVED_CONTROL_30 +#define PMA_CONTROL_1 0x0 // 0x1 +#define PMA_STATUS_1 0x1 // 0x1 +#define PMA_DEV_IDENTIFIER_1 0x2 // 0x1 +#define PMA_DEV_IDENTIFIER_2 0x3 // 0x1 +#define PMA_SPEED_ABILITY 0x4 // 0x1 +#define PMA_DEV_PACKAGE_1 0x5 // 0x1 +#define PMA_DEV_PACKAGE_2 0x6 // 0x1 +#define PMA_STATUS_2 0x8 // 0x1 +#define PMA_RX_SIGNAL_DET_STATUS 0xa // 0x1 +#define PMA_EXTENDED_ABILITY 0xb // 0x1 +#define LT_TRAIN_CONTROL 0x96 // 0x1 +#define LT_TRAIN_STATUS 0x97 // 0x1 +#define LT_LINK_PARTNER_CONTROL 0x98 // 0x1 +#define LT_LINK_PARTNER_STATUS 0x99 // 0x1 +#define LT_LOCAL_DEVICE_CONTROL 0x9a // 0x1 +#define LT_LOCAL_DEVICE_STATUS 0x9b // 0x1 +#define KX_STATUS 0xa1 // 0x1 +#define KR_FEC_ABILITY 0xaa // 0x1 +#define KR_FEC_CONTROL 0xab // 0x1 +#define KR_FEC_C_COUNT_1 0xac // 0x1 +#define KR_FEC_C_COUNT_2 0xad // 0x1 +#define KR_FEC_UC_COUNT_1 0xae // 0x1 +#define KR_FEC_UC_COUNT_2 0xaf // 0x1 +#define TI_RESERVED_CONTROL_34 +#define KR_VS_FIFO_CONTROL_1 0x8001 // 0x1 +#define KR_VS_TP_GEN_CONTROL 0x8002 // 0x1 +#define KR_VS_TP_VER_CONTROL 0x8003 // 0x1 +#define KR_VS_CTC_ERR_CODE_LN0 0x8005 // 0x1 +#define KR_VS_CTC_ERR_CODE_LN1 0x8006 // 0x1 +#define KR_VS_CTC_ERR_CODE_LN2 0x8007 // 0x1 +#define KR_VS_CTC_ERR_CODE_LN3 0x8008 // 0x1 +#define KR_VS_LN0_EOP_ERROR_COUNTER 0x8010 // 0x1 +#define KR_VS_LN1_EOP_ERROR_COUNTER 0x8011 // 0x1 +#define KR_VS_LN2_EOP_ERROR_COUNTER 0x8012 // 0x1 +#define KR_VS_LN3_EOP_ERROR_COUNTER 0x8013 // 0x1 +#define KR_VS_TX_CTC_DROP_COUNT 0x8014 // 0x1 +#define KR_VS_TX_CTC_INSERT_COUNT 0x8015 // 0x1 +#define KR_VS_RX_CTC_DROP_COUNT 0x8016 // 0x1 +#define KR_VS_RX_CTC_INSERT_COUNT 0x8017 // 0x1 +#define KR_VS_STATUS_1 0x8018 // 0x1 +#define KR_VS_TX_CRCJ_ERR_COUNT_1 0x8019 // 0x1 +#define KR_VS_TX_CRCJ_ERR_COUNT_2 0x801a // 0x1 +#define KR_VS_TX_LN0_HLM_ERR_COUNT 0x801b // 0x1 +#define KR_VS_TX_LN1_HLM_ERR_COUNT 0x801c // 0x1 +#define KR_VS_TX_LN2_HLM_ERR_COUNT 0x801d // 0x1 +#define KR_VS_TX_LN3_HLM_ERR_COUNT 0x801e // 0x1 +#define TI_RESERVED_STATUS_22 +#define TI_RESERVED_STATUS_23 +#define TI_RESERVED_STATUS_24 +#define TI_RESERVED_STATUS_25 +#define TI_RESERVED_STATUS_26 +#define TI_RESERVED_STATUS_27 +#define TI_RESERVED_CONTROL_35 +#define TI_RESERVED_CONTROL_36 +#define TI_RESERVED_CONTROL_37 +#define TI_RESERVED_CONTROL_38 +#define TI_RESERVED_CONTROL_39 +#define TI_RESERVED_CONTROL_40 +#define TI_RESERVED_CONTROL_41 +#define TI_RESERVED_CONTROL_42 +#define TI_RESERVED_CONTROL_43 +#define TI_RESERVED_CONTROL_44 +#define TI_RESERVED_CONTROL_45 +#define TI_RESERVED_CONTROL_46 +#define TI_RESERVED_CONTROL_47 +#define TI_RESERVED_CONTROL_48 +#define TI_RESERVED_CONTROL_49 +#define TI_RESERVED_CONTROL_50 +#define TI_RESERVED_CONTROL_51 +#define TI_RESERVED_CONTROL_52 +#define TI_RESERVED_STATUS_28 +#define TI_RESERVED_STATUS_29 +#define TI_RESERVED_STATUS_30 +#define TI_RESERVED_STATUS_31 +#define TI_RESERVED_STATUS_32 +#define TI_RESERVED_STATUS_33 +#define TI_RESERVED_STATUS_34 +#define TI_RESERVED_STATUS_35 +#define TI_RESERVED_STATUS_36 +#define TI_RESERVED_STATUS_37 +#define PCS_CONTROL 0 // 0x3 +#define PCS_STATUS_1 0x1 // 0x3 +#define PCS_STATUS_2 0x8 // 0x3 +#define KR_PCS_STATUS_1 0x20 // 0x3 +#define KR_PCS_STATUS_2 0x21 // 0x3 +#define PCS_TP_SEED_A0 0x22 // 0x3 +#define PCS_TP_SEED_A1 0x23 // 0x3 +#define PCS_TP_SEED_A2 0x24 // 0x3 +#define PCS_TP_SEED_A3 0x25 // 0x3 +#define PCS_TP_SEED_B0 0x26 // 0x3 +#define PCS_TP_SEED_B1 0x27 // 0x3 +#define PCS_TP_SEED_B2 0x28 // 0x3 +#define PCS_TP_SEED_B3 0x29 // 0x3 +#define PCS_TP_CONTROL 0x2a // 0x3 +#define PCS_TP_ERR_COUNT 0x2b // 0x3 +#define PCS_VS_CONTROL 0x8000 // 0x3 +#define PCS_VS_STATUS 0x8010 // 0x3 +#define AN_CONTROL 0 // 0x7 +#define AN_STATUS 0x1 // 0x7 +#define AN_DEV_PACKAGE 0x5 // 0x7 +#define AN_ADVERTISEMENT_1 0x10 // 0x7 +#define AN_ADVERTISEMENT_2 0x11 // 0x7 +#define AN_ADVERTISEMENT_3 0x12 // 0x7 +#define AN_LP_ADVERTISEMENT_1 0x13 // 0x7 +#define AN_LP_ADVERTISEMENT_2 0x14 // 0x7 +#define AN_LP_ADVERTISEMENT_3 0x15 // 0x7 +#define AN_XNP_TRANSMIT_1 0x16 // 0x7 +#define AN_XNP_TRANSMIT_2 0x17 // 0x7 +#define AN_XNP_TRANSMIT_3 0x18 // 0x7 +#define AN_LP_XNP_ABILITY_1 0x19 // 0x7 +#define AN_LP_XNP_ABILITY_2 0x1a // 0x7 +#define AN_LP_XNP_ABILITY_3 0x1b // 0x7 +#define AN_BP_STATUS 0x30 // 0x7 +#define AN_VS_CONTROL + +#define REGISTER_00 +#define REGISTER_01 +#define REGISTER_02 +#define REGISTER_04 +#define REGISTER_05 +#define REGISTER_06 +#define REGISTER_0C +#define REGISTER_0D +#define REGISTER_0E + +#define GLOBAL_CONTROL_01 +#define CHANNEL_CONTROL_01 +#define RESERVED_1 +#define TX_SWING_CONTROL +#define RESERVED_2 +#define TP_CONTROL +#define LANE_CONFIG_CONTROL +#define LAS_BER_TIMER_CONTROL_1 +#define CHANNEL_STATUS_01 +#define CRPAT_ERROR_COUNTER +#define LN0_ERROR_COUNTER +#define LN1_ERROR_COUNTER +#define LN2_ERROR_COUNTER +#define LN3_ERROR_COUNTER +#define LN0_TRANSCEIVER_STATUS +#define LN1_TRANSCEIVER_STATUS +#define LN2_TRANSCEIVER_STATUS +#define LN3_TRANSCEIVER_STATUS +#define CHANNEL_STATUS_02 + +#define CLK_REGISTER_0 +#define CLK_REGISTER_1 +#define CLK_REGISTER_2 +#define CLK_REGISTER_3 +#define CLK_REGISTER_4 +#define CLK_REGISTER_5 +#define CLK_REGISTER_6 +#define CLK_REGISTER_7 +#define CLK_REGISTER_8 +#define CLK_REGISTER_9 +#define CLK_REGISTER_10 +#define CLK_REGISTER_11 +#define CLK_REGISTER_12 +#define CLK_REGISTER_13 +#define CLK_REGISTER_14 +#define CLK_REGISTER_15 +#define CLK_REGISTER_16 +#define CLK_REGISTER_17 +#define CLK_REGISTER_18 +#define CLK_REGISTER_19 +#define CLK_REGISTER_20 + +#endif // _TLK10232_H Index: sys/dev/tn40xx/TLK10232_phy.c =================================================================== --- /dev/null +++ sys/dev/tn40xx/TLK10232_phy.c @@ -0,0 +1,595 @@ +#include "tn40.h" +#include "TLK10232_phy.h" +int bdx_speed_set(struct bdx_priv *priv, u32 speed); +void sff_reset(struct bdx_priv *priv); +int sff_read_str(struct bdx_priv *priv, unsigned char sfp_adr, unsigned char addr,int len, char *buf); +int sff_write_str(struct bdx_priv *priv, unsigned char sfp_adr, unsigned char addr,int len, char *buf); +int i2c_write_byte(struct bdx_priv *priv,int send_start, int send_stop, unsigned char byte); +unsigned char i2c_read_byte(struct bdx_priv *priv,int nack, int send_stop); +int i2c_read_bit(struct bdx_priv *priv); +int i2c_write_bit(struct bdx_priv *priv,int bit); +int i2c_start_cond(struct bdx_priv *priv, int I2C_started); +int i2c_stop_cond(struct bdx_priv *priv); +int i2c_SCL_stretch(struct bdx_priv *priv); +int read_sfp_id(struct bdx_priv *priv); +void set_GPIO(struct bdx_priv *priv); +void clear_GPIO_N(struct bdx_priv *priv, u32 n); +u32 read_GPIO_N(struct bdx_priv *priv, u32 n); +int TLK10232_phy_config(struct bdx_priv *priv); +int TLK10232_mdio_reset(struct bdx_priv *priv, int port, unsigned short phy); +u32 TLK10232_get_link_speed(struct bdx_priv *priv); +u32 TLK10232_link_changed(struct bdx_priv *priv); +void TLK10232_leds(struct bdx_priv *priv, enum PHY_LEDS_OP op); + +#define LINK_LOOP_MAX (80) + +void TLK10232_register_settings(struct bdx_priv *priv); + +enum _SFP_MOD_TYPE{ +SFP_ABS=0, +SFP_NA, +SFP_1G, +SFP_10G, +SFP_10G_DA +}; + +#define TEST_SFP_OM + +#ifdef TEST_SFP_OM + +#define SCL_GPIO 4 +#define SDA_GPIO 5 +#define TX_DISABLE_GPIO 1 +#define MOD_ABS_GPIO 2 + +#define I2C_delay(priv) udelay(8) +#define RWDELAY(priv) udelay(1) + +#define WRITE_GPOI_REG(priv,reg,val) do{\ + WRITE_REG(priv, 0x51E0,0x30010000|((reg&0xf)));\ +READ_REG(priv, 0x5030); WRITE_REG(priv, 0x51F0, ( val) );\ +} while(0) + +#define READ_GPOI_REG(priv,reg,val) do{\ + WRITE_REG(priv, 0x51E0,0x30000000|((reg&0xf)));\ + READ_REG(priv, 0x5030); val=READ_REG(priv, 0x51F0);\ +} while(0) + +#define LOG_I2C DBG + +//------------------------------------------------------------------------------------------------- + +u32 read_GPIO_N(struct bdx_priv *priv, u32 n){ + u32 ret,rw,i,msk=(1<<(n&0x7)); + // get current GPIO state + READ_GPOI_REG(priv,6,rw); + // set to input GPIO N + WRITE_GPOI_REG(priv,6,rw|msk); + RWDELAY(priv); + // read + READ_GPOI_REG(priv,4,i); + ret= (i&msk)?1:0; +LOG_I2C("read_GPIO_N(%x) 4= %x 6=(%x | %x) ret=%x) \n",n,i,rw,msk,ret); + + return ret; + +} // read_GPIO_N() + +//------------------------------------------------------------------------------------------------- + +void clear_GPIO_N(struct bdx_priv *priv, u32 n){ + u32 rw,msk= ~(1<<(n&0x7)); + // get current GPIO state + READ_GPOI_REG(priv,6,rw); + // set to output GPIO N + WRITE_GPOI_REG(priv,6,(rw & msk)); + RWDELAY(priv); + LOG_I2C("clear_GPIO_N(%x) 6=(%x & %x)\n",n,rw , msk); + +} // clear_GPIO_N() + +//------------------------------------------------------------------------------------------------- + +// Set SCL as input and return current level of line, 0 or 1 +#define read_SCL(p) read_GPIO_N((p),SCL_GPIO) +// Set SDA as input and return current level of line, 0 or 1 +#define read_SDA(p) read_GPIO_N((p),SDA_GPIO) +// Actively drive SCL signal low +#define clear_SCL(p) clear_GPIO_N((p),SCL_GPIO) +// Actively drive SDA signal low +#define clear_SDA(p) clear_GPIO_N((p),SDA_GPIO) + +//return 0-ok 1-CLK==0 + +//------------------------------------------------------------------------------------------------- + +int i2c_SCL_stretch(struct bdx_priv *priv){ +int i; + for(i=50;i;i--){ + if(read_SCL(priv)) break; + udelay(1); + } + + return (i)?0:1; + +} // i2c_SCL_stretch() + +//------------------------------------------------------------------------------------------------- + +int i2c_start_cond(struct bdx_priv *priv, int I2C_started) { +int ret=0; + LOG_I2C("TLK10232 i2c_start_cond start=====================\n"); + I2C_delay(priv); + I2C_delay(priv); + if(I2C_started){ + read_SDA(priv); + I2C_delay(priv); + ret=i2c_SCL_stretch(priv); + if(ret) { + LOG_I2C("TLK10232 i2c_start_cond failed SCL==0\n"); + } + I2C_delay(priv); + } + + if (read_SDA(priv) == 0) { + LOG_I2C("TLK10232 i2c_start_cond failed SDA==0\n"); + ret=1; + } + + // SCL is high, set SDA from 1 to 0. + clear_SDA(priv); + I2C_delay(priv); + clear_SCL(priv); + LOG_I2C("TLK10232 i2c_start_cond "STRING_FMT"======================\n",ret?"Failed ":"OK"); + + return ret; + +} // i2c_start_cond() + +//------------------------------------------------------------------------------------------------- + +int i2c_stop_cond(struct bdx_priv *priv){ + int ret=0; + LOG_I2C("TLK10232 i2c_stop_cond start===================\n"); + clear_SCL(priv); + // set SDA to 0 + clear_SDA(priv); + I2C_delay(priv); + // Clock stretching + ret=i2c_SCL_stretch(priv); + if(ret){ + LOG_I2C("TLK10232 i2c_stop_cond failed SCL==0\n"); + ret=1; + } + + // Stop bit setup time, minimum 4us + I2C_delay(priv); + // SCL is high, set SDA from 0 to 1 + if (read_SDA(priv) == 0) { + LOG_I2C("TLK10232 i2c_stop_cond failed SDA==0\n"); + ret=1; + } + I2C_delay(priv); + LOG_I2C("TLK10232 i2c_stop_cond end===================\n"); + + return ret; + +} // i2c_stop_cond() + +//------------------------------------------------------------------------------------------------- + +// Write a bit to I2C bus +int i2c_write_bit(struct bdx_priv *priv,int bit) { +int ret=0; + LOG_I2C("TLK10232 i2c_write_bit ==%x start \n", bit); + if (bit) { + read_SDA(priv); + } else { + clear_SDA(priv); + } + i2c_SCL_stretch(priv); + I2C_delay(priv); + // SCL is high, now data is valid + // If SDA is high, check that nobody else is driving SDA + if (bit) if( read_SDA(priv) == 0) { + //arbitration_lost(); + ret=1; + } + I2C_delay(priv); + clear_SCL(priv); + LOG_I2C("TLK10232 i2c_write_bit "STRING_FMT"\n",ret?"failed":"OK"); + + return ret; + +} // i2c_write_bit() + +//------------------------------------------------------------------------------------------------- + +// Read a bit from I2C bus +int i2c_read_bit(struct bdx_priv *priv) { + int bit; + LOG_I2C("TLK10232 i2c_read_bit start \n"); + // Let the slave drive data + read_SDA(priv); + i2c_SCL_stretch(priv); + I2C_delay(priv); + // SCL is high, now data is valid + bit = read_SDA(priv); + I2C_delay(priv); + clear_SCL(priv); + LOG_I2C("TLK10232 i2c_read_bit %x \n",bit); + + return bit?1:0; + +} // i2c_read_bit() + +//------------------------------------------------------------------------------------------------- + +// Write a byte to I2C bus. Return 0 if ack by the slave. +int i2c_write_byte(struct bdx_priv *priv,int send_start, + int send_stop, + unsigned char byte) { + unsigned bit; + int nack; +LOG_I2C("i2c_write_byte 0x%x start\n",byte); + if (send_start) { + i2c_start_cond(priv,(send_start==2)?1:0); + } + for (bit = 0; bit < 8; bit++) { + i2c_write_bit(priv,(byte & 0x80) != 0); + byte <<= 1; + } + nack = i2c_read_bit(priv); + if (send_stop) { + i2c_stop_cond(priv); + } +LOG_I2C("i2c_write_byte end nack=%x\n",nack); + + return nack; + +} // i2c_write_byte() + +//------------------------------------------------------------------------------------------------- + +// Read a byte from I2C bus +unsigned char i2c_read_byte(struct bdx_priv *priv,int nack, int send_stop) { + unsigned char byte = 0; + unsigned bit; +LOG_I2C("i2c_read_byte start nack=%x\n",nack); + for (bit = 0; bit < 8; bit++) { + byte = (byte << 1); + byte |= i2c_read_bit(priv); + } + i2c_write_bit(priv, nack); + if (send_stop) { + i2c_stop_cond(priv); + } +LOG_I2C("i2c_read_byte stop byte=%x\n",byte); + + return byte; + +} // i2c_read_byte() + +//------------------------------------------------------------------------------------------------- + +void sff_reset(struct bdx_priv *priv){ + int i; + + for (i=0;i<9;i++){ + i2c_read_bit(priv); + } + i2c_start_cond(priv,0); + I2C_delay(priv); + read_SDA(priv); + +} // sff_reset() + +//------------------------------------------------------------------------------------------------- + +/* +Return len or 0 on error +*/ +int sff_read_str(struct bdx_priv *priv, unsigned char sfp_adr, unsigned char addr,int len, char *buf){ + unsigned char data; + int i=0,err=0; + + if(buf==0) return 0; + if(len==0) return 0; + if(len&0xff00) return 0; + +DBG("TLK10232 sff_read_str sfp_adr=%x addr=%x start \n",sfp_adr,addr); + + do{ + err=i2c_write_byte(priv,/*send_start*/1,/*send_stop*/ 0,sfp_adr&0xfe); + if(err){ err=1; break;} + + err=i2c_write_byte(priv,/*send_start*/0,/*send_stop*/ 1,addr&0xff); + if(err){ err=2; break;} + + err=i2c_write_byte(priv,/*send_start*/1,/*send_stop*/ 0,sfp_adr|1); + if(err){ err=3; break;} + + len--; + for(i=0;i8) return 0; // not more then 7 bytes by SFF spec + if(len&0xff00) return 0; + +DBG("TLK10232 sff_write_str sfp_adr=%x addr=%x start \n",sfp_adr,addr); + + do{ + err=i2c_write_byte(priv,/*send_start*/1,/*send_stop*/ 0,sfp_adr&0xfe); + if(err){ err=1; break;} + + err=i2c_write_byte(priv,/*send_start*/0,/*send_stop*/ 0,addr&0xff); + if(err){ err=2; break;} + + len--; + for(i=0;iphy_mdio_port; + + u32 sfp_mod_type=priv->sfp_mod_type; + if(sfp_mod_type==SFP_ABS) return 0; + + + switch(sfp_mod_type){ + default: + case SFP_10G: + BDX_MDIO_WRITE(priv,0x1e, CHANNEL_CONTROL_1, 0x0B00); + BDX_MDIO_WRITE(priv,0x1e, HS_SERDES_CONTROL_2, 0xA848); //reg 1e.3 + BDX_MDIO_WRITE(priv,0x1e, HS_SERDES_CONTROL_3, 0x9518); //reg 1e.4 + BDX_MDIO_WRITE(priv,0x1e, HS_SERDES_CONTROL_4, 0x3300); //reg 1e.5 + break; + + case SFP_10G_DA: + BDX_MDIO_WRITE(priv,0x1e, CHANNEL_CONTROL_1, 0x0B00); + BDX_MDIO_WRITE(priv,0x1e, HS_SERDES_CONTROL_2, 0xF848); //reg 1e.3 + BDX_MDIO_WRITE(priv,0x1e, HS_SERDES_CONTROL_3, 0x1500); //reg 1e.4 + BDX_MDIO_WRITE(priv,0x1e, HS_SERDES_CONTROL_4, 0x2000); //reg 1e.5 + break; + + case SFP_1G: + BDX_MDIO_WRITE(priv,0x1e, CHANNEL_CONTROL_1, 0x0300); + BDX_MDIO_WRITE(priv,0x1e, HS_SERDES_CONTROL_2, 0xA848); //reg 1e.3 + BDX_MDIO_WRITE(priv,0x1e, HS_SERDES_CONTROL_3, 0x9518); //reg 1e.4 + BDX_MDIO_WRITE(priv,0x1e, HS_SERDES_CONTROL_4, 0x3300); //reg 1e.5 + + break; + } + + + // Datapath reset + do + { + udelay(25); + BDX_MDIO_WRITE(priv,0x1e, RESET_CONTROL, 0x8); + BDX_MDIO_WRITE(priv,0x1e, RESET_CONTROL, 0x0); + udelay(25); + regVal = bdx_mdio_read(priv, 0x1e, port, CHANNEL_STATUS_1); + regVal = bdx_mdio_read(priv, 0x1e, port, CHANNEL_STATUS_1); + DBG("TLK10232_phy_config() CHANNEL_STATUS_1 = 0x%x Fail:%x loops:%d (Fail mask 0x0100)\n", regVal, (regVal & 0x0100), j); + } while ((regVal & 0x0100) && (j++ < 100)); + + return 0; +} + +//------------------------------------------------------------------------------------------------- + + int TLK10232_mdio_reset(struct bdx_priv *priv, int port, unsigned short phy) +{ + int regVal; + priv->sfp_mod_type=0; //read_sfp_id(priv); + + // Device reset + BDX_MDIO_WRITE(priv,0x1e, GLOBAL_CONTROL_1, 0x8610); + regVal = bdx_mdio_read(priv, 0x1e, port, GLOBAL_CONTROL_1); + DBG("TLK10232_mdio_reset() GLOBAL_CONTROL_1 = 0x%x\n", regVal); + msleep(100); + + BDX_MDIO_WRITE(priv,0x7, AN_CONTROL, 0x2000); + BDX_MDIO_WRITE(priv,0x1, LT_TRAIN_CONTROL, 0x0); + + priv->link_speed = TLK10232_get_link_speed(priv); + bdx_speed_set(priv, priv->link_speed); + + return 0; + +} // TLK10232_mdio_reset + +//------------------------------------------------------------------------------------------------- + +u32 TLK10232_get_link_speed(struct bdx_priv *priv) +{ + u32 sfp_mod_type,speed; + + sfp_mod_type=read_sfp_id(priv); + // ERR("TLK10232_get_link_speed sfp_mod_type=%u\n",sfp_mod_type); + if(priv->sfp_mod_type!=sfp_mod_type){ + priv->sfp_mod_type=sfp_mod_type; + TLK10232_phy_config(priv); + } + switch (sfp_mod_type){ + case SFP_10G: + case SFP_10G_DA: + speed=SPEED_10000;break; + case SFP_1G: + //speed=SPEED_1000; break; + default: + speed=0; break; + } + + return speed; + +} // TLK10232_get_link_speed() + +//------------------------------------------------------------------------------------------------- + +u32 TLK10232_link_changed(struct bdx_priv *priv) +{ + u32 link = 0; + + link = READ_REG(priv,regMAC_LNK_STAT) & MAC_LINK_STAT; + if (link) + { + priv->link_speed = TLK10232_get_link_speed(priv); + link = priv->link_speed; + DBG("TLK10232 link speed is "STRING_FMT"\n", (priv->link_speed == SPEED_10000) ? "10G" : "1G"); + WRITE_REG(priv, 0x5150,0); // stop timer + } + else + { + if(priv->link_loop_cnt++ > LINK_LOOP_MAX) + { + DBG("TLK10232 trying to recover link after %d tries\n", LINK_LOOP_MAX); + priv->link_speed = TLK10232_get_link_speed(priv); + // MAC reset + bdx_speed_set(priv,0); + bdx_speed_set(priv,priv->link_speed); + priv->link_loop_cnt = 0; + priv->sfp_mod_type=SFP_ABS; + } + //DBG("TLK10232 no link, setting 1/5 sec timer\n"); + WRITE_REG(priv, 0x5150,1000000); // 1/5 sec timeout + } + + return link; + +} // TLK10232_link_changed() + +//------------------------------------------------------------------------------------------------- + +void TLK10232_leds(struct bdx_priv *priv, enum PHY_LEDS_OP op) +{ + switch (op) + { + case PHY_LEDS_SAVE: + break; + + case PHY_LEDS_RESTORE: + break; + + case PHY_LEDS_ON: + WRITE_REG(priv, regBLNK_LED, 4); + break; + + case PHY_LEDS_OFF: + WRITE_REG(priv, regBLNK_LED, 0); + break; + + default: + DBG("TLK10232_leds() unknown op 0x%x\n", op); + break; + + } + +} // TLK10232_leds() + +//------------------------------------------------------------------------------------------------- + +__init enum PHY_TYPE TLK10232_register(struct bdx_priv *priv) +{ + priv->isr_mask= IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | IR_TMR0 | IR_RX_DESC_0 | IR_TX_FREE_0; + priv->phy_ops.mdio_reset = TLK10232_mdio_reset; + priv->phy_ops.link_changed = TLK10232_link_changed; + priv->phy_ops.ledset = TLK10232_leds; + priv->phy_ops.mdio_speed = MDIO_SPEED_1MHZ; + TLK10232_register_settings(priv); + + return PHY_TYPE_TLK10232; + +} // TLK10232_init() + +//------------------------------------------------------------------------------------------------- + Index: sys/dev/tn40xx/TLK10232_phy_FreeBSD.c =================================================================== --- /dev/null +++ sys/dev/tn40xx/TLK10232_phy_FreeBSD.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include "tn40.h" + +void TLK10232_register_settings(struct bdx_priv *priv); +int TLK10232_setMedia (struct bdx_priv *priv, int ifm_media); +//------------------------------------------------------------------------------------------------- + +int TLK10232_setMedia(struct bdx_priv *priv, int ifm_media) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + struct ifnet *ifp = tn40_priv->ifp; + + ERR("%s Does not support ifconfig media option\n", ifp->if_xname); + + return EPERM; + +} // TLK10232_setMedia() + +//------------------------------------------------------------------------------------------------- + +__init void TLK10232_register_settings(struct bdx_priv *priv) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + struct ifmedia *ifm = &tn40_priv->media; + + priv->autoneg = AUTONEG_ENABLE; + ifmedia_add(ifm, IFM_ETHER | IFM_10G_LR | IFM_FDX, 0, NULL); + ifmedia_add(ifm, IFM_ETHER | IFM_10G_SR | IFM_FDX, 0, NULL); + ifmedia_set(ifm, IFM_ETHER | IFM_10G_LR | IFM_FDX); + + priv->phy_ops.set_settings = TLK10232_setMedia; + +} // TLK10232_register_settings() + +//------------------------------------------------------------------------------------------------- + Index: sys/dev/tn40xx/tn40.h =================================================================== --- /dev/null +++ sys/dev/tn40xx/tn40.h @@ -0,0 +1,147 @@ + +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __TN40_H__ +#define __TN40_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tn40_hw.h" +// #include "tn40_ioctl.h" + +#define CONTAINING_RECORD(addr, type, field) ((type *)((vm_offset_t)(addr) - (vm_offset_t)(&((type *)0)->field))) + +#define TN40_STATE_NONE (0x00000000) +#define TN40_STATE_ALLOC_MSI (0x00000001) +#define TN40_STATE_ATTACH (0x00000002) +#define TN40_BR_SIZE (4096) +typedef struct +{ + uint16_t vid; + uint16_t pid; + uint16_t subvendor; + uint16_t subdev; + char *name; +} tn40_devid_t; +#ifdef TN40_COUNTERS +typedef struct +{ + u64 tx_pkts; + u64 tx_deferred_pkts; + u64 tx_locked_pkts; +} tn40_counters_t; + +#endif +typedef struct +{ + device_t dev; + struct mtx mtx; + struct callout callout; + struct resource *pci_mem; + struct resource *irq; + struct ifmedia media; + bus_space_tag_t bus_tag; + bus_space_handle_t bus_handle; + void *intr_handle; + eventhandler_tag vlan_attach; + eventhandler_tag vlan_detach; + struct ifnet *ifp; + struct buf_ring *br; + struct mtx tx_lock; + struct task txq_task; + struct taskqueue *tq; + struct bdx_priv bdx_priv; + uint32_t state; +#ifdef TN40_COUNTERS + tn40_counters_t counters; +#endif +}tn40_priv_t; + +u32 tn40_read_reg (struct bdx_priv *priv, u32 reg); +void tn40_write_reg (struct bdx_priv *priv, u32 reg, u32 value); +int tn40_alloc_dma (struct bdx_priv *priv, u32 size, tn40_dma_t *dma); +int tn40_dma_tag_create (struct bdx_priv *priv, u32 size, u32 seg_size, int nsegments, bus_dma_tag_t *dma_tag); +void tn40_free_dma (tn40_dma_t *dma); +void tn40_checksum_results (struct mbuf *m, uint32_t pkt_type); +// +//uint16_t pci_get_vendor (device_t dev); +//uint16_t pci_get_device (device_t dev); +//uint16_t pci_get_subvendor (device_t dev); +//uint16_t pci_get_subdevice (device_t dev); +#if __FreeBSD_version < 1102000 +#define ifr_data_get_ptr(ifr) ifr->ifr_data +#endif + +#endif Index: sys/dev/tn40xx/tn40.c =================================================================== --- /dev/null +++ sys/dev/tn40xx/tn40.c @@ -0,0 +1,933 @@ +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "tn40.h" + +static tn40_devid_t g_tn40DevIds[] = +{ + {TEHUTI_VID,0x4010,TEHUTI_VID, 0x4010, "TN4010 Clean SROM" }, + {TEHUTI_VID,0x4020,TEHUTI_VID, 0x3015, "TN9030 10GbE CX4 Ethernet Adapter" }, +#ifdef PHY_QT2025 + {TEHUTI_VID,0x4022,TEHUTI_VID, 0x3015, "TN9310 10GbE SFP+ Ethernet Adapter" }, + {TEHUTI_VID,0x4022,DLINK_VID, 0x4d00, "D-Link DXE-810S 10GbE SFP+ Ethernet Adapter" }, + {TEHUTI_VID,0x4022,ASUS_VID, 0x8709, "ASUS XG-C100F 10GbE SFP+ Ethernet Adapter" }, + {TEHUTI_VID,0x4022,EDIMAX_VID, 0x8103, "Edimax 10 Gigabit Ethernet SFP+ PCI Express Adapter" }, +#endif +#ifdef PHY_MV88X3120 + {TEHUTI_VID,0x4024,TEHUTI_VID, 0x3015, "TN9210 10GBase-T Ethernet Adapter" }, +#endif +#ifdef PHY_MV88X3310 + {TEHUTI_VID,0x4027,TEHUTI_VID, 0x3015, "TN9710P 10GBase-T/NBASE-T Ethernet Adapter" }, + {TEHUTI_VID,0x4027,EDIMAX_VID, 0x8104, "Edimax 10 Gigabit Ethernet PCI Express Adapter" }, + {TEHUTI_VID,0x4027,BUFFALO_VID,0x0368, "Buffalo LGY-PCIE-MG Ethernet Adapter"}, + {TEHUTI_VID,0x4027,0x1546, 0x4027, "IOI9710P 10Gbase-T/NBASE-T Ethernet Adapter"}, +#endif +#ifdef PHY_MV88E2010 + {TEHUTI_VID,0x4527,TEHUTI_VID, 0x3015, "TN9710Q 5GBase-T/NBASE-T Ethernet Adapter" }, +#endif +#ifdef PHY_TLK10232 + {TEHUTI_VID,0x4026,TEHUTI_VID, 0x3015, "TN9610 10GbE SFP+ Ethernet Adapter" }, +#endif +#ifdef PHY_AQR105 + {TEHUTI_VID,0x4025,DLINK_VID, 0x2900, "D-Link DXE-810T 10GBase-T Ethernet Adapter" }, + {TEHUTI_VID,0x4025,TEHUTI_VID, 0x3015, "TN9510 10GBase-T/NBASE-T Ethernet Adapter" }, + {TEHUTI_VID,0x4025,EDIMAX_VID, 0x8102, "Edimax 10 Gigabit Ethernet PCI Express Adapter" }, +#endif + {0} +}; + +/********************************************************************* + * Function prototypes + *********************************************************************/ +static int tn40_probe(device_t); +static int tn40_attach(device_t); +static int tn40_detach(device_t); +static int tn40_shutdown(device_t); +static int tn40_if_ioctl(struct ifnet *, u_long, caddr_t); +static void tn40_transmit_deferred(void *context, int pending); + + +/********************************************************************* + * FreeBSD Device Interface Entry Points + *********************************************************************/ + +static device_method_t tn40_methods[] = +{ + /* Device interface */ + DEVMETHOD(device_probe, tn40_probe), + DEVMETHOD(device_attach, tn40_attach), + DEVMETHOD(device_detach, tn40_detach), + DEVMETHOD(device_shutdown, tn40_shutdown), + DEVMETHOD_END +}; +//------------------------------------------------------------------------------------------------- + +static driver_t tn40_driver = +{ + "tn40", + tn40_methods, + sizeof(tn40_priv_t), +}; +//------------------------------------------------------------------------------------------------- + +devclass_t tn40_devclass; +DRIVER_MODULE(tn40, pci, tn40_driver, tn40_devclass, 0, 0); +MODULE_DEPEND(tn40, pci, 1, 1, 1); +MODULE_DEPEND(tn40, ether, 1, 1, 1); + +//------------------------------------------------------------------------------------------------- + +static void tn40_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) +{ + + if (error == 0) + { + *(bus_addr_t *) arg = segs->ds_addr; + } + +} // tn40_dmamap_cb() + +//------------------------------------------------------------------------------------------------- + +int tn40_dma_tag_create(struct bdx_priv *priv, u32 size, u32 seg_size, int nsegments, bus_dma_tag_t *dma_tag) +{ + int err; + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + + ENTER; + err = bus_dma_tag_create(bus_get_dma_tag(tn40_priv->dev), /* parent */ + 1, 0, /* alignment, bounds */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + size, /* maxsize */ + nsegments, /* nsegments */ + seg_size, /* maxsegsize */ + BUS_DMA_ALLOCNOW, /* flags */ + NULL, /* lockfunc */ + NULL, /* lockfuncarg */ + dma_tag); + RET(err); + +} // tn40_dma_tag_create() + +//------------------------------------------------------------------------------------------------- + +int tn40_alloc_dma(struct bdx_priv *priv, u32 size, tn40_dma_t *dma) +{ + int err; + + ENTER; + do + { + err = tn40_dma_tag_create(priv, size, size, 1, &dma->dma_tag); + + if (err != 0) + { + ERR("bus_dma_tag_create FAILED !\n"); + break; + } + err = bus_dmamem_alloc(dma->dma_tag, &dma->tn40_dmamap.va, BUS_DMA_NOWAIT, &dma->tn40_dmamap.dma_map); + if (err != 0) + { + ERR("tn40_alloc() bus_dmamem_alloc FAILED !\n"); + bus_dma_tag_destroy(dma->dma_tag); + break; + } + err = bus_dmamap_load(dma->dma_tag, dma->tn40_dmamap.dma_map, dma->tn40_dmamap.va, size, tn40_dmamap_cb, (void *)&dma->tn40_dmamap.pa, BUS_DMA_ZERO | BUS_DMA_NOWAIT); + if (err != 0) + { + ERR("bus_dmamap_load FAILED !\n"); + bus_dmamem_free(dma->dma_tag, dma->tn40_dmamap.va, dma->tn40_dmamap.dma_map); + bus_dma_tag_destroy(dma->dma_tag); + break; + } + + } while (0); + + RET(err); + +} // tn40_alloc_dma() + +//------------------------------------------------------------------------------------------------- + +void tn40_free_dma(tn40_dma_t *dma) +{ + ENTER; + DBG("dma %p\n", dma); + if (dma && dma->tn40_dmamap.va != NULL) + { + DBG("dma_tag %p dma_map %p\n", dma->dma_tag, dma->tn40_dmamap.dma_map); + bus_dmamap_sync(dma->dma_tag, dma->tn40_dmamap.dma_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(dma->dma_tag, dma->tn40_dmamap.dma_map); + bus_dmamem_free(dma->dma_tag, dma->tn40_dmamap.va, dma->tn40_dmamap.dma_map); + bus_dma_tag_destroy(dma->dma_tag); + dma->tn40_dmamap.va = NULL; + } + EXIT; +} // tn40_free_dma() + +//------------------------------------------------------------------------------------------------- + +u32 tn40_read_reg(struct bdx_priv *priv, u32 reg) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + return bus_space_read_4(tn40_priv->bus_tag, tn40_priv->bus_handle, reg); + +} // tn40_read_reg() + + +//------------------------------------------------------------------------------------------------- + +void tn40_write_reg(struct bdx_priv *priv, u32 reg, u32 value) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + + bus_space_write_4(tn40_priv->bus_tag, tn40_priv->bus_handle, reg, value); + +} // tn40_write_reg() + +//------------------------------------------------------------------------------------------------- + +void tn40_checksum_results(struct mbuf *mBuf, uint32_t pkt_type) +{ + + ENTER; + switch (pkt_type) + { + case PKT_TYPE_UDP: + case PKT_TYPE_TCP: + mBuf->m_pkthdr.csum_flags = CSUM_L3_CALC | CSUM_L3_VALID | CSUM_L4_CALC | CSUM_L4_VALID; + mBuf->m_pkthdr.csum_data = htons(0xffff); + DBG("%s checksum OK\n",(pkt_type == PKT_TYPE_UDP) ? "UDP" : "TCP"); + break; + + case PKT_TYPE_IP: + mBuf->m_pkthdr.csum_flags = CSUM_L3_CALC | CSUM_L3_VALID; + DBG("IP non TCP/UDP checksum OK\n"); + break; + + default: + mBuf->m_pkthdr.csum_flags = 0; + DBG("unknown packet type %d !\n",(int)pkt_type); + break; + } + EXIT; + +} // tn40_checksum_results + +//------------------------------------------------------------------------------------------------- + +static int tn40_my_device(uint16_t vendor,uint16_t device, uint16_t sub_vendor,uint16_t sub_device) +{ + uint32_t j; + int bFound = -1; + + ENTER; + DBG("v 0x%x d 0x%x\n", vendor, device); + for(j = 0; g_tn40DevIds[j].vid; j++) + { + DBG("%d. v 0x%x d 0x%x\n", j, g_tn40DevIds[j].vid, g_tn40DevIds[j].pid); + if((g_tn40DevIds[j].vid == vendor) && + (g_tn40DevIds[j].pid == device) && + (g_tn40DevIds[j].subvendor == sub_vendor) && + (g_tn40DevIds[j].subdev == sub_device)) + { + bFound = j; + DBG("found %d\n", bFound); + break; + } + } + RET(bFound); + +} // tn40_my_device + +//------------------------------------------------------------------------------------------------- + +static int tn40_probe(device_t dev) +{ + int tn40Dev; + u16 pci_vendor_id = pci_get_vendor(dev); + u16 pci_device_id = pci_get_device(dev); + u16 pci_subvendor_id = pci_get_subvendor(dev); + u16 pci_subdevice_id = pci_get_subdevice(dev); + int rVal = ENXIO; + + ENTER; + if ((tn40Dev = tn40_my_device(pci_vendor_id, pci_device_id, pci_subvendor_id, pci_subdevice_id)) >= 0) + { + MSG("Detected 0x%x 0x%x 0x%x 0x%x %s\n", pci_vendor_id,pci_device_id,pci_subvendor_id, pci_subdevice_id, g_tn40DevIds[tn40Dev].name); + device_set_desc_copy(dev, g_tn40DevIds[tn40Dev].name); + rVal = BUS_PROBE_DEFAULT; + } + else + { + + DBG("PCI id 0x%x 0x%x 0x%x 0x%x\n", pci_vendor_id,pci_device_id,pci_subvendor_id, pci_subdevice_id); + + } + + RET(rVal); + +} // tn40_probe() + +static void tn40_vlan(tn40_priv_t *tn40_priv, u16 vtag, int enable) +{ + struct bdx_priv *bdx_priv = &tn40_priv->bdx_priv; + + mtx_lock(&tn40_priv->mtx); + bdx_vlan_rx_vid(bdx_priv, vtag , enable); + mtx_unlock(&tn40_priv->mtx); + +} // tn40_vlan() +//------------------------------------------------------------------------------------------------- + +static void tn40_add_vlan(void *arg, struct ifnet *ifp, u16 vtag) +{ + tn40_priv_t *tn40_priv = ifp->if_softc; + + tn40_vlan(tn40_priv, vtag, 1); + +} // tn40_add_vlan() + +//------------------------------------------------------------------------------------------------- + +static void tn40_remove_vlan(void *arg, struct ifnet *ifp, u16 vtag) +{ + tn40_priv_t *tn40_priv = ifp->if_softc; + + tn40_vlan(tn40_priv, vtag, 0); + +} // tn40_add_vlan() + +//------------------------------------------------------------------------------------------------- + +static void tn40_if_init(void *xsc) +{ + tn40_priv_t *tn40_priv = xsc; + struct ifnet *ifp = tn40_priv->ifp; + + ENTER; + + mtx_lock(&tn40_priv->mtx); + + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + ifp->if_hwassist = 0; + if (ifp->if_capenable & IFCAP_TSO4) + { + ifp->if_hwassist |= CSUM_TSO; + } + if (ifp->if_capenable & IFCAP_TXCSUM) + { + ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); + } + mtx_unlock(&tn40_priv->mtx); + +} // tn40_if_init() + +//------------------------------------------------------------------------------------------------- + +static int tn40_transmit_locked(struct ifnet *ifp) +{ + struct mbuf *mBuf; + tn40_priv_t *tn40_priv = ifp->if_softc; + int err = 0; + + while (1) + { + if (ifp->if_drv_flags & IFF_DRV_OACTIVE) + { + break;; + } + if ((mBuf = drbr_peek(ifp, tn40_priv->br)) == NULL) + { + break; + } + COUNT_INC(tn40_priv->counters, tx_locked_pkts); + err = bdx_tx_transmit(&tn40_priv->bdx_priv, mBuf); + if (err != 0) + { + drbr_putback(ifp, tn40_priv->br, mBuf); + DBG2("drbr_putback --> m %p len %d\n", mBuf, mBuf->m_pkthdr.len); + break; + } + drbr_advance(ifp, tn40_priv->br); + ETHER_BPF_MTAP(ifp, mBuf); + } + + return err; + +} // tn40_transmit_locked() + +//------------------------------------------------------------------------------------------------- +/* +static int tn40_transmit_lockedX(struct ifnet *ifp) +{ + struct mbuf *mBuf; + int err = 0; + + tn40_priv_t *tn40_priv = ifp->if_softc; + + while ((mBuf = drbr_peek(ifp, tn40_priv->br)) != NULL) + { + //DBG2("m %p\n", mBuf); + err = bdx_tx_transmit(&tn40_priv->bdx_priv, mBuf); + if (err != 0) + { + drbr_putback(ifp, tn40_priv->br, mBuf); + break; + } + drbr_advance(ifp, tn40_priv->br); + ETHER_BPF_MTAP(ifp, mBuf); + } + + return err; + +} // tn40_transmit_locked() +*/ +//------------------------------------------------------------------------------------------------- + +static void tn40_transmit_deferred(void *context, int pending) +{ + struct ifnet *ifp = (struct ifnet *)context; + tn40_priv_t *tn40_priv = ifp->if_softc; + + //DBG2("\n"); + mtx_lock(&tn40_priv->tx_lock); + COUNT_INC(tn40_priv->counters, tx_deferred_pkts); + if (!drbr_empty(ifp, tn40_priv->br)) + { + tn40_transmit_locked(ifp); + } + mtx_unlock(&tn40_priv->tx_lock); + +} // tn40_transmit_deferred() + +//------------------------------------------------------------------------------------------------- + +static int tn40_transmit(struct ifnet *ifp, struct mbuf *m) +{ + int err; + tn40_priv_t *tn40_priv = ifp->if_softc; + + ENTER; + + DBG("m %p\n", m); + COUNT_INC(tn40_priv->counters, tx_pkts); + err = drbr_enqueue(ifp, tn40_priv->br, m); + if (!err) + { + if (mtx_trylock(&tn40_priv->tx_lock)) + { + err = tn40_transmit_locked(ifp); + mtx_unlock(&tn40_priv->tx_lock); + } + else + { + taskqueue_enqueue(tn40_priv->tq, &tn40_priv->txq_task); + DBG("deferred --> m %p len %d\n", m, m->m_pkthdr.len); + } + } + + RET(err); + +} // tn40_transmit() + +//------------------------------------------------------------------------------------------------- +/* +static void tn40_start_locked(struct ifnet *ifp) +{ + tn40_priv_t *tn40_priv = ifp->if_softc; + struct mbuf *mBuf = NULL; + int err = 0; + + + while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + { + IFQ_DRV_DEQUEUE(&ifp->if_snd, mBuf); + if (mBuf == NULL) + { + break; + } + err = bdx_tx_transmit(&tn40_priv->bdx_priv, mBuf); + if (err != 0) + { + IFQ_DRV_PREPEND(&ifp->if_snd, mBuf); + break; + } + + ETHER_BPF_MTAP(ifp, mBuf); + } + +} // tn40_start_locked() + +//------------------------------------------------------------------------------------------------- + +static void tn40_start(struct ifnet *ifp) +{ + tn40_priv_t *tn40_priv = ifp->if_softc; + + mtx_lock(&tn40_priv->tx_lock); + tn40_start_locked(ifp); + mtx_unlock(&tn40_priv->tx_lock); + +} // tn40_start() +*/ +//------------------------------------------------------------------------------------------------- + +static void tn40_if_qflush(struct ifnet *ifp) +{ + + ENTER; + + if_qflush(ifp); + + EXIT; + +} // tn40_if_qflush() + +//------------------------------------------------------------------------------------------------- + +static void tn40_media_status(struct ifnet * ifp, struct ifmediareq * ifmr) +{ + tn40_priv_t *tn40_priv = ifp->if_softc; + struct bdx_priv *priv = &tn40_priv->bdx_priv; + + mtx_lock(&tn40_priv->mtx); + + ifmr->ifm_status = IFM_AVALID; + ifmr->ifm_active = IFM_ETHER | IFM_FDX; + + if (priv->link_speed) + { + ifmr->ifm_status |= IFM_ACTIVE; + switch (priv->link_speed) + { + case SPEED_10000: + ifmr->ifm_active |= IFM_10G_T; + break; + + case SPEED_5000: + ifmr->ifm_active |= IFM_5000_T; + break; + + case SPEED_2500: + ifmr->ifm_active |= IFM_2500_T; + break; + + case SPEED_1000X: + case SPEED_1000: + ifmr->ifm_active |= IFM_1000_T; + break; + + case SPEED_100X: + case SPEED_100: + ifmr->ifm_active |= IFM_100_T; + break; + + } + } + + mtx_unlock(&tn40_priv->mtx); + +} // tn40_media_status() + +//------------------------------------------------------------------------------------------------- +// ifconfig for media options + +static int tn40_media_change(struct ifnet * ifp) +{ + tn40_priv_t *tn40_priv = ifp->if_softc; + struct bdx_priv *bdx_priv = &tn40_priv->bdx_priv; + struct ifmedia *ifm = &tn40_priv->media; + + DBG("type 0x%x subtype 0x%x\n", IFM_TYPE(ifm->ifm_media), IFM_SUBTYPE(ifm->ifm_media)); + return bdx_priv->phy_ops.set_settings(bdx_priv, IFM_SUBTYPE(ifm->ifm_media)); + +} // tn40_media_change() + +//------------------------------------------------------------------------------------------------- + +static void tn40_isr(void *arg) +{ + u32 isr; + tn40_priv_t *tn40_priv = (tn40_priv_t *)arg; + struct bdx_priv *bdx_priv = &tn40_priv->bdx_priv; + +/*** + struct thread *td; + uintptr_t stackStart, stackEnd; + unsigned int stackSize; + int stackPages; + + td = curthread; + stackStart = (uintptr_t) td->td_kstack; + stackEnd = (uintptr_t) td->td_kstack + td->td_kstack_pages * PAGE_SIZE; + stackPages = td->td_kstack_pages; + stackSize = stackEnd - stackStart; + +***/ + + + + isr = bdx_isr(bdx_priv); + + if (isr & IR_RX_DESC_0) + { + bdx_rx_receive(bdx_priv); + } + if (isr & IR_TX_FREE_0) + { + mtx_lock(&tn40_priv->tx_lock); + bdx_tx_cleanup(bdx_priv); + if (!drbr_empty(tn40_priv->ifp, tn40_priv->br)) + { + tn40_transmit_locked(tn40_priv->ifp); + } + mtx_unlock(&tn40_priv->tx_lock); + } + if (isr & (IR_LNKCHG0|IR_LNKCHG1|IR_TMR0)) + { + bdx_link_changed(bdx_priv); + } + + bdx_enable_interrupts(bdx_priv); + +} // tn40_isr() + +//------------------------------------------------------------------------------------------------- + +static int tn40_attach(device_t dev) +{ + int count; + struct ifnet *ifp; + tn40_priv_t *tn40_priv = device_get_softc(dev); + struct bdx_priv *priv = &tn40_priv->bdx_priv; + int rid = PCIR_BAR(0); + int err = ENXIO; + + ENTER; + do + { + bzero(tn40_priv, sizeof(tn40_priv_t)); + tn40_priv->dev = dev; + priv->deviceId = pci_get_device(dev); + priv->subsystem_device = pci_get_subdevice(dev); + priv->subsystem_vendor = pci_get_subvendor(dev); + mtx_init(&tn40_priv->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); + callout_init_mtx(&tn40_priv->callout, &tn40_priv->mtx, 0); + mtx_init(&tn40_priv->tx_lock, device_get_nameunit(dev), "TN40xx TX", MTX_DEF); + pci_enable_busmaster(dev); + tn40_priv->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (tn40_priv->pci_mem == NULL) + { + ERR("Failed to allocate PCI memory !\n"); + break; + } + tn40_priv->bus_tag = rman_get_bustag(tn40_priv->pci_mem); + tn40_priv->bus_handle = rman_get_bushandle(tn40_priv->pci_mem); + count = pci_msi_count(dev); + if (pci_alloc_msi(dev, &count) != 0) + { + ERR("Failed to allocate MSI !\n"); + break; + } + tn40_priv->state |= TN40_STATE_ALLOC_MSI; + rid = 1; + tn40_priv->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); + if (tn40_priv->irq == NULL) + { + ERR("Failed to allocate IRQ !\n"); + break; + } + err = tn40_dma_tag_create(priv, TN40_MAX_TSO_PACKET_SIZE, MJUM16BYTES, MAX_SEGMENTS, &priv->tx_dma_tag); + if (err != 0) + { + ERR("tn40_dma_tag_create tx FAILED !\n"); + break; + } + err = BUS_SETUP_INTR(device_get_parent(dev), dev, tn40_priv->irq, INTR_TYPE_NET | INTR_MPSAFE, + NULL, tn40_isr, tn40_priv, &tn40_priv->intr_handle); + if (err != 0) + { + ERR("bus_setup_intr FAILED !\n"); + break; + } + ifmedia_init(&tn40_priv->media, IFM_IMASK, tn40_media_change, tn40_media_status); + ifp = tn40_priv->ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) + { + ERR("if_alloc FAILED !\n"); + break; + } + tn40_priv->br = buf_ring_alloc(TN40_BR_SIZE, M_DEVBUF, M_WAITOK, &tn40_priv->tx_lock); + if (tn40_priv->br == NULL) + { + ERR("buf_ring_alloc FAILED !\n"); + break; + } + TASK_INIT(&tn40_priv->txq_task, 0, tn40_transmit_deferred, ifp); + tn40_priv->tq = taskqueue_create_fast("tn40_que", M_NOWAIT, taskqueue_thread_enqueue, &tn40_priv->tq); + taskqueue_start_threads(&tn40_priv->tq, 1, PI_NET, "%s que", device_get_nameunit(tn40_priv->dev)); + ifp->if_softc = tn40_priv; + ifp->if_baudrate = 1000000000; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_mtu = ETHERMTU; + ifp->if_init = tn40_if_init; + ifp->if_ioctl = tn40_if_ioctl; + ifp->if_transmit = tn40_transmit; +// ifp->if_start = tn40_start; + ifp->if_qflush = tn40_if_qflush; + ifp->if_capabilities= IFCAP_HWCSUM | IFCAP_TSO4 | IFCAP_VLAN_HWCSUM | IFCAP_JUMBO_MTU | + IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU /*| IFCAP_TOE4*/ | + IFCAP_VLAN_HWFILTER | IFCAP_LINKSTATE | IFCAP_HWSTATS; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_capenable = ifp->if_capabilities; + if (bdx_probe(priv) != 0) + { + ERR("bdx_probe FAILED !\n"); + break; + } + tn40_priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, tn40_add_vlan, tn40_priv, EVENTHANDLER_PRI_FIRST); + tn40_priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, tn40_remove_vlan, tn40_priv, EVENTHANDLER_PRI_FIRST); + ether_ifattach(ifp, priv->mac_address); + if (bdx_open(priv) != 0) + { + ERR("bdx_probe FAILED !\n"); + break; + } + err = 0; + + tn40_priv->state |= TN40_STATE_ATTACH; + } while (0); + + if (err != 0) + { + tn40_detach(dev); + } + + RET(err); + +} // tn40_attach() + +//------------------------------------------------------------------------------------------------- + +static int tn40_detach(device_t dev) +{ + tn40_priv_t *tn40_priv = device_get_softc(dev); + struct bdx_priv *priv = &tn40_priv->bdx_priv; + int rid = 1; + + ENTER; + if (tn40_priv->ifp && (tn40_priv->ifp->if_vlantrunk != NULL)) + { + MSG("Vlan in use, can't detach\n"); + return (EBUSY); + } + if (tn40_priv->state & TN40_STATE_ATTACH) + { + mtx_lock(&tn40_priv->mtx); + callout_stop(&tn40_priv->callout); + mtx_unlock(&tn40_priv->mtx); + callout_drain(&tn40_priv->callout); + } + if (tn40_priv->br != NULL) + { + buf_ring_free(tn40_priv->br, M_DEVBUF); + } + if (tn40_priv->vlan_attach != NULL) + { + EVENTHANDLER_DEREGISTER(vlan_config, tn40_priv->vlan_attach); + } + if (tn40_priv->vlan_detach != NULL) + { + EVENTHANDLER_DEREGISTER(vlan_unconfig, tn40_priv->vlan_detach); + } + if (tn40_priv->ifp) + { + ether_ifdetach(tn40_priv->ifp); + if_free(tn40_priv->ifp); + } + bdx_close(priv); + if (tn40_priv->tq) + { + taskqueue_drain(tn40_priv->tq, &tn40_priv->txq_task); + taskqueue_free(tn40_priv->tq); + } + if (tn40_priv->intr_handle) + { + BUS_TEARDOWN_INTR(device_get_parent(dev), dev, tn40_priv->irq, tn40_priv->intr_handle); + } + if (tn40_priv->irq) + { + bus_release_resource(dev, SYS_RES_IRQ, rid, tn40_priv->irq); + } + if (tn40_priv->state & TN40_STATE_ALLOC_MSI) + { + pci_release_msi(dev); + tn40_priv->state &= ~TN40_STATE_ALLOC_MSI; + } + if (tn40_priv->pci_mem) + { + rid = PCIR_BAR(0); + bus_release_resource(dev, SYS_RES_MEMORY, rid, tn40_priv->pci_mem); + } + if (tn40_priv->state & TN40_STATE_ATTACH) + { + mtx_destroy(&tn40_priv->tx_lock); + mtx_destroy(&tn40_priv->mtx); + } + tn40_priv->state &= ~TN40_STATE_ATTACH; + + RET(0); + +} // tn40_detach() + +///------------------------------------------------------------------------------------------------- + +static int tn40_shutdown(device_t dev) +{ + tn40_priv_t *tn40_priv = device_get_softc(dev); + struct bdx_priv *priv = &tn40_priv->bdx_priv; + + ENTER; + mtx_lock(&tn40_priv->mtx); + callout_stop(&tn40_priv->callout); + mtx_unlock(&tn40_priv->mtx); + + bdx_remove(priv); + + RET(0); + +} // tn40_shutdown() + +//------------------------------------------------------------------------------------------------- + +static int tn40_if_ioctl(struct ifnet * ifp, u_long command, caddr_t data) +{ + tn40_priv_t *tn40_priv = ifp->if_softc; + struct bdx_priv *priv = &tn40_priv->bdx_priv; + struct ifreq *ifr = (struct ifreq *)data; + int err = 0; + int flags = 0; + + ENTER; + + switch (command) { + case SIOCSIFMTU: + DBG("SIOCSIFMTU %d\n", ifr->ifr_mtu); + mtx_lock(&tn40_priv->mtx); + if (bdx_change_mtu(priv, ifr->ifr_mtu) == 0) + { + ifp->if_mtu = ifr->ifr_mtu; + } + else + { + err = EINVAL; + } + mtx_unlock(&tn40_priv->mtx); + break; + + case SIOCSIFFLAGS: + DBG("SIOCSIFFLAGS 0x%x\n", ifp->if_flags); + mtx_lock(&tn40_priv->mtx); + if (ifp->if_flags & IFF_PROMISC) + { + flags |= IFF_PROMISC; + } + if (ifp->if_flags & IFF_ALLMULTI) + { + flags |= IFF_ALLMULTI; + } + if (ifp->if_flags & IFF_BROADCAST) + { + flags |= IFF_BROADCAST; + } + if (memcmp(if_getlladdr(tn40_priv->ifp), priv->mac_address, ETHER_ADDR_LEN)) + { + DBG("%s MAC change\n", tn40_priv->ifp->if_xname); + bdx_set_mac(priv, if_getlladdr(tn40_priv->ifp)); + } + bdx_setbroadcast(priv, flags); + mtx_unlock(&tn40_priv->mtx); + break; + + case SIOCADDMULTI: + DBG("SIOCADDMULTI 0x%x\n", ifp->if_flags); + mtx_lock(&tn40_priv->mtx); + bdx_setmulti(priv); + mtx_unlock(&tn40_priv->mtx); + break; + + case SIOCDELMULTI: + DBG("SIOCDELMULTI not implemented\n"); + break; + + case SIOCSIFMEDIA: + case SIOCGIFMEDIA: + case SIOCGIFXMEDIA: + DBG("%s\n", (command == SIOCSIFMEDIA) ? "SIOCSIFMEDIA" : + (command == SIOCGIFMEDIA) ? "SIOCGIFMEDIA" : "SIOCGIFXMEDIA"); + err = ifmedia_ioctl(ifp, ifr, &tn40_priv->media, command); + break; + + case SIOCSIFCAP: + { + int mask = ifr->ifr_reqcap ^ ifp->if_capenable; + DBG("SIOCSIFCAP 0x%x\n", mask); + break; + } + case SIOCGPRIVATE_0: +// err = priv_check(curthread, PRIV_DRIVER); +// if (err != 0) +// break; + err = bdx_ioctl_priv(priv, ifr); + break; + + case SIOCGIFMAC: + { + DBG("SIOCGIFMAC\n"); + break; + } + + case SIOCSIFMAC: + { + DBG("SIOCSIFMAC\n"); + break; + } + + default: + err = ether_ioctl(ifp, command, data); + DBG("Unknown command %lu (0x%X) return %d\n", command & 0xFF, (int)command, err); + break; + } + + RET(err); + +} // tn40_if_ioctl() + + + Index: sys/dev/tn40xx/tn40_fw.h =================================================================== --- /dev/null +++ sys/dev/tn40xx/tn40_fw.h @@ -0,0 +1,10737 @@ +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* Loading Firmware */ + +#ifndef _TN40XX_FW_H +#define _TN40XX_FW_H + +static u32 s_firmLoad[] __initdata = { +0xf0002, +0x40718000, +0x2d, +0xc0000000, +0xf0002, +0x40718000, +0x2d, +0xc0000000, +0xf0002, +0x718001, +0x2d, +0xc0800000, +0xf0002, +0x718002, +0x2d, +0xc1000000, +0xf0002, +0x718003, +0x2d, +0xc1800000, +0xf0002, +0x718004, +0x2d, +0xc2000000, +0xf0002, +0x718005, +0x2d, +0xc2800000, +0xf0002, +0x718006, +0x2d, +0xc3000000, +0xf0002, +0x718007, +0x2d, +0xc3800000, +0xf0002, +0x718008, +0x2d, +0xc4000000, +0xf0002, +0x718009, +0x2d, +0xc4800000, +0xf0002, +0x71800a, +0x2d, +0xc5000000, +0xf0002, +0x71800b, +0x2d, +0xc5800000, +0xf0002, +0x71800c, +0x2d, +0xc6000000, +0xf0002, +0x71800d, +0x2d, +0xc6800000, +0xf0002, +0x71800e, +0x2d, +0xc7000000, +0xf0002, +0x71800f, +0x2d, +0xc7800000, +0xf0002, +0x718010, +0x2d, +0xc8000000, +0xf0002, +0x718011, +0x2d, +0xc8800000, +0xf0002, +0x718012, +0x2d, +0xc9000000, +0xf0002, +0x718013, +0x2d, +0xc9800000, +0xf0002, +0x718014, +0x2d, +0xca000000, +0xf0002, +0x718015, +0x2d, +0xca800000, +0xf0002, +0x718016, +0x2d, +0xcb000000, +0xf0002, +0x718017, +0x2d, +0xcb800000, +0xf0002, +0x718018, +0x2d, +0xcc000000, +0xf0002, +0x718019, +0x2d, +0xcc800000, +0xf0002, +0x71801a, +0x2d, +0xcd000000, +0xf0002, +0x71801b, +0x2d, +0xcd800000, +0xf0002, +0x71801c, +0x2d, +0xce000000, +0xf0002, +0x71801d, +0x2d, +0xce800000, +0xf0002, +0x71801e, +0x2d, +0xcf000000, +0xf0002, +0x71801f, +0x2d, +0xcf800000, +0xf0002, +0x718020, +0x2d, +0xd0000000, +0xf0002, +0x718021, +0x2d, +0xd0800000, +0xf0002, +0x718022, +0x2d, +0xd1000000, +0xf0002, +0x718023, +0x2d, +0xd1800000, +0xf0002, +0x718024, +0x2d, +0xd2000000, +0xf0002, +0x718025, +0x2d, +0xd2800000, +0xf0002, +0x718026, +0x2d, +0xd3000000, +0xf0002, +0x718027, +0x2d, +0xd3800000, +0xf0002, +0x718028, +0x2d, +0xd4000000, +0xf0002, +0x718029, +0x2d, +0xd4800000, +0xf0002, +0x71802a, +0x2d, +0xd5000000, +0xf0002, +0x71802b, +0x2d, +0xd5800000, +0xf0002, +0x71802c, +0x2d, +0xd6000000, +0xf0002, +0x71802d, +0x2d, +0xd6800000, +0xf0002, +0x71802e, +0x2d, +0xd7000000, +0xf0002, +0x71802f, +0x2d, +0xd7800000, +0xf0002, +0x718030, +0x2d, +0xd8000000, +0xf0002, +0x718031, +0x2d, +0xd8800000, +0xf0002, +0x718032, +0x2d, +0xd9000000, +0xf0002, +0x718033, +0x2d, +0xd9800000, +0xf0002, +0x718034, +0x2d, +0xda000000, +0xf0002, +0x718035, +0x2d, +0xda800000, +0xf0002, +0x718036, +0x2d, +0xdb000000, +0xf0002, +0x718037, +0x2d, +0xdb800000, +0xf0002, +0x718038, +0x7b, +0xdd608000, +0xf0002, +0x718039, +0x2d, +0xdd000000, +0xf0002, +0x71803a, +0x2d, +0xdb800000, +0xf0002, +0x71803b, +0x2d, +0xdd000000, +0xf0002, +0x71803c, +0x2d, +0xdd000000, +0xf0002, +0x71803d, +0, +0, +0xf0002, +0x71803e, +0, +0, +0xf0002, +0x71803f, +0, +0, +0xf0002, +0x718040, +0, +0, +0xf0002, +0x718041, +0, +0, +0xf0002, +0x718042, +0, +0, +0xf0002, +0x718043, +0, +0, +0xf0002, +0x718044, +0, +0, +0xf0002, +0x718045, +0, +0, +0xf0002, +0x718046, +0, +0, +0xf0002, +0x718047, +0, +0, +0xf0002, +0x718048, +0, +0, +0xf0002, +0x718049, +0, +0, +0xf0002, +0x71804a, +0, +0, +0xf0002, +0x71804b, +0, +0, +0xf0002, +0x71804c, +0, +0, +0xf0002, +0x71804d, +0, +0, +0xf0002, +0x71804e, +0, +0, +0xf0002, +0x71804f, +0, +0, +0xf0002, +0x718050, +0, +0, +0xf0002, +0x718051, +0, +0, +0xf0002, +0x718052, +0, +0, +0xf0002, +0x718053, +0, +0, +0xf0002, +0x718054, +0, +0, +0xf0002, +0x718055, +0, +0, +0xf0002, +0x718056, +0, +0, +0xf0002, +0x718057, +0, +0, +0xf0002, +0x718058, +0, +0, +0xf0002, +0x718059, +0, +0, +0xf0002, +0x71805a, +0, +0, +0xf0002, +0x71805b, +0, +0, +0xf0002, +0x71805c, +0, +0, +0xf0002, +0x71805d, +0, +0, +0xf0002, +0x71805e, +0, +0, +0xf0002, +0x71805f, +0, +0, +0xf0002, +0x718060, +0, +0, +0xf0002, +0x718061, +0, +0, +0xf0002, +0x718062, +0, +0, +0xf0002, +0x718063, +0, +0, +0xf0002, +0x718064, +0x2d, +0xdb000000, +0xf0002, +0x718065, +0x3f, +0xdd000104, +0xf0002, +0x718066, +0x3f, +0xdd180001, +0xf0002, +0x718067, +0x69, +0xdd003d7a, +0xf0002, +0x718068, +0x3f, +0xdd000804, +0xf0002, +0x718069, +0x69, +0xdd003d7a, +0xf0002, +0x71806a, +0x3f, +0xdd003004, +0xf0002, +0x71806b, +0x3f, +0xdd180001, +0xf0002, +0x71806c, +0x69, +0xdd003d7a, +0xf0002, +0x71806d, +0x3f, +0xdd000004, +0xf0002, +0x71806e, +0x69, +0xdd003d7a, +0xf0002, +0x71806f, +0x3f, +0xdd003d04, +0xf0002, +0x718070, +0x3f, +0xdd180001, +0xf0002, +0x718071, +0x69, +0xdd003d7a, +0xf0002, +0x718072, +0x3f, +0xdd000704, +0xf0002, +0x718073, +0x69, +0xdd003d7a, +0xf0002, +0x718074, +0x3f, +0xdd002884, +0xf0002, +0x718075, +0x3f, +0xdd180001, +0xf0002, +0x718076, +0x69, +0xdd003d7a, +0xf0002, +0x718077, +0x3f, +0xdd003704, +0xf0002, +0x718078, +0x69, +0xdd003d7a, +0xf0002, +0x718079, +0x3f, +0xdd002904, +0xf0002, +0x71807a, +0x3f, +0xdd180001, +0xf0002, +0x71807b, +0x69, +0xdd003d7a, +0xf0002, +0x71807c, +0x3f, +0xdd04aa04, +0xf0002, +0x71807d, +0x69, +0xdd003d7a, +0xf0002, +0x71807e, +0x3f, +0xdd002804, +0xf0002, +0x71807f, +0x3f, +0xdd180001, +0xf0002, +0x718080, +0x69, +0xdd003d7a, +0xf0002, +0x718081, +0x3f, +0xdd003104, +0xf0002, +0x718082, +0x69, +0xdd003d7a, +0xf0002, +0x718083, +0x3f, +0xdd002b84, +0xf0002, +0x718084, +0x3f, +0xdd180001, +0xf0002, +0x718085, +0x69, +0xdd003d7a, +0xf0002, +0x718086, +0x3f, +0xdd01e404, +0xf0002, +0x718087, +0x69, +0xdd003d7a, +0xf0002, +0x718088, +0x3f, +0xd7800084, +0xf0002, +0x718089, +0x3f, +0xd7980001, +0xf0002, +0x71808a, +0x59, +0xd78037ef, +0xf0002, +0x71808b, +0x3d, +0xf780006f, +0xf0002, +0x71808c, +0x3d, +0xf780006f, +0xf0002, +0x71808d, +0x3d, +0xf780006f, +0xf0002, +0x71808e, +0x2d, +0xd7d6027f, +0xf0002, +0x71808f, +0x18, +0x17ff0081, +0xf0002, +0x718090, +0x3d, +0xf780006f, +0xf0002, +0x718091, +0x3d, +0xf780006f, +0xf0002, +0x718092, +0x2d, +0xd7d800b8, +0xf0002, +0x718093, +0x18, +0x17eb0081, +0xf0002, +0x718094, +0x3f, +0xdd002904, +0xf0002, +0x718095, +0x3f, +0xdd180001, +0xf0002, +0x718096, +0x69, +0xdd003d7a, +0xf0002, +0x718097, +0x3f, +0xdd04aa84, +0xf0002, +0x718098, +0x69, +0xdd003d7a, +0xf0002, +0x718099, +0x3f, +0xdd002b04, +0xf0002, +0x71809a, +0x3f, +0xdd180001, +0xf0002, +0x71809b, +0x69, +0xdd003d7a, +0xf0002, +0x71809c, +0x3f, +0xdd000004, +0xf0002, +0x71809d, +0x69, +0xdd003d7a, +0xf0002, +0x71809e, +0x3f, +0xdd002984, +0xf0002, +0x71809f, +0x3f, +0xdd180001, +0xf0002, +0x7180a0, +0x69, +0xdd003d7a, +0xf0002, +0x7180a1, +0x3f, +0xdd000004, +0xf0002, +0x7180a2, +0x69, +0xdd003d7a, +0xf0002, +0x7180a3, +0x3f, +0xdd002a04, +0xf0002, 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=================================================================== --- /dev/null +++ sys/dev/tn40xx/tn40_hw.h @@ -0,0 +1,956 @@ +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _TN40_HW_H_ +#define _TN40_HW_H_ + +#include "tn40.h" +#include "tn40_ioctl.h" + +#define TN40_DRV_NAME "tn40xx" +#define TN40_DRV_VERSION "1.2" +#define TN40_DRV_DESC "Tehuti FreeBSD Network Driver" + +# define HTONS(x) (((x >> 8) & 0x00FF) | ((x << 8) & 0xFF00)) + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; +typedef bus_addr_t dma_addr_t; +#define __iomem +#define __init +#define __exit +#define __initdata +#define ETHER_TYPE_IP HTONS(0x800) +#define VLAN_HLEN (4) +#define VLAN_ETH_HLEN (ETHER_HDR_LEN + VLAN_HLEN) +#define TN40_MAX_PACKET_SIZE (1 << 14) +#define TN40_MAX_TSO_PACKET_SIZE (1 << 16) +#define TN40_MIN_PACKET_SIZE (60) +#define SHORT_PKT_LEN (64) +#define udelay(usec) DELAY(usec) +#define mdelay(x) DELAY(x*1000) +#undef msleep +#define msleep(x) DELAY(1000*(x)) +#define BYTES2PAGES(bytes) (((bytes) - 1) / PAGE_SIZE + 1) +#define ETHER_MIN_MTU (68) +#define unlikely(x) x +#define likely(x) x +/* + * Trace log + */ +#ifdef _TRACE_LOG_ +#include "trace.h" +#else +#define traceInit() +#define traceOn() +#define traceOff() +#define traceOnce() +#define tracePrint() +#define traceAdd(loc, val) +#endif + +/* Debugging Macros */ + +#define ERR(fmt, args...) printf(TN40_DRV_NAME": "fmt, ## args) +#define MSG(fmt, args...) printf(TN40_DRV_NAME": "fmt, ## args) + +//#define BDX_ASSERT(x) BUG_ON(x) + +//#define BDX_ASSERT(x) +#define BDX_ASSERT(x) if ((x)) printf(TN40_DRV_NAME" ASSERT at %s:%-5d\n", __func__, __LINE__) +#define TN40_ASSERT(x, fmt, args...) if (!(x)) printf(TN40_DRV_NAME" ASSERT : ""%s:%-5d: " fmt, __func__, __LINE__, ## args) + +#define TN40_DEBUG +#define FTRACE +//#define REGLOG +#define WARNING + +#ifdef WARNING +#define WRN(fmt, args...) if (g_dbg)printf(TN40_DRV_NAME": " fmt, ## args) +#else +#define WRN(fmt, args...) +#endif +// M E M L O G +#ifdef TN40_MEMLOG +#include "memLog.h" +extern int g_memLog; +#define MEMLOG_ON g_memLog = 1 +#define MEMLOG1_ON g_memLog = 2 +#define MEMLOG_OFF g_memLog = 0 +//#define DBG(arg...) if (g_memLog) memLog(TN40_DRV_NAME": " arg) + +#else +#define MEMLOG_ON +#define MEMLOG1_ON +#define MEMLOG_OFF +#define memLog(args, ...) +#define memLogInit() +#define memLogDmesg() +#define memLogGetLine(x) (0) +#define memLogPrint() +#endif +// D E B U G +#define STRING_FMT "%s" +#if defined(TN40_DEBUG) +extern int g_dbg; +#define DBG_ON g_dbg = 1 +#define DBG1_ON g_dbg = 2 +#define DBG2_ON g_dbg = 3 +#define DBG_OFF g_dbg = 0 +#else +#define DBG_ON +#define DBG_OFF +#endif + +#if defined(TN40_DEBUG) && defined(TN40_MEMLOG) +#define DBG(fmt, args...) if (g_memLog) memLog(fmt, ##args); else if (g_dbg) printf(TN40_DRV_NAME": ""%s:%-5d: " fmt, __func__, __LINE__, ## args) +#define DBG1(fmt, args...) if (g_memLog > 1) memLog(fmt, ##args); else if (g_dbg > 1) printf(TN40_DRV_NAME": ""%s:%-5d: " fmt, __func__, __LINE__, ## args) +#define DBG2(fmt, args...) if (g_memLog > 2) memLog(fmt, ##args); else if (g_dbg > 1) printf(TN40_DRV_NAME": ""%s:%-5d: " fmt, __func__, __LINE__, ## args) +#elif defined(TN40_MEMLOG) +#define DBG(fmt, args...) if (g_memLog) memLog(fmt, ##args) +#define DBG1(fmt, args...) if (g_memLog > 1) memLog(fmt, ##args) +#define DBG2(fmt, args...) if (g_memLog > 2) memLog(fmt, ##args) +#elif defined(TN40_DEBUG) +#define DBG(fmt, args...) if (g_dbg == 1) printf(TN40_DRV_NAME": ""%s:%-5d: " fmt, __func__, __LINE__, ## args) +#define DBG1(fmt, args...) if (g_dbg == 2) printf(TN40_DRV_NAME": ""%s:%-5d: " fmt, __func__, __LINE__, ## args) +#define DBG2(fmt, args...) if (g_dbg == 3) printf(TN40_DRV_NAME": ""%s:%-5d: " fmt, __func__, __LINE__, ## args) +#define DMSG(fmt, args...) if (g_dbg == 1) printf(TN40_DRV_NAME": "fmt, ## args) +#else +#define DBG(fmt, args...) +#define DBG1(fmt, args...) +#define DBG2(fmt, args...) +#define DMSG(fmt, args...) +#endif + +// F T R A C E +#if defined(FTRACE) +extern int g_ftrace; +#define FTRACE_ON g_ftrace = 1 +#define FTRACE_OFF g_ftrace = 0 +//#define ENTER do { if (g_ftrace) printf("%s:%-5d: - enter\n", __func__, __LINE__); } while (0) +//#define RET(args...) do { if (g_ftrace) printf("%s:%-5d: - return\n", __func__, __LINE__); return args; } while (0) +#define ENTER do { if (g_ftrace) printf(TN40_DRV_NAME": %s: - enter\n" , __func__); } while (0) +#define RET(args...) do { if (g_ftrace) printf(TN40_DRV_NAME": %s: - return\n", __func__); return args; } while (0) +#define EXIT do { if (g_ftrace) printf(TN40_DRV_NAME": %s(): - exit\n", __func__);return;} while (0) +#else +#define FTRACE_ON +#define FTRACE_OFF +#define ENTER +#define EXIT +#define RET(args...) return args +#endif +#define BITS_PER_LONG 64 +#define TN40_LITTLE_ENDIAN +#if BITS_PER_LONG == 64 +# define H32_64(x) (u32) ((u64)(x) >> 32) +# define L32_64(x) (u32) ((u64)(x) & 0xffffffff) +#elif BITS_PER_LONG == 32 +# define H32_64(x) 0 +# define L32_64(x) ((u32) (x)) +#else /* BITS_PER_LONG == ?? */ +# error BITS_PER_LONG is undefined. Must be 64 or 32 +#endif /* BITS_PER_LONG */ +#define swab16 bswap16 +#ifdef TN40_LITTLE_ENDIAN +# define CPU_CHIP_SWAP32(x) (x) +# define CPU_CHIP_SWAP16(x) (x) +#else +# define CPU_CHIP_SWAP32(x) (SwapBytes32(x)) +# define CPU_CHIP_SWAP16(x) (SwapBytes16 (x)) +#endif + +#define TEHUTI_VID 0x1FC9 +#define DLINK_VID 0x1186 +#define ASUS_VID 0x1043 +#define EDIMAX_VID 0x1432 +#define PROMISE_VID 0x105a +#define BUFFALO_VID 0x1154 + +#define MDIO_SPEED_1MHZ (1) +#define MDIO_SPEED_6MHZ (6) +#define TN40_MAX_PAGE_SIZE (0x40000) + +enum LOAD_FW +{ + NO_FW_LOAD=0, + FW_LOAD, +}; + +/* Supported PHYs */ + +#define PHY_MV88X3310 +#define PHY_MV88E2010 +#define PHY_MV88X3120 +#define PHY_TLK10232 +#define PHY_AQR105 +#define PHY_QT2025 +struct bdx_priv; +int MV88X3310_set_speed(struct bdx_priv *priv, signed int speed); +int MV88X3120_set_speed(struct bdx_priv *priv, signed int speed); +int TLK10232_set_speed (struct bdx_priv *priv, signed int speed); +int AQR105_set_speed (struct bdx_priv *priv, signed int speed); +int QT2025_set_speed (struct bdx_priv *priv, signed int speed); + +#define AUTONEG_DISABLE (0) +#define AUTONEG_ENABLE (1) + +enum PHY_TYPE +{ + PHY_TYPE_NA, /* Port not exists or unknown PHY */ + PHY_TYPE_CX4, /* PHY works without initialization */ + PHY_TYPE_QT2025, /* QT2025 10 Gbps SFP+ */ + PHY_TYPE_MV88X3120, /* MV88X3120 10baseT */ + PHY_TYPE_MV88X3310, /* MV88X3310 10baseT */ + PHY_TYPE_MV88E2010, /* MV88E2010 5NbaseT */ + PHY_TYPE_TLK10232, /* TI TLK10232 SFP+ */ + PHY_TYPE_AQR105, /* AQR105 10baseT */ + PHY_TYPE_CNT +}; + +enum PHY_LEDS_OP +{ + PHY_LEDS_SAVE, + PHY_LEDS_RESTORE, + PHY_LEDS_ON, + PHY_LEDS_OFF, + PHY_LEDS_CNT +}; + +enum TX_STATE +{ + TX_STATE_OK, + TX_STATE_QUEUE_FULL +}; + +/* Driver states */ + +#define BDX_STATE_NONE (0x00000000) +#define BDX_STATE_HW_STOPPED (0x00000001) +#define BDX_STATE_STARTED (0x00000002) +#define BDX_STATE_OPEN (0x00000004) + +#define BDX_NDEV_TXQ_LEN 3000 +#define FIFO_SIZE 4096 +#define FIFO_EXTRA_SPACE 1024 +#define BDX_MAX_RX_DONE 150 +#define BDX_TXF_DESC_SZ 16 +#define BDX_MAX_TX_LEVEL (priv->txd_fifo0.m.memsz - 16) +#define BDX_MIN_TX_LEVEL 256 +#define BDX_NO_UPD_PACKETS 40 +#define BDX_MAX_MTU (1 << 14) + +#define PCK_TH_MULT 128 +#define INT_COAL_MULT 2 + +#define BITS_MASK(nbits) ((1 << nbits)-1) +#define GET_BITS_SHIFT(x, nbits, nshift) (((x) >> nshift)&BITS_MASK(nbits)) +#define BITS_SHIFT_MASK(nbits, nshift) (BITS_MASK(nbits) << nshift) +#define BITS_SHIFT_VAL(x, nbits, nshift) (((x) & BITS_MASK(nbits)) << nshift) +#define BITS_SHIFT_CLEAR(x, nbits, nshift) ((x)&(~BITS_SHIFT_MASK(nbits, nshift))) + +#define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0) +#define GET_INT_COAL_RC(x) GET_BITS_SHIFT(x, 1, 15) +#define GET_RXF_TH(x) GET_BITS_SHIFT(x, 4, 16) +#define GET_PCK_TH(x) GET_BITS_SHIFT(x, 4, 20) + +#define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th) \ + ((coal) | ((coal_rc) << 15) | ((rxf_th) << 16) | ((pck_th) << 20)) + +typedef struct +{ + void *va; + bus_addr_t pa; + bus_dmamap_t dma_map; +}tn40_dmamap_t; + +typedef struct +{ + bus_dma_tag_t dma_tag; + tn40_dmamap_t tn40_dmamap; +}tn40_dma_t; + + +struct fifo +{ + dma_addr_t da; /* Physical address of fifo (used by HW) */ + char *va; /* Virtual address of fifo (used by SW) */ + u32 rptr, wptr; /* Cached values of RPTR and WPTR registers, + they're 32 bits on both 32 and 64 archs */ + u16 reg_CFG0, reg_CFG1; + u16 reg_RPTR, reg_WPTR; + u16 memsz; /* Memory size allocated for fifo */ + u16 size_mask; + u16 pktsz; /* Skb packet size to allocate */ + u16 rcvno; /* Number of buffers that come from this RXF */ + tn40_dma_t dma; +}; + +struct txf_fifo +{ + struct fifo m; /* The minimal set of variables used by all fifos */ +}; + +struct txd_fifo +{ + struct fifo m; /* The minimal set of variables used by all fifos */ +}; + +struct rxf_fifo +{ + struct fifo m; /* The minimal set of variables used by all fifos */ +}; + +struct rxd_fifo +{ + struct fifo m; /* The minimal set of variables used by all fifos */ +}; + +struct rx_map +{ + bus_dmamap_t dma_map; + struct mbuf *mBuf; +}; + +struct rxdb +{ + int *stack; + struct rx_map *elems; + int nelem; + int top; + tn40_dma_t pkt; + int rxfSize; + int rxfAvail; +}; + +struct tx_map +{ + bus_dmamap_t dma_map; + int64_t len; + struct mbuf *mBuf; +}; + +/* tx database - implemented as circular fifo buffer*/ +struct txdb +{ + struct tx_map *start; /* Points to the first element */ + struct tx_map *end; /* Points just AFTER the last element */ + struct tx_map *rptr; /* Points to the next element to read */ + struct tx_map *wptr; /* Points to the next element to write */ + int size; /* Number of elements in the db */ +}; + +/*Internal stats structure*/ +struct bdx_stats +{ + u64 InUCast; /* 0x7200 */ + u64 InMCast; /* 0x7210 */ + u64 InBCast; /* 0x7220 */ + u64 InPkts; /* 0x7230 */ + u64 InErrors; /* 0x7240 */ + u64 InDropped; /* 0x7250 */ + u64 FrameTooLong; /* 0x7260 */ + u64 FrameSequenceErrors; /* 0x7270 */ + u64 InVLAN; /* 0x7280 */ + u64 InDroppedDFE; /* 0x7290 */ + u64 InDroppedIntFull; /* 0x72A0 */ + u64 InFrameAlignErrors; /* 0x72B0 */ + + /* 0x72C0-0x72E0 RSRV */ + + u64 OutUCast; /* 0x72F0 */ + u64 OutMCast; /* 0x7300 */ + u64 OutBCast; /* 0x7310 */ + u64 OutPkts; /* 0x7320 */ + + /* 0x7330-0x7360 RSRV */ + + u64 OutVLAN; /* 0x7370 */ + u64 InUCastOctects; /* 0x7380 */ + u64 OutUCastOctects; /* 0x7390 */ + + /* 0x73A0-0x73B0 RSRV */ + + u64 InBCastOctects; /* 0x73C0 */ + u64 OutBCastOctects; /* 0x73D0 */ + u64 InOctects; /* 0x73E0 */ + u64 OutOctects; /* 0x73F0 */ +}; +#define PHY_LEDS (4) +struct bdx_phy_operations +{ + unsigned short leds[PHY_LEDS]; + int (*mdio_reset) (struct bdx_priv *, int, unsigned short); + u32 (*link_changed)(struct bdx_priv *); + void (*ledset) (struct bdx_priv *, enum PHY_LEDS_OP); + int (*get_settings)(struct bdx_priv *); + int (*set_settings)(struct bdx_priv *, int); + +#ifdef _EEE_ + int (*get_eee) (struct net_device *, struct ethtool_eee *); + int (*set_eee) (struct bdx_priv *); + int (*reset_eee) (struct bdx_priv *); +#endif + u32 mdio_speed; +}; + +//#define TN40_COUNTERS +#ifdef TN40_COUNTERS +typedef struct +{ + u64 tx_pkts; + u64 tx_bytes; + u64 tx_fixed_bytes; + u64 tx_free_pkts; + u64 tx_free_bytes; +} bdx_counters_t; + +#define COUNT_INC(x, counter) atomic_add_64(&(x.counter), 1) +#define COUNT_ADD(x, counter, n) atomic_add_64(&(x.counter), n) +#else +#define COUNT_INC(x, counter) +#define COUNT_ADD(x, counter, n) +#endif +struct bdx_priv +{ + u8 *pBdxRegs; + struct rte_eth_dev *eth_dev; +// struct napi_struct napi; + /* RX FIFOs: 1 for data (full) descs, and 2 for free descs */ + struct rxd_fifo rxd_fifo0; + struct rxf_fifo rxf_fifo0; + struct rxdb *rxdb0; /* Rx dbs to store skb pointers */ + int napi_stop; + struct vlan_group *vlgrp; + /* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */ + struct txd_fifo txd_fifo0; + struct txf_fifo txf_fifo0; + struct txdb txdb; + int tx_level; + int tx_update_mark; + int tx_noupd; + /* Rarely used */ + u8 port; + u8 phy_mdio_port; + enum PHY_TYPE phy_type; + u32 msg_enable; + int stats_flag; + struct bdx_stats hw_stats; +// struct net_device_stats net_stats; +// struct pci_dev *pdev; +// struct pci_nic *nic; + u8 txd_size; + u8 txf_size; + u8 rxd_size; + u8 rxf_size; + u32 rdintcm; + u32 tdintcm; + u16 id; + u16 count; +// struct timer_list blink_timer; + u32 isr_mask; + int link_speed; // 0- no link or SPEED_100 SPEED_1000 SPEED_10000 + u32 link_loop_cnt; + u32 sfp_mod_type; + struct bdx_phy_operations phy_ops; + // SHORT_PKT_FIX + tn40_dma_t short_pkt; + const char *name; /* device driver name */ + u32 errmsg_count; + u32 state; + u16 deviceId; + u16 subsystem_vendor; + u16 subsystem_device; + u32 advertising, autoneg; + u32 eee_enabled; + u8 mac_address[ETHER_ADDR_LEN]; + u16 mtu; + u32 rx_buf_size; + unsigned int socket_id; + enum TX_STATE tx_state; + bus_dma_tag_t tx_dma_tag; + bus_dma_tag_t rx_dma_tag; +#ifdef TN40_COUNTERS + bdx_counters_t counters; +#endif +}; + +#define SPEED_NOT_SUPPORTED 0 +#define SPEED_AUTO 1 +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_5000 5000 +#define SPEED_10000 10000 +#define SPEED_1000X (1001) +#define SPEED_100X (101) + +#define MAX_ERRMSGS (3) +/* RX FREE descriptor - 64bit*/ + +struct pbl +{ + u32 pa_lo; + u32 pa_hi; + u32 len; +}; + +struct rxf_desc +{ + u32 info; /* Buffer Count + Info - described below */ + u32 va_lo; /* VAdr[31:0] */ + u32 va_hi; /* VAdr[63:32] */ + struct pbl pbl[1]; /* DMA scatter gather */ +}__attribute__ ((packed)); + +#define GET_RXD_BC(x) GET_BITS_SHIFT((x), 5, 0) +#define GET_RXD_RXFQ(x) GET_BITS_SHIFT((x), 2, 8) +#define GET_RXD_TO(x) GET_BITS_SHIFT((x), 1, 15) +#define GET_RXD_TYPE(x) GET_BITS_SHIFT((x), 4, 16) +#define GET_RXD_ERR(x) GET_BITS_SHIFT((x), 6, 21) +#define GET_RXD_RXP(x) GET_BITS_SHIFT((x), 1, 27) +#define GET_RXD_PKT_ID(x) GET_BITS_SHIFT((x), 3, 28) +#define GET_RXD_VTAG(x) GET_BITS_SHIFT((x), 1, 31) +#define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0) +#define GET_RXD_VLAN_TCI(x) GET_BITS_SHIFT((x), 16, 0) +#define GET_RXD_CFI(x) GET_BITS_SHIFT((x), 1, 12) +#define GET_RXD_PRIO(x) GET_BITS_SHIFT((x), 3, 13) + +#define GET_RSS_FUNC(x) GET_BITS_SHIFT((x), 2, 0) +#define GET_RSS_TYPE(x) GET_BITS_SHIFT((x), 8, 8) +#define GET_RSS_TCPU(x) GET_BITS_SHIFT((x), 8, 16) + +enum +{ + PKT_TYPE_NON_IP = 0, + PKT_TYPE_TCP = 1, + PKT_TYPE_UDP = 2, + PKT_TYPE_IP = 3, // Not TCP or UDP + PKT_TYPE_RESERVED = 4, + PKT_TYPE_TCPV6 = 5, + PKT_TYPE_UDPV6 = 6, + PKT_TYPE_IPV6 = 7, // Not TCP or UDP +}; + +typedef struct eth_header +{ + u8 dstAddr[ETHER_ADDR_LEN]; + u8 srcAddr[ETHER_ADDR_LEN]; + u16 type; +} __attribute__ ((packed)) ETHER_HEADER; + +struct ip_header +{ + u8 ihl:4, version:4; + u8 ToS; + u16 tLen; + u16 id; + u16 fragOff; + u8 TTL; + u8 protocol; + u16 checkSum; + u32 srcAddr; + u32 dstAddr; +}__attribute__ ((packed)); + +struct rxd_desc +{ + u32 rxd_val1; + u16 len; + u16 rxd_vlan; + u32 va_lo; + u32 va_hi; + u32 rss_lo; + u32 rss_hash; +}; + +#define MAX_SEGMENTS (64) +#define MAX_PBL (19) +/* PBL describes each virtual buffer to be transmitted from the host. */ + + +/* + * First word for TXD descriptor. It means: type = 3 for regular Tx packet, + * hw_csum = 7 for IP+UDP+TCP HW checksums. + */ + +#define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id) \ + ((bc) | ((checksum) << 5) | ((vtag) << 8) | \ + ((lgsnd) << 9) | (0x30000) | ((vlan_id & 0x0fff) << 20) | (((vlan_id >> 13) & 7) << 13)) + +struct txd_desc +{ + u32 txd_val1; + u16 mss; + u16 length; + u32 va_lo; + u32 va_hi; + struct pbl pbl[0]; /* Fragments */ +} __attribute__ ((packed)); + +struct txf_desc +{ + u32 status; + u32 va_lo; /* VAdr[31:0] */ + u32 va_hi; /* VAdr[63:32] */ + u32 pad; +}__attribute__ ((packed)); + +#define READ_REG(pp, reg) tn40_read_reg (pp, reg) +#define WRITE_REG(pp, reg, val) tn40_write_reg(pp, reg, val) + +/* Register region size */ +#define BDX_REGS_SIZE 0x10000 + +/* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */ +#define regTXD_CFG1_0 0x4000 +#define regTXD_CFG1_1 0x4004 +#define regTXD_CFG1_2 0x4008 +#define regTXD_CFG1_3 0x400C + +#define regRXF_CFG1_0 0x4010 +#define regRXF_CFG1_1 0x4014 +#define regRXF_CFG1_2 0x4018 +#define regRXF_CFG1_3 0x401C + +#define regRXD_CFG1_0 0x4020 +#define regRXD_CFG1_1 0x4024 +#define regRXD_CFG1_2 0x4028 +#define regRXD_CFG1_3 0x402C + +#define regTXF_CFG1_0 0x4030 +#define regTXF_CFG1_1 0x4034 +#define regTXF_CFG1_2 0x4038 +#define regTXF_CFG1_3 0x403C + +#define regTXD_CFG0_0 0x4040 +#define regTXD_CFG0_1 0x4044 +#define regTXD_CFG0_2 0x4048 +#define regTXD_CFG0_3 0x404C + +#define regRXF_CFG0_0 0x4050 +#define regRXF_CFG0_1 0x4054 +#define regRXF_CFG0_2 0x4058 +#define regRXF_CFG0_3 0x405C + +#define regRXD_CFG0_0 0x4060 +#define regRXD_CFG0_1 0x4064 +#define regRXD_CFG0_2 0x4068 +#define regRXD_CFG0_3 0x406C + +#define regTXF_CFG0_0 0x4070 +#define regTXF_CFG0_1 0x4074 +#define regTXF_CFG0_2 0x4078 +#define regTXF_CFG0_3 0x407C + +#define regTXD_WPTR_0 0x4080 +#define regTXD_WPTR_1 0x4084 +#define regTXD_WPTR_2 0x4088 +#define regTXD_WPTR_3 0x408C + +#define regRXF_WPTR_0 0x4090 +#define regRXF_WPTR_1 0x4094 +#define regRXF_WPTR_2 0x4098 +#define regRXF_WPTR_3 0x409C + +#define regRXD_WPTR_0 0x40A0 +#define regRXD_WPTR_1 0x40A4 +#define regRXD_WPTR_2 0x40A8 +#define regRXD_WPTR_3 0x40AC + +#define regTXF_WPTR_0 0x40B0 +#define regTXF_WPTR_1 0x40B4 +#define regTXF_WPTR_2 0x40B8 +#define regTXF_WPTR_3 0x40BC + +#define regTXD_RPTR_0 0x40C0 +#define regTXD_RPTR_1 0x40C4 +#define regTXD_RPTR_2 0x40C8 +#define regTXD_RPTR_3 0x40CC + +#define regRXF_RPTR_0 0x40D0 +#define regRXF_RPTR_1 0x40D4 +#define regRXF_RPTR_2 0x40D8 +#define regRXF_RPTR_3 0x40DC + +#define regRXD_RPTR_0 0x40E0 +#define regRXD_RPTR_1 0x40E4 +#define regRXD_RPTR_2 0x40E8 +#define regRXD_RPTR_3 0x40EC + +#define regTXF_RPTR_0 0x40F0 +#define regTXF_RPTR_1 0x40F4 +#define regTXF_RPTR_2 0x40F8 +#define regTXF_RPTR_3 0x40FC + +/* Hardware versioning */ +#define FW_VER 0x5010 +#define SROM_VER 0x5020 +#define FPGA_VER 0x5030 +#define FPGA_SEED 0x5040 + +/* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */ +#define regISR regISR0 +#define regISR0 0x5100 + +#define regIMR regIMR0 +#define regIMR0 0x5110 + +#define regRDINTCM0 0x5120 +#define regRDINTCM2 0x5128 + +#define regTDINTCM0 0x5130 + +#define regISR_MSK0 0x5140 + +#define regINIT_SEMAPHORE 0x5170 +#define regINIT_STATUS 0x5180 + +#define regMAC_LNK_STAT 0x0200 +#define MAC_LINK_STAT 0x0004 /* Link state */ + +#define regBLNK_LED 0x0210 + +#define regGMAC_RXF_A 0x1240 + +#define regUNC_MAC0_A 0x1250 +#define regUNC_MAC1_A 0x1260 +#define regUNC_MAC2_A 0x1270 + +#define regVLAN_0 0x1800 + +#define regMAX_FRAME_A 0x12C0 + +#define regRX_MAC_MCST0 0x1A80 +#define regRX_MAC_MCST1 0x1A84 +#define MAC_MCST_NUM 15 +#define regRX_MCST_HASH0 0x1A00 +#define MAC_MCST_HASH_NUM 8 + +#define regVPC 0x2300 +#define regVIC 0x2320 +#define regVGLB 0x2340 + +#define regCLKPLL 0x5000 + +/* MDIO interface */ + +#define regMDIO_CMD_STAT 0x6030 +#define regMDIO_CMD 0x6034 +#define regMDIO_DATA 0x6038 +#define regMDIO_ADDR 0x603C +#define GET_MDIO_BUSY(x) GET_BITS_SHIFT(x, 1, 0) +#define GET_MDIO_RD_ERR(x) GET_BITS_SHIFT(x, 1, 1) + +/*for 10G only*/ +#define regRSS_CNG 0x000000b0 + +#define RSS_ENABLED 0x00000001 +#define RSS_HFT_TOEPLITZ 0x00000002 +#define RSS_HASH_IPV4 0x00000100 +#define RSS_HASH_TCP_IPV4 0x00000200 +#define RSS_HASH_IPV6 0x00000400 +#define RSS_HASH_IPV6_EX 0x00000800 +#define RSS_HASH_TCP_IPV6 0x00001000 +#define RSS_HASH_TCP_IPV6_EX 0x00002000 + +#define regRSS_HASH_BASE 0x0400 +#define RSS_HASH_LEN 40 +#define regRSS_INDT_BASE 0x0600 +#define RSS_INDT_LEN 256 + +#define regREVISION 0x6000 +#define regSCRATCH 0x6004 +#define regCTRLST 0x6008 +#define regMAC_ADDR_0 0x600C +#define regMAC_ADDR_1 0x6010 +#define regFRM_LENGTH 0x6014 +#define regPAUSE_QUANT 0x6054 +#define regRX_FIFO_SECTION 0x601C +#define regTX_FIFO_SECTION 0x6020 +#define regRX_FULLNESS 0x6024 +#define regTX_FULLNESS 0x6028 +#define regHASHTABLE 0x602C + +#define regRST_PORT 0x7000 +#define regDIS_PORT 0x7010 +#define regRST_QU 0x7020 +#define regDIS_QU 0x7030 + +#define regCTRLST_TX_ENA 0x0001 +#define regCTRLST_RX_ENA 0x0002 +#define regCTRLST_PRM_ENA 0x0010 +#define regCTRLST_PAD_ENA 0x0020 + +#define regCTRLST_BASE (regCTRLST_PAD_ENA|regCTRLST_PRM_ENA) + +#define regRX_FLT 0x1400 + +/* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c*/ +#define TX_RX_CFG1_BASE 0xffffffff /*0-31 */ +#define TX_RX_CFG0_BASE 0xfffff000 /*31:12 */ +#define TX_RX_CFG0_RSVD 0x00000ffc /*11:2 */ +#define TX_RX_CFG0_SIZE 0x00000003 /*1:0 */ + +/* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */ +#define TXF_WPTR_WR_PTR 0x00007ff8 /*14:3 */ + +/* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */ +#define TXF_RPTR_RD_PTR 0x00007ff8 /*14:3 */ + +#define TXF_WPTR_MASK 0x7ff0 /* The last 4 bits are dropped +* size is rounded to 16 */ + +/* regISR 0x0100 */ +/* regIMR 0x0110 */ +#define IMR_INPROG 0x80000000 /*31 */ +#define IR_LNKCHG1 0x10000000 /*28 */ +#define IR_LNKCHG0 0x08000000 /*27 */ +#define IR_GPIO 0x04000000 /*26 */ +#define IR_RFRSH 0x02000000 /*25 */ +#define IR_RSVD 0x01000000 /*24 */ +#define IR_SWI 0x00800000 /*23 */ +#define IR_RX_FREE_3 0x00400000 /*22 */ +#define IR_RX_FREE_2 0x00200000 /*21 */ +#define IR_RX_FREE_1 0x00100000 /*20 */ +#define IR_RX_FREE_0 0x00080000 /*19 */ +#define IR_TX_FREE_3 0x00040000 /*18 */ +#define IR_TX_FREE_2 0x00020000 /*17 */ +#define IR_TX_FREE_1 0x00010000 /*16 */ +#define IR_TX_FREE_0 0x00008000 /*15 */ +#define IR_RX_DESC_3 0x00004000 /*14 */ +#define IR_RX_DESC_2 0x00002000 /*13 */ +#define IR_RX_DESC_1 0x00001000 /*12 */ +#define IR_RX_DESC_0 0x00000800 /*11 */ +#define IR_PSE 0x00000400 /*10 */ +#define IR_TMR3 0x00000200 /* 9 */ +#define IR_TMR2 0x00000100 /* 8 */ +#define IR_TMR1 0x00000080 /* 7 */ +#define IR_TMR0 0x00000040 /* 6 */ +#define IR_VNT 0x00000020 /* 5 */ +#define IR_RxFL 0x00000010 /* 4 */ +#define IR_SDPERR 0x00000008 /* 3 */ +#define IR_TR 0x00000004 /* 2 */ +#define IR_PCIE_LINK 0x00000002 /* 1 */ +#define IR_PCIE_TOUT 0x00000001 /* 0 */ + +#define IR_EXTRA (IR_RX_FREE_0 | IR_LNKCHG0 | IR_LNKCHG1 | IR_PSE | \ + IR_TMR0 | IR_PCIE_LINK | IR_PCIE_TOUT) +#define IR_RUN (IR_EXTRA | IR_RX_DESC_0 | IR_TX_FREE_0) +#define IR_ALL 0xfdfffff7 + +#define IR_LNKCHG0_ofst 27 + +#define GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */ +#define GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */ +#define GMAC_RX_FILTER_RSV0 0x0200 /* reserved */ +#define GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */ +#define GMAC_RX_FILTER_AOF 0x0080 /* accept over run */ +#define GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */ +#define GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */ +#define GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */ +#define GMAC_RX_FILTER_AM 0x0008 /* accept multicast */ +#define GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */ +#define GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscuous mode */ + +#define MAX_FRAME_AB_VAL 0x3fff /* 13:0 */ + +#define CLKPLL_PLLLKD 0x0200 /* 9 */ +#define CLKPLL_RSTEND 0x0100 /* 8 */ +#define CLKPLL_SFTRST 0x0001 /* 0 */ + +#define CLKPLL_LKD (CLKPLL_PLLLKD|CLKPLL_RSTEND) + +/* + * PCI-E Device Control Register (Offset 0x88) + * Source: Luxor Data Sheet, 7.1.3.3.3 + */ +#define PCI_DEV_CTRL_REG 0x88 +#define GET_DEV_CTRL_MAXPL(x) GET_BITS_SHIFT(x, 3, 5) +#define GET_DEV_CTRL_MRRS(x) GET_BITS_SHIFT(x, 3, 12) + +/* + * PCI-E Link Status Register (Offset 0x92) + * Source: Luxor Data Sheet, 7.1.3.3.7 + */ +#define PCI_LINK_STATUS_REG 0x92 +#define GET_LINK_STATUS_LANES(x) GET_BITS_SHIFT(x, 6, 4) +#if !defined(ROUND_UP) +#define ROUND_UP(n, m) (((n) + (m - 1)) & ~(m - 1)) +#endif +int bdx_mdio_write(struct bdx_priv *priv, int device, int port, u16 addr, u16 data); +int bdx_mdio_read(struct bdx_priv *priv, int device, int port, u16 addr); + +#define PHY_MDIO_READ(priv,device,addr) bdx_mdio_read(priv,(device),(priv)->phy_mdio_port,(addr)) +#define PHY_MDIO_WRITE(priv,device,addr,data) bdx_mdio_write((priv),(device),(priv)->phy_mdio_port, (addr), (data)) + +#define BDX_MDIO_WRITE(priv, space, addr, val) \ + if (bdx_mdio_write((priv), (space), port, (addr), (val))) { \ + ERR("bdx: failed to write to phy at %x.%x val %x\n", \ + (space),(addr),(val)); \ + return 1; \ + } +enum PHY_TYPE MV88X3310_register(struct bdx_priv *priv); +enum PHY_TYPE MV88X3120_register(struct bdx_priv *priv); +enum PHY_TYPE QT2025_register (struct bdx_priv *priv); +enum PHY_TYPE CX4_register (struct bdx_priv *priv); +enum PHY_TYPE TLK10232_register (struct bdx_priv *priv); +enum PHY_TYPE AQR105_register (struct bdx_priv *priv); + +void bdx_link_changed (struct bdx_priv *priv); +int bdx_probe (struct bdx_priv *priv); +void bdx_speed_changed (struct bdx_priv *priv, u32 speed); +int bdx_mdio_read (struct bdx_priv *priv, int device, int port, u16 addr); +int bdx_mdio_write (struct bdx_priv *priv, int device, int port, u16 addr, u16 data); +int bdx_tx_init (struct bdx_priv *priv); +int bdx_rx_init (struct bdx_priv *priv); +void bdx_rx_free (struct bdx_priv *priv); +void bdx_tx_free (struct bdx_priv *priv); +int bdx_open (struct bdx_priv *priv); +int bdx_close (struct bdx_priv *priv); +int bdx_set_mac (struct bdx_priv *priv, u8 *addr); +int bdx_change_mtu (struct bdx_priv *priv, int new_mtu); +int bdx_tx_transmit (struct bdx_priv *priv, struct mbuf *mBuf); +void bdx_enable_interrupts (struct bdx_priv *priv); +void bdx_disable_interrupts (struct bdx_priv *priv); +void bdx_update_stats (struct bdx_priv *priv); +u16 bdx_get_rxbuf_size (struct bdx_priv *priv); +u16 bdx_rx_pkt_size (struct bdx_priv *priv); +int bdx_get_status (struct bdx_priv *priv); +int bdx_speed_set (struct bdx_priv *priv, u32 speed); +void bdx_remove (struct bdx_priv *priv); +void bdx_setbroadcast (struct bdx_priv *priv, int flags); +void bdx_setmulti (struct bdx_priv *priv); +int bdx_ioctl_priv (struct bdx_priv *priv, struct ifreq *ifr); +void bdx_rx_receive (struct bdx_priv *priv); +void bdx_tx_cleanup (struct bdx_priv *priv); +void bdx_link_changed (struct bdx_priv *priv); +int bdx_isr (struct bdx_priv *priv); +u32 bdx_mdio_get (struct bdx_priv *priv); +void bdx_vlan_rx_vid (struct bdx_priv *priv, uint16_t vid, int enable); + +#endif /* _TN40_HW_H_ */ Index: sys/dev/tn40xx/tn40_hw.c =================================================================== --- /dev/null +++ sys/dev/tn40xx/tn40_hw.c @@ -0,0 +1,3234 @@ + /* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "tn40.h" +#include "tn40_fw.h" +#include "tn40_mbuf.h" + +MALLOC_DEFINE(M_TN40, "tn40", "tn40"); + +u32 bdx_force_no_phy_mode = 0; + + +/* Definitions needed by ISR */ +static int bdx_rx_alloc_buffers(struct bdx_priv *priv); +/* Definitions needed by FW loading */ +static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size); + +/* Definitions needed by bdx_probe */ +#ifdef _DRIVER_RESUME_ +//static int bdx_suspend(struct pci_dev *pdev, pm_message_t state); +//static int bdx_resume (struct pci_dev *pdev); +static int bdx_suspend(struct device *dev); +static int bdx_resume(struct device *dev); +#endif +//#define USE_RSS +#if defined(USE_RSS) +/* bdx_init_rss - Initialize RSS hash HW function. + * + * @priv - NIC private structure + */ +#if defined(RHEL_RELEASE_CODE) +#define prandom_seed(seed) +#define prandom_u32 random32 +#endif +static int bdx_init_rss(struct bdx_priv *priv) +{ + int i; + u32 seed; + + /* Disable RSS before starting the configuration */ + + WRITE_REG(priv, regRSS_CNG, 0); + /* + * Notes: + * - We do not care about the CPU, we just need the hash value, the + * Linux kernel is doing the rest of the work for us. We set the + * CPU table length to 0. + * + * - We use random32() to initialize the Toeplitz secret key. This is + * probably not cryptographically secure way but who cares. + */ + + /* UPDATE THE HASH SECRET KEY */ + seed = (uint32_t_t)(0xFFFFFFFF & jiffies); + prandom_seed(seed); + for (i =0; i < 4 * RSS_HASH_LEN; i += 4) + { + u32 rnd = prandom_u32(); + WRITE_REG(priv, regRSS_HASH_BASE + 4 * i, rnd); + DBG("bdx_init_rss() rnd 0x%x\n", rnd); + } + WRITE_REG(priv, regRSS_CNG, + RSS_ENABLED | RSS_HFT_TOEPLITZ | + RSS_HASH_IPV4 | RSS_HASH_TCP_IPV4 | + RSS_HASH_IPV6 | RSS_HASH_TCP_IPV6); + + DBG("regRSS_CNG =%x\n", READ_REG(priv, regRSS_CNG)); + RET(0); +} +#else +#define bdx_init_rss(priv) +#endif + +#if defined(TN40_DEBUG) +struct +{ + u32 rx; + u32 tx; + +}g_dbgCounters = {0,0}; + +int g_dbg=0; +#endif +#if defined(TN40_FTRACE) +int g_ftrace=0; +#endif +#if defined(TN40_REGLOG) +int g_regLog=0; +#endif +#if defined (TN40_MEMLOG) +int g_memLog=0; +#endif + +//------------------------------------------------------------------------------------------------- + +static struct +{ + u16 bytes; + u16 qwords; /* qword = 64 bit */ +} txd_sizes[MAX_PBL]; + +static struct +{ + u16 bytes; + u16 qwords; /* qword = 64 bit */ +} rxd_sizes[MAX_PBL]; + +#if defined(TN40_DEBUG) + +//------------------------------------------------------------------------------------------------- + +static void dbg_printFifo(struct bdx_priv *priv, struct fifo *m, const char *fName) +{ + DBG("%s fifo:\n", fName); + DBG("WPTR (0x%x) 0x%x RPTR (0x%x) 0x%x\n",m->reg_WPTR, m->wptr, m->reg_RPTR, m->rptr); + DBG("READ_REG 0x%04x m->reg_WPTR=0x%x\n", m->reg_WPTR, READ_REG(priv, m->reg_WPTR)); + DBG("READ_REG 0x%04x m->reg_RPTR=0x%x\n", m->reg_RPTR, READ_REG(priv, m->reg_RPTR)); + DBG("f->va %p f->da %p\n", m->va, (void*)m->da); + DBG("READ_REG 0x%04x m->reg_CFG0=0x%x\n", m->reg_CFG0, READ_REG(priv, m->reg_CFG0)); + DBG("READ_REG 0x%04x m->reg_CFG1=0x%x\n", m->reg_CFG1, READ_REG(priv, m->reg_CFG1)); + +} // dbg_printFifo() + +//------------------------------------------------------------------------------------------------- + +static void dbg_printRegs(struct bdx_priv *priv, char *msg) +{ + ENTER; + DBG("* %s * \n", msg); + DBG("~~~~~~~~~~~~~\n"); + DBG("veneto:"); + DBG("pc = 0x%x li = 0x%x ic = %d\n", READ_REG(priv, 0x2300), READ_REG(priv, 0x2310), READ_REG(priv, 0x2320)); + dbg_printFifo(priv, &priv->txd_fifo0.m, (const char *)"TXD"); + dbg_printFifo(priv, &priv->rxf_fifo0.m, (const char *)"RXF"); + dbg_printFifo(priv, &priv->rxd_fifo0.m, (const char *)"RXD"); + DBG("~~~~~~~~~~~~~\n"); + + EXIT; + +} // dbg_printRegs() + +//------------------------------------------------------------------------------------------------- + +static void dbg_printPBL(struct pbl *pbl) +{ + DBG("pbl: len %u pa_lo 0x%x pa_hi 0x%x\n", pbl->len, pbl->pa_lo, pbl->pa_hi); + +} // dbg_printPBL() + +//------------------------------------------------------------------------------------------------- + +static void dbg_print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len, u16 rxd_vlan) +{ + DBG("rxdd bc %d rxfq %d to %d type %d err %d rxp %d " + "pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d " + "va_lo %d va_hi %d\n", + GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1), + GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1), + GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1), + GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan), + GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo, + rxdd->va_hi); + +} // dbg_dbg_print_rxdd() + +//------------------------------------------------------------------------------------------------- + +static void dbg_print_rxfd(struct rxf_desc *rxfd) +{ + DBG("info 0x%x va_hi 0x%x va_lo %u\n", + rxfd->info, rxfd->va_hi, rxfd->va_lo); + +} // dbg_print_rxfd() + +//------------------------------------------------------------------------------------------------- + +static void dbg_printIoctl(void) +{ + MSG("DBG_ON %d, DBG_OFF %d, DBG_SUSPEND %d, DBG_RESUME %d DBG_PRINT_PAGE_TABLE %d DBG_PRINT_COUNTERS %d DBG_CLEAR_COUNTERS %d\n", + DBG_START_DBG, DBG_STOP_DBG, DBG_SUSPEND, DBG_RESUME, DBG_PRINT_PAGE_TABLE, DBG_PRINT_COUNTERS, DBG_CLEAR_COUNTERS); + +} // dbg_printIoctl + +//------------------------------------------------------------------------------------------------- +static void dbg_printMbuf(struct mbuf *m, int line) __attribute__((unused)); +static void dbg_printMbuf(struct mbuf *m, int line) +{ + int j = 1; + if (g_dbg == 1) + { + MSG("%d mbuf:\n", line); + while (m) + { + MSG(" %d. m %p nxt %p nxtp %p dat %p len %d %d typ 0x%x flgs 0x%x\n", j, + m, m->m_next, m->m_nextpkt, m->m_data, m->m_len, + (m->m_flags & M_PKTHDR) ? m->m_pkthdr.len: 0, m->m_type, m->m_flags); + if (m->m_flags & M_EXT) + { + MSG(" xbuf %p xsize %d xtyp 0x%x xflgs 0x%x csum 0x%x\n", + m->m_ext.ext_buf, m->m_ext.ext_size, m->m_ext.ext_type, m->m_ext.ext_flags, (uint32_t)m->m_pkthdr.csum_flags); + } + m = m->m_next; + j += 1; + } + } +} // dbg_printMbuf() + +//------------------------------------------------------------------------------------------------- +void dbg_printSges(bus_dma_segment_t *segs, int len) __attribute__((unused)); +void dbg_printSges(bus_dma_segment_t *segs, int len) +{ + int j = 1; + uint64_t prevAddrEnd = 0; + if (g_dbg == 1) + { + MSG("Segs:\n"); + for (j = 0; j <= len; j++) + { + MSG(" 0x%08lx %lu %s\n", segs[j].ds_addr, segs[j].ds_len, + (segs[j].ds_addr == prevAddrEnd)? " *" : ""); + prevAddrEnd = segs[j].ds_addr + segs[j].ds_len; + } + + } + +} // dbg_printSges() + +//------------------------------------------------------------------------------------------------- +static void dbg_printRxPkt(struct mbuf *mBuf, char *pkt, u16 len) __attribute__((unused)); +static void dbg_printRxPkt(struct mbuf *mBuf, char *pkt, u16 len) +{ + int i; + + if (g_dbg == 1) + { + if (pkt == NULL) + { + pkt = mBuf->m_data; + } + MSG("RX: len=%d\n",len); + if (pkt) + { + for(i=0; icounters.tx_pkts); + MSG("tn40.tx_deferred_pkts %lu\n", tn40_priv->counters.tx_deferred_pkts); + MSG("tn40.tx_locked_pkts %lu\n", tn40_priv->counters.tx_locked_pkts); + MSG("bdx.tx_pkts %lu\n", priv->counters.tx_pkts); + MSG("bdx.tx_bytes %lu\n", priv->counters.tx_bytes); + MSG("bdx.tx_fixed_bytes %lu\n", priv->counters.tx_fixed_bytes); + MSG("bdx.tx_free_pkts %lu\n", priv->counters.tx_free_pkts); + MSG("bdx.tx_free_bytes %lu\n", priv->counters.tx_free_bytes); + +} // bdx_printCounters() + +//------------------------------------------------------------------------------------------------- + +static void bdx_clearCounters(struct bdx_priv *priv) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + + bzero((void *)&tn40_priv->counters, sizeof(tn40_priv->counters)); + bzero((void *)&priv->counters, sizeof(priv->counters)); + +} // bdx_clearCounters() + +#endif + +//------------------------------------------------------------------------------------------------- + +static void bdx_print_phys(void) +{ + #ifdef PHY_MV88X3120 + MSG("MV88X3120 phy supported\n"); + #endif + #ifdef PHY_MV88X3310 + MSG("MV88X3310 phy supported\n"); + #endif + #ifdef PHY_MV88E2010 + MSG("MV88E2010 phy supported\n"); + #endif + #ifdef PHY_TLK10232 + MSG("TLK10232 phy supported\n"); + #endif + #ifdef PHY_QT2025 + MSG("QT2025 phy supported\n"); + #endif + #ifdef PHY_AQ2104 + MSG("AQ2104 phy supported\n"); + #endif + +} // bdx_print_phys() + +//------------------------------------------------------------------------------------------------- + +static void print_driver_id(void) +{ + MSG("%s, %s\n", TN40_DRV_DESC, TN40_DRV_VERSION); + bdx_print_phys(); + +} // print_driver_id() + + +/************************************************************************* + * MDIO Interface * + *************************************************************************/ +/* bdx_mdio_get - read MDIO_CMD_STAT until the device is not busy + * + * returns the CMD_STAT value read, or -1 (0xFFFFFFFF) for failure + * (since the busy bit should be off, -1 can never be a valid value for + * mdio_get). + */ + +u32 bdx_mdio_get(struct bdx_priv *priv) +{ +#define BDX_MAX_MDIO_BUSY_LOOPS 1024 + int tries = 0; + while (++tries < BDX_MAX_MDIO_BUSY_LOOPS) + { + u32 mdio_cmd_stat = READ_REG(priv, regMDIO_CMD_STAT); + + if (GET_MDIO_BUSY(mdio_cmd_stat)== 0) + { + // ERR("mdio_get success after %d tries (val=%u 0x%x)\n", tries, mdio_cmd_stat, mdio_cmd_stat); + return mdio_cmd_stat; + } + } + ERR("MDIO busy!\n"); + return 0xFFFFFFFF; + +} // bdx_mdio_get() + +//------------------------------------------------------------------------------------------------- + +/* bdx_mdio_read - read a 16bit word through the MDIO interface + * @priv + * @device - 5 bit device id + * @port - 5 bit port id + * @addr - 16 bit address + * returns a 16bit value or -1 for failure + */ +int bdx_mdio_read(struct bdx_priv *priv, int device, int port, u16 addr) +{ + u32 tmp_reg, i; + /* Wait until MDIO is not busy */ + if (bdx_mdio_get(priv)== 0xFFFFFFFF) + { + return -1; + } + i=( (device&0x1F) | ((port&0x1F)<<5) ); + WRITE_REG(priv, regMDIO_CMD, i); + WRITE_REG(priv, regMDIO_ADDR, (u32)addr); + if ((tmp_reg = bdx_mdio_get(priv)) == 0xFFFFFFFF) + { + ERR("MDIO busy after read command\n"); + return -1; + } + WRITE_REG(priv, regMDIO_CMD, ((1<<15) |i)); + /* Read CMD_STAT until not busy */ + if ((tmp_reg = bdx_mdio_get(priv)) == 0xFFFFFFFF) + { + ERR("MDIO busy after read command\n"); + return -1; + } + if (GET_MDIO_RD_ERR(tmp_reg)) + { + DBG("MDIO error after read command\n"); + return -1; + } + tmp_reg = READ_REG(priv, regMDIO_DATA); + + // ERR("MDIO_READ: MDIO_DATA =0x%x \n", (tmp_reg & 0xFFFF)); + return (int)(tmp_reg & 0xFFFF); + +} // bdx_mdio_read() + +//------------------------------------------------------------------------------------------------- + +/* bdx_mdio_write - writes a 16bit word through the MDIO interface + * @priv + * @device - 5 bit device id + * @port - 5 bit port id + * @addr - 16 bit address + * @data - 16 bit value + * returns 0 for success or -1 for failure + */ +int bdx_mdio_write(struct bdx_priv *priv, int device, int port, u16 addr, u16 data) +{ + u32 tmp_reg; + + /* Wait until MDIO is not busy */ + if (bdx_mdio_get(priv)== 0xFFFFFFFF) + { + return -1; + } + WRITE_REG(priv, regMDIO_CMD, ((device&0x1F)|((port&0x1F)<<5))); + WRITE_REG(priv, regMDIO_ADDR, (u32)addr); + if (bdx_mdio_get(priv)== 0xFFFFFFFF) { return -1; } + WRITE_REG(priv, regMDIO_DATA, (u32)data); + /* Read CMD_STAT until not busy */ + if ((tmp_reg = bdx_mdio_get(priv)) == 0xFFFFFFFF) + { + ERR("MDIO busy after write command\n"); + return -1; + } + if (GET_MDIO_RD_ERR(tmp_reg)) + { + ERR("MDIO error after write command\n"); + return -1; + } + return 0; + +} // bdx_mdio_write() + +//------------------------------------------------------------------------------------------------- + +static void setMDIOSpeed(struct bdx_priv *priv, u32 speed) +{ + int mdio_cfg; + + mdio_cfg = READ_REG(priv, regMDIO_CMD_STAT); + if(1==speed) + { + mdio_cfg = (0x7d<<7) | 0x08; // 1MHz + } + else + { + mdio_cfg = 0xA08; // 6MHz + } + mdio_cfg |= (1<<6); + WRITE_REG(priv, regMDIO_CMD_STAT, mdio_cfg); + msleep(100); + +} // setMDIOSpeed() + +//------------------------------------------------------------------------------------------------- + +static int bdx_mdio_look_for_phy(struct bdx_priv *priv, int port) +{ + int phy_id, i; + int rVal = -1; + + i=port; + setMDIOSpeed(priv, MDIO_SPEED_1MHZ); + + phy_id = bdx_mdio_read(priv, 1, i, 0x0002); // PHY_ID_HIGH + phy_id &=0xFFFF; + for (i = 0; i < 32; i++) + { + msleep(10); + DBG("LOOK FOR PHY: port=0x%x\n",i); + phy_id = bdx_mdio_read(priv, 1, i, 0x0002); // PHY_ID_HIGH + phy_id &=0xFFFF; + if (phy_id!=0xFFFF && phy_id!= 0) + { + rVal = i; + break; + } + } + if (rVal == -1) + { + ERR("PHY not found\n"); + } + + return rVal; + +} // bdx_mdio_look_for_phy() + +//------------------------------------------------------------------------------------------------- + +static int __init bdx_mdio_phy_search(struct bdx_priv *priv, int *port_t, enum PHY_TYPE *phy_t) +{ + int i, phy_id; + const char *s; + + if (bdx_force_no_phy_mode) + { + ERR("Forced NO PHY mode\n"); + i = 0; + } + else + { + i = bdx_mdio_look_for_phy(priv,*port_t); + if (i >= 0) // PHY found + { + *port_t = i; + phy_id = bdx_mdio_read(priv, 1, *port_t, 0x0002); // PHY_ID_HI + i = phy_id << 16; + phy_id = bdx_mdio_read(priv, 1, *port_t, 0x0003); // PHY_ID_LOW + phy_id &=0xFFFF; + i |= phy_id; + } + } + switch(i) + { + +#ifdef PHY_QT2025 + case 0x0043A400: + *phy_t=PHY_TYPE_QT2025; + s="QT2025 10Gbps SFP+"; + *phy_t = QT2025_register(priv); + break; +#endif + +#ifdef PHY_MV88X3120 + case 0x01405896: + s="MV88X3120 10Gbps 10GBase-T"; + *phy_t = MV88X3120_register(priv); + break; + +#endif + +#if (defined PHY_MV88X3310) || (defined PHY_MV88E2010) + case 0x02b09aa: + case 0x02b09ab: + if (priv->deviceId == 0x4027) + { + s="MV88X3310 (A0) 10Gbps 10GBase-T"; + *phy_t = MV88X3310_register(priv); + } + else if (priv->deviceId == 0x4527) + { + s="MV88E2010 (A0) 5Gbps 5GBase-T"; + *phy_t = MV88X3310_register(priv); + } + else if (priv->deviceId == 0x4010) + { + s="Dummy CX4"; + *phy_t = CX4_register(priv); + } + else + { + s = ""; + ERR("Unsupported device id/phy id 0x%x/0x%x !\n",priv->deviceId, i); + } + break; + +#endif + +#ifdef PHY_TLK10232 + case 0x40005100: + s="TLK10232 10Gbps SFP+"; + *phy_t = TLK10232_register(priv); + break; +#endif + +#ifdef PHY_AQR105 + case 0x03A1B462: //AQR105 B0 + case 0x03A1B463: //AQR105 B1 + case 0x03A1B4A3: //AQR105 B1 + + s="AQR105 10Gbps 10GBase-T"; + *phy_t = AQR105_register(priv); + break; +#endif + + default: + *phy_t=PHY_TYPE_CX4; + s=(const char*)&"Native 10Gbps CX4"; + *phy_t = CX4_register(priv); + break; + + + } // switch(i) + setMDIOSpeed(priv, priv->phy_ops.mdio_speed); + MSG("PHY detected on port %u ID=%X - %s\n", *port_t,i,s); + + return (PHY_TYPE_NA == *phy_t) ? -1 : 0; + +} // bdx_mdio_phy_search() + +//------------------------------------------------------------------------------------------------- + +static int bdx_mdio_reset(struct bdx_priv *priv, int port) +{ + int port_t = ++port; + enum PHY_TYPE phy; + + priv->phy_mdio_port=0xFF; + if(-1 == bdx_mdio_phy_search(priv, &port_t, &phy)) + { + return -1; + } + port = port_t; + priv->phy_mdio_port = port; + priv->phy_type = phy; + + return priv->phy_ops.mdio_reset(priv, port, phy); + +} // bdx_mdio_reset() + +/************************************************************************* + * Print Info * + *************************************************************************/ + +static void print_hw_id(struct bdx_priv *priv) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + u16 pci_link_status = 0; + u16 pci_ctrl = 0; + + pci_link_status = pci_read_config(tn40_priv->dev, PCI_LINK_STATUS_REG, 2); + pci_ctrl = pci_read_config(tn40_priv->dev, PCI_DEV_CTRL_REG, 2); + + MSG("srom 0x%x HWver %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n", + READ_REG(priv, SROM_VER), + READ_REG(priv, FPGA_VER) & 0xFFFF, + READ_REG(priv, FPGA_SEED), + GET_LINK_STATUS_LANES(pci_link_status), + GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl)); + +} // print_hw_id() + +//------------------------------------------------------------------------------------------------- + +static void print_fw_id(struct bdx_priv *priv) +{ + MSG("fw 0x%x\n", READ_REG(priv, FW_VER)); +} + +//------------------------------------------------------------------------------------------------- + +static void print_eth_id(struct bdx_priv *priv) +{ + MSG("%s, Port %d\n", priv->name, priv->port); +} + +//------------------------------------------------------------------------------------------------- + +inline void bdx_enable_interrupts(struct bdx_priv *priv) +{ + WRITE_REG(priv, regIMR, priv->isr_mask); +// EXIT; +} + +//------------------------------------------------------------------------------------------------- + +void inline bdx_disable_interrupts(struct bdx_priv *priv) +{ + WRITE_REG(priv, regIMR, 0); + EXIT; +} + +//------------------------------------------------------------------------------------------------- + +/* bdx_fifo_init + * Create TX/RX descriptor fifo for host-NIC communication. 1K extra space is + * allocated at the end of the fifo to simplify processing of descriptors that + * wraps around fifo's end. + * + * @priv - NIC private structure + * @f - Fifo to initialize + * @fsz_type - Fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB + * @reg_XXX - Offsets of registers relative to base address + * + * Returns 0 on success, negative value on failure + * + */ + +static int +bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type, + u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR, const char* fifo_name) +{ + int Status; + u16 memsz = FIFO_SIZE * (1 << fsz_type); + + memset(f, 0, sizeof(struct fifo)); + Status = tn40_alloc_dma(priv, memsz+FIFO_EXTRA_SPACE, &f->dma); + if (Status == 0) + { + f->va = (char *)f->dma.tn40_dmamap.va; + f->da = f->dma.tn40_dmamap.pa; + f->reg_CFG0 = reg_CFG0; + f->reg_CFG1 = reg_CFG1; + f->reg_RPTR = reg_RPTR; + f->reg_WPTR = reg_WPTR; + f->rptr = 0; + f->wptr = 0; + f->memsz = memsz; + f->size_mask = memsz - 1; + WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type)); + WRITE_REG(priv, reg_CFG1, H32_64(f->da)); + bus_dmamap_sync(f->dma.dma_tag, f->dma.tn40_dmamap.dma_map, BUS_DMASYNC_PREREAD); + //dbg_printFifo(priv, f, fifo_name); + } + else + { + ERR("fifo_init - tn40_alloc_dma FAILED %r\n", Status); + } + RET(Status); + +} // bdx_fifo_init() + +//------------------------------------------------------------------------------------------------- + +/* bdx_fifo_free - Free all resources used by fifo + * @priv - Nic private structure + * @f - Fifo to release + */ +static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f) +{ + ENTER; + + tn40_free_dma(&f->dma); + + EXIT; + +} // bdx_fifo_free() +//------------------------------------------------------------------------------------------------- + +int bdx_speed_set(struct bdx_priv *priv, u32 speed) +{ + int i; + u32 val; + //void __iomem * regs=priv->pBdxRegs; + //int port=priv->phy_mdio_port; + + DBG("speed %d\n", speed); + + switch(speed) + { + case SPEED_10000: + case SPEED_5000: + case SPEED_2500: + case SPEED_1000X: + case SPEED_100X: + DBG("link_speed %d\n", speed); + // BDX_MDIO_WRITE(priv, 1,0,0x2040); + WRITE_REG(priv, 0x1010, 0x217); /*ETHSD.REFCLK_CONF */ + WRITE_REG(priv, 0x104c, 0x4c); /*ETHSD.L0_RX_PCNT */ + WRITE_REG(priv, 0x1050, 0x4c); /*ETHSD.L1_RX_PCNT */ + WRITE_REG(priv, 0x1054, 0x4c); /*ETHSD.L2_RX_PCNT */ + WRITE_REG(priv, 0x1058, 0x4c); /*ETHSD.L3_RX_PCNT */ + WRITE_REG(priv, 0x102c, 0x434); /*ETHSD.L0_TX_PCNT */ + WRITE_REG(priv, 0x1030, 0x434); /*ETHSD.L1_TX_PCNT */ + WRITE_REG(priv, 0x1034, 0x434); /*ETHSD.L2_TX_PCNT */ + WRITE_REG(priv, 0x1038, 0x434); /*ETHSD.L3_TX_PCNT */ + WRITE_REG(priv, 0x6300, 0x0400); /*MAC.PCS_CTRL*/ + // udelay(50); val = READ_REG(priv,0x6300);ERR("MAC init:0x6300= 0x%x \n",val); + WRITE_REG(priv, 0x1018, 0x00); /*Mike2*/ + udelay(5); + WRITE_REG(priv, 0x1018, 0x04); /*Mike2*/ + udelay(5); + WRITE_REG(priv, 0x1018, 0x06); /*Mike2*/ + udelay(5); + //MikeFix1 + //L0: 0x103c , L1: 0x1040 , L2: 0x1044 , L3: 0x1048 =0x81644 + WRITE_REG(priv, 0x103c, 0x81644); /*ETHSD.L0_TX_DCNT */ + WRITE_REG(priv, 0x1040, 0x81644); /*ETHSD.L1_TX_DCNT */ + WRITE_REG(priv, 0x1044, 0x81644); /*ETHSD.L2_TX_DCNT */ + WRITE_REG(priv, 0x1048, 0x81644); /*ETHSD.L3_TX_DCNT */ + WRITE_REG(priv, 0x1014, 0x043); /*ETHSD.INIT_STAT*/ + for(i=1000; i; i--) + { + udelay(50); + val = READ_REG(priv,0x1014); /*ETHSD.INIT_STAT*/ + if(val & (1<<9)) + { + WRITE_REG(priv, 0x1014, 0x3); /*ETHSD.INIT_STAT*/ + val = READ_REG(priv,0x1014); /*ETHSD.INIT_STAT*/ + // ERR("MAC init:0x1014=0x%x i=%d\n",val,i); + break; + } + } + if(0==i) + { + ERR("MAC init timeout!\n"); + } + + WRITE_REG(priv, 0x6350, 0x0); /*MAC.PCS_IF_MODE*/ + WRITE_REG(priv, regCTRLST, 0xC13);//0x93//0x13 + WRITE_REG(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT*/ + for(i=40; i--;) + { + udelay(50); + } + WRITE_REG(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT*/ + //WRITE_REG(priv, 0x1104,0x24); // EEE_CTRL.EXT_PHY_LINK=1 (bit 2) + break; + + case SPEED_1000: + case SPEED_100: + //BDX_MDIO_WRITE(priv, 1,0,0x2000); // write 1.0 0x2000 # Force 1G + WRITE_REG(priv, 0x1010, 0x613); /*ETHSD.REFCLK_CONF */ + WRITE_REG(priv, 0x104c, 0x4d); /*ETHSD.L0_RX_PCNT */ + WRITE_REG(priv, 0x1050, 0x0); /*ETHSD.L1_RX_PCNT */ + WRITE_REG(priv, 0x1054, 0x0); /*ETHSD.L2_RX_PCNT */ + WRITE_REG(priv, 0x1058, 0x0); /*ETHSD.L3_RX_PCNT */ + WRITE_REG(priv, 0x102c, 0x35); /*ETHSD.L0_TX_PCNT */ + WRITE_REG(priv, 0x1030, 0x0); /*ETHSD.L1_TX_PCNT */ + WRITE_REG(priv, 0x1034, 0x0); /*ETHSD.L2_TX_PCNT */ + WRITE_REG(priv, 0x1038, 0x0); /*ETHSD.L3_TX_PCNT */ + WRITE_REG(priv, 0x6300, 0x01140); /*MAC.PCS_CTRL*/ + // udelay(50); val = READ_REG(priv,0x6300);ERR("MAC init:0x6300= 0x%x \n",val); + WRITE_REG(priv, 0x1014, 0x043); /*ETHSD.INIT_STAT*/ + for(i=1000; i; i--) + { + udelay(50); + val = READ_REG(priv,0x1014); /*ETHSD.INIT_STAT*/ + if(val & (1<<9)) + { + WRITE_REG(priv, 0x1014, 0x3); /*ETHSD.INIT_STAT*/ + val = READ_REG(priv,0x1014); /*ETHSD.INIT_STAT*/ + // ERR("MAC init:0x1014= 0x%x i=%d\n",val,i); + break; + } + } + if(0==i) + { + ERR("MAC init timeout!\n"); + } + WRITE_REG(priv, 0x6350, 0x2b); /*MAC.PCS_IF_MODE 1g*/ + WRITE_REG(priv, 0x6310, 0x9801); /*MAC.PCS_DEV_AB */ + //100 WRITE_REG(priv, 0x6350, 0x27); /*MAC.PCS_IF_MODE 100m*/ + //100 WRITE_REG(priv, 0x6310, 0x9501); /*MAC.PCS_DEV_AB */ + + WRITE_REG(priv, 0x6314, 0x1); /*MAC.PCS_PART_AB */ + WRITE_REG(priv, 0x6348, 0xc8); /*MAC.PCS_LINK_LO */ + WRITE_REG(priv, 0x634c, 0xc8); /*MAC.PCS_LINK_HI */ + udelay(50); + WRITE_REG(priv, regCTRLST, 0xC13);//0x93//0x13 + WRITE_REG(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT*/ + for(i=40; i--;) + { + udelay(50); + } + WRITE_REG(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT*/ + WRITE_REG(priv, 0x6300, 0x1140); /*MAC.PCS_CTRL*/ + // WRITE_REG(priv, 0x1104,0x24); // EEE_CTRL.EXT_PHY_LINK=1 (bit 2) + break; + + case 0: // Link down + // WRITE_REG(priv, 0x1010, 0x613); /*ETHSD.REFCLK_CONF */ + WRITE_REG(priv, 0x104c, 0x0); /*ETHSD.L0_RX_PCNT */ + WRITE_REG(priv, 0x1050, 0x0); /*ETHSD.L1_RX_PCNT */ + WRITE_REG(priv, 0x1054, 0x0); /*ETHSD.L2_RX_PCNT */ + WRITE_REG(priv, 0x1058, 0x0); /*ETHSD.L3_RX_PCNT */ + WRITE_REG(priv, 0x102c, 0x0); /*ETHSD.L0_TX_PCNT */ + WRITE_REG(priv, 0x1030, 0x0); /*ETHSD.L1_TX_PCNT */ + WRITE_REG(priv, 0x1034, 0x0); /*ETHSD.L2_TX_PCNT */ + WRITE_REG(priv, 0x1038, 0x0); /*ETHSD.L3_TX_PCNT */ + + // WRITE_REG(priv, 0x1104,0x20); // EEE_CTRL.EXT_PHY_LINK=0 (bit 2) + + WRITE_REG(priv, regCTRLST, 0x800); + WRITE_REG(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT*/ + for(i=40; i--;) + { + udelay(50); + } + WRITE_REG(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT*/ + break; + default: + ERR("%s Link speed was not identified yet (%d)\n", priv->name, speed); + speed=0; + break; + } + + return speed; + +} // bdx_speed_set() + +//------------------------------------------------------------------------------------------------- + +void bdx_speed_changed(struct bdx_priv *priv, u32 speed) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + + DBG("speed %d\n", speed); + speed = bdx_speed_set(priv, speed); + DBG("link_speed %d speed %d\n", priv->link_speed, speed); + if (priv->link_speed != speed) + { + priv->link_speed = speed; + DBG("Speed changed %d\n", priv->link_speed); + mtx_lock(&tn40_priv->mtx); + mtx_unlock(&tn40_priv->mtx); + } + +} // bdx_speed_changed() + +//------------------------------------------------------------------------------------------------- +/* + * bdx_link_changed - Notify the OS about hw link state. + * + * @bdx_priv - HW adapter structure + */ + +void bdx_link_changed(struct bdx_priv *priv) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + struct ifnet *ifp = tn40_priv->ifp; + + ENTER; + u32 link = priv->phy_ops.link_changed(priv);; + + if (!link) + { + if_link_state_change(ifp, LINK_STATE_DOWN); + DBG("Link Down\n"); + +#ifdef _EEE_ + if(NULL!=priv->phy_ops.reset_eee) + { + priv->phy_ops.reset_eee(priv); + } +#endif + } + else + { + if_link_state_change(ifp, LINK_STATE_UP); + MSG("%s Link Up %s\n", ifp->if_xname, (priv->link_speed == SPEED_10000) ? "10G" : + (priv->link_speed == SPEED_5000) ? "5G" : + (priv->link_speed == SPEED_2500) ? "2.5G" : + (priv->link_speed == SPEED_1000) || (priv->link_speed == SPEED_1000X) ? "1G" : + (priv->link_speed == SPEED_100) || (priv->link_speed == SPEED_100X) ? "100M" : + " "); + } + EXIT; +} // bdx_link_changed() + +//------------------------------------------------------------------------------------------------- + +/* bdx_isr - Interrupt Service Routine for Bordeaux NIC + */ +int bdx_isr(struct bdx_priv *priv) +{ + u32 isr = READ_REG(priv, regISR_MSK0); + + DBG("isr = 0x%x\n", isr); + + RET(isr); + +} // bdx_isr() + +//------------------------------------------------------------------------------------------------- + +static inline int bdx_tx_space(struct bdx_priv *priv) +{ + struct txd_fifo *f = &priv->txd_fifo0; + int fsize; + + f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR; + fsize = f->m.rptr - f->m.wptr; + if (fsize <= 0) + fsize = f->m.memsz + fsize; + return (fsize); + +} // bdx_tx_space() + +//------------------------------------------------------------------------------------------------- + +static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size) +{ + struct txd_fifo *f = &priv->txd_fifo0; + int i = f->m.memsz - f->m.wptr; + + if (size == 0) + return; + + if (i > size) + { + memcpy(f->m.va + f->m.wptr, data, size); + f->m.wptr += size; + } + else + { + memcpy(f->m.va + f->m.wptr, data, i); + f->m.wptr = size - i; + memcpy(f->m.va, (char *)data + i, f->m.wptr); + } + WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); + +} // bdx_tx_push_desc() + +//------------------------------------------------------------------------------------------------- + +static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size) +{ + int timer = 0; + ENTER; + + while (size > 0) + { + /* + * We subtract 8 because when the fifo is full rptr == wptr, which + * also means that fifo is empty, we can understand the difference, + * but could the HW do the same ??? :) + */ + int avail = bdx_tx_space(priv) - 8; + if (avail <= 0) + { + if (timer++ > 300) /* Prevent endless loop */ + { + DBG("timeout while writing desc to TxD fifo\n"); + break; + } + udelay(50); /* Give the HW a chance to clean the fifo */ + continue; + } + avail = MIN(avail, size); + DBG("about to push %d bytes starting %p size %d\n", avail, data, size); + bdx_tx_push_desc(priv, data, avail); + size -= avail; + data = (char *)data + avail; + } + + EXIT; + +} // bdx_tx_push_desc_safe() + +//------------------------------------------------------------------------------------------------- + +/* bdx_fw_load - Load the firmware to the NIC + * @priv - NIC private structure + * + * The firmware is loaded via TXD fifo, which needs be initialized first. + * The firmware needs to be loaded once per NIC and not per PCI device + * provided by NIC (a NIC can have multiple devices). So all the drivers use + * semaphore register to load the FW only once. + */ + +static int __init bdx_fw_load(struct bdx_priv *priv) +{ + int master, i; + int rVal = 0; + + ENTER; + master = READ_REG(priv, regINIT_SEMAPHORE); + if (!READ_REG(priv, regINIT_STATUS) && master) + { + DBG("Loading FW...\n"); + bdx_tx_push_desc_safe(priv, s_firmLoad, sizeof(s_firmLoad)); + mdelay(100); + } + for (i = 0; i < 200; i++) + { + if (READ_REG(priv, regINIT_STATUS)) + break; + mdelay(2); + } + if (master) + WRITE_REG(priv, regINIT_SEMAPHORE, 1); + + if (i == 200) + { + ERR("%s firmware loading failed\n", priv->name); + DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i =%d\n", + READ_REG(priv, regVPC), + READ_REG(priv, regVIC), READ_REG(priv, regINIT_STATUS), i); + rVal = -1; + } + else + { + DBG("%s firmware loading success\n", priv->name); + } + print_fw_id(priv); + RET(rVal); + +} // bdx_fw_load() + +//------------------------------------------------------------------------------------------------- + +static void bdx_restore_mac(struct bdx_priv *priv) +{ + u32 val; + + ENTER; + DBG("mac0 =%x mac1 =%x mac2 =%x\n", + READ_REG(priv, regUNC_MAC0_A), + READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A)); + + val = (priv->mac_address[0] << 8) | (priv->mac_address[1]); + WRITE_REG(priv, regUNC_MAC2_A, val); + val = (priv->mac_address[2] << 8) | (priv->mac_address[3]); + WRITE_REG(priv, regUNC_MAC1_A, val); + val = (priv->mac_address[4] << 8) | (priv->mac_address[5]); + WRITE_REG(priv, regUNC_MAC0_A, val); + /* More then IP MAC address */ + WRITE_REG(priv, regMAC_ADDR_0, (priv->mac_address[3] << 24) | (priv->mac_address[2] << 16) | (priv->mac_address[1] << 8) | (priv->mac_address[0])); + WRITE_REG(priv, regMAC_ADDR_1, (priv->mac_address[5] << 8) | (priv->mac_address[4])); + DBG("mac0 =%x mac1 =%x mac2 =%x\n", + READ_REG(priv, regUNC_MAC0_A), + READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A)); + EXIT; + +} // bdx_restore_mac() + +//------------------------------------------------------------------------------------------------- + +static void bdx_CX4_hw_start(struct bdx_priv *priv) +{ + int i; + u32 val; + + WRITE_REG(priv, 0x1010, 0x217); /*ETHSD.REFCLK_CONF */ + WRITE_REG(priv, 0x104c, 0x4c); /*ETHSD.L0_RX_PCNT */ + WRITE_REG(priv, 0x1050, 0x4c); /*ETHSD.L1_RX_PCNT */ + WRITE_REG(priv, 0x1054, 0x4c); /*ETHSD.L2_RX_PCNT */ + WRITE_REG(priv, 0x1058, 0x4c); /*ETHSD.L3_RX_PCNT */ + WRITE_REG(priv, 0x102c, 0x434); /*ETHSD.L0_TX_PCNT */ + WRITE_REG(priv, 0x1030, 0x434); /*ETHSD.L1_TX_PCNT */ + WRITE_REG(priv, 0x1034, 0x434); /*ETHSD.L2_TX_PCNT */ + WRITE_REG(priv, 0x1038, 0x434); /*ETHSD.L3_TX_PCNT */ + WRITE_REG(priv, 0x6300, 0x0400); /*MAC.PCS_CTRL*/ + // udelay(50); val = READ_REG(priv,0x6300);ERR("MAC init:0x6300= 0x%x \n",val); + WRITE_REG(priv, 0x1018, 0x00); /*Mike2*/ + udelay(5); + WRITE_REG(priv, 0x1018, 0x04); /*Mike2*/ + udelay(5); + WRITE_REG(priv, 0x1018, 0x06); /*Mike2*/ + udelay(5); + //MikeFix1 + //L0: 0x103c , L1: 0x1040 , L2: 0x1044 , L3: 0x1048 =0x81644 + WRITE_REG(priv, 0x103c, 0x81644); /*ETHSD.L0_TX_DCNT */ + WRITE_REG(priv, 0x1040, 0x81644); /*ETHSD.L1_TX_DCNT */ + WRITE_REG(priv, 0x1044, 0x81644); /*ETHSD.L2_TX_DCNT */ + WRITE_REG(priv, 0x1048, 0x81644); /*ETHSD.L3_TX_DCNT */ + WRITE_REG(priv, 0x1014, 0x043); /*ETHSD.INIT_STAT*/ + for(i=1000; i; i--) + { + udelay(50); + val = READ_REG(priv,0x1014); /*ETHSD.INIT_STAT*/ + if(val & (1<<9)) + { + WRITE_REG(priv, 0x1014, 0x3); /*ETHSD.INIT_STAT*/ + val = READ_REG(priv,0x1014); /*ETHSD.INIT_STAT*/ + // ERR("MAC init:0x1014=0x%x i=%d\n",val,i); + break; + } + } + if(0==i) + { + ERR("MAC init timeout!\n"); + } + WRITE_REG(priv, 0x6350, 0x0); /*MAC.PCS_IF_MODE*/ + WRITE_REG(priv, regCTRLST, 0xC13);//0x93//0x13 + WRITE_REG(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT*/ + for(i=40; i--;) + { + udelay(50); + } + WRITE_REG(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT*/ + //WRITE_REG(priv, 0x1104,0x24); // EEE_CTRL.EXT_PHY_LINK=1 (bit 2) + +} // bdx_CX4_hw_start + +//------------------------------------------------------------------------------------------------- + +/* bdx_hw_start - Initialize registers and starts HW's Rx and Tx engines + * @priv - NIC private structure + */ +static int bdx_hw_start(struct bdx_priv *priv) +{ + + ENTER; + + DBG("********** bdx_hw_start() ************\n"); + priv->link_speed=0; /* -1 */ + if(priv->phy_type==PHY_TYPE_CX4) + { + bdx_CX4_hw_start(priv); + } + else + { + DBG("********** bdx_hw_start() NOT CX4 ************\n"); + WRITE_REG(priv, regFRM_LENGTH, 0X3FE0); + WRITE_REG(priv, regGMAC_RXF_A, 0X10fd); + //MikeFix1 + //L0: 0x103c , L1: 0x1040 , L2: 0x1044 , L3: 0x1048 =0x81644 + WRITE_REG(priv, 0x103c, 0x81644); /*ETHSD.L0_TX_DCNT */ + WRITE_REG(priv, 0x1040, 0x81644); /*ETHSD.L1_TX_DCNT */ + WRITE_REG(priv, 0x1044, 0x81644); /*ETHSD.L2_TX_DCNT */ + WRITE_REG(priv, 0x1048, 0x81644); /*ETHSD.L3_TX_DCNT */ + WRITE_REG(priv, regRX_FIFO_SECTION, 0x10); + WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010); + WRITE_REG(priv, regRX_FULLNESS, 0); + WRITE_REG(priv, regTX_FULLNESS, 0); + } + WRITE_REG(priv, regVGLB, 0); + WRITE_REG(priv, regMAX_FRAME_A, priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL); + + DBG("RDINTCM =%08x\n", priv->rdintcm); /*NOTE: test script uses this */ + WRITE_REG(priv, regRDINTCM0, priv->rdintcm); + WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */ + + DBG("TDINTCM =%08x\n", priv->tdintcm); /*NOTE: test script uses this */ + WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */ + + /* Enable timer interrupt once in 2 secs. */ + /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */ + bdx_restore_mac(priv); + /* Pause frame */ + WRITE_REG(priv, 0x12E0, 0x28); + WRITE_REG(priv, regPAUSE_QUANT, 0xFFFF); + WRITE_REG(priv, 0x6064, 0xF); + + WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN | GMAC_RX_FILTER_TXFC | GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB); + + // bdx_setAffinity(priv->pdev->irq); + bdx_link_changed(priv); + bdx_enable_interrupts(priv); + + RET(0); + +} // bdx_hw_start() + +//------------------------------------------------------------------------------------------------- + +static void bdx_hw_stop(struct bdx_priv *priv) +{ + ENTER; + + if ((priv->state & BDX_STATE_HW_STOPPED) == 0) + { + priv->state |= BDX_STATE_HW_STOPPED; + bdx_disable_interrupts(priv); + } + + EXIT; + +} // bdx_hw_stop() + +//------------------------------------------------------------------------------------------------- + +static int bdx_hw_reset(struct bdx_priv *priv) +{ + u32 val, i; + ENTER; + + if (priv->port == 0) + { + /* Reset sequences: read, write 1, read, write 0 */ + val = READ_REG(priv, regCLKPLL); + WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8); + udelay(50); + val = READ_REG(priv, regCLKPLL); + WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST); + } + /* Check that the PLLs are locked and reset ended */ + for (i = 0; i < 70; i++, mdelay(10)) + { + if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) + { + udelay(50); + /* Do any PCI-E read transaction */ + READ_REG(priv, regRXD_CFG0_0); + return 0; + + } + } + ERR("HW reset failed\n"); + + RET(1); /* Failure */ + +} // bdx_hw_reset() + +//------------------------------------------------------------------------------------------------- + +static int bdx_sw_reset(struct bdx_priv *priv) +{ + int i; + + ENTER; + /* 1. load MAC (obsolete) */ + /* 2. disable Rx (and Tx) */ + WRITE_REG(priv, regGMAC_RXF_A, 0); + mdelay(100); + /* 3. Disable port */ + WRITE_REG(priv, regDIS_PORT, 1); + /* 4. Disable queue */ + WRITE_REG(priv, regDIS_QU, 1); + /* 5. Wait until hw is disabled */ + for (i = 0; i < 50; i++) + { + if (READ_REG(priv, regRST_PORT) & 1) + break; + mdelay(10); + } + if (i == 50) + { + ERR("%s SW reset timeout. continuing anyway\n", priv->name); + } + /* 6. Disable interrupts */ + WRITE_REG(priv, regRDINTCM0, 0); + WRITE_REG(priv, regTDINTCM0, 0); + WRITE_REG(priv, regIMR, 0); + READ_REG(priv, regISR); + + /* 7. Reset queue */ + WRITE_REG(priv, regRST_QU, 1); + /* 8. Reset port */ + WRITE_REG(priv, regRST_PORT, 1); + /* 9. Zero all read and write pointers */ + //for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) + // DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR); + for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) + WRITE_REG(priv, i, 0); + /* 10. Unset port disable */ + WRITE_REG(priv, regDIS_PORT, 0); + /* 11. Unset queue disable */ + WRITE_REG(priv, regDIS_QU, 0); + /* 12. Unset queue reset */ + WRITE_REG(priv, regRST_QU, 0); + /* 13. Unset port reset */ + WRITE_REG(priv, regRST_PORT, 0); + /* 14. Enable Rx */ + /* Skipped. will be done later */ + /* 15. Save MAC (obsolete) */ + //for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) + //{ + // DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR); + //} + + RET(0); + +} // bdx_sw_reset() + +//------------------------------------------------------------------------------------------------- + +/* bdx_reset - Perform the right type of reset depending on hw type */ +static int bdx_reset(struct bdx_priv *priv) +{ + ENTER; + // RET((priv->pdev->device == 0x4010) ? bdx_hw_reset(priv) : bdx_sw_reset(priv)); + RET(bdx_hw_reset(priv)); + +} // bdx_reset() + +//------------------------------------------------------------------------------------------------- + +static int bdx_start(struct bdx_priv *priv, int bLoadFw) +{ + int rc = 0; + + if ((priv->state & BDX_STATE_STARTED) == 0) + { + priv->state |= BDX_STATE_STARTED; + do + { + rc = -1; + if (bdx_tx_init(priv)) + { + break; + } + if (bdx_rx_init(priv)) + { + break; + } + bdx_rx_alloc_buffers(priv); + if (bLoadFw && bdx_fw_load(priv)) + { + break; + } + bdx_init_rss(priv); + rc = 0; + } while(0); + } + if (rc == 0) + { + if (priv->state & BDX_STATE_OPEN) + { + rc = bdx_hw_start(priv); + } + } + + return rc; + +} // bdx_start() + +//------------------------------------------------------------------------------------------------- + +static void bdx_stop(struct bdx_priv *priv) +{ + if (priv->state & BDX_STATE_STARTED) + { + priv->state &= ~BDX_STATE_STARTED; + bdx_hw_stop(priv); + bdx_sw_reset(priv); + bdx_rx_free(priv); + bdx_tx_free(priv); + } +} // bdx_stop() + +//------------------------------------------------------------------------------------------------- + +int bdx_close(struct bdx_priv *priv) +{ + ENTER; + bdx_stop(priv); + priv->state &= ~BDX_STATE_OPEN; + + RET(0); + +} // bdx_close() + +//------------------------------------------------------------------------------------------------- + +int bdx_open(struct bdx_priv *priv) +{ + int rc = 0; + + ENTER; + if ((priv->state & BDX_STATE_OPEN) == 0) + { + priv->state |= BDX_STATE_OPEN; + bdx_sw_reset(priv); + + if ((rc = bdx_start(priv, NO_FW_LOAD)) != 0) + { + bdx_close(priv); + } + } + RET(rc); + +} // bdx_open() + +//------------------------------------------------------------------------------------------------- + +#ifdef TN40_BIG_ENDIAN +static void __init bdx_firmware_endianess(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(s_firmLoad); i++) + { + s_firmLoad[i] = CPU_CHIP_SWAP32(s_firmLoad[i]); + } +} +#endif + +//------------------------------------------------------------------------------------------------- + +void bdx_vlan_rx_vid(struct bdx_priv *priv, uint16_t vid, int enable) +{ + u32 reg, bit, val; + + ENTER; + DBG("vid =%d value =%d\n", (int)vid, enable); + if (unlikely(vid >= 4096)) + { + ERR("invalid VID: %u (> 4096)\n", vid); + RET(); + } + reg = regVLAN_0 + (vid / 32) * 4; + bit = 1 << vid % 32; + val = READ_REG(priv, reg); + DBG("reg =%x, val =%x, bit =%d\n", reg, val, bit); + if (enable) + val |= bit; + else + val &= ~bit; + DBG("new val %x\n", val); + WRITE_REG(priv, reg, val); + RET(); + +} // bdx_vlan_rx_vid() + +//------------------------------------------------------------------------------------------------- +/** + * bdx_change_mtu - Change the Maximum Transfer Unit + * + * @netdev - Network interface device structure + * @new_mtu - New value for maximum frame size + * + * Returns 0 on success, negative error code on failure + */ +int bdx_change_mtu(struct bdx_priv *priv, int new_mtu) +{ + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + + ENTER; + + if (new_mtu == priv->mtu) + { + RET(0); + } + /* enforce minimum frame size */ + if (new_mtu < ETHER_MIN_MTU) + { + ERR("%s mtu %d is less then minimal %d\n", priv->name, new_mtu, ETHER_MIN_MTU); + RET(-1); + } + else if (new_mtu > BDX_MAX_MTU) + { + ERR("%s mtu %d is greater then max mtu %d\n", priv->name, new_mtu, BDX_MAX_MTU); + RET(-1); + } + priv->mtu = new_mtu; + mtx_lock(&tn40_priv->tx_lock); + bdx_close(priv); + bdx_open (priv); + mtx_unlock(&tn40_priv->tx_lock); + + RET(0); + +} // bdx_change_mtu() + +//------------------------------------------------------------------------------------------------- + +int bdx_set_mac(struct bdx_priv *priv, u8 *addr) +{ + + ENTER; + + memcpy(priv->mac_address, addr, ETHER_ADDR_LEN); + bdx_restore_mac(priv); + + RET(0); + +} // bdx_set_mac() + +//------------------------------------------------------------------------------------------------- + +static int bdx_read_mac(struct bdx_priv *priv) +{ + u16 mac_address[3], i; + ENTER; + + mac_address[2] = READ_REG(priv, regUNC_MAC0_A); + mac_address[2] = READ_REG(priv, regUNC_MAC0_A); + mac_address[1] = READ_REG(priv, regUNC_MAC1_A); + mac_address[1] = READ_REG(priv, regUNC_MAC1_A); + mac_address[0] = READ_REG(priv, regUNC_MAC2_A); + mac_address[0] = READ_REG(priv, regUNC_MAC2_A); + for (i = 0; i < 3; i++) + { + priv->mac_address[i * 2 + 1] = (u8)(mac_address[i]); + priv->mac_address[i * 2] = (u8)(mac_address[i] >> 8); + } + DBG("Mac address : %02x:%02x:%02x:%02x:%02x:%02x\n", priv->mac_address[0],priv->mac_address[1],priv->mac_address[2], + priv->mac_address[3], priv->mac_address[4], priv->mac_address[5]); + RET(0); + +} // bdx_read_mac() + +//------------------------------------------------------------------------------------------------- + +static int bdx_range_check(struct bdx_priv *priv, u32 offset) +{ + return ((offset > (u32) (BDX_REGS_SIZE)) ? -EINVAL : 0); +} + +//------------------------------------------------------------------------------------------------- + +int bdx_ioctl_priv(struct bdx_priv *priv, struct ifreq *ifr) +{ + tn40_ioctl_t tn40_ioctl; + int error; + u16 dev,addr; + + ENTER; + error = copyin(ifr_data_get_ptr(ifr), &tn40_ioctl, sizeof(tn40_ioctl)); + if (error) + { + ERR("cant copy from user\n"); + RET(error); + } + DBG("%d 0x%x 0x%x 0x%p\n", tn40_ioctl.data[0], tn40_ioctl.data[1], tn40_ioctl.data[2], tn40_ioctl.buf); + + switch (tn40_ioctl.data[0]) + { + case OP_INFO: + switch(tn40_ioctl.data[1]) + { + case 1: + tn40_ioctl.data[2] = 1; + break; + case 2: + tn40_ioctl.data[2] = priv->phy_mdio_port; + break; + default: + tn40_ioctl.data[2] = 0xFFFFFFFF; + break; + } + error = copyout(&tn40_ioctl, ifr_data_get_ptr(ifr), sizeof(tn40_ioctl)); + if (error) + RET(error); + break; + + case OP_READ_REG: + error = bdx_range_check(priv, tn40_ioctl.data[1]); + if (error < 0) + return error; + tn40_ioctl.data[2] = READ_REG(priv, tn40_ioctl.data[1]); + DBG("read_reg(0x%x)=0x%x (dec %d)\n", tn40_ioctl.data[1], tn40_ioctl.data[2], + tn40_ioctl.data[2]); + error = copyout(&tn40_ioctl, ifr_data_get_ptr(ifr), sizeof(tn40_ioctl)); + if (error) + RET(error); + break; + + case OP_WRITE_REG: + error = bdx_range_check(priv, tn40_ioctl.data[1]); + if (error < 0) + return error; + WRITE_REG(priv, tn40_ioctl.data[1], tn40_ioctl.data[2]); + break; + + case OP_MDIO_READ: + if(priv->phy_mdio_port==0xFF) return -EINVAL; + dev=(u16)(0xFFFF&(tn40_ioctl.data[1]>>16)); + addr=(u16)(0xFFFF&tn40_ioctl.data[1]); + tn40_ioctl.data[2] =0xFFFF&PHY_MDIO_READ(priv,dev,addr); + error = copyout(&tn40_ioctl, ifr_data_get_ptr(ifr), sizeof(tn40_ioctl)); + if (error) + RET(error); + break; + + case OP_MDIO_WRITE: + if(priv->phy_mdio_port==0xFF) return -EINVAL; + dev=(u16)(0xFFFF&(tn40_ioctl.data[1]>>16)); + addr=(u16)(0xFFFF&tn40_ioctl.data[1]); + PHY_MDIO_WRITE(priv,dev,addr,(u16)(tn40_ioctl.data[2])); + break; + +#ifdef _TRACE_LOG_ + case op_TRACE_ON: + traceOn(); + break; + + case op_TRACE_OFF: + traceOff(); + break; + + case op_TRACE_ONCE: + traceOnce(); + break; + + case op_TRACE_PRINT: + tracePrint(); + break; +#endif +#ifdef TN40_MEMLOG + case OP_MEMLOG_DMESG: + memLogDmesg(); + break; + + case OP_MEMLOG_PRINT: + { + char *buf; + uint buf_size; + unsigned long bytes; + + error = 0; + buf = memLogGetLine(&buf_size); + if (buf != NULL) + { + + tn40_ioctl.data[2] = min(tn40_ioctl.data[1], buf_size); + bytes = copyout(&tn40_ioctl, ifr_data_get_ptr(ifr), sizeof(tn40_ioctl)); + bytes = copyout(&tn40_ioctl.buf, buf, tn40_ioctl.data[2]); + DBG("copyout %p %u return %lu\n", tn40_ioctl.buf, tn40_ioctl.data[2], bytes); + } + else + { + DBG("=================== EOF =================\n"); + error = -EIO; + } + RET(error); + break; + } +#endif +#ifdef TN40_DEBUG + case OP_DBG: + switch (tn40_ioctl.data[1]) + { +#ifdef _DRIVER_RESUME_DBG + + pm_message_t pmMsg = {0}; + + case DBG_SUSPEND: + bdx_suspend(priv->pdev, pmMsg); + bdx_resume(priv->pdev); + break; + + case DBG_RESUME: + bdx_resume(priv->pdev); + break; +#endif + case DBG_START_DBG: + DBG_ON; + break; + + case DBG_STOP_DBG: + DBG_OFF; + break; +#ifdef TN40_COUNTERS + case DBG_PRINT_COUNTERS: + bdx_printCounters(priv); + break; + + case DBG_CLEAR_COUNTERS: + bdx_clearCounters(priv); + break; + +#endif + +#ifdef RX_REUSE_PAGES + case DBG_PRINT_PAGE_TABLE: + dbg_printRxPageTable(priv); + break; +#endif + default: + dbg_printIoctl(); + break; + + } + break; +#endif // TN40_DEBUG + + default: + RET(-EOPNOTSUPP); + } + + return 0; + +} // bdx_ioctl_priv() + + +/************************************************************************* + * Rx DB * + *************************************************************************/ + +static void bdx_rxdb_destroy(struct rxdb *db) +{ + ENTER; + if (db->pkt.tn40_dmamap.va != NULL) + { + tn40_free_dma(&db->pkt); + } + if (db) + { + free((void *)db, M_TN40); + } + EXIT; + +} // bdx_rxdb_destroy() + +//------------------------------------------------------------------------------------------------- + +static struct rxdb *bdx_rxdb_create(struct bdx_priv *priv, bool bAlloc) +{ + struct rxdb *db; + tn40_dma_t pkt; + int i; + + int rxfSize = priv->rxf_fifo0.m.memsz; + u16 pktSize = priv->rxf_fifo0.m.pktsz; + int nelem = rxfSize / sizeof(struct rxf_desc); + size_t size = sizeof(struct rxdb) + (nelem * sizeof(int)) + (nelem * sizeof(struct rx_map)); + DBG("bdx_rxdb_create() nelem %d\n", nelem); + if (bAlloc) + { + db = malloc(size, M_TN40, M_NOWAIT); + if (db) + { + bzero((void *)db, size); + if (tn40_alloc_dma(priv, priv->rxf_fifo0.m.pktsz, &pkt) != 0) + { + ERR("bdx_rxdb_create() failed to alloc %d\n", (int)pktSize); + bdx_rxdb_destroy(db); + db = NULL; + } + } + } + else + { + db = priv->rxdb0; + pkt = db->pkt; + } + if (likely(db != NULL)) + { + db->stack = (int *)(db + 1); + db->elems = (struct rx_map *)(db->stack + nelem); + db->nelem = nelem; + db->top = nelem; + db->rxfSize = rxfSize; + db->rxfAvail = rxfSize; + db->pkt = pkt; + for (i = 0; i < nelem; i++) + { + db->stack[i] = nelem - i - 1; /* To make the first alloc close to db struct */ + } + } + + return db; + +} // bdx_rxdb_create() + +//------------------------------------------------------------------------------------------------- + +static inline int bdx_rxdb_alloc_elem(struct rxdb *db, int rxfdSize) +{ + BDX_ASSERT(db->top <= 0); + + db->rxfAvail -= rxfdSize; + + BDX_ASSERT(db->rxfAvail < 0); + + return db->stack[--(db->top)]; + +} // bdx_rxdb_alloc_elem() + +//------------------------------------------------------------------------------------------------- + +static inline void bdx_rxdb_free_elem(struct rxdb *db, unsigned n, int rxfdSize) +{ + BDX_ASSERT((n >= (unsigned)db->nelem)); + + db->rxfAvail += rxfdSize; + + BDX_ASSERT((db->rxfAvail > db->rxfSize)); + + db->stack[(db->top)++] = n; + +} // bdx_rxdb_free_elem() + +//------------------------------------------------------------------------------------------------- + +static inline void *bdx_rxdb_addr_elem(struct rxdb *db, unsigned n) +{ + BDX_ASSERT((n >= (unsigned)db->nelem)); + + return db->elems + n; + +} // bdx_rxdb_addr_elem() + +//------------------------------------------------------------------------------------------------- +/* +static inline int bdx_rxdb_nelem(struct rxdb *db) +{ + return db->nelem; + +} // bdx_rxdb_nelem() +*/ +//------------------------------------------------------------------------------------------------- + +static inline int bdx_rxdb_available(struct rxdb *db) +{ + return db->top; + +} // bdx_rxdb_available() + +/************************************************************************* + * Rx Init * + *************************************************************************/ + +/* bdx_rx_init - Initialize RX all related HW and SW resources + * @priv - NIC private structure + * + * Returns 0 on success, a negative value on failure + * + * bdx_rx_init creates rxf and rxd fifos, updates the relevant HW registers, + * preallocates skbs for rx. It assumes that Rx is disabled in HW funcs are + * grouped for better cache usage + * + * RxD fifo is smaller then RxF fifo by design. Upon high load, RxD will be + * filled and packets will be dropped by the NIC without getting into the host + * or generating interrupts. In this situation the host has no chance of + * processing all the packets. Dropping packets by the NIC is cheaper, since it + * takes 0 CPU cycles. + */ + +/* TBD: Ensure proper packet size */ + +static u16 bdx_rx_set_mbuf_size(u16 pktsz) +{ + u16 mBufSize = 0; + + if (pktsz <= MCLBYTES) + { + mBufSize = MCLBYTES; + } + else if (pktsz <= MJUMPAGESIZE) + { + mBufSize = MJUMPAGESIZE; + } + else if (pktsz <= MJUM9BYTES) + { + mBufSize = MJUM9BYTES; + } + else if (pktsz <= MJUM16BYTES) + { + mBufSize = MJUM16BYTES; + } + else + { + ERR("invalid MTU %d !\n", (int)pktsz); + } + + return mBufSize; + +} // bdx_rx_set_mbuf_size() + +//------------------------------------------------------------------------------------------------- + +int bdx_rx_init(struct bdx_priv *priv) +{ + int rVal = -1; + + ENTER; + do + { + if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size, + regRXD_CFG0_0, regRXD_CFG1_0, + regRXD_RPTR_0, regRXD_WPTR_0, (const char*)"RXD")) + { + break; + } + if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size, + regRXF_CFG0_0, regRXF_CFG1_0, + regRXF_RPTR_0, regRXF_WPTR_0, (const char*)"RXF")) + { + break; + } + priv->rxf_fifo0.m.pktsz = priv->mtu + VLAN_ETH_HLEN; + if ((priv->rx_buf_size = bdx_rx_set_mbuf_size(priv->rxf_fifo0.m.pktsz)) == 0) + { + break; + } + if (!(priv->rxdb0 = bdx_rxdb_create(priv, true))) + { + break; + } + rVal = tn40_dma_tag_create(priv, priv->rx_buf_size, priv->rx_buf_size, 1, &priv->rx_dma_tag); + if (rVal != 0) + { + ERR("tn40_dma_tag_create rx FAILED !\n"); + break; + } + + rVal = 0; + + } while(0); + + RET(rVal); + +} // bdx_rx_init() + +//------------------------------------------------------------------------------------------------- + +static void bdx_rx_free_buffers(struct bdx_priv *priv) +{ + struct rxdb *db = priv->rxdb0; + struct rx_map *dm; + u16 i; + + ENTER; + DBG("total = %d free = %d busy = %d\n", db->nelem, bdx_rxdb_available(db), db->nelem - bdx_rxdb_available(db)); + while (bdx_rxdb_available(db) > 0) + { + i = bdx_rxdb_alloc_elem(db, 0); + dm = (struct rx_map *)bdx_rxdb_addr_elem(db, i); + dm->mBuf = NULL; + } + for (i = 0; i < db->nelem; i++) + { + dm = (struct rx_map *)bdx_rxdb_addr_elem(db, i); + if (dm->mBuf) + { + m_free(dm->mBuf); + dm->mBuf = NULL; + } + bus_dmamap_destroy(priv->rx_dma_tag, dm->dma_map); + } + EXIT; + +} // bdx_rx_free_buffers() + +//------------------------------------------------------------------------------------------------- + +void bdx_rx_free(struct bdx_priv *priv) +{ + ENTER; + + if (priv->rxdb0) + { + bdx_rx_free_buffers(priv); + bdx_rxdb_destroy(priv->rxdb0); + priv->rxdb0 = NULL; + } + bdx_fifo_free(priv, &priv->rxf_fifo0.m); + bdx_fifo_free(priv, &priv->rxd_fifo0.m); + bus_dma_tag_destroy(priv->rx_dma_tag); + EXIT; + +} // bdx_rx_free() + +/************************************************************************* + * Rx Engine * + *************************************************************************/ + +//------------------------------------------------------------------------------------------------- + +static inline u16 tcpCheckSum(u16 *buf, u16 len, u16 *saddr, u16 *daddr, u16 proto) +{ + u32 sum; + u16 j = len; + + sum = 0; + while (j > 1) + { + sum += *buf++; + if (sum & 0x80000000) + { + sum = (sum & 0xFFFF) + (sum >> 16); + } + j -= 2; + } + if ( j & 1 ) + { + sum += *((u8 *)buf); + } + // Add the tcp pseudo-header + sum += *(saddr++); + sum += *saddr; + sum += *(daddr++); + sum += *daddr; + sum += htons(proto); + sum += htons(len); + // Fold 32-bit sum to 16 bits + while (sum >> 16) + { + sum = (sum & 0xFFFF) + (sum >> 16); + } + // One's complement of sum + + //return ( (u16)(~sum) ); + + return ( (u16)(sum) ); + +} // tcpCheckSum() + +//------------------------------------------------------------------------------------------------- + +#define PKT_ERR_LEN (70) + +static int bdx_rx_error(char *pkt, u32 rxd_err, u16 len) +{ + struct ether_header *eth = (struct ether_header *)pkt; + struct ip *iph = (struct ip *)(pkt + sizeof(struct ether_header) + ((eth->ether_type == htons(ETHERTYPE_VLAN)) ? VLAN_HLEN : 0)); + int rVal = 1; + + if (rxd_err == 0x8) // UDP checksum error + { + struct udphdr *udp = (struct udphdr *)((u8 *)iph + sizeof(struct ip)); + if (udp->uh_sum == 0) + { + DBG("false rxd_err = 0x%x\n", rxd_err); + rVal = 0; // Work around H/W false error indication + } + else if (len < PKT_ERR_LEN) + { + u16 udpSum; + udpSum = tcpCheckSum((u16 *)udp, htons(iph->ip_len) - (iph->ip_hl * sizeof(u32)), (u16 *)&iph->ip_src, (u16 *)&iph->ip_dst, IPPROTO_UDP); + if (udpSum == 0xFFFF) + { + DBG("false rxd_err = 0x%x\n", rxd_err); + rVal = 0; // Work around H/W false error indication + } + } + } + else if ((rxd_err == 0x10) && (len < PKT_ERR_LEN)) // TCP checksum error + { + u16 tcpSum; + struct tcphdr *tcp = (struct tcphdr *)((u8 *)iph + sizeof(struct ip)); + tcpSum = tcpCheckSum((u16 *)tcp, htons(iph->ip_len) - (iph->ip_hl * sizeof(u32)), (u16 *)&iph->ip_src, (u16 *)&iph->ip_dst, IPPROTO_TCP); + if (tcpSum == 0xFFFF) + { + DBG("false rxd_err = 0x%x\n", rxd_err); + rVal = 0; // Work around H/W false error indication + } + } + + return rVal; + +} // bdx_rx_error() + +//------------------------------------------------------------------------------------------------- + +static inline int bdx_rx_map_mbuf(struct bdx_priv *priv, struct mbuf *mBuf, struct rx_map *dm, struct rxf_desc *rxfd) +{ + int nsegs; + bus_dma_segment_t seg[1]; + int err = 0; + struct pbl *pbl = &rxfd->pbl[0]; + + ENTER; + + do + { + if (dm->dma_map == NULL) + { + DBG("Creating DMA map\n"); + err = bus_dmamap_create(priv->rx_dma_tag, 0, &dm->dma_map); + if (err != 0) + { + ERR("bdx_rx_map_mbuf() create FAILED !\n"); + } + } + else + { + DBG("Unloading DMA map\n"); + bus_dmamap_unload(priv->rx_dma_tag, dm->dma_map); + } + err = bus_dmamap_load_mbuf_sg(priv->rx_dma_tag, dm->dma_map, mBuf, seg, &nsegs, BUS_DMA_NOWAIT); + if (err != 0) + { + ERR("bdx_rx_map_mbuf() load FAILED !\n"); + break; + } + bus_dmamap_sync(priv->rx_dma_tag, dm->dma_map, BUS_DMASYNC_PREREAD); + pbl->len = (u32)CPU_CHIP_SWAP32(seg[0].ds_len); + pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(seg[0].ds_addr)); + pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(seg[0].ds_addr)); + DBG("m %p dmap %p nsegs %d\n", mBuf, dm->dma_map, nsegs); + dbg_printPBL(pbl); + + } while(0); + RET(err); + +} // bdx_rx_map_mbuf() + +//------------------------------------------------------------------------------------------------- + +int bdx_rx_alloc_buffers(struct bdx_priv *priv) +{ +// struct mbuf *mBuf, *mPrev, **m; +// int j; + struct mbuf *mBuf; + struct rxf_desc *rxfd; + struct rx_map *dm; + int delta; + int rxfdSize; + struct rxdb *db = priv->rxdb0; + struct rxf_fifo *f = &priv->rxf_fifo0; + int nBufs = (f->m.pktsz + f->m.pktsz -1) / priv->rx_buf_size;; + int nFrags = nBufs -1; + int idx = 0; + int nAllocs = 0; + + ENTER; + DBG("bdx_rx_alloc_buffers() nelem %d pktsz %d avail %d first idx %d\n", db->nelem, f->m.pktsz, db->rxfAvail, db->stack[db->top-1]); + while (db->rxfAvail > sizeof(struct rxf_desc)) + { +/* + mBuf = NULL; + m = &mBuf; + for (j = 0; j < nBufs; j++) + { + *m = m_getcl(M_NOWAIT, MT_DATA, M_EXT); + //DBG("m %p\n", *m); + if (*m == NULL) + { + if (mBuf != NULL) + { + m_freem(mBuf); + mBuf = NULL; + } + break; + } + (*m)->m_len = priv->rx_buf_size; + mPrev = *m; + m = &((*m)->m_next); + } +*/ + mBuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,priv->rx_buf_size); + if (mBuf == NULL) + { + break; + } +// mBuf->m_pkthdr.len = priv->rx_buf_size * nBufs; +// mBuf->m_flags |= M_PKTHDR; +// mPrev->m_flags |= M_EOR; + mBuf->m_len = mBuf->m_pkthdr.len = priv->rx_buf_size; + rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); + rxfdSize = rxd_sizes[nFrags].bytes; + if ((rxfdSize > db->rxfAvail) || (nFrags < 0)) + { + ERR("bdx_rx_alloc_buffers() no room: rxfdSize %d > rxfAvail %d , nFrags %d\n", rxfdSize, db->rxfAvail, nFrags); + m_freem(mBuf); + break; + } + idx = bdx_rxdb_alloc_elem(db, rxfdSize); + dm = (struct rx_map *)bdx_rxdb_addr_elem(db, idx); + if (bdx_rx_map_mbuf(priv, mBuf, dm, rxfd) != 0) + { + bdx_rxdb_free_elem(db, idx, rxfdSize); + m_freem(mBuf); + break; + } + dbg_printMbuf(mBuf,__LINE__); + dm->mBuf = mBuf; + rxfd->info = CPU_CHIP_SWAP32(0x10000 | rxd_sizes[nFrags].qwords); /* INFO =1 */ + rxfd->va_lo = idx; + rxfd->va_hi = rxfdSize; + DBG("idx %d nFrags %d info 0x%x\n", idx, nFrags, rxfd->info); + if ((idx % 200) == 0) + { + DBG("idx %d nFrags %d info 0x%x\n", idx, nFrags, rxfd->info); + dbg_print_rxfd(rxfd); + } + f->m.wptr += rxfdSize; + delta = f->m.wptr - f->m.memsz; + if (unlikely(delta >= 0)) + { + f->m.wptr = delta; + if (delta > 0) + { + memcpy(f->m.va, f->m.va + f->m.memsz, delta); + DBG("Wrapped descriptor %d\n", idx); + } + } + nAllocs += 1; + } + WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); + DBG("bdx_rx_alloc_buffers() allocated %u last idx %d avail %d rxfd size %d wptr %d\n", nAllocs, idx, db->rxfAvail, rxd_sizes[nFrags].bytes, (int)f->m.wptr); + //DBG("WRITE_REG 0x%04x f->m.reg_WPTR 0x%x\n", f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); + //DBG("READ_REG 0x%04x f->m.reg_RPTR=0x%x\n", f->m.reg_RPTR, READ_REG(priv, f->m.reg_RPTR)); + //DBG("READ_REG 0x%04x f->m.reg_WPTR=0x%x\n", f->m.reg_WPTR, READ_REG(priv, f->m.reg_WPTR)); + //dbg_printFifo(priv, &priv->rxf_fifo0.m, (char *)"RXF"); + + RET(nAllocs); + +} // bdx_rx_alloc_buffers() + +//------------------------------------------------------------------------------------------------- + +void bdx_rx_receive(struct bdx_priv *priv) +{ + struct rxd_desc *rxdd; + struct rx_map *dm; + struct mbuf *mBuf; + int tmp_len, size; + u32 rxd_val1, rxd_err, pktType; + u16 len; + u16 rxd_vlan; + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + struct rxd_fifo *f = &priv->rxd_fifo0; + struct rxdb *db = priv->rxdb0; + u32 nRcv = 0; + + ENTER; + + bus_dmamap_sync(f->m.dma.dma_tag, f->m.dma.tn40_dmamap.dma_map, BUS_DMASYNC_POSTREAD); + f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR; + size = f->m.wptr - f->m.rptr; + if (size < 0) + { + size += f->m.memsz; /* Size is negative :-) */ + } + DBG("<-- bdx_rx_receive() size %d\n", size); + while (size > 0) + { + rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr); + /* + * Note: We have a chicken and egg problem here. If the + * descriptor is wrapped we first need to copy the tail + * of the descriptor to the end of the buffer before + * extracting values from the descriptor. However in + * order to know if the descriptor is wrapped we need to + * obtain the length of the descriptor from (the + * wrapped) descriptor. Luckily the length is the first + * word of the descriptor. Descriptor lengths are + * multiples of 8 bytes so in case of a wrapped + * descriptor the first 8 bytes guaranteed to appear + * before the end of the buffer. We first obtain the + * length, we then copy the rest of the descriptor if + * needed and then extract the rest of the values from + * the descriptor. + * + * Do not change the order of operations as it will + * break the code!!! + */ + rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1); + tmp_len = GET_RXD_BC(rxd_val1) << 3; + pktType = GET_RXD_PKT_ID(rxd_val1); + BDX_ASSERT(tmp_len <= 0); + size -= tmp_len; + /* CHECK FOR A PARTIALLY ARRIVED DESCRIPTOR */ + if (size < 0) + { + DBG("<-- bdx_rx_receive() partial descriptor\n"); + break; + } + /* HAVE WE REACHED THE END OF THE QUEUE? */ + f->m.rptr += tmp_len; + tmp_len = f->m.rptr - f->m.memsz; + if (unlikely(tmp_len >= 0)) + { + f->m.rptr = tmp_len; + if (tmp_len > 0) + { + /* COPY PARTIAL DESCRIPTOR TO THE END OF THE QUEUE */ + DBG("wrapped desc rptr=%d tmp_len=%d\n", f->m.rptr, tmp_len); + memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len); + } + } + dm = (struct rx_map *)bdx_rxdb_addr_elem(db, rxdd->va_lo); + len = CPU_CHIP_SWAP16(rxdd->len); + rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan); + mBuf = dm->mBuf; + //DBG("mBuf %p dmap %p\n", mBuf, dm->dma_map); + bus_dmamap_sync(priv->rx_dma_tag, dm->dma_map, BUS_DMASYNC_POSTREAD); + dbg_print_rxdd(rxdd, rxd_val1, len, rxd_vlan); + nRcv += 1; + /* CHECK FOR ERRORS */ + if (unlikely((rxd_err = GET_RXD_ERR(rxd_val1)))) + { + int bErr = 1; + char *pkt = NULL; + if ( ( !( rxd_err & 0x4)) && // NOT CRC error + ( + ((rxd_err == 0x8) && (pktType == 2)) || // UDP checksum error + ((rxd_err == 0x10) && (len < PKT_ERR_LEN) && (pktType == 1)) // TCP checksum error + ) + ) + { + pkt = malloc(len, M_TN40, M_NOWAIT); + DBG("rxd_err 0x%x dm->mBu %p len %d pkt %p\n", rxd_err, mBuf, len, pkt); + if (pkt) + { + m_copydata (mBuf, 0, len, pkt); + bErr = bdx_rx_error(pkt, rxd_err, len); + } + } + if (bErr) + { + ERR("rxd_err 0x%x len %d\n", rxd_err, (int)len); +//#define DUMP_RX_ERRORS +#ifdef DUMP_RX_ERRORS + dbg_printRxPkt(mBuf, pkt, len); + // Debug code : dump packet and do not drop +#else + //priv->net_stats.rx_errors++; + // Drop bad packets + bdx_rxdb_free_elem(db, rxdd->va_lo, rxdd->va_hi); + m_freem(mBuf); + if (pkt != NULL) + { + free((void *)pkt, M_TN40); + } + continue; +#endif + } + } + /* PROCESS PACKET */ +/* + if (len <= 128) + { + struct mbuf *m = m_gethdr(M_NOWAIT, MT_DATA); + if (m != NULL) + { + memcpy(m->m_data, mBuf->m_data, len); + mBuf = m; + m_freem(mBuf); + } + } +*/ + mBuf->m_len = mBuf->m_pkthdr.len = len; + mBuf->m_pkthdr.rcvif = tn40_priv->ifp; + // mBuf->m_pkthdr.flowid = 0; + // M_HASHTYPE_SET(mBuf, M_HASHTYPE_OPAQUE); + if (GET_RXD_VTAG(rxd_val1))/* Vlan case */ + { + mBuf->m_pkthdr.ether_vtag = GET_RXD_VLAN_TCI(rxd_vlan); + mBuf->m_flags |= M_VLANTAG; + } + DBG("<-- bdx_rx_receive() mbuf %p len %u rxfdSize %d type %d\n", mBuf, (u32)len, rxdd->va_hi, pktType); + tn40_checksum_results(mBuf, pktType); + dbg_printMbuf(mBuf, __LINE__); + dbg_printRxPkt(mBuf, NULL, len); + (*tn40_priv->ifp->if_input)(tn40_priv->ifp, mBuf); + DBG("<-- bdx_rx_receive rxAvail %d\n", db->rxfAvail); + bdx_rxdb_free_elem(db, rxdd->va_lo, rxdd->va_hi); + } + /* CLEANUP */ + WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); + bus_dmamap_sync(f->m.dma.dma_tag, f->m.dma.tn40_dmamap.dma_map, BUS_DMASYNC_PREWRITE); + bdx_rx_alloc_buffers(priv); + DBG("bdx_rx_receive() received %u\n", nRcv); + EXIT; + +} // bdx_rx_receive() + +/************************************************************************* + * Tx DB * + *************************************************************************/ +/* __bdx_tx_ptr_next - A helper function, increment read/write pointer + wrap. + * + * @d - Tx data base + * @ptr - Read or write pointer + */ +static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr) +{ + BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */ + BDX_ASSERT(*pptr != db->rptr && /* expect either read */ + *pptr != db->wptr); /* or write pointer */ + BDX_ASSERT(*pptr < db->start || /* pointer has to be */ + *pptr >= db->end); /* in range */ + + ++*pptr; + if (unlikely(*pptr == db->end)) + *pptr = db->start; +} + +//------------------------------------------------------------------------------------------------- +/* bdx_tx_db_inc_rptr - Increment the read pointer. + * + * @d - tx data base + */ +static inline void bdx_tx_db_inc_rptr(struct txdb *db) +{ + BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */ + __bdx_tx_db_ptr_next(db, &db->rptr); +} + +//------------------------------------------------------------------------------------------------- +/* bdx_tx_db_inc_rptr - Increment the write pointer. + * + * @d - tx data base + */ +static inline void bdx_tx_db_inc_wptr(struct txdb *db) +{ + __bdx_tx_db_ptr_next(db, &db->wptr); + BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as + a result of write */ +} + +//------------------------------------------------------------------------------------------------- +/* bdx_tx_db_init - Create and initialize txdb. + * + * @db - tx data base + * @sz_type - size of tx fifo + * Returns 0 on success, error code otherwise + */ +static int bdx_tx_db_init(struct bdx_priv *priv, int sz_type) +{ + int j, err = 0; + int memsz = FIFO_SIZE * (1 << (sz_type + 1)); + struct txdb *db = &priv->txdb; + + db->start = malloc(memsz, M_TN40, M_NOWAIT); + if (!db->start) + { + ERR("bdx_tx_db_init() malloc FAILED ! (%d)\n", memsz); + return -1; + } + bzero((void *)db->start, memsz); + /* + * In order to differentiate between an empty db state and a full db + * state at least one element should always be empty in order to + * avoid rptr == wptr, which means that the db is empty. + */ + db->size = memsz / sizeof(struct tx_map) - 1; + db->end = db->start + db->size + 1; /* just after last element */ + + /* All dbs are created empty */ + db->rptr = db->start; + db->wptr = db->start; + for (j = 0; j < db->size; j++) + { + err = bus_dmamap_create(priv->tx_dma_tag, 0, &db->wptr->dma_map); + if (err != 0) + { + free(db->start, M_TN40); + ERR("bus_dmamap_create() FAILD at %d\n", j); + break; + } + bdx_tx_db_inc_wptr(db); + } + db->wptr = db->start; + + return err; + +} // bdx_tx_db_init() + +//------------------------------------------------------------------------------------------------- +/* bdx_tx_db_close - Close tx db and free all memory. + * + * @d - tx data base + */ +static void bdx_tx_db_close(struct bdx_priv *priv) +{ + int j; + struct txdb *db = &priv->txdb; + + BDX_ASSERT(db == NULL); + + if (db->start) + { + db->wptr = db->start; + for (j = 0; j < db->size; j++) + { + bus_dmamap_destroy(priv->tx_dma_tag, db->wptr->dma_map); + } + free(db->start, M_TN40); + db->start = NULL; + } +} // bdx_tx_db_close() + +//------------------------------------------------------------------------------------------------- + +static int desc_lwords(int minSize, int nFrags) +{ + int lwords; + + // 3 - is number of lwords used for every additional phys buffer + + lwords = minSize + (nFrags * 3); + if (lwords & 1) + { + lwords++; /* pad it with 1 lword */ + } + + return lwords; + +} // desc_lwords + +//------------------------------------------------------------------------------------------------- + +/* + * init_txd_sizes - Pre-calculate the sizes of descriptors for skbs up to 16 + * frags The number of frags is used as an index to fetch the correct + * descriptors size, instead of calculating it each time + */ +static void __init init_txd_sizes(void) +{ + int i, lwords; + + /* 7 - is number of lwords in txd with one phys buffer */ + DBG("txd_size:\n"); + for (i = 0; i < MAX_PBL; i++) + { + lwords = desc_lwords(7, i); + txd_sizes[i].qwords = lwords >> 1; + txd_sizes[i].bytes = lwords << 2; + DBG("%2d. %d\n", i, txd_sizes[i].bytes); + } + +} // init_txd_sizes() + +//------------------------------------------------------------------------------------------------- + +static void __init init_rxd_sizes(void) +{ + int i, lwords; + + /* 6 - is number of lwords in rxfd with one phys buffer */ + DBG("rxd_size:\n"); + for (i = 0; i < MAX_PBL; i++) + { + lwords = desc_lwords(6, i); + rxd_sizes[i].qwords = lwords >> 1; + rxd_sizes[i].bytes = lwords << 2; + DBG("%2d. %d\n", i, rxd_sizes[i].qwords); + } + +} // init_rxd_sizes() + +//------------------------------------------------------------------------------------------------- +/* + * bdx_tx_init - Initialize all Tx related stuff. Namely, TXD and TXF fifos, + * database etc + */ +int bdx_tx_init(struct bdx_priv *priv) +{ + + int rVal = -1; + + do + { + if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size, + regTXD_CFG0_0, regTXD_CFG1_0, + regTXD_RPTR_0, regTXD_WPTR_0, (const char*)"TXD")) + { + break; + } + if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size, + regTXF_CFG0_0, regTXF_CFG1_0, + regTXF_RPTR_0, regTXF_WPTR_0, (const char*)"TXF")) + { + break; + } + /* + * The TX db has to keep mappings for all packets sent (on TxD) + * and not yet reclaimed (on TxF) + */ + if (bdx_tx_db_init(priv, MAX(priv->txd_size, priv->txf_size))) + { + break; + } + // SHORT_PKT_FIX + if (tn40_alloc_dma(priv, SHORT_PKT_LEN, &priv->short_pkt) != 0) + { + ERR("short packet alloc FAILED !\n"); + break; + } + bzero((void *)priv->short_pkt.tn40_dmamap.va, SHORT_PKT_LEN); + // SHORT_PKT_FIX end + + priv->tx_level = BDX_MAX_TX_LEVEL; + priv->tx_update_mark = priv->tx_level - 1024; + + rVal = 0; + } while(0); + if (rVal != 0) + { + ERR("bdx_tx_init FAILED ! (%d)\n", rVal); + } + + RET(rVal); +} // bdx_tx_init() + +//------------------------------------------------------------------------------------------------- + +void bdx_tx_free(struct bdx_priv *priv) +{ + ENTER; + bdx_fifo_free(priv, &priv->txd_fifo0.m); + bdx_fifo_free(priv, &priv->txf_fifo0.m); + bdx_tx_db_close(priv); + // SHORT_PKT_FIX + if(priv->short_pkt.tn40_dmamap.va != NULL) + { + tn40_free_dma(&priv->short_pkt); + } + // SHORT_PKT_FIX end + +} // bdx_tx_free() + +//------------------------------------------------------------------------------------------------- + +int bdx_probe(struct bdx_priv *priv) +{ + int err = -1; + do + { + bdx_reset(priv); + print_hw_id(priv); + if ((READ_REG(priv,FPGA_VER) & 0xFFF) == 308) + { + DBG("HW statistics not supported\n"); + priv->stats_flag = 0; + } + bdx_mdio_reset(priv, 0); + /* Initialize fifo sizes. */ + priv->name = (const char*)TN40_DRV_NAME; + priv->txd_size = 3; + priv->txf_size = 3; + priv->rxd_size = 3; + priv->rxf_size = 3; + priv->mtu = 1500; + /* Initialize the initial coalescing registers. */ + priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12); + priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12); + traceInit(); + init_txd_sizes(); + init_rxd_sizes(); + print_driver_id(); + if (bdx_read_mac(priv)) + { + ERR("load MAC address failed\n"); + break; + } + bdx_reset(priv); + WRITE_REG(priv, 0x51E0,0x30010006); // GPIO_OE_ WR CMD + WRITE_REG(priv, 0x51F0,0x0); // GPIO_OE_ DATA + WRITE_REG(priv, regMDIO_CMD_STAT, 0x3ec8); + if ((err = bdx_tx_init(priv))) + { + break; + } + if ((err = bdx_fw_load(priv))) + { + break; + } + bdx_tx_free(priv); + print_eth_id(priv); +#ifdef TN40_MEMLOG + memLogInit(); +#endif + + err = 0; + } while(0); + + RET(err); + +} // bdx_probe() + +//------------------------------------------------------------------------------------------------- + +/** + * bdx_remove - Device removal routine. + * + * @pdev - PCI device information struct + * + * bdx_remove is called by the PCI subsystem to notify the driver + * that it should release a PCI device. This could be caused by a + * Hot-Plug event, or because the driver is going to be removed from + * memory. + */ +void bdx_remove(struct bdx_priv *priv) +{ + + bdx_hw_stop(priv); + bdx_sw_reset(priv); + bdx_rx_free(priv); + bdx_tx_free(priv); +#if (defined VM_KLNX) + bdx_freeAllCmem(priv); +#endif + + MSG("Device removed\n"); + + EXIT; + +} // bdx_remove() + + + //------------------------------------------------------------------------------------------------- + // Use PMF to accept first MAC_MCST_NUM (15) addresses and accept the rest of addresses through IMF. + // + // TODO: Sort the addresses and write them in ascending order into RX_MAC_MCST regs. + // + // Currently we skip this phase now and accept ALL the multicast frames through IMF. + + //------------------------------------------------------------------------------------------------- + +void bdx_setbroadcast(struct bdx_priv *priv, int flags) +{ + int j; + u32 rxf_val = GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN | GMAC_RX_FILTER_TXFC; + + ENTER; + if (flags & IFF_PROMISC) + { + rxf_val |= GMAC_RX_FILTER_PRM; + } + if (flags & IFF_ALLMULTI) + { + /* set IMF to accept all multicast frames */ + for (j = 0; j < MAC_MCST_HASH_NUM; j++) + { + WRITE_REG(priv, regRX_MCST_HASH0 + j * 4, ~0); + } + } + if (flags & IFF_BROADCAST) + { + rxf_val |= GMAC_RX_FILTER_AB; + } + + WRITE_REG(priv, regGMAC_RXF_A, rxf_val); + EXIT; + +} // bdx_set_broadcast() + +//------------------------------------------------------------------------------------------------- + +void bdx_setmulti(struct bdx_priv *priv) + +{ + int j; + u8 hash; + u32 reg, val; + struct ifmultiaddr *ifma; + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + struct ifnet *ifp = tn40_priv->ifp; + + ENTER; + if_maddr_rlock(ifp); + // Set IMF to deny all multicast frames + for (j = 0; j < MAC_MCST_HASH_NUM; j++) + { + WRITE_REG(priv, regRX_MCST_HASH0 + j * 4, 0); + } + // Set PMF to deny all multicast frames + for (j = 0; j < MAC_MCST_NUM; j++) + { + WRITE_REG(priv, regRX_MAC_MCST0 + j * 8, 0); + WRITE_REG(priv, regRX_MAC_MCST1 + j * 8, 0); + } +#if __FreeBSD_version >= 1200000 + CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) +#else + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) +#endif + { + if (ifma->ifma_addr->sa_family != AF_LINK) + { + continue; + } + hash = 0; + for (j = 0; j < ETHER_ADDR_LEN; j++) + { + hash ^= (LLADDR((struct sockaddr_dl *)ifma->ifma_addr->sa_data))[j]; + + } + reg = regRX_MCST_HASH0 + ((hash >> 5) << 2); + val = READ_REG(priv, reg); + val |= (1 << (hash % 32)); + WRITE_REG(priv, reg, val); + } + if_maddr_runlock(ifp); + EXIT; + + } // bdx_setmulti() + +//------------------------------------------------------------------------------------------------- + +static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg) +{ + u64 val; + + val = READ_REG(priv, reg); + val |= ((u64) READ_REG(priv, reg + 8)) << 32; + return val; +} // bdx_read_l2stat() + +//------------------------------------------------------------------------------------------------- + +void bdx_update_stats(struct bdx_priv *priv) +{ + struct bdx_stats *stats = &priv->hw_stats; + u64 *stats_vector = (u64 *) stats; + int i; + int addr; + + /*Fill HW structure */ + addr = 0x7200; + + /*First 12 statistics - 0x7200 - 0x72B0 */ + for (i = 0; i < 12; i++) + { + stats_vector[i] = bdx_read_l2stat(priv, addr); + addr += 0x10; + } BDX_ASSERT(addr != 0x72C0); + + /* 0x72C0-0x72E0 RSRV */ + addr = 0x72F0; + for (; i < 16; i++) + { + stats_vector[i] = bdx_read_l2stat(priv, addr); + addr += 0x10; + } BDX_ASSERT(addr != 0x7330); + + /* 0x7330-0x7360 RSRV */ + addr = 0x7370; + for (; i < 19; i++) + { + stats_vector[i] = bdx_read_l2stat(priv, addr); + addr += 0x10; + } BDX_ASSERT(addr != 0x73A0); + + /* 0x73A0-0x73B0 RSRV */ + addr = 0x73C0; + for (; i < 23; i++) + { + stats_vector[i] = bdx_read_l2stat(priv, addr); + addr += 0x10; + } + + BDX_ASSERT(addr != 0x7400); BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i); + +} // bdx_update_stats() + +//------------------------------------------------------------------------------------------------- + +static inline void +tn40_map_mbuf(struct bdx_priv *priv, struct mbuf *mBuf, struct txd_desc *txdd, bus_dma_segment_t *segs, int nr_frags, size_t pktLen) +{ + int i; + struct txdb *db = &priv->txdb; + struct pbl *pbl = &txdd->pbl[0]; + u32 tLen = 0; + + DBG1("=== nr_frags : %d pktLen %lu================\n", nr_frags, pktLen); + DBG1("=== dma_addr : 0x%lx ================\n", segs->ds_addr); + for (i = 0; i <= nr_frags; i++) + { + db->wptr->len = segs->ds_len; + pbl->len = CPU_CHIP_SWAP32(db->wptr->len); + pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(segs->ds_addr)); + pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(segs->ds_addr)); + dbg_printPBL(pbl); + bdx_tx_db_inc_wptr(db); + tLen += segs->ds_len; + DBG1("pbl[%d]: ph 0x%08x pl 0x%08x l %u\n", i, pbl->pa_hi, pbl->pa_lo, pbl->len); + pbl++; + segs++; + } + if (pktLen != tLen) + { + ERR("tn40MapMbuf() BAD packet length %u != %lu\n", tLen, pktLen); + } + if(pktLen < 60) + { + ++nr_frags; // SHORT_PKT_FIX + } + DBG1("tn40MapMbuf() packet len %u segments %d\n", tLen, nr_frags); + /* Add mbuf clean up info. */ + db->wptr->len = -txd_sizes[nr_frags].bytes; + db->wptr->mBuf = mBuf; + bdx_tx_db_inc_wptr(db); + +} // tn40_map_mbuf() + +//------------------------------------------------------------------------------------------------- + +/* bdx_tx_transmit - Send a packet to the NIC. + * + * @skb - Packet to send + */ +#define MAX_SHRIK_TRIES (5) // safety counter +int bdx_tx_transmit(struct bdx_priv *priv, struct mbuf *mBuf) +{ + struct txd_desc *txdd; + int len; + int nr_frags; + size_t pktLen; + int txTrigger; + int err; + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + struct txdb *db = &priv->txdb; + u32 coLen = 0; + int txd_checksum = 0; /* no checksum */ + int txd_vlan_id = 0; + int txd_vtag = 0; + int shrik_tries = 0; + u32 txd_mss = 0; + u32 txd_lgsnd = 0; + struct txd_fifo *f = &priv->txd_fifo0; + bus_dma_segment_t segs[MAX_SEGMENTS]; + + ENTER; + + pktLen = mBuf->m_pkthdr.len; + + DBG("--> m %p len %lu\n", mBuf, pktLen); + // mtx_lock(&priv->tx_lock); + // traceAdd(0x11, pktLen); + do + { + do + { + err = bus_dmamap_load_mbuf_sg(priv->tx_dma_tag, db->wptr->dma_map, mBuf, segs, &nr_frags, BUS_DMA_NOWAIT); + if (err != 0) + { + if (err == EFBIG) + { + nr_frags = MAX_SEGMENTS; + } + else + { + ERR("bdx_tx_transmit() bus_dmamap_load_mbuf_sg 1 FAILED %d\n", err); + dbg_printMbuf(mBuf, __LINE__); + break; + } + } + if (nr_frags > MAX_PBL) + { + shrik_tries += 1; + dbg_printMbuf(mBuf,__LINE__); + dbg_printSges(segs, nr_frags); + if ((err = tn40_mbuf_shrink(mBuf, nr_frags)) != 0) + { + ERR("tn40_mbuf_shrink() FAILED %d\n", err); + break; + } + } + } while ((nr_frags > MAX_PBL) && (shrik_tries < MAX_SHRIK_TRIES)); + + if (nr_frags > MAX_PBL) + { + err = ENOBUFS; + } + if (err != 0) + { + ERR("bdx_tx_transmit() max PBL exceeded %d !\n", nr_frags); + break; + } + bus_dmamap_sync(priv->tx_dma_tag, db->wptr->dma_map, BUS_DMASYNC_PREWRITE); + nr_frags -= 1; + DBG1("bdx_tx_transmit() coLen %u\n", coLen); + if (mBuf->m_pkthdr.csum_flags & CSUM_IP ) txd_checksum |= 0x4; // Turn on H/W IP checksum + if (mBuf->m_pkthdr.csum_flags & CSUM_TCP) txd_checksum |= 0x2; // Turn on H/W TCP checksum + else + if (mBuf->m_pkthdr.csum_flags & CSUM_UDP) txd_checksum |= 0x1; // Turn on H/W UDP checksum + /* Build tx descriptor */ + BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */ + txdd = (struct txd_desc *)(f->m.va + f->m.wptr); + if (mBuf->m_flags & M_VLANTAG) + { + txd_vlan_id = htole16(mBuf->m_pkthdr.ether_vtag); + DBG("txd_vlan_id 0x%x\n", txd_vlan_id); + txd_vtag = 1; + } + if (mBuf->m_pkthdr.csum_flags & CSUM_IP_TSO) + { + txd_mss = mBuf->m_pkthdr.tso_segsz; + txd_lgsnd = 1; + } + //////////////////////// + if (txd_mss >= pktLen) + { + txd_mss = 0; + txd_lgsnd = 0; + } + //////////////////////// + txdd->length = CPU_CHIP_SWAP16(pktLen); + txdd->mss = CPU_CHIP_SWAP16(txd_mss); + txdd->txd_val1 = CPU_CHIP_SWAP32(TXD_W1_VAL(txd_sizes[nr_frags].qwords, + txd_checksum, txd_vtag, + txd_lgsnd, txd_vlan_id)); + txdd->va_hi = coLen; + //txdd->va_lo = (u32)((u64)mBuf); + tn40_map_mbuf(priv, mBuf, txdd , segs, nr_frags, pktLen); + // SHORT_PKT_FIX + if(pktLen < 60) + { + struct pbl *pbl = &txdd->pbl[++nr_frags]; + txdd->length = CPU_CHIP_SWAP16(60); + txdd->txd_val1 = CPU_CHIP_SWAP32(TXD_W1_VAL(txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,txd_lgsnd, txd_vlan_id)); + pbl->len = (u32)CPU_CHIP_SWAP32(60 - pktLen); + pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(priv->short_pkt.tn40_dmamap.pa)); + pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(priv->short_pkt.tn40_dmamap.pa)); + DBG1("=== SHORT_PKT_FIX ================\n"); + DBG1("=== nr_frags : %d ================\n", nr_frags); + dbg_printPBL(pbl); + COUNT_ADD(priv->counters, tx_fixed_bytes, 60 - pktLen); + } + // SHORT_PKT_FIX end + DBG1("=== txdd %p =====\n" , txdd); + DBG1("=== w1 qwords[%d] %d =====\n" , nr_frags, txd_sizes[nr_frags].qwords); + DBG1("=== TxD desc =====================\n"); + DBG1("=== w1: 0x%x ================\n", txdd->txd_val1); + DBG1("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length); + /* + * Increment TXD write pointer. In case of fifo wrapping copy reminder of + * the descriptor to the beginning + */ + f->m.wptr += txd_sizes[nr_frags].bytes; + len = f->m.wptr - f->m.memsz; + if (unlikely(len >= 0)) + { + f->m.wptr = len; + if (len > 0) + { + BDX_ASSERT(len > f->m.memsz); + memcpy(f->m.va, f->m.va + f->m.memsz, len); + } + } + DBG("--> bdx_tx_transmit() mbuf %p wptr %u\n", mBuf, f->m.wptr); + BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */ + priv->tx_level -= txd_sizes[nr_frags].bytes; + BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL); + DBG1("tx_level = %d tx_update_mark = %d tx_noupd =%d\n",priv->tx_level, priv->tx_update_mark, priv->tx_noupd); + txTrigger = 0; + if (priv->tx_level > priv->tx_update_mark) + { + txTrigger = 1; + } + else + { + if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) + { + priv->tx_noupd = 0; + txTrigger = 1; + } + } + COUNT_INC(priv->counters, tx_pkts); + COUNT_ADD(priv->counters, tx_bytes, pktLen); + if (txTrigger) + { + WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); + DBG1("WRITE_REG 0x%04x f->m.reg_WPTR 0x%x\n", f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); + bus_dmamap_sync(f->m.dma.dma_tag, f->m.dma.tn40_dmamap.dma_map, BUS_DMASYNC_PREWRITE); + } + DBG("--> bdx_tx_transmit() TX %s triggered rptr %u wptr %u tx_level %d tx_update_mark %d tx_noupd %d \n", + txTrigger ? "" : "*NOT*", READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR, f->m.wptr, priv->tx_level, priv->tx_update_mark, priv->tx_noupd); + dbg_printRegs(priv,(char *)"TX"); + if (priv->tx_level < BDX_MIN_TX_LEVEL) + { + DBG2("TX Q STOP level %d\n", priv->tx_level); + tn40_priv->ifp->if_drv_flags |= IFF_DRV_OACTIVE; + priv->tx_state = TX_STATE_QUEUE_FULL; + break; + } + err = 0; + + } while(0); + +// mtx_unlock(&priv->tx_lock); + + RET(err); + +} // bdx_tx_transmit() + +//------------------------------------------------------------------------------------------------- + +/* bdx_tx_cleanup - Clean the TXF fifo, run in the context of IRQ. + * + * @priv - bdx adapter + * + * This function scans the TXF fifo for descriptors, frees DMA mappings and + * reports to the OS that those packets were sent. + */ +void bdx_tx_cleanup(struct bdx_priv *priv) +{ + struct txf_desc *txfd; + tn40_priv_t *tn40_priv = CONTAINING_RECORD(priv, tn40_priv_t, bdx_priv); + struct txf_fifo *f = &priv->txf_fifo0; + struct txdb *db = &priv->txdb; + int tx_level = 0; + + ENTER; + bus_dmamap_sync(f->m.dma.dma_tag, f->m.dma.tn40_dmamap.dma_map, BUS_DMASYNC_POSTREAD); + f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK; + BDX_ASSERT(f->m.rptr >= f->m.memsz); /* Started with valid rptr */ +// mtx_lock(&priv->tx_lock); + while (f->m.wptr != f->m.rptr) + { + txfd = (struct txf_desc *)(f->m.va + f->m.rptr); + if (txfd->va_hi != 0) + { + //freeCmem(size_t(txfd->va_hi)); + } + f->m.rptr += BDX_TXF_DESC_SZ; + f->m.rptr &= f->m.size_mask; + BDX_ASSERT(db->rptr->len == 0); + do + { + BDX_ASSERT(db->rptr->len == 0); + bdx_tx_db_inc_rptr(db); + } while (db->rptr->len > 0); + tx_level -= db->rptr->len; // '-' Because the len is negative + DBG("m %p %d\n", db->rptr->mBuf, db->rptr->mBuf ? db->rptr->mBuf->m_pkthdr.len : 0); + COUNT_INC(priv->counters, tx_free_pkts); + COUNT_ADD(priv->counters, tx_free_bytes, db->rptr->mBuf ? db->rptr->mBuf->m_pkthdr.len : 0); + m_freem(db->rptr->mBuf); + bdx_tx_db_inc_rptr(db); + DBG("<-- bdx_tx_cleanup va_hi %u va_lo 0x%x tx_level %d + %d %s\n", + txfd->va_hi, txfd->va_lo, priv->tx_level, tx_level,txfd->status & 0x80000000 ? "TXE!" :""); + } + /* Let the HW know which TXF descriptors were cleaned */ + BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz); + WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); + /* + * We reclaimed resources, so in case the Q is stopped by xmit callback, + */ + priv->tx_level += tx_level; + BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL); + DBG("<-- bdx_tx_cleanup() TX %s triggered rptr %u wptr %u tx_level %d tx_noupd %d \n", + priv->tx_noupd ? "" : "*NOT*", READ_REG(priv, priv->txd_fifo0.m.reg_RPTR) & TXF_WPTR_WR_PTR, priv->txd_fifo0.m.wptr, priv->tx_level, priv->tx_noupd); + if (priv->tx_noupd) + { + priv->tx_noupd = 0; + WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR, priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR); + //dbg_printTXQ(priv); + } + bus_dmamap_sync(f->m.dma.dma_tag, f->m.dma.tn40_dmamap.dma_map, BUS_DMASYNC_PREWRITE); + if (priv->tx_state == TX_STATE_QUEUE_FULL) + { + if (priv->tx_level >= BDX_MIN_TX_LEVEL) + { + priv->tx_state = TX_STATE_OK; + DBG("TX Q wake level %d\n", priv->tx_level); + tn40_priv->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + } + else + { + DBG("bdx_tx_cleanup() TX Q stall at level %d\n", priv->tx_level); + } + } +// mtx_unlock(&priv->tx_lock); + + EXIT; + +} // bdx_tx_cleanup() + +//------------------------------------------------------------------------------------------------- + Index: sys/dev/tn40xx/tn40_ioctl.h =================================================================== --- /dev/null +++ sys/dev/tn40xx/tn40_ioctl.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#ifndef _TN40XX_IOCTL_H +#define _TN40XX_IOCTL_H + +/* ioctl ops */ + +enum +{ + OP_INFO, + OP_READ_REG, + OP_WRITE_REG, + OP_MDIO_READ, + OP_MDIO_WRITE, + op_TRACE_ON, + op_TRACE_OFF, + op_TRACE_ONCE, + op_TRACE_PRINT, + OP_DBG, + OP_MEMLOG_DMESG, + OP_MEMLOG_PRINT, +}; +enum +{ + DBG_STOP_DBG = 0, + DBG_START_DBG = 1, + DBG_SUSPEND = 2, + DBG_RESUME = 3, + DBG_PRINT_PAGE_TABLE = 4, + DBG_PRINT_COUNTERS = 5, + DBG_CLEAR_COUNTERS = 6, +}; + +#define IOCTL_DATA_SIZE (3) + +typedef struct _tn40_ioctl_ +{ + unsigned int data[IOCTL_DATA_SIZE]; + char *buf; +} tn40_ioctl_t; + +#endif /* _TN40XX_IOCTL_H */ Index: sys/dev/tn40xx/tn40_mbuf.h =================================================================== --- /dev/null +++ sys/dev/tn40xx/tn40_mbuf.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#ifndef __TN40_MBUF__ +#define __TN40_MBUF__ + +#include "tn40.h" + +#define NEW_MBUF_SIZE (MJUM16BYTES) + +int tn40_mbuf_shrink(struct mbuf *mBuf, int nr_frags); + +#endif // __TN40_MBUF__ Index: sys/dev/tn40xx/tn40_mbuf.c =================================================================== --- /dev/null +++ sys/dev/tn40xx/tn40_mbuf.c @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2019 Tehuti Networks Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include "tn40.h" +#include "tn40_mbuf.h" + +#define TN40_CHECK_MBUF_COPY + +//------------------------------------------------------------------------------------------------- + +static int tn40_mbuf_find(struct mbuf *mBuf, int count, struct mbuf **mHead, struct mbuf **mLast) +{ + int j, l, len, k = 0, coLen=mBuf->m_pkthdr.len; + + struct mbuf *m, *m1; + + for (m = mBuf; m; m=m->m_next) + { + len = 0; + m1 = m->m_next; // Skip the header + for (j = 0; j < count; j++) + { + len += m1->m_len; + if (m1->m_next != NULL) + { + m1 = m1->m_next; + } + else + { + break; + } + } + if (j >= count - 1) + { + if (len < coLen) + { + coLen = len; + *mHead = m; // The one *BEFORE* the first + *mLast = m1; // The last one; + l = k; // size + } + } + else + { + break; + } + k += 1; + } + DBG("Found (%p) at %d size %d bytes %d last %p\n", *mHead, l, count, coLen, *mLast); + + return coLen; + +} // tn40_mbuf_find() + +//------------------------------------------------------------------------------------------------- + +static int tn40_mbuf_copy(struct mbuf *fromBuf, struct mbuf *toBuf, int nCopy) +{ + int len, fLen, tLen; + caddr_t from, to; + struct mbuf *m; + int j = 0; + int nBytes = 0; + ENTER; + + DBG("copy from %p to %p\n", fromBuf, toBuf); + from = fromBuf->m_data; + to = toBuf->m_data; + fLen = fromBuf->m_len; + tLen = toBuf->m_len; + for (; ; ) + { + len = min(fLen, tLen); +#ifdef TN40_CHECK_MBUF_COPY + if ((from == NULL) || (to == NULL)) + { + ERR("tn40_mbuf_copy() internal error from %p to %p\n", from, to); + return 0; + } + if (from +len > fromBuf->m_data + fromBuf->m_len) + { + ERR("tn40_mbuf_copy() internal error from %p + %d > %p + %d\n", from, len, fromBuf->m_data, fromBuf->m_len); + return 0; + + } + if (to +len > toBuf->m_data + toBuf->m_len) + { + ERR("tn40_mbuf_copy() internal error to %p + %d > %p + %d\n", to, len, toBuf->m_data, toBuf->m_len); + return 0; + + } +#endif + memcpy(to, from, len); + nBytes += len; + fLen -= len; + tLen -= len; + if (fLen == 0) + { + j += 1; + m = fromBuf; + DBG("Copied from %p len %d\n", m, m->m_len); + if (j == nCopy) + { + m_free(m); + break; + } + fromBuf = fromBuf->m_next; + fLen = fromBuf->m_len; + from = fromBuf->m_data; + m_free(m); + } + else + { + from += len; + } + if (tLen == 0) + { + toBuf = toBuf->m_next; + tLen = toBuf->m_len; + to = toBuf->m_data; + } + else + { + to += len; + } + } + toBuf->m_len -= tLen; + toBuf->m_next = fromBuf->m_next; // Link the new mBuf head + DBG("linked new mbuf tail %p to %p\n", toBuf, fromBuf->m_next); + + return nBytes; + +} // tn40_mbuf_copy() + +//------------------------------------------------------------------------------------------------- + +int tn40_mbuf_shrink(struct mbuf *mBuf, int nr_frags) +{ + int coLen, nAllocs, j; + struct mbuf *mHead, *mLast, *m, *m1; + struct mbuf *newBuf = NULL; + int mBufSize = 0; + int nBytes = 0; + int err = 0; + int nCopy = nr_frags - MAX_PBL +1; + int nBufs = MAX_PBL; // for the first iteration + + if (nr_frags > MAX_PBL) + { + for (m = mBuf; m; m = m->m_next) mBufSize += 1; + // Find the start mbuf and the number of the new mbufs to allocate + do + { + nCopy += nBufs - MAX_PBL; + if (nCopy >= mBufSize) // this Mbuf cannot be shriked + { + nBufs = mBufSize; + break; + } + coLen = tn40_mbuf_find(mBuf, nCopy, &mHead, &mLast); + nAllocs = (coLen + NEW_MBUF_SIZE) / NEW_MBUF_SIZE; + nBufs = mBufSize - nCopy + nAllocs; + } while (nBufs > MAX_PBL); + // Allocate new mbufs + if (nBufs <= MAX_PBL) + { + for (j = 0; j < nAllocs; j++) + { + m = m_getjcl(M_NOWAIT, MT_DATA, 0, NEW_MBUF_SIZE); + if (m != NULL) + { + m->m_len = NEW_MBUF_SIZE; + if (newBuf == NULL) + { + newBuf = m1 = m; + } + else + { + m1->m_next = m; + m1 = m; + } + } + else + { + if (newBuf) + { + m_freem(newBuf); + newBuf = NULL; + err = ENOBUFS; // cannot allocate new mBuf + break; + } + } + } + DBG("New mbuf %p count %d\n", newBuf, nAllocs); + } + else + { + err = E2BIG; // mBuf too long + } + if ((err == 0) && (newBuf != NULL)) + { + nBytes = tn40_mbuf_copy(mHead->m_next, newBuf, nCopy); + mHead->m_next = newBuf; // Link the new mBuf + DBG("link %p to new mbuf %p\n", mHead, newBuf); + } + DBG("m %p len %d frags %d size %d -> %d copied %d \n", mBuf, m_length(mBuf, &m), nr_frags, mBufSize, nBufs, nBytes); + } + + RET(err); + +}// tn40_mbuf_shrink() + + + Index: sys/modules/Makefile =================================================================== --- sys/modules/Makefile +++ sys/modules/Makefile @@ -851,4 +851,6 @@ SUBDIR:= ${SUBDIR:u:O} +SUBDIR+= tn40xx + .include Index: sys/modules/tn40xx/Makefile =================================================================== --- /dev/null +++ sys/modules/tn40xx/Makefile @@ -0,0 +1,11 @@ +# $FreeBSD$ + +.PATH: ${SRCTOP}/sys/dev/tn40xx + +KMOD= tn40xx +SRCS= tn40.c tn40_hw.c tn40_mbuf.c CX4_FreeBSD.c CX4.c \ + AQR105_phy_FreeBSD.c AQR105_phy.c QT2025_phy_FreeBSD.c QT2025_phy.c \ + TLK10232_phy_FreeBSD.c TLK10232_phy.c +SRCS+= device_if.h bus_if.h pci_if.h + +.include