Index: sys/arm64/rockchip/clk/rk3399_cru.c
===================================================================
--- sys/arm64/rockchip/clk/rk3399_cru.c
+++ sys/arm64/rockchip/clk/rk3399_cru.c
@@ -79,6 +79,10 @@
 	CRU_GATE(0, "cpll_aclk_perihp_src", "cpll", 0x314, 0)
 	CRU_GATE(0, "gpll_aclk_perihp_src", "gpll", 0x314, 1)
 
+	/* CRU_CLKGATE_CON6 */
+	CRU_GATE(0, "gpll_aclk_emmc_src", "gpll", 0x318, 12)
+	CRU_GATE(0, "cpll_aclk_emmc_src", "cpll", 0x318, 13)
+
 	/* CRU_CLKGATE_CON7 */
 	CRU_GATE(0, "gpll_aclk_perilp0_src", "gpll", 0x31C, 0)
 	CRU_GATE(0, "cpll_aclk_perilp0_src", "cpll", 0x31C, 1)
@@ -1178,6 +1182,130 @@
 	.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
 };
 
+/*
+ * SD/MMC
+ */
+
+#define HCLK_SD				461
+#define SCLK_SDMMC			76
+#define SCLK_SDIO			77
+#define SCLK_EMMC			78
+#define ACLK_EMMC			240
+
+static const char *hclk_sd_parents[] = {"cpll", "gpll"};
+
+static struct rk_clk_composite_def hclk_sd = {
+	.clkdef = {
+		.id = HCLK_SD,
+		.name = "hclk_sd",
+		.parent_names = hclk_sd_parents,
+		.parent_cnt = nitems(hclk_sd_parents),
+	},
+	/* CRU_CLKSEL_CON13 */
+	.muxdiv_offset = 0x134,
+	.mux_shift = 15,
+	.mux_width = 1,
+
+	.div_shift = 8,
+	.div_width = 5,
+
+	/* CRU_CLKGATE_CON12 */
+	.gate_offset = 0x330,
+	.gate_shift = 13,
+
+	.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
+};
+
+static const char *sclk_sd_parents[] = {
+	"cpll", "gpll", "npll", "ppll", "xin24m" /* XXX: "upll" */, "xin24m"
+};
+
+static struct rk_clk_composite_def sclk_sdmmc = {
+	.clkdef = {
+		.id = SCLK_SDMMC,
+		.name = "sclk_sdmmc",
+		.parent_names = sclk_sd_parents,
+		.parent_cnt = nitems(sclk_sd_parents),
+	},
+	/* CRU_CLKSEL_CON16 */
+	.muxdiv_offset = 0x140,
+	.mux_shift = 8,
+	.mux_width = 3,
+
+	.div_shift = 0,
+	.div_width = 6,
+
+	/* CRU_CLKGATE_CON6 */
+	.gate_offset = 0x318,
+	.gate_shift = 1,
+
+	.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
+};
+
+static struct rk_clk_composite_def sclk_sdio = {
+	.clkdef = {
+		.id = SCLK_SDIO,
+		.name = "sclk_sdio",
+		.parent_names = sclk_sd_parents,
+		.parent_cnt = nitems(sclk_sd_parents),
+	},
+	/* CRU_CLKSEL_CON15 */
+	.muxdiv_offset = 0x13c,
+	.mux_shift = 8,
+	.mux_width = 3,
+
+	.div_shift = 0,
+	.div_width = 6,
+
+	/* CRU_CLKGATE_CON6 */
+	.gate_offset = 0x318,
+	.gate_shift = 0,
+
+	.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
+};
+
+static struct rk_clk_composite_def clk_emmc = {
+	.clkdef = {
+		.id = SCLK_EMMC,
+		.name = "clk_emmc",
+		.parent_names = sclk_sd_parents,
+		.parent_cnt = nitems(sclk_sd_parents),
+	},
+	/* CRU_CLKSEL_CON22 */
+	.muxdiv_offset = 0x158,
+	.mux_shift = 8,
+	.mux_width = 3,
+
+	.div_shift = 0,
+	.div_width = 7,
+
+	/* CRU_CLKGATE_CON6 */
+	.gate_offset = 0x318,
+	.gate_shift = 14,
+
+	.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
+};
+
+static const char *aclk_emmc_parents[] = {"cpll_aclk_emmc_src", "gpll_aclk_emmc_src"};
+
+static struct rk_clk_composite_def aclk_emmc = {
+	.clkdef = {
+		.id = ACLK_EMMC,
+		.name = "aclk_emmc",
+		.parent_names = aclk_emmc_parents,
+		.parent_cnt = nitems(aclk_emmc_parents),
+	},
+	/* CRU_CLKSEL_CON21 */
+	.muxdiv_offset = 0x154,
+	.mux_shift = 7,
+	.mux_width = 1,
+
+	.div_shift = 0,
+	.div_width = 5,
+
+	.flags = RK_CLK_COMPOSITE_HAVE_MUX,
+};
+
 /*
  * ARM CPU clocks (LITTLE and big)
  */
@@ -1476,6 +1604,27 @@
 		.clk.composite = &i2c7,
 	},
 
+	{
+		.type = RK_CLK_COMPOSITE,
+		.clk.composite = &hclk_sd,
+	},
+	{
+		.type = RK_CLK_COMPOSITE,
+		.clk.composite = &sclk_sdmmc,
+	},
+	{
+		.type = RK_CLK_COMPOSITE,
+		.clk.composite = &sclk_sdio,
+	},
+	{
+		.type = RK_CLK_COMPOSITE,
+		.clk.composite = &clk_emmc,
+	},
+	{
+		.type = RK_CLK_COMPOSITE,
+		.clk.composite = &aclk_emmc,
+	},
+
 	{
 		.type = RK_CLK_ARMCLK,
 		.clk.armclk = &armclk_l,
Index: sys/dev/mmc/host/dwmmc_rockchip.c
===================================================================
--- sys/dev/mmc/host/dwmmc_rockchip.c
+++ sys/dev/mmc/host/dwmmc_rockchip.c
@@ -50,11 +50,13 @@
 enum RKTYPE {
 	RK2928 = 1,
 	RK3328,
+	RK3399,
 };
 
 static struct ofw_compat_data compat_data[] = {
 	{"rockchip,rk2928-dw-mshc",	RK2928},
 	{"rockchip,rk3328-dw-mshc",	RK3328},
+	{"rockchip,rk3399-dw-mshc",	RK3399},
 	{NULL,				0},
 };
 
Index: sys/dev/sdhci/sdhci_fdt.c
===================================================================
--- sys/dev/sdhci/sdhci_fdt.c
+++ sys/dev/sdhci/sdhci_fdt.c
@@ -66,12 +66,14 @@
 #define	SDHCI_FDT_GENERIC	2
 #define	SDHCI_FDT_XLNX_ZY7	3
 #define	SDHCI_FDT_QUALCOMM	4
+#define	SDHCI_FDT_ARASAN	5
 
 static struct ofw_compat_data compat_data[] = {
 	{ "marvell,armada-380-sdhci",	SDHCI_FDT_ARMADA38X },
 	{ "sdhci_generic",		SDHCI_FDT_GENERIC },
 	{ "qcom,sdhci-msm-v4",		SDHCI_FDT_QUALCOMM },
 	{ "xlnx,zy7_sdhci",		SDHCI_FDT_XLNX_ZY7 },
+	{ "arasan,sdhci-5.1",		SDHCI_FDT_ARASAN },
 	{ NULL, 0 }
 };
 
@@ -216,6 +218,9 @@
 		sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
 		device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller");
 		break;
+	case SDHCI_FDT_ARASAN:
+		device_set_desc(dev, "Arasan generic fdt SDHCI controller");
+		break;
 	default:
 		return (ENXIO);
 	}