Index: sys/arm/mv/files.arm7 =================================================================== --- sys/arm/mv/files.arm7 +++ sys/arm/mv/files.arm7 @@ -34,7 +34,7 @@ dev/uart/uart_dev_ns8250.c optional uart dev/uart/uart_dev_snps.c optional uart dev/usb/controller/ehci_mv.c optional ehci -dev/usb/controller/xhci_mv.c optional xhci +dev/usb/controller/xhci_fdt.c optional xhci dev/ahci/ahci_mv_fdt.c optional ahci kern/kern_clocksource.c standard Index: sys/arm/mv/files.mv =================================================================== --- sys/arm/mv/files.mv +++ sys/arm/mv/files.mv @@ -31,7 +31,7 @@ dev/uart/uart_dev_ns8250.c optional uart dev/uart/uart_dev_snps.c optional uart dev/usb/controller/ehci_mv.c optional ehci -dev/usb/controller/xhci_mv.c optional xhci +dev/usb/controller/xhci_fdt.c optional xhci dev/ahci/ahci_mv_fdt.c optional ahci kern/kern_clocksource.c standard Index: sys/arm64/conf/GENERIC =================================================================== --- sys/arm64/conf/GENERIC +++ sys/arm64/conf/GENERIC @@ -196,7 +196,8 @@ device ehci # EHCI USB interface (USB 2.0) device ehci_mv # Marvell EHCI USB interface device xhci # XHCI PCI->USB interface (USB 3.0) -device xhci_mv # Marvell XHCI USB interface +device xhci_fdt # Marvell/DWC3/Generic XHCI USB interface +device rk_xhci # Rockchip glue for DWC3 XHCI interface device usb # USB Bus (required) device ukbd # Keyboard device umass # Disks/Mass storage - Requires scbus and da Index: sys/arm64/rockchip/rk_xhci.c =================================================================== --- /dev/null +++ sys/arm64/rockchip/rk_xhci.c @@ -0,0 +1,121 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018-2019 Greg V + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * The Rockchip glue node for the Synopsys DesignWare USB 3.0 controller + * enables clocks, deasserts resets, and attaches the actual controller. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include + +#include +#include + +static int +rk_xhci_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + if (!(ofw_bus_is_compatible(dev, "rockchip,rk3328-dwc3") || + ofw_bus_is_compatible(dev, "rockchip,rk3399-dwc3"))) + return (ENXIO); + device_set_desc(dev, "Rockchip DWC3 USB 3.0 Controller"); + + return (BUS_PROBE_DEFAULT); +} + +static int +rk_xhci_attach(device_t dev) +{ + size_t off; + hwreset_t rst; + clk_t clk; + phandle_t node; + + for (off = 0; clk_get_by_ofw_index(dev, 0, off, &clk) == 0; off++) { + if (bootverbose) + device_printf(dev, "enabling clock %s\n", + clk_get_name(clk)); + if (clk_enable(clk) != 0) { + device_printf(dev, "could not enable clock %s\n", + clk_get_name(clk)); + return (ENXIO); + } + } + + for (off = 0; hwreset_get_by_ofw_idx(dev, 0, off, &rst) == 0; off++) { + if (bootverbose) + device_printf(dev, "deasserting reset\n"); + if (hwreset_deassert(rst) != 0) { + device_printf(dev, "could not deassert reset\n"); + return (ENXIO); + } + } + + /* Attach the actual xhci child device */ + node = ofw_bus_get_node(dev); + + simplebus_init(dev, node); + bus_generic_probe(dev); + + for (node = OF_child(node); node > 0; node = OF_peer(node)) + simplebus_add_device(dev, node, 0, NULL, -1, NULL); + + return (bus_generic_attach(dev)); +} + +static device_method_t rk_xhci_methods[] = { + DEVMETHOD(device_probe, rk_xhci_probe), + DEVMETHOD(device_attach, rk_xhci_attach), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + + DEVMETHOD_END +}; + +static devclass_t rk_xhci_devclass; + +DEFINE_CLASS_1(rk_xhci, rk_xhci_driver, rk_xhci_methods, + sizeof(struct simplebus_softc), simplebus_driver); +DRIVER_MODULE(rk_xhci, simplebus, rk_xhci_driver, rk_xhci_devclass, 0, 0); +MODULE_DEPEND(rk_xhci, xhci, 1, 1, 1); Index: sys/conf/files.arm64 =================================================================== --- sys/conf/files.arm64 +++ sys/conf/files.arm64 @@ -233,7 +233,7 @@ dev/usb/controller/generic_ehci.c optional ehci acpi dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt -dev/usb/controller/xhci_mv.c optional xhci_mv fdt +dev/usb/controller/xhci_fdt.c optional xhci_fdt fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov @@ -269,6 +269,7 @@ arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 +arm64/rockchip/rk_xhci.c optional fdt rk_xhci soc_rockchip_rk3328 | fdt rk_xhci soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 Index: sys/dev/usb/controller/xhci_fdt.c =================================================================== --- sys/dev/usb/controller/xhci_fdt.c +++ sys/dev/usb/controller/xhci_fdt.c @@ -2,6 +2,8 @@ * Copyright (c) 2015 Semihalf. * Copyright (c) 2015 Stormshield. * All rights reserved. + * Copyright (c) 2017 Mark Kettenis + * Copyright (c) 2018 Greg V * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -64,32 +66,111 @@ #include #include -#define XHCI_HC_DEVSTR "Marvell Integrated USB 3.0 controller" -#define XHCI_HC_VENDOR "Marvell" +#define XHCI_MARVELL_DEVSTR "Marvell Integrated USB 3.0 controller" +#define XHCI_MARVELL_VENDOR "Marvell" +#define XHCI_DWC_DEVSTR "Synopsys DesignWare USB 3.0 controller" +#define XHCI_DWC_VENDOR "Synopsys" +#define XHCI_GENERIC_DEVSTR "Generic USB 3.0 controller" +#define XHCI_GENERIC_VENDOR "Generic" #define IS_DMA_32B 1 +enum xhci_fdt_id { + XHCI_GENERIC = 1, + XHCI_MARVELL, + XHCI_DWC, +}; + static device_attach_t xhci_attach; static device_detach_t xhci_detach; static struct ofw_compat_data compat_data[] = { - {"marvell,armada-380-xhci", true}, - {"marvell,armada3700-xhci", true}, - {"marvell,armada-8k-xhci", true}, - {NULL, false} + {"marvell,armada-380-xhci", XHCI_MARVELL}, + {"marvell,armada3700-xhci", XHCI_MARVELL}, + {"marvell,armada-8k-xhci", XHCI_MARVELL}, + {"snps,dwc3", XHCI_DWC}, + {"synopsys,dwc3", XHCI_DWC}, + {"generic-xhci", XHCI_GENERIC}, + {NULL, 0} }; +/* + * Synopsys DesignWare (DWC3) needs some additional configuration + **/ +#define USB3_GCTL 0xc110 +#define USB3_GCTL_PRTCAPDIR_MASK (0x3 << 12) +#define USB3_GCTL_PRTCAPDIR_HOST (0x1 << 12) +#define USB3_GCTL_PRTCAPDIR_DEVICE (0x2 << 12) +#define USB3_GUCTL1 0xc11c +#define USB3_GUCTL1_TX_IPGAP_LINECHECK_DIS (1 << 28) +#define USB3_GUSB2PHYCFG0 0xc200 +#define USB3_GUSB2PHYCFG0_U2_FREECLK_EXISTS (1 << 30) +#define USB3_GUSB2PHYCFG0_USBTRDTIM(n) ((n) << 10) +#define USB3_GUSB2PHYCFG0_ENBLSLPM (1 << 8) +#define USB3_GUSB2PHYCFG0_SUSPENDUSB20 (1 << 6) +#define USB3_GUSB2PHYCFG0_PHYIF (1 << 3) + +static void +xhci_dwc3_init(struct xhci_softc *sc, phandle_t node) +{ + char phy_type[16] = { 0 }; + uint32_t reg; + + /* We don't support device mode, so always force host mode. */ + reg = bus_space_read_4(sc->sc_io_tag, sc->sc_io_hdl, USB3_GCTL); + reg &= ~USB3_GCTL_PRTCAPDIR_MASK; + reg |= USB3_GCTL_PRTCAPDIR_HOST; + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, USB3_GCTL, reg); + + /* Configure USB2 PHY type and quirks. */ + OF_getprop(node, "phy_type", phy_type, sizeof(phy_type)); + reg = bus_space_read_4(sc->sc_io_tag, sc->sc_io_hdl, USB3_GUSB2PHYCFG0); + reg &= ~USB3_GUSB2PHYCFG0_USBTRDTIM(0xf); + if (strcmp(phy_type, "utmi_wide") == 0) { + reg |= USB3_GUSB2PHYCFG0_PHYIF; + reg |= USB3_GUSB2PHYCFG0_USBTRDTIM(0x5); + } else { + reg &= ~USB3_GUSB2PHYCFG0_PHYIF; + reg |= USB3_GUSB2PHYCFG0_USBTRDTIM(0x9); + } + if (OF_getproplen(node, "snps,dis-u2-freeclk-exists-quirk") == 0) + reg &= ~USB3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; + if (OF_getproplen(node, "snps,dis_enblslpm_quirk") == 0) + reg &= ~USB3_GUSB2PHYCFG0_ENBLSLPM; + if (OF_getproplen(node, "snps,dis_u2_susphy_quirk") == 0) + reg &= ~USB3_GUSB2PHYCFG0_SUSPENDUSB20; + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, USB3_GUSB2PHYCFG0, reg); + + /* Configure USB3 quirks. */ + reg = bus_space_read_4(sc->sc_io_tag, sc->sc_io_hdl, USB3_GUCTL1); + if (OF_getproplen(node, "snps,dis-tx-ipgap-linecheck-quirk") == 0) + reg |= USB3_GUCTL1_TX_IPGAP_LINECHECK_DIS; + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, USB3_GUCTL1, reg); +} + static int xhci_probe(device_t dev) { + enum xhci_fdt_id vendor; if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + vendor = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + if (!vendor) return (ENXIO); - device_set_desc(dev, XHCI_HC_DEVSTR); + switch (vendor) { + case XHCI_MARVELL: + device_set_desc(dev, XHCI_MARVELL_DEVSTR); + break; + case XHCI_DWC: + device_set_desc(dev, XHCI_DWC_DEVSTR); + break; + case XHCI_GENERIC: + device_set_desc(dev, XHCI_GENERIC_DEVSTR); + break; + } return (BUS_PROBE_DEFAULT); } @@ -98,6 +179,7 @@ xhci_attach(device_t dev) { struct xhci_softc *sc = device_get_softc(dev); + enum xhci_fdt_id vendor; int err = 0, rid = 0; sc->sc_bus.parent = dev; @@ -133,8 +215,24 @@ device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); - sprintf(sc->sc_vendor, XHCI_HC_VENDOR); - device_set_desc(sc->sc_bus.bdev, XHCI_HC_DEVSTR); + vendor = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + if (!vendor) + return (ENXIO); + + switch (vendor) { + case XHCI_MARVELL: + sprintf(sc->sc_vendor, XHCI_MARVELL_VENDOR); + device_set_desc(sc->sc_bus.bdev, XHCI_MARVELL_DEVSTR); + break; + case XHCI_DWC: + sprintf(sc->sc_vendor, XHCI_DWC_VENDOR); + device_set_desc(sc->sc_bus.bdev, XHCI_DWC_DEVSTR); + break; + case XHCI_GENERIC: + sprintf(sc->sc_vendor, XHCI_GENERIC_VENDOR); + device_set_desc(sc->sc_bus.bdev, XHCI_GENERIC_DEVSTR); + break; + } err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); @@ -145,6 +243,9 @@ return (err); } + if (vendor == XHCI_DWC) + xhci_dwc3_init(sc, ofw_bus_get_node(dev)); + err = xhci_init(sc, dev, IS_DMA_32B); if (err != 0) { device_printf(dev, "Failed to init XHCI, with error %d\n", err);