Index: sys/mips/conf/SWARM
===================================================================
--- sys/mips/conf/SWARM
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# $FreeBSD$
-#
-
-include		"std.SWARM"
-
-ident		SWARM
-
-machine		mips mips
-
-makeoptions	ARCH_FLAGS="-mabi=32 -march=mips32"
-makeoptions	LDSCRIPT_NAME=	ldscript.mips.cfe
Index: sys/mips/conf/SWARM_SMP
===================================================================
--- sys/mips/conf/SWARM_SMP
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# $FreeBSD$
-#
-
-include		"std.SWARM"
-
-ident		SWARM_SMP
-
-options 	SMP
-options 	PRINTF_BUFR_SIZE=128
-
-machine		mips mips
-
-makeoptions	ARCH_FLAGS="-mabi=32 -march=mips32"
-makeoptions	LDSCRIPT_NAME=	ldscript.mips.cfe
Index: sys/mips/include/cpufunc.h
===================================================================
--- sys/mips/include/cpufunc.h
+++ sys/mips/include/cpufunc.h
@@ -346,27 +346,19 @@
 	__asm __volatile ("break");
 }
 
-#if defined(__GNUC__) && !defined(__mips_o32)
-#define	mips3_ld(a)	(*(const volatile uint64_t *)(a))
-#define	mips3_sd(a, v)	(*(volatile uint64_t *)(a) = (v))
-#else
-uint64_t mips3_ld(volatile uint64_t *va);
-void mips3_sd(volatile uint64_t *, uint64_t);
-#endif	/* __GNUC__ */
-
 #endif /* _KERNEL */
 
 #define	readb(va)	(*(volatile uint8_t *) (va))
 #define	readw(va)	(*(volatile uint16_t *) (va))
 #define	readl(va)	(*(volatile uint32_t *) (va))
-#if defined(__GNUC__) && !defined(__mips_o32)
+#if !defined(__mips_o32)
 #define	readq(a)	(*(volatile uint64_t *)(a))
 #endif
  
 #define	writeb(va, d)	(*(volatile uint8_t *) (va) = (d))
 #define	writew(va, d)	(*(volatile uint16_t *) (va) = (d))
 #define	writel(va, d)	(*(volatile uint32_t *) (va) = (d))
-#if defined(__GNUC__) && !defined(__mips_o32)
+#if !defined(__mips_o32)
 #define	writeq(va, d)	(*(volatile uint64_t *) (va) = (d))
 #endif
 
Index: sys/mips/mips/support.S
===================================================================
--- sys/mips/mips/support.S
+++ sys/mips/mips/support.S
@@ -1022,78 +1022,3 @@
 	jr	ra
 	li	v0, 1			# longjmp return
 END(longjmp)
-
-LEAF(mips3_ld)
-	.set push
-	.set noreorder
-	.set mips64
-#if defined(__mips_o32)
-	mfc0	t0, MIPS_COP_0_STATUS		# turn off interrupts
-	and	t1, t0, ~(MIPS_SR_INT_IE)
-	mtc0	t1, MIPS_COP_0_STATUS
-	COP0_SYNC
-	nop
-	nop
-	nop
-
-	ld	v0, 0(a0)
-#if _BYTE_ORDER == _BIG_ENDIAN
-	dsll	v1, v0, 32
-	dsra	v1, v1, 32			# low word in v1
-	dsra	v0, v0, 32			# high word in v0
-#else
-	dsra	v1, v0, 32			# high word in v1
-	dsll	v0, v0, 32
-	dsra	v0, v0, 32			# low word in v0
-#endif
-
-	mtc0	t0, MIPS_COP_0_STATUS		# restore intr status.
-	COP0_SYNC
-	nop
-#else /* !__mips_o32 */
-	ld	v0, 0(a0)
-#endif /* !__mips_o32 */
-
-	jr	ra
-	nop
-	.set pop
-END(mips3_ld)
-
-LEAF(mips3_sd)
-	.set push
-	.set mips64
-	.set noreorder
-#if defined(__mips_o32)
-	mfc0	t0, MIPS_COP_0_STATUS		# turn off interrupts
-	and	t1, t0, ~(MIPS_SR_INT_IE)
-	mtc0	t1, MIPS_COP_0_STATUS
-	COP0_SYNC
-	nop
-	nop
-	nop
-
-	# NOTE: a1 is padding!
-
-#if _BYTE_ORDER == _BIG_ENDIAN
-	dsll	a2, a2, 32			# high word in a2
-	dsll	a3, a3, 32			# low word in a3
-	dsrl	a3, a3, 32
-#else
-	dsll	a2, a2, 32			# low word in a2
-	dsrl	a2, a2, 32
-	dsll	a3, a3, 32			# high word in a3
-#endif
-	or	a1, a2, a3
-	sd	a1, 0(a0)
-
-	mtc0	t0, MIPS_COP_0_STATUS		# restore intr status.
-	COP0_SYNC
-	nop
-#else /* !__mips_o32 */
-	sd	a1, 0(a0)
-#endif /* !__mips_o32 */
-
-	jr	ra
-	nop
-	.set pop
-END(mips3_sd)
Index: sys/mips/sibyte/sb_machdep.c
===================================================================
--- sys/mips/sibyte/sb_machdep.c
+++ sys/mips/sibyte/sb_machdep.c
@@ -250,6 +250,9 @@
 	 *
 	 * For now work around this by copying the TLB exception handling
 	 * code to the XTLB exception vector.
+	 *
+	 * XXX
+	 * Now that we only support running in 64-bit mode, how true is this?
 	 */
 	{
 		bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC,
Index: sys/mips/sibyte/sb_scd.c
===================================================================
--- sys/mips/sibyte/sb_scd.c
+++ sys/mips/sibyte/sb_scd.c
@@ -39,15 +39,8 @@
 
 #include "sb_scd.h"
 
-/*
- * We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit
- * processor. It has some registers that must be accessed using 64-bit load
- * and store instructions.
- *
- * We use the mips_ld() and mips_sd() functions to do this for us.
- */
-#define	sb_store64(addr, val)	mips3_sd((uint64_t *)(uintptr_t)(addr), (val))
-#define	sb_load64(addr)		mips3_ld((uint64_t *)(uintptr_t)(addr))
+#define	sb_store64(addr, val)	writeq((uint64_t *)(intptr_t)(addr), (val))
+#define	sb_load64(addr)		readq((uint64_t *)(intptr_t)(addr))
 
 /*
  * System Control and Debug (SCD) unit on the Sibyte ZBbus.