Index: head/sys/dev/sfxge/common/ef10_nic.c
===================================================================
--- head/sys/dev/sfxge/common/ef10_nic.c
+++ head/sys/dev/sfxge/common/ef10_nic.c
@@ -1672,6 +1672,16 @@
 	 */
 	encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
 
+	encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
+	/* No boundary crossing limits */
+	encp->enc_tx_dma_desc_boundary = 0;
+
+	/*
+	 * Maximum number of bytes into the frame the TCP header can start for
+	 * firmware assisted TSO to work.
+	 */
+	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
+
 
 	/* Get remaining controller-specific board config */
 	if ((rc = enop->eno_board_cfg(enp)) != 0)
Index: head/sys/dev/sfxge/common/hunt_nic.c
===================================================================
--- head/sys/dev/sfxge/common/hunt_nic.c
+++ head/sys/dev/sfxge/common/hunt_nic.c
@@ -232,10 +232,6 @@
 	encp->enc_rx_buf_align_start = 1;
 	encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
 
-	encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
-	/* No boundary crossing limits */
-	encp->enc_tx_dma_desc_boundary = 0;
-
 	/*
 	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
 	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
@@ -280,12 +276,6 @@
 	}
 	encp->enc_intr_vec_base = base;
 	encp->enc_intr_limit = nvec;
-
-	/*
-	 * Maximum number of bytes into the frame the TCP header can start for
-	 * firmware assisted TSO to work.
-	 */
-	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
 
 	if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
 		goto fail7;
Index: head/sys/dev/sfxge/common/medford2_nic.c
===================================================================
--- head/sys/dev/sfxge/common/medford2_nic.c
+++ head/sys/dev/sfxge/common/medford2_nic.c
@@ -166,10 +166,6 @@
 	}
 	encp->enc_rx_buf_align_end = end_padding;
 
-	encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
-	/* No boundary crossing limits */
-	encp->enc_tx_dma_desc_boundary = 0;
-
 	/*
 	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
 	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
@@ -215,12 +211,6 @@
 	}
 	encp->enc_intr_vec_base = base;
 	encp->enc_intr_limit = nvec;
-
-	/*
-	 * Maximum number of bytes into the frame the TCP header can start for
-	 * firmware assisted TSO to work.
-	 */
-	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
 
 	/*
 	 * Medford2 stores a single global copy of VPD, not per-PF as on
Index: head/sys/dev/sfxge/common/medford_nic.c
===================================================================
--- head/sys/dev/sfxge/common/medford_nic.c
+++ head/sys/dev/sfxge/common/medford_nic.c
@@ -163,10 +163,6 @@
 	}
 	encp->enc_rx_buf_align_end = end_padding;
 
-	encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
-	/* No boundary crossing limits */
-	encp->enc_tx_dma_desc_boundary = 0;
-
 	/*
 	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
 	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
@@ -212,12 +208,6 @@
 	}
 	encp->enc_intr_vec_base = base;
 	encp->enc_intr_limit = nvec;
-
-	/*
-	 * Maximum number of bytes into the frame the TCP header can start for
-	 * firmware assisted TSO to work.
-	 */
-	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
 
 	/*
 	 * Medford stores a single global copy of VPD, not per-PF as on