Index: head/sys/arm64/arm64/gic_v3_acpi.c =================================================================== --- head/sys/arm64/arm64/gic_v3_acpi.c +++ head/sys/arm64/arm64/gic_v3_acpi.c @@ -305,6 +305,8 @@ struct gic_v3_acpi_devinfo *di; struct gic_v3_softc *sc; device_t child, dev; + u_int xref; + int err, pxm; if (entry->Type == ACPI_MADT_TYPE_GENERIC_TRANSLATOR) { /* We have an ITS, add it as a child */ @@ -321,7 +323,14 @@ resource_list_add(&di->di_rl, SYS_RES_MEMORY, 0, gict->BaseAddress, gict->BaseAddress + 128 * 1024 - 1, 128 * 1024); - di->di_gic_dinfo.gic_domain = -1; + err = acpi_iort_its_lookup(gict->TranslationId, &xref, &pxm); + if (err == 0) { + di->di_gic_dinfo.gic_domain = pxm; + di->di_gic_dinfo.msi_xref = xref; + } else { + di->di_gic_dinfo.gic_domain = -1; + di->di_gic_dinfo.msi_xref = ACPI_MSI_XREF; + } sc->gic_nchildren++; device_set_ivars(child, di); } Index: head/sys/arm64/arm64/gic_v3_var.h =================================================================== --- head/sys/arm64/arm64/gic_v3_var.h +++ head/sys/arm64/arm64/gic_v3_var.h @@ -87,6 +87,7 @@ struct gic_v3_devinfo { int gic_domain; + int msi_xref; }; #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc) Index: head/sys/arm64/arm64/gicv3_its.c =================================================================== --- head/sys/arm64/arm64/gicv3_its.c +++ head/sys/arm64/arm64/gicv3_its.c @@ -1722,6 +1722,7 @@ gicv3_its_acpi_attach(device_t dev) { struct gicv3_its_softc *sc; + struct gic_v3_devinfo *di; int err; sc = device_get_softc(dev); @@ -1729,13 +1730,13 @@ if (err != 0) return (err); - sc->sc_pic = intr_pic_register(dev, - device_get_unit(dev) + ACPI_MSI_XREF); + di = device_get_ivars(dev); + sc->sc_pic = intr_pic_register(dev, di->msi_xref); intr_pic_add_handler(device_get_parent(dev), sc->sc_pic, gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length); /* Register this device to handle MSI interrupts */ - intr_msi_register(dev, device_get_unit(dev) + ACPI_MSI_XREF); + intr_msi_register(dev, di->msi_xref); return (0); }